JP2010020690A - Serial interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of a serial interface circuit. <P>SOLUTION: During transmission of a particular signal from a physical layer 2, the serial interface circuit determines the status of a protocol control circuit 3 by a power saving control circuit 4. By selectively shifting the physical layer 2 and the protocol control circuit 3 into the power saving mode, power consumption can be reduced by itself without requiring a sequence to the power saving mode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power saving method in a serial interface circuit.

  2. Description of the Related Art As information recording / reproducing devices, devices using various forms of media such as optical disks and magnetic disks are known. Among them, hard disk drives (hereinafter referred to as HDDs) and optical disk drives (hereinafter referred to as ODDs) are widely used as storage devices, and are indispensable storage devices in current computer systems and the like.

  As an interface for data transmission between the host and the HDD or ODD, a parallel transfer type SCSI interface, an ATA interface, or the like is generally used. In particular, the ATA interface is used in many computers from the viewpoint of improved interface function and low cost. The demand for the data transfer rate of the ATA interface has become increasingly severe due to the demand for improved recording density and performance of the storage medium.

  For this reason, an ATA interface by serial transmission has been proposed instead of the conventional transmission system by parallel transmission. The serial ATA standard is being developed by the serial ATA working group and is described in detail in the specification document.

  On the other hand, various power management techniques for reducing power consumption in the interface device have been proposed. In serial ATA, two modes have been proposed depending on the time required for recovery, and a partial with a short recovery time and a slumber with a long recovery time have been proposed.

  In addition, according to a certain prior art, in a serial interface device such as serial ATA, a command from the host is received so as to reduce power consumption of the serial interface unit, and after the command execution is completed or during the command execution, To a power save mode by performing a specific handshake (see Patent Document 1).

Furthermore, according to another prior art, the scrambler is stopped by entering a specific pattern from the specific pattern generation circuit and notifying the unintentional state so as to reduce the power consumption in the state of the transmission signal, and shift to the power save mode (See Patent Document 2).
JP 2006-99665 A JP 62-268231 A

  By the way, in the technique such as Patent Document 1, a specific sequence by handshaking is required to shift to the power save mode, and the shift to the power save mode can be performed in connection with a communication partner that does not support power management. Therefore, power consumption cannot be reduced. Further, since a specific sequence by handshaking is required to perform power management, a long time is required.

  In addition, in the technique such as Patent Document 2, a pattern with a low appearance frequency is always generated to stop the scrambler / descrambler and subsequent circuits, and the pattern is reliably transmitted to the receiving circuit of the counterpart device. It is necessary to be recognized. Therefore, if the specific pattern cannot be correctly recognized by the other device by reducing the characteristics of the transmitted signal to be transmitted, it will be interpreted as a randomized pattern sequence and the scrambler / descrambler and subsequent circuits will operate and malfunction. Cause.

  The present invention solves the problems in the prior art as described above, and an object thereof is to reduce the power consumption of a serial interface circuit.

  In order to solve the above problem, a serial interface circuit according to claim 1 of the present invention includes a transmitter circuit or a receiver circuit constituting a physical layer, and a protocol control circuit for controlling an interface protocol and encoding / decoding data. And a power save control circuit for controlling power save of the circuit group, and either the transmitter circuit or the receiver circuit has a structure for adjusting electrical characteristics, and the transmitter of the protocol control circuit The power saving control circuit detects a specific pattern declaring that the output to the circuit enters an involuntary communication state with respect to the connected counterpart device, so that the electrical power of the physical layer can be transmitted at the time of data transmission after the specific pattern. To change the characteristic to a value suitable for low power consumption Characterized in that it has.

  The serial interface circuit according to claim 2 of the present invention is the serial interface circuit according to claim 1, wherein the power save control circuit is connected to an output of the protocol control circuit with respect to the transmitter circuit. And a function of detecting a specific pattern declaring return to a significant communication state, and a function of returning the electrical characteristics of the circuits constituting the physical layer to characteristics suitable for normal operation.

  According to a third aspect of the present invention, there is provided a serial interface circuit comprising a transmitter circuit or a receiver circuit constituting a physical layer, a protocol control circuit for controlling an interface protocol and encoding / decoding data, and the circuit group. A power save control circuit that controls the power save of the protocol control circuit, and the power save control circuit has a function of monitoring the sequence state of the protocol control circuit, and detects that the state shifts to a specific sequence state And a function of selectively stopping a part of the protocol control circuit.

  A serial interface circuit according to a fourth aspect of the present invention is the serial interface circuit according to the third aspect, wherein the power save control circuit restores the protocol control circuit by detecting that the power save control circuit has returned from a specific sequence. A serial interface circuit characterized by having a function of

  According to a fifth aspect of the present invention, there is provided a serial interface circuit comprising a transmitter circuit or a receiver circuit constituting a physical layer, a protocol control circuit for controlling an interface protocol and encoding / decoding data, and the circuit group. A power save control circuit for controlling the power save of the protocol, and the power save control circuit has a function of monitoring a sequence state of the protocol control circuit, and further has an electrical characteristic of a circuit constituting the physical layer And a function of adjusting the electrical characteristics by the power save control circuit when it is detected that the state shifts to a specific sequence state.

  The serial interface circuit according to a sixth aspect of the present invention is the serial interface circuit according to the fifth aspect, wherein the power save control circuit configures the physical layer by detecting that it has returned from a specific sequence. It has a function of returning the electrical characteristics of the circuit to normal operation.

  According to a seventh aspect of the present invention, there is provided a serial interface circuit having the functions described in the third and fifth aspects.

  An integrated circuit according to an eighth aspect of the present invention includes a serial interface circuit having the characteristics described in any one of the first to seventh aspects.

  An electronic apparatus according to a ninth aspect of the present invention uses the integrated circuit according to the eighth aspect.

  According to a tenth aspect of the present invention, there is provided an electronic apparatus including a serial interface circuit configured by a plurality of parts of the feature according to any one of the first to seventh aspects.

  According to the present invention, even in connection with a device that does not support the power saving mode according to the prior art of Patent Document 1, it is possible to minimize power consumption as in the power saving mode. Further, it is not necessary to perform handshake to shift to the power save mode, and it does not require time for blocking communication.

  Further, even in the involuntary communication state according to the prior art of Patent Document 2, it is possible to minimize power consumption by reducing the signal characteristics of the transmission signal.

  Hereinafter, as an example of an embodiment of the present invention, an ODD having a serial ATA interface will be described as an example with reference to the drawings.

  FIG. 1 is a block diagram showing a serial interface circuit according to an embodiment of the present invention. Hereinafter, each block will be described.

  In FIG. 1, reference numeral 1 denotes a serial interface circuit according to an embodiment of the present invention, which includes a physical layer 2, a protocol control circuit 3, and a power save control circuit 4.

  The physical layer 2 converts the serial data signal TxData on the transmission side into differential signals Tx +, Tx− and outputs them, and the transmitter circuit 5 capable of adjusting the electrical characteristics, and the received differential signals Rx +, Rx−. Is converted to a serial data signal RxData on the receiving side and output to perform adjustment of electrical characteristics, and is connected to the protocol control circuit 3 via these serial data signals. Yes.

  The protocol control circuit 3 includes a deserializer 12 that converts RxData that is serial data from the receiver circuit 6 into parallel data, a decoding circuit 13 that performs 10b / 8b conversion, and an undecoder that performs decoding on the frame. The scramble circuit 14 includes a serializer 9 that converts parallel data into TxData, which is serial data, an encoder circuit 10 that performs 8b / 10b conversion, and a scramble circuit 11 that encodes a frame. And a frame payload called FIS (Frame Information Structure) for exchanging data commands with the host, and a link layer 7 for controlling control characters called primitives for controlling transmission / reception and communication of frames. And the structure in the received FIS The analysis of the elements has a transport layer 8 which performs signal conversion from the physical layer 2, control is performed on a serial interface.

  The power save control circuit 4 is a control state of the link layer 7 in the protocol control circuit 3, a control state of the transport layer 8 in the protocol control circuit 3, or a data pattern output from the protocol control circuit 3 or the transmitter circuit 5. Has a function of selectively stopping the protocol control circuit 3 or electrically adjusting the physical layer 2, and is connected to the physical layer 2 and the protocol control circuit 3. ing.

  The operation of the power saving method as the serial ATA interface in the serial interface circuit 1 configured as described above will be described.

  First, a transmission method using serial ATA will be described. FIG. 2 shows a startup sequence between the host and the ODD, and FIG. 3 is a diagram for explaining a configuration example of a transmission signal in the serial ATA transmission sequence.

  As shown in FIG. 3, the transmission signal is composed of a frame and a primitive. The frame is composed of a number of D words (Double Word: 32 bits). A frame usually starts with an SOF (Start Of Frame) primitive, followed by a user payload called FIS (Frame Information Structure), and ends with a CRC, EOF (End Of Frame). If the FIS is continuous, several flow control primitives such as HOLD primitives, HOLDA primitives, etc. are allowed between SOF and EOF for the purpose of adjusting the speed of the data flow.

  FIG. 2 shows a power-on sequence between the host and the device. The host issues an initialization signal COMRESET to the device, and then issues an initialization signal COMINIT from the device to the host. Communication is established by issuing an activation signal COMWAKE in the burst signal format to the device, the device issuing COMWAKE, and receiving an ALIGN primitive from the host. When serial communication is established with the host, data and commands are exchanged by FIS, and primitive exchange (primitive handshake) with the host to maintain serial communication with the host. I do. Therefore, even when there is no exchange of user data and commands for data writing or reading with the host, the primitive is always in operation to exchange data, and consumes power.

  The primitive is composed of 4 bytes as shown in FIG. 4, and is composed of K28.5 or K28.3 called a control character in byte 0, which is the first byte, and 3-byte data. The primitives include ALIGN (Phy layer control), CONT (Continue repeating previous primitive), DMAT (DMA terminate), EOF (End of frame), HOLD (Hold data transmission), HOLDA (Hold acknowledge), PMACK (Power management). acknowledge), PMNAK (Power management denial), PMREQ_P (Power management request to Partial), PMREQ_S (Power management request to Slumber), R_ERR (Reception error), R_IP (Reception in Progress), R_OK (Reception with no error), R_RDY (Receiver ready), SOF (Start of frame), SYNC (Synchronization), WTRM (Wait for frame termination), and X_RDY (Transmission data ready).

  Next, the operation of the power saving method according to the present invention will be described. First, when communicating with a partner device during transmission of meaningless data to the partner after sending the CONT primitive to the transmission transmission line, the power save control circuit 4 transmits the protocol control circuit 3 transmitter. In order to reduce power consumption by detecting that the output to the circuit 5 is a CONT primitive, the power save control circuit 4 has the amplitude, slew rate, or transmission frequency of the output characteristic of the transmitter circuit 5 with respect to the physical layer 2. The power consumption is reduced by reducing the power consumption or the combination within the range within the standard to the minimum value that the other device can determine as a signal.

  In addition, the protocol control circuit 3 detects that the output to the transmitter circuit 5 is K28.5 or K28.3 when data having no meaning is being transmitted to the other party after the CONT primitive is transmitted. Thus, in order to return to the normal state, the power save control circuit 4 can return the output characteristics of the transmitter circuit 5 to the normal state with respect to the physical layer 2 to return the transmission transmission line to the normal state.

  Further, the power save control circuit 4 detects that the sequence of the protocol control circuit 3 is in the FIS transmission standby state in response to the command from the host or the HOLD primitive transmission state during the FIS transfer, and the deserializer 12 and the decoding circuit 13. Stop supply of the clock signal or power to the unscramble circuit 14 and the receiver circuit 6 of the physical layer 2 to reduce power consumption.

  In addition, the power save control circuit 4 detects that the sequence of the protocol control circuit 3 starts the FIS transmission in response to the command from the host, the release of the HOLD primitive transmission state during the FIS transmission, etc., and the deserializer 12, the decoding circuit 13, and the unscramble By returning the circuit 14 and the receiver circuit 6 of the physical layer 2 to the normal state, the transmission transmission line can be returned to the normal state.

  As described above, unnecessary power consumption can be suppressed, and the power save control circuit 4 keeps operating even in a state where power consumption is suppressed, so that the clock is restored when returning to normal operation. It is possible to resume the supply of signals or power.

  5 is a block diagram of the electronic device 16 using the integrated circuit 17 incorporating the serial interface circuit 18 according to the embodiment of the present invention. FIG. 6 shows a plurality of serial interface circuits according to the embodiment of the present invention. 3 is a block diagram of an electronic device 23 constituted by parts 25, 27, and 29. FIG.

  The power saving method of the serial interface circuit according to the present invention is to reduce the power consumption by setting the serial interface circuit to the power save mode in a steady state without interrupting the communication sequence or the communication partner. Further, the transmission signal characteristics can be lowered even in an involuntary state, which is useful for reducing the power consumption of the serial interface circuit.

1 is a block diagram showing a schematic configuration of a serial interface circuit according to an embodiment of the present invention. It is the figure which showed the outline of the initialization sequence in serial ATA. It is the figure which showed the structural example of the transmission signal in serial ATA. It is the figure which showed the structure of the primitive in serial ATA. 1 is a block diagram showing a schematic configuration of an electronic apparatus having an integrated circuit incorporating a serial interface circuit according to an embodiment of the present invention. It is a block diagram which shows schematic structure of the electronic device which comprised the serial interface circuit with the some components which concern on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Serial interface circuit 2 Physical layer 3 Protocol control circuit 4 Power save control circuit 5 Transmitter circuit 6 Receiver circuit 7 Link layer 8 Transport layer 9 Serializer 10 Encoding circuit 11 Scramble circuit 12 Deserializer 13 Decode circuit 14 Unscramble circuit 16 Used electronic device 17 Integrated circuit 18 using the present invention Serial interface circuit 19 Physical layer 20 Protocol control circuit 21 Power save control circuit 23 Electronic device 25 using the present invention Block 27 constituting the physical layer Constructing a power save control circuit Block 29 Blocks constituting the protocol control circuit

Claims (10)

A transmitter circuit or receiver circuit constituting the physical layer, a protocol control circuit for controlling interface protocol and data encoding / decoding, and a power saving control circuit for controlling power saving of the circuit group, In addition, either the transmitter circuit or the receiver circuit has a structure for adjusting electrical characteristics,
Data transmission after the specific pattern is detected by the power save control circuit detecting a specific pattern in which the output of the protocol control circuit to the transmitter circuit declares that the connected device is in an involuntary communication state. A serial interface circuit characterized by having a function of changing the electrical characteristics of the physical layer to a value suitable for low power consumption. The serial interface circuit according to claim 1,
The power save control circuit has a function of detecting a specific pattern in which an output of the protocol control circuit to the transmitter circuit is declared to return to a significant communication state with respect to a connected counterpart device, and the physical layer A serial interface circuit characterized by having a function of returning electrical characteristics of a circuit to a characteristic suitable for normal operation. A transmitter circuit or receiver circuit constituting the physical layer, a protocol control circuit for controlling interface protocol and data encoding / decoding, and a power saving control circuit for controlling power saving of the circuit group,
The power save control circuit has a function of monitoring a sequence state of the protocol control circuit, and a function of selectively stopping a part of the protocol control circuit when it is detected that a transition to a specific sequence state is detected. A serial interface circuit comprising: The serial interface circuit according to claim 3,
The power saving control circuit has a function of returning the protocol control circuit by detecting return from a specific sequence. A transmitter circuit or receiver circuit constituting the physical layer, a protocol control circuit for controlling interface protocol and data encoding / decoding, and a power saving control circuit for controlling power saving of the circuit group,
The power save control circuit has a function of monitoring a sequence state of the protocol control circuit, and has a structure for adjusting electrical characteristics of a circuit constituting the physical layer,
A serial interface circuit having a function of adjusting the electrical characteristics by the power save control circuit when it is detected that the state shifts to a specific sequence state. The serial interface circuit according to claim 5,
The serial interface circuit, wherein the power save control circuit has a function of returning the electrical characteristics of the circuits constituting the physical layer to normal operation by detecting the return from a specific sequence.   6. A serial interface circuit having the functions according to claim 3 and claim 5.   An integrated circuit including a serial interface circuit, wherein the integrated circuit has the characteristics according to claim 1.   An electronic device using the integrated circuit according to claim 8.   An electronic apparatus having a serial interface circuit in which the feature according to claim 1 is configured by a plurality of parts.

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