TW201435118A - Sputtering target, oxide semiconductor thin film, and production methods for both - Google Patents

Sputtering target, oxide semiconductor thin film, and production methods for both Download PDF

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TW201435118A
TW201435118A TW103101536A TW103101536A TW201435118A TW 201435118 A TW201435118 A TW 201435118A TW 103101536 A TW103101536 A TW 103101536A TW 103101536 A TW103101536 A TW 103101536A TW 201435118 A TW201435118 A TW 201435118A
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thin film
oxide semiconductor
semiconductor thin
sputtering
oxide
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TWI607104B (en
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Nozomi Tajima
Kazuaki Ebata
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Idemitsu Kosan Co
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/3407Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08Oxides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08Oxides
    • C23C14/086Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02565Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation

Abstract

A sputtering target comprising an oxide containing indium (In), tin (Sn), zinc (Zn), and magnesium (Mg), and including a homologous structure compound indicate by In2O3(ZnO)m (m being 0.1-20) and a spinel structure compound indicated by Zn2SnO4.

Description

濺鍍靶、氧化物半導體薄膜及彼等之製造方法 Sputtering target, oxide semiconductor film, and manufacturing method thereof

本發明係關於一種氧化物半導體或透明導電膜等氧化物薄膜製作用之濺鍍靶、使用該靶製作之薄膜、包含該薄膜之薄膜電晶體及該等之製造方法。 The present invention relates to a sputtering target for producing an oxide thin film such as an oxide semiconductor or a transparent conductive film, a film produced using the target, a thin film transistor including the film, and the like.

薄膜電晶體(TFT,thin film Transistor)等場效型電晶體廣泛用作半導體記憶體積體電路之單位電子元件、高頻信號放大元件、液晶驅動用元件等,係當前實用最多之電子器件。其中,隨著近年來之顯示裝置之飛速發展,於液晶顯示裝置(LCD,Liquid-crystal display)、電致發光顯示裝置(EL,electroluminescence,電致發光)、場發射顯示器(FED,field emission display)等各種顯示裝置中,大多使用TFT作為對顯示元件施加驅動電壓而使顯示裝置驅動之開關元件。 A field effect transistor such as a thin film transistor (TFT) is widely used as a unit electronic component of a semiconductor memory bulk circuit, a high frequency signal amplifying element, a liquid crystal driving element, etc., and is currently the most practical electronic device. Among them, with the rapid development of display devices in recent years, liquid crystal display devices (LCD), electroluminescence display devices (EL, electroluminescence), field emission displays (FED, field emission display) Among various display devices, a TFT is often used as a switching element that applies a driving voltage to a display element to drive a display device.

作為場效型電晶體之主要構件即半導體層(通道層)之材料,最廣泛使用矽半導體化合物。通常,於需要高速動作之高頻放大元件或積體電路用元件等使用單晶矽。另一方面,於液晶驅動用元件等,因大面積化之要求而使用非晶質性矽半導體(非晶矽)。 As a material of a semiconductor layer (channel layer) which is a main component of a field effect type transistor, a germanium semiconductor compound is most widely used. Usually, a single crystal germanium is used for a high frequency amplifying element or an integrated circuit element which requires high speed operation. On the other hand, an amorphous germanium semiconductor (amorphous germanium) is used for a liquid crystal driving element or the like due to a large area.

非晶矽之薄膜雖然可於相對低溫下形成,但與晶體性薄膜相比,開關速度較慢,故而於驅動顯示裝置之開關元件時,存在無法追隨於高速動態畫面之顯示之情形。具體而言,於解像度為VGA(Video Graphics Array,視頻圖形陣列)之液晶電視中,可使用移動度為0.5~1cm2/Vs之非晶矽,若解像度成為SXGA(Super Extended Graphics Array,超級擴展圖形陣列)、UXGA(Ultra Extended Graphics Array,極速擴展圖形陣列)、QXGA(Quantum Extended Graphics Array,量子擴展圖形陣列)或其以上,則要求2cm2/Vs以上之移動度。另外,若為了提昇畫質而提高驅動頻率,則需要更高之移動度。 Although the film of amorphous germanium can be formed at a relatively low temperature, the switching speed is slower than that of the crystalline thin film. Therefore, when the switching element of the display device is driven, there is a case where the display of the high-speed dynamic picture cannot be followed. Specifically, in a liquid crystal television having a resolution of VGA (Video Graphics Array), an amorphous germanium having a mobility of 0.5 to 1 cm 2 /Vs can be used, and if the resolution is SXGA (Super Extended Graphics Array) A graphics array), a UXGA (Ultra Extended Graphics Array), a QXGA (Quantum Extended Graphics Array), or the like, requires a mobility of 2 cm 2 /Vs or more. In addition, if the driving frequency is increased in order to improve the image quality, a higher degree of mobility is required.

另一方面,晶體性之矽系薄膜雖然移動度較高,但存在製造時需要很大之能量及步驟數等問題、或大面積化較為困難之問題。例如,於使矽系薄膜晶體化時,需要800℃以上之高溫或使用昂貴之設備之雷射退火。另外,晶體性之矽系薄膜由於通常將TFT之元件構成限定於頂閘極構成,故而掩膜片數之削減等成本降低較為困難。 On the other hand, although the crystalline ruthenium-based film has a high degree of mobility, it has a problem that it requires a large amount of energy and the number of steps at the time of production, or a large area is difficult. For example, in order to crystallize a lanthanide film, a high temperature of 800 ° C or higher or a laser annealing using an expensive apparatus is required. Further, since the crystalline ruthenium-based film is generally configured to limit the element configuration of the TFT to the top gate, it is difficult to reduce the cost of the number of masks.

為了解決上述問題,對使用包含氧化銦、氧化鋅及氧化鎵之氧化物半導體膜之薄膜電晶體進行了研究。通常,氧化物半導體薄膜之製作係藉由使用包含氧化物燒結體之靶(濺鍍靶)之濺鍍而進行。 In order to solve the above problems, a thin film transistor using an oxide semiconductor film containing indium oxide, zinc oxide, and gallium oxide has been studied. Generally, the production of an oxide semiconductor thin film is performed by sputtering using a target (sputter target) containing an oxide sintered body.

例如,已知包含顯示通式In2Ga2ZnO7、InGaZnO4表示之同源晶體結構之化合物之靶(專利文獻1、2及3)。 For example, a target containing a compound exhibiting a homologous crystal structure represented by the general formulas In 2 Ga 2 ZnO 7 and InGaZnO 4 is known (Patent Documents 1, 2, and 3).

然而,為了提高該靶之燒結密度(相對密度),必需於氧化性環境中進行燒結,於該情形時,為降低靶之電阻而必需於燒結後進行高溫下之還原處理。另外,若長時間使用靶,則存在如下等問題:所獲得之膜之特性或成膜速度變化較大,產生因燒結時異常成長之InGaZnO4或In2Ga2ZnO7所致之異常放電,及成膜時產生較多微粒。若頻繁地引起異常放電,則電漿放電狀態變得不穩定,無法進行穩定之成膜,對膜特性造成不良影響。 However, in order to increase the sintered density (relative density) of the target, it is necessary to perform sintering in an oxidizing atmosphere. In this case, in order to lower the electric resistance of the target, it is necessary to carry out a reduction treatment at a high temperature after sintering. Further, when the target is used for a long period of time, there is a problem that the characteristics of the obtained film or the film formation rate vary greatly, and abnormal discharge due to abnormal growth of InGaZnO 4 or In 2 Ga 2 ZnO 7 during sintering occurs. And when the film is formed, more particles are generated. When the abnormal discharge is frequently caused, the plasma discharge state becomes unstable, and stable film formation cannot be performed, which adversely affects the film characteristics.

另一方面,亦提出有使用不含鎵而含有氧化銦及氧化鋅之非晶質氧化物半導體膜之薄膜電晶體(專利文獻4)。 On the other hand, a thin film transistor using an amorphous oxide semiconductor film containing no indium oxide and containing zinc oxide has been proposed (Patent Document 4).

然而,若不提高成膜時之氧分壓,則存在無法實現TFT之常斷開動作之問題。 However, if the partial pressure of oxygen at the time of film formation is not increased, there is a problem that the normally-off operation of the TFT cannot be achieved.

另外,對於以氧化錫作為主成分之In2O3-SnO2-ZnO系氧化物中包 含Ta、Y或Si等添加元素之光資訊記錄媒體之保護層用濺鍍靶進行了研究(專利文獻5及6)。 In addition, a sputtering target for a protective layer of an optical information recording medium containing an additive element such as Ta, Y or Si in an In 2 O 3 -SnO 2 -ZnO-based oxide containing tin oxide as a main component has been studied (Patent Literature) 5 and 6).

然而,該等靶並非用於氧化物半導體,另外,存在容易形成絕緣性物質之凝集體,電阻值變高,或者容易引起異常放電之問題。 However, these targets are not used for an oxide semiconductor, and there is a problem that an aggregate of an insulating substance is easily formed, a resistance value is high, or an abnormal discharge is likely to occur.

先前技術文獻 Prior technical literature 專利文獻 Patent literature

專利文獻1:日本專利特開平8-245220號公報 Patent Document 1: Japanese Patent Laid-Open No. Hei 8-245220

專利文獻2:日本專利特開2007-73312號公報 Patent Document 2: Japanese Patent Laid-Open Publication No. 2007-73312

專利文獻3:國際公開第2009/084537號公報 Patent Document 3: International Publication No. 2009/084537

專利文獻4:國際公開第2005/088726號公報 Patent Document 4: International Publication No. 2005/088726

專利文獻5:國際公開第2005/078152號公報 Patent Document 5: International Publication No. 2005/078152

專利文獻6:國際公開第2005/078153號公報 Patent Document 6: International Publication No. 2005/078153

本發明之目的在於提供一種包含含有銦元素(In)、錫元素(Sn)、鋅元素(Zn)及鎂元素(Mg)之氧化物,且可實現具有較高之移動度及較高之可靠性之TFT之濺鍍靶。 An object of the present invention is to provide an oxide containing an indium element (In), a tin element (Sn), a zinc element (Zn), and a magnesium element (Mg), and can achieve high mobility and high reliability. The sputtering target of the TFT.

進而,本發明之目的在於提供一種可藉由後通道蝕刻法而以較高之生產性製造具有較高之移動度及較高之可靠性之TFT之濺鍍靶。 Further, it is an object of the present invention to provide a sputtering target which can produce a TFT having high mobility and high reliability with high productivity by a back channel etching method.

根據本發明,可提供以下之濺鍍靶等。 According to the present invention, the following sputtering targets and the like can be provided.

1.一種濺鍍靶,其包含含有氧化物,且以In2O3(ZnO)m(m為0.1~20)表示之同源結構化合物、及以Zn­2SnO4表示之尖晶石結構化合物,該氧化物含有銦元素(In)、錫元素(Sn)、鋅元素(Zn)及鎂元素(Mg)。 A sputtering target comprising a homologous structural compound containing an oxide and having In 2 O 3 (ZnO) m (m is 0.1 to 20), and a spinel structure represented by Zn­ 2 SnO 4 A compound containing an indium element (In), a tin element (Sn), a zinc element (Zn), and a magnesium element (Mg).

2.如上述1之濺鍍靶,其中上述銦元素、錫元素、鋅元素及鎂元素之原子比滿足下述式(1)~(4)。 2. The sputtering target according to the above 1, wherein the atomic ratio of the indium element, the tin element, the zinc element, and the magnesium element satisfies the following formulas (1) to (4).

0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1) 0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1)

0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2) 0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2)

0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3) 0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3)

0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4) 0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4)

(式中,In、Sn、Zn及Mg分別表示濺鍍靶中之各元素之原子比) (wherein, In, Sn, Zn, and Mg represent the atomic ratios of the respective elements in the sputtering target, respectively)

3.如上述1或2之濺鍍靶,其中相對密度為97%以上,體比電阻為10mΩcm以下。 3. The sputtering target according to 1 or 2 above, wherein the relative density is 97% or more and the volume specific resistance is 10 m?cm or less.

4.一種如上述1至3中任一項之濺鍍靶之製造方法,其包括如下步驟:於300℃~500℃之溫度範圍內以2℃/分鐘鐘以下之升溫速度使成形體升溫,且以1200℃~1650℃保持10~5o小時而對上述成形體進行燒結。 4. The method for producing a sputtering target according to any one of the above 1 to 3, comprising the step of heating the molded body at a temperature increase rate of 2 ° C /min or less in a temperature range of 300 ° C to 500 ° C. The formed body was sintered by holding it at 1200 ° C to 1650 ° C for 10 to 5 hours.

5.一種氧化物半導體薄膜,其係使用如上述1至3中任一項之濺鍍靶且藉由濺鍍法進行成膜而成。 An oxide semiconductor thin film formed by sputtering using a sputtering target according to any one of the above 1 to 3.

6.如上述5之氧化物半導體薄膜,其不溶於磷酸系蝕刻液,且可溶於草酸系蝕刻液。 6. The oxide semiconductor thin film according to the above 5, which is insoluble in the phosphoric acid-based etching liquid and soluble in the oxalic acid-based etching liquid.

7.如上述6之氧化物半導體薄膜,其中利用上述磷酸系蝕刻液之於35℃之蝕刻速度為10nm/分鐘以下,且利用上述草酸蝕刻液之於35℃之蝕刻速度為20nm/分鐘以上。 7. The oxide semiconductor thin film according to the above 6, wherein the etching rate of the phosphoric acid-based etching solution at 35 ° C is 10 nm/min or less, and the etching rate of the oxalic acid etching solution at 35 ° C is 20 nm/min or more.

8.一種氧化物半導體薄膜之製造方法,其係於含有選自水蒸氣、氧氣及一氧化二氮氣體中之1種以上及稀有氣體之混合氣體之環境下,使用如上述1至3中任一項之濺鍍靶並利用濺鍍法進行成膜。 A method for producing an oxide semiconductor thin film, which is used in an environment containing a mixed gas of one or more selected from the group consisting of water vapor, oxygen, and nitrous oxide gas and a rare gas, and is used as described in the above 1 to 3 A sputtering target is formed by sputtering.

9.如上述8之氧化物半導體薄膜之製造方法,其於至少含有水蒸氣及稀有氣體之混合氣體的環境下進行上述氧化物半導體薄膜之成膜。 9. The method for producing an oxide semiconductor thin film according to the above 8, wherein the oxide semiconductor thin film is formed in an atmosphere containing at least a mixed gas of water vapor and a rare gas.

10.如上述8或9之氧化物半導體薄膜之製造方法,其中上述混合氣體中所含之水蒸氣之比率以分壓比計為0.1%~25%。 10. The method for producing an oxide semiconductor thin film according to the above 8 or 9, wherein the ratio of the water vapor contained in the mixed gas is 0.1% to 25% in terms of a partial pressure ratio.

11.如上述8至10中任一項之氧化物半導體薄膜之製造方法,其中 上述混合氣體中所含之氧氣之比率以分壓比計為0.1%~30%。 11. The method of producing an oxide semiconductor thin film according to any one of the above 8 to 10, wherein The ratio of the oxygen contained in the mixed gas is 0.1% to 30% in terms of a partial pressure ratio.

12.如上述8至11中任一項之氧化物半導體薄膜之製造方法,其中藉由如下濺鍍方法而進行上述氧化物半導體薄膜之成膜,該濺鍍方法係將基板依序搬送至與隔開特定間隔而並排設置於真空腔室內之3片以上之靶對向之位置,於自交流電源對上述各靶交替施加負電位及正電位之情形時,一面將來自上述交流電源之輸出之至少1者分支而於連接之2片以上之靶間進行施加電位之靶的切換,一面於靶上產生電漿而於基板表面成膜。 12. The method for producing an oxide semiconductor thin film according to any one of the above 8 to 11, wherein the film formation of the oxide semiconductor film is carried out by a sputtering method in which the substrate is sequentially transferred to and The position of the three or more targets placed side by side in the vacuum chamber at a predetermined interval is opposite to each other, and when the negative potential and the positive potential are alternately applied to the respective targets from the AC power source, the output from the AC power source is turned on. At least one of the branches is switched between the two or more connected targets, and a plasma is generated on the target to form a film on the surface of the substrate.

13.如上述12之氧化物半導體薄膜之製造方法,其中上述交流電源之交流功率密度為3W/cm2以上且20W/cm2以下。 13. The method for producing an oxide semiconductor thin film according to the above 12, wherein the AC power source has an AC power density of 3 W/cm 2 or more and 20 W/cm 2 or less.

14.如上述12或13之氧化物半導體薄膜之製造方法,其中上述交流電源之頻率為10kHz~1MHz。 14. The method of producing an oxide semiconductor thin film according to the above 12 or 13, wherein the frequency of the alternating current power source is 10 kHz to 1 MHz.

15.一種薄膜電晶體,其具有如上述5至7中任一項之氧化物半導體薄膜作為通道層。 A thin film transistor having the oxide semiconductor film according to any one of the above 5 to 7 as a channel layer.

16.如上述15之薄膜電晶體,其中場效移動度為10cm2/Vs以上。 16. The thin film transistor according to the above 15, wherein the field effect mobility is 10 cm 2 /Vs or more.

17.一種薄膜電晶體,其於如上述5至7中任一項之氧化物半導體薄膜上具有至少含有SiNx(x為任意數)之保護膜。 A thin film transistor having a protective film containing at least SiN x (x is an arbitrary number) on the oxide semiconductor thin film according to any one of the above 5 to 7.

18.一種薄膜電晶體之製造方法,其係使用如上述5至7中任一項之氧化物半導體薄膜作為半導體活性層之薄膜電晶體之製造方法,且包括如下步驟,即不於上述半導體薄膜上積層蝕刻終止層,而使用不同之蝕刻液使上述半導體薄膜及電極圖案化,且於使電極圖案化時蝕刻液直接接觸於上述半導體薄膜。 A method of producing a thin film transistor, which is the method for producing a thin film transistor using the oxide semiconductor thin film according to any one of the above 5 to 7 as a semiconductor active layer, and comprising the step of not using the semiconductor thin film The etch stop layer is laminated, and the semiconductor thin film and the electrode are patterned using different etching liquids, and the etching liquid directly contacts the semiconductor thin film when the electrodes are patterned.

19.一種顯示裝置,其具備如上述15至17中任一項之薄膜電晶體。 A display device comprising the thin film transistor according to any one of the above 15 to 17.

根據本發明,可提供一種包含含有銦元素(In)、錫元素(Sn)、鋅元素(Zn)及鎂元素(Mg)之氧化物,且可實現具有較高之移動度及較高 之可靠性的TFT之濺鍍靶。 According to the present invention, it is possible to provide an oxide containing an indium element (In), a tin element (Sn), a zinc element (Zn), and a magnesium element (Mg), and can achieve higher mobility and higher The reliability of the TFT sputtering target.

另外,可提供一種可藉由後通道蝕刻法而以較高之生產性製造具有較高之移動度及較高之可靠性的TFT之濺鍍靶。 In addition, it is possible to provide a sputtering target which can produce a TFT having high mobility and high reliability with high productivity by a back channel etching method.

17a‧‧‧交流電源 17a‧‧‧AC power supply

17b‧‧‧交流電源 17b‧‧‧AC power supply

17c‧‧‧交流電源 17c‧‧‧AC power supply

31a‧‧‧靶 31a‧‧ Target

31b‧‧‧靶 31b‧‧‧ target

31c‧‧‧靶 31c‧‧ Target

31d‧‧‧靶 31d‧‧‧ target

31e‧‧‧靶 31e‧‧ Target

31f‧‧‧靶 31f‧‧‧ target

40a‧‧‧磁場形成機構 40a‧‧‧Magnetic field forming mechanism

40b‧‧‧磁場形成機構 40b‧‧‧Magnetic field forming mechanism

40c‧‧‧磁場形成機構 40c‧‧‧Magnetic field forming mechanism

40d‧‧‧磁場形成機構 40d‧‧‧Magnetic field forming mechanism

40e‧‧‧磁場形成機構 40e‧‧‧Magnetic field forming mechanism

40f‧‧‧磁場形成機構 40f‧‧‧Magnetic field forming mechanism

圖1係實施例1中所獲得之燒結體之X射線圖表。 Fig. 1 is an X-ray chart of the sintered body obtained in Example 1.

圖2係實施例2中所獲得之燒結體之X射線圖表。 2 is an X-ray chart of the sintered body obtained in Example 2.

圖3係實施例3中所獲得之燒結體之X射線圖表。 Fig. 3 is an X-ray chart of the sintered body obtained in Example 3.

圖4係表示本發明之一實施形態中所使用之濺鍍裝置之圖。 Fig. 4 is a view showing a sputtering apparatus used in an embodiment of the present invention.

以下,對本發明之濺鍍靶、氧化物薄膜、薄膜電晶體、顯示裝置及其等之製造方法進行詳細地說明,但本發明並不限定於下述實施態樣及實施例。 Hereinafter, the sputtering target, the oxide film, the thin film transistor, the display device, and the like of the present invention will be described in detail, but the present invention is not limited to the following embodiments and examples.

本發明之濺鍍靶包含含有氧化物,且以In2O3(ZnO)m(m為0.1~20)表示之同源結構化合物、及以Zn­2SnO4表示之尖晶石結構化合物,該氧化物含有銦元素(In)、錫元素(Sn)、鋅元素(Zn)及鎂元素(Mg)。 The sputtering target of the present invention comprises a homologous structural compound containing an oxide and having In 2 O 3 (ZnO) m (m is 0.1 to 20), and a spinel structure compound represented by Zn­ 2 SnO 4 , The oxide contains an indium element (In), a tin element (Sn), a zinc element (Zn), and a magnesium element (Mg).

同源結構化合物及尖晶石結構化合物可藉由X射線折射而確認其是否存在。 The homologous structural compound and the spinel structure compound can be confirmed by X-ray refraction.

所謂同源結構,係指包括具有使不同物質之晶體層重疊有若干層之長週期的「自然超晶格」結構之晶體結構。於晶體週期或各薄膜層之厚度為奈米程度之情形時,藉由其等各層之化學組成或層之厚度的組合而獲得與單一物質或均勻地混合各層而成之混晶之性質不同之固有特性。而且,同源相之晶體結構例如可根據將靶粉碎而得之粉末之X射線折射圖案與自組成比所設想的同源相之晶體結構X射線折射圖案一致之情況而確認。具體而言,可根據與自JCPDS(Joint Committee of Powder Diffraction Standards)卡或ICSD(Inorganic Crystal Structure Database)所獲得之同源相之晶體結構X射線折射圖案一致之情況而確認。 The term "homologous structure" refers to a crystal structure including a "natural superlattice" structure having a long period in which a plurality of layers of crystal layers of different substances are overlapped. In the case where the crystal period or the thickness of each film layer is in the degree of nanometer, the chemical composition of each layer or the combination of the thicknesses of the layers is used to obtain a property different from that of a single substance or a mixture of layers uniformly mixed. Inherent characteristics. Further, the crystal structure of the homologous phase can be confirmed, for example, by the fact that the X-ray refracting pattern of the powder obtained by pulverizing the target coincides with the crystal structure X-ray refracting pattern of the homologous phase assumed from the composition ratio. Specifically, it can be based on the JCPDS (Joint Committee of Powder Diffraction Standards) card or ICSD (Inorganic It was confirmed that the crystal structure X-ray refraction patterns of the homologous phases obtained by the Crystal Structure Database were identical.

關於尖晶石結構,對濺鍍靶進行X射線折射測定,結果觀察到尖晶石結構化合物之峰值,藉此可確認出尖晶石結構。 Regarding the spinel structure, X-ray refraction measurement was performed on the sputtering target, and as a result, the peak of the spinel structure compound was observed, whereby the spinel structure was confirmed.

對於尖晶石結構,於「西方固態化學入門」(講談社科技)中進行了詳細地記載,根據上述情況,尖晶石結構為如下所述之結構。 The spinel structure is described in detail in "Introduction to Western Solid State Chemistry" (Kodansha Technology). According to the above, the spinel structure is as follows.

尖晶石具有AB2O4之組成式,若根據A離子與B離子之配位狀態而分類,則可分成正尖晶石結構、逆尖晶石結構、兩者中間之結構。 The spinel has a composition formula of AB 2 O 4 , and if classified according to the coordination state of the A ion and the B ion, it can be classified into a spinel structure, a reverse spinel structure, and a structure in between.

正尖晶石具有於O2-所形成之立體面心形晶格之四面體間隙之八分之一中填充有A且於八面體間隙之二分之一中填充有B的結構。逆尖晶石結構具有於四面體間隙之八分之一中填充有B且於八面體間隙之二分之一中填充有A及B之結構。雖然通常為立方晶,但其中亦存在立方晶變形者。 The positive spinel has a structure in which one eighth of the tetrahedral gap of the three-dimensional surface-shaped lattice formed by O 2- is filled with A and one of the octahedral gaps is filled with B. The inverse spinel structure has a structure in which one-eighth of the tetrahedral gap is filled with B and one-half of the octahedral gap is filled with A and B. Although it is usually cubic crystal, there are also cubic crystal deformers.

另外,於尖晶石結構化合物中亦包括使晶體結構中之原子或離子之一部分由其他原子取代之取代型固溶體、及於晶格間位置加入有其他原子之侵入型固溶體。 Further, the spinel structure compound also includes a substituted solid solution in which one of atoms or ions in the crystal structure is substituted by another atom, and an intrusive solid solution in which other atoms are added at an intercrystalline position.

藉由包含以In2O3(ZnO)m(m為0.1~20)表示之同源結構化合物,可製成靶之相對密度容易提昇、比電阻亦容易降低、不易進行異常放電之靶。 By including a homologous structural compound represented by In 2 O 3 (ZnO) m (m is 0.1 to 20), it is possible to obtain a target in which the relative density of the target is easily increased, the specific resistance is also easily lowered, and abnormal discharge is difficult.

m例如為整數,較佳為0.1~10,更佳為0.5~7,進而佳為2~5。 m is, for example, an integer, preferably 0.1 to 10, more preferably 0.5 to 7, and further preferably 2 to 5.

另外,藉由包含以Zn­2SnO4表示之尖晶石結構化合物而使Mg元素固溶,即便Mg之含量較多,亦可防止靶中生成高電阻之MgO,藉此容易降低靶電阻,容易抑制異常放電。 In addition, by including a spinel structure compound represented by Zn­ 2 SnO 4 , the Mg element is solid-solved, and even if the content of Mg is large, it is possible to prevent the formation of high-resistance MgO in the target, thereby easily lowering the target resistance. It is easy to suppress abnormal discharge.

本發明之濺鍍靶較佳為各元素之原子比滿足下述式(1)~(4)。 In the sputtering target of the present invention, it is preferred that the atomic ratio of each element satisfies the following formulas (1) to (4).

0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1) 0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1)

0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2) 0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2)

0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3) 0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3)

0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4) 0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4)

(式中,In、Sn、Zn及Mg分別表示濺鍍靶中之各元素之原子比) (wherein, In, Sn, Zn, and Mg represent the atomic ratios of the respective elements in the sputtering target, respectively)

上述式(1)中,若In元素之量為0.05以上,則濺鍍靶之體電阻值容易變低,容易進行DC(Direct Current,直流)濺鍍。 In the above formula (1), when the amount of the In element is 0.05 or more, the bulk resistance value of the sputtering target is likely to be low, and DC (Direct Current) sputtering can be easily performed.

另一方面,若In元素之量為0.70以下,則使用該靶製作之薄膜之載子濃度不會變得過高,可用作半導體用薄膜。 On the other hand, when the amount of the In element is 0.70 or less, the carrier concentration of the film produced using the target does not become too high, and it can be used as a film for semiconductor.

根據以上,In之濃度較佳為0.05≦In/(In+Sn+Zn+Mg)≦0.70。更佳為In元素之量[In/(In+Sn+Zn+Mg)]為0.10~0.60。 From the above, the concentration of In is preferably 0.05 ≦ In / (In + Sn + Zn + Mg) ≦ 0.70. More preferably, the amount of In element [In/(In+Sn+Zn+Mg)] is 0.10 to 0.60.

上述式(2)中,若Sn元素之量為0.01以上,則靶之密度容易提昇,濺鍍靶之體電阻值容易降低。 In the above formula (2), when the amount of the Sn element is 0.01 or more, the density of the target is likely to increase, and the volume resistance of the sputtering target is likely to be lowered.

另一方面,若Sn元素之量為0.35以下,則成為異常放電之原因之SnO2不易於靶中析出。 On the other hand, when the amount of the Sn element is 0.35 or less, SnO 2 which is a cause of abnormal discharge is not easily precipitated in the target.

根據以上所述,Sn之濃度較佳為0.01≦Sn/(In+Sn+Zn+Mg)≦0.35。 According to the above, the concentration of Sn is preferably 0.01 ≦Sn / (In + Sn + Zn + Mg) ≦ 0.35.

Sn元素之量[Sn/(In+Sn+Zn+Mg)]更佳為0.03~0.35,進而佳為0.05~0.30。 The amount of Sn element [Sn/(In+Sn+Zn+Mg)] is more preferably 0.03 to 0.35, and further preferably 0.05 to 0.30.

上述式(3)中,若Zn元素之量為0.01以上,則靶密度容易提昇,且靶電阻亦容易變低。另一方面,若Zn元素之量為0.90以下,則成為異常放電之原因之ZnO不易於靶中析出。 In the above formula (3), when the amount of the Zn element is 0.01 or more, the target density is likely to increase, and the target resistance is also likely to be low. On the other hand, when the amount of the Zn element is 0.90 or less, ZnO which is a cause of abnormal discharge is not easily precipitated in the target.

根據以上所述,Zn之濃度較佳為0.01≦Zn/(In+Sn+Zn+Mg)≦0.90。 According to the above, the concentration of Zn is preferably 0.01 ≦ Zn / (In + Sn + Zn + Mg) ≦ 0.90.

Zn元素之量[Zn/(In+Sn+Zn+Mg)]更佳為0.03~0.85,進而佳為0.05~0.80。 The amount of Zn element [Zn/(In+Sn+Zn+Mg)] is preferably from 0.03 to 0.85, and more preferably from 0.05 to 0.80.

上述式(4)中,若Mg元素之量為0.01以上,則使用該靶製作之薄膜之載子濃度不易變高,容易顯示良好之半導體特性。 In the above formula (4), when the amount of the Mg element is 0.01 or more, the carrier concentration of the film produced using the target is not easily increased, and it is easy to exhibit good semiconductor characteristics.

另一方面,若Mg元素之量為0.30以下,則不易引起由MgO之單獨表現所導致的靶之高電阻化。 On the other hand, when the amount of the Mg element is 0.30 or less, it is less likely to cause a high resistance of the target due to the individual expression of MgO.

根據以上,Mg之濃度較佳為0.01≦Mg/(In+Sn+Zn+Mg)≦0.30。 From the above, the concentration of Mg is preferably 0.01 ≦Mg/(In+Sn+Zn+Mg) ≦0.30.

Mg元素之量[Mg/(In+Sn+Zn+Mg)]更佳為0.02~0.27,進而佳為0.02~0.25。 The amount of Mg element [Mg/(In+Sn+Zn+Mg)] is more preferably 0.02 to 0.27, and further preferably 0.02 to 0.25.

濺鍍靶所含之各元素之原子比可藉由感應耦合電漿發光分析裝置(ICP-AES,inductively coupled plasma-optical emission spectroscop,感應耦合電漿原子發射光譜儀)對所含元素進行定量分析而求出。 The atomic ratio of each element contained in the sputtering target can be quantitatively analyzed by an inductively coupled plasma-optical emission spectroscop (ICP-AES). Find out.

具體而言,若利用噴霧器使溶液試樣成為霧狀而導入至氬氣電漿(約6000~8000℃)中,則試樣中之元素吸收熱能而被激發,軌道電子自基態移至較高能階之軌道。該軌道電子歷經10-7~10-8秒左右移至更低能階之軌道。此時,作為光而放射能量差並發光。該光顯示元素固有之波長(光譜線),故而可藉由光譜線之有無而確認元素之存在(定性分析)。 Specifically, if the solution sample is sprayed into an argon plasma (about 6000 to 8000 ° C) by a sprayer, the element in the sample absorbs thermal energy and is excited, and the orbital electrons move from the ground state to a higher energy. The track of the order. The orbital electrons move to a lower energy orbit for about 10-7 to 10-8 seconds. At this time, the energy difference is emitted as light and emits light. This light shows the wavelength (spectral line) inherent to the element, so the presence of the element (qualitative analysis) can be confirmed by the presence or absence of the spectral line.

另外,各條光譜線之大小(發光強度)由於與試樣中之元素數成比例,故而可藉由與已知濃度之標準液比較而求出試樣濃度(定量分析)。 Further, since the size (emission intensity) of each spectral line is proportional to the number of elements in the sample, the sample concentration (quantitative analysis) can be obtained by comparison with a standard solution of a known concentration.

利用定性分析而特定所含之元素後,利用定量分析求出含量,根據其結果,可求出各元素之原子比。 After specifying the elements contained in the qualitative analysis, the content is determined by quantitative analysis, and based on the results, the atomic ratio of each element can be obtained.

如上所述,濺鍍靶所含之金屬元素實質上包含In、Sn、Zn及Mg,亦可於不損害本發明之效果之範圍內包含其他不可避免之雜質。 As described above, the metal element contained in the sputtering target substantially contains In, Sn, Zn, and Mg, and may contain other unavoidable impurities within a range that does not impair the effects of the present invention.

本發明中,所謂「實質上」,係指作為濺鍍靶之效果由上述以In、Sn、Zn及Mg所引起,或濺鍍靶之金屬元素之95重量%以上且100 重量%以下(較佳為98重量%以上且100重量%以下)為In、Sn、Zn及Mg。 In the present invention, the term "substantially" means that the effect as a sputtering target is caused by the above-mentioned In, Sn, Zn, and Mg, or 95% by weight or more of the metal element of the sputtering target. The weight% or less (preferably 98% by weight or more and 100% by weight or less) is In, Sn, Zn, and Mg.

本發明之濺鍍靶較佳為相對密度為97%以上。於大型基板(1G尺寸以上)提高濺鍍輸出而使氧化物半導體薄膜成膜之情形時,較佳為相對密度為97%以上。所謂相對密度,係指相對於自加權平均值算出之理論密度而相對性地算出之密度。自各原料之密度之加權平均值算出之密度為理論密度,將其設為100%。 The sputtering target of the present invention preferably has a relative density of 97% or more. When a large substrate (1G or more) is used to increase the sputtering output and the oxide semiconductor thin film is formed, the relative density is preferably 97% or more. The relative density refers to the density calculated relative to the theoretical density calculated from the weighted average. The density calculated from the weighted average of the densities of the respective raw materials is the theoretical density, which is set to 100%.

若相對密度為97%以上,則可保持穩定之濺鍍狀態。於利用大型基板提高濺鍍輸出而成膜之情形時,若相對密度未達97%,則存在靶表面黑化或產生異常放電之情況。相對密度更佳為98.5%以上,進而佳為99%以上。 If the relative density is 97% or more, a stable sputtering state can be maintained. When a large substrate is used to increase the sputtering output and the film is formed, if the relative density is less than 97%, the target surface may be blackened or abnormal discharge may occur. The relative density is more preferably 98.5% or more, and further preferably 99% or more.

相對密度可根據藉由阿基米德法測得之實測密度及理論密度而算出。相對密度較佳為100%以下。若為100%以下,則不易於燒結體中產生金屬粒子或者生成低級氧化物,即便不嚴格地調整成膜時之氧供給量亦可完成。 The relative density can be calculated from the measured density and theoretical density measured by the Archimedes method. The relative density is preferably 100% or less. When it is 100% or less, it is not easy to generate metal particles or form a low-order oxide in the sintered body, and the oxygen supply amount can be completed even if the film formation is not strictly adjusted.

另外,燒結後,亦可進行還原性環境下之熱處理操作等後處理步驟等而調整密度。還原性環境可使用氬氣、氮氣、氫氣等環境、或該等之混合氣體環境。 Further, after the sintering, the density may be adjusted by performing a post-treatment step such as a heat treatment operation in a reducing environment. The reducing environment may use an environment such as argon gas, nitrogen gas, hydrogen gas, or the like, or a mixed gas atmosphere.

另外,本發明之濺鍍靶較佳為相對密度為97%以上,且體比電阻為10mΩcm以下。藉此,於對本發明之濺鍍靶進行濺鍍時,可抑制異常放電之產生。本發明之濺鍍靶可使高品質氧化物半導體薄膜有效率地、廉價地且節能地成膜。 Further, the sputtering target of the present invention preferably has a relative density of 97% or more and a bulk specific resistance of 10 m?cm or less. Thereby, when the sputtering target of the present invention is sputtered, the occurrence of abnormal discharge can be suppressed. The sputtering target of the present invention enables a high quality oxide semiconductor film to be formed efficiently, inexpensively, and energy-savingly.

體比電阻例如可藉由實施例中所記載之方法而測定。 The bulk specific resistance can be measured, for example, by the method described in the examples.

本發明之濺鍍靶中之晶體之最大粒徑較理想為8μm以下。若晶體之粒徑為8μm以下,則不易產生結核。 The maximum particle diameter of the crystal in the sputtering target of the present invention is preferably 8 μm or less. When the particle diameter of the crystal is 8 μm or less, no tuberculosis is likely to occur.

於藉由濺鍍削刮靶表面之情形時,其削刮速度根據晶體面之方 向而不同,於靶表面產生凹凸。該凹凸之大小依存於濺鍍靶中所存在之晶體粒徑。關於具有較大之晶體粒徑之靶,可認為其凹凸變大,自該凸部產生結核。 When the target surface is scraped by sputtering, the shaving speed is based on the crystal plane Different from each other, irregularities are generated on the surface of the target. The size of the concavities and convexities depends on the crystal grain size present in the sputtering target. Regarding a target having a large crystal grain size, it is considered that the unevenness thereof is large, and tuberculosis is generated from the convex portion.

該等濺鍍靶之晶體之最大粒徑係對在如下5個部位在100μm見方之框內觀察到的具有最大徑之粒子測定其最大徑,以於該等5個部位之框內分別存在的最大粒子之粒徑之平均值表示,上述5個部位於濺鍍靶之形狀為圓形之情形時,為圓之中心點(1個部位)、及於該中心點正交之2條中心線上之中心點與周緣部的中間點(4個部位)之合計5個部位,另外,於濺鍍靶之形狀為四邊形之情形時,為其中心點(1個部位)、及四邊形之對角線上之中心點與角部的中間點(4個部位)之合計5個部位。粒徑係對晶粒之長徑進行測定。晶粒可藉由掃描型電子顯微鏡(SEM,scanning electron microscope)進行觀察。 The maximum particle diameter of the crystal of the sputtering target is measured for the largest diameter of the particles having the largest diameter observed in the frame of 100 μm square at the following five locations, and is present in the frames of the five locations. The average value of the particle diameters of the largest particles indicates that the five portions are located at the center point of the circle (one portion) and the two center lines orthogonal to the center point when the shape of the sputtering target is circular. The total of the center point and the intermediate point (four parts) of the peripheral portion is five, and when the shape of the sputtering target is a quadrangle, the center point (one part) and the diagonal of the quadrangle The total of the center point and the middle point of the corner (four parts) is five parts in total. The particle size is used to measure the long diameter of the crystal grains. The crystal grains can be observed by a scanning electron microscope (SEM).

本發明之濺鍍靶之製造方法包括以下之2個步驟。 The method of manufacturing the sputtering target of the present invention comprises the following two steps.

(1)使原料化合物混合並成形而形成成形體之步驟 (1) Step of mixing and shaping a raw material compound to form a shaped body

(2)對上述成形體進行燒結之步驟 (2) a step of sintering the above shaped body

以下,對各步驟進行說明。 Hereinafter, each step will be described.

(1)使原料化合物混合並成形而形成成形體之步驟 (1) Step of mixing and shaping a raw material compound to form a shaped body

原料化合物並無特別限定,只要使用包含In、Sn、Zn及Mg且燒結體可具有以下之原子比之化合物即可。 The raw material compound is not particularly limited as long as it is a compound containing In, Sn, Zn, and Mg and the sintered body may have the following atomic ratio.

0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1) 0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1)

0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2) 0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2)

0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3) 0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3)

0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4) 0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4)

(式中,In、Sn、Zn及Mg分別表示濺鍍靶中之各元素之原子比) (wherein, In, Sn, Zn, and Mg represent the atomic ratios of the respective elements in the sputtering target, respectively)

例如可列舉氧化銦、氧化錫、氧化鋅及氧化鎂之組合等。再者,原料較佳為粉末。 For example, a combination of indium oxide, tin oxide, zinc oxide, and magnesium oxide can be mentioned. Further, the raw material is preferably a powder.

原料較佳為氧化銦、氧化錫、氧化鋅及氧化鎂之混合粉末。 The raw material is preferably a mixed powder of indium oxide, tin oxide, zinc oxide and magnesium oxide.

於原料使用單體金屬之情形時,例如於使用氧化銦、氧化錫、氧化鋅及單體Mg之組合作為原料粉末之情形時,有時於所獲得之燒結體中存在單體Mg之顆粒,靶表面之金屬粒在成膜過程中熔融而不會自靶中釋放出,存在所獲得之膜之組成與燒結體的組成差異較大之情況。 In the case where a monomer metal is used as the raw material, for example, when a combination of indium oxide, tin oxide, zinc oxide, and monomer Mg is used as the raw material powder, particles of the monomer Mg are sometimes present in the obtained sintered body. The metal particles on the surface of the target are melted during the film formation without being released from the target, and there is a case where the composition of the obtained film differs greatly from the composition of the sintered body.

原料粉末之平均粒徑較佳為0.1μm~1.2μm,更佳為0.1μm~1.0μm以下。原料粉末之平均粒徑可利用雷射折射式粒度分佈裝置等進行測定。 The average particle diameter of the raw material powder is preferably from 0.1 μm to 1.2 μm, more preferably from 0.1 μm to 1.0 μm. The average particle diameter of the raw material powder can be measured by a laser refracting type particle size distribution device or the like.

例如,以包含平均粒徑為0.1μm~1.2μm之In2O3粉末、平均粒徑為0.1μm~1.2μm之SnO2粉末、平均粒徑為0.1μm~1.2μm之ZnO粉末及平均粒徑為0.1μm~1.2μm之MgO粉末的氧化物作為原料粉末,按照滿足上述式(1)~(4)之比率對該等進行調合。 For example, an In 2 O 3 powder having an average particle diameter of 0.1 μm to 1.2 μm, a SnO 2 powder having an average particle diameter of 0.1 μm to 1.2 μm, a ZnO powder having an average particle diameter of 0.1 μm to 1.2 μm, and an average particle diameter are used. The oxide of the MgO powder of 0.1 μm to 1.2 μm is used as a raw material powder, and these are blended in accordance with the ratios satisfying the above formulas (1) to (4).

步驟(1)之混合、成形方法並無特別限定,可利用公知之方法而進行。例如,於包含含有氧化銦粉末、氧化錫、氧化鋅及氧化鎂粉末之氧化物之混合粉末的原料粉末中調配水系溶劑,將所獲得之漿料混合12小時以上,其後進行固液分離‧乾燥‧造粒,繼而,將該造粒物加入至模框中而進行成形。 The mixing and molding method of the step (1) is not particularly limited, and it can be carried out by a known method. For example, an aqueous solvent is prepared in a raw material powder containing a mixed powder of an oxide containing indium oxide powder, tin oxide, zinc oxide, and magnesium oxide powder, and the obtained slurry is mixed for 12 hours or more, followed by solid-liquid separation. Drying ‧ granulation, and then the granules are added to the mold frame for forming.

混合可使用濕式或乾式之球磨機、振磨機、珠磨機等。為了獲得均勻且微細之晶粒及空孔,最佳為於短時間內凝集體之壓碎效率高且添加物之分散狀態亦良好之珠磨機混合法。 For mixing, a wet or dry ball mill, a vibrating mill, a bead mill, or the like can be used. In order to obtain uniform and fine crystal grains and pores, it is preferable to use a bead mill mixing method in which the crushing efficiency of the aggregate is high in a short time and the dispersion state of the additive is also good.

利用球磨機之混合時間較佳為設為15小時以上,更佳為設為19小時以上。其原因在於,若混合時間不足,則有於最終所獲得之燒結體中生成MgO等之高電阻化合物之虞。 The mixing time by the ball mill is preferably set to 15 hours or longer, more preferably 19 hours or longer. The reason for this is that if the mixing time is insufficient, a high-resistance compound such as MgO is formed in the sintered body finally obtained.

利用珠磨機之粉碎、混合時間係根據裝置之大小、處理之漿料量而不同,但以使漿料中之粒度分佈全部為1μm以下而變得均勻之方 式適當調整。 The pulverization and mixing time by the bead mill differ depending on the size of the apparatus and the amount of the slurry to be processed, but the particle size distribution in the slurry is all 1 μm or less and becomes uniform. Appropriate adjustment.

另外,較佳為混合時僅添加任意量之黏合劑,同時進行混合。黏合劑可使用聚乙烯醇、乙酸乙烯酯等。 Further, it is preferred to add only an arbitrary amount of the binder while mixing, and to carry out mixing at the same time. As the binder, polyvinyl alcohol, vinyl acetate or the like can be used.

其次,自原料粉末漿料中獲得造粒粉末。造粒時,較佳為進行急速乾燥造粒。作為用以進行急速乾燥造粒之裝置,廣泛使用噴霧乾燥器。具體之乾燥條件係根據乾燥之漿料之漿料濃度、乾燥所使用之熱風溫度、風量等各條件而決定,故而實施時,必需預先求出最佳條件。 Next, a granulated powder is obtained from the raw material powder slurry. In the case of granulation, it is preferred to carry out rapid drying granulation. As a device for performing rapid drying granulation, a spray dryer is widely used. The specific drying conditions are determined according to various conditions such as the slurry concentration of the dried slurry, the hot air temperature used for drying, and the amount of air. Therefore, it is necessary to obtain optimum conditions in advance when performing.

若進行自然乾燥,由於沈澱速度係根據原料粉末之比重差而不同,故而有引起In2O3粉末、Sn2O2粉末、ZnO粉末及MgO粉末之分離而無法獲得均勻之造粒粉末之虞。 In the case of natural drying, since the precipitation rate differs depending on the difference in specific gravity of the raw material powder, separation of In 2 O 3 powder, Sn 2 O 2 powder, ZnO powder, and MgO powder may occur, and uniform granulated powder may not be obtained. .

對於造粒粉末,通常藉由模具加壓或冷均壓加壓(CIP,cold isostatic pressing)並以例如1.2ton/cm2以上之壓力實施成形而獲得成形體。 For the granulated powder, the molded body is usually obtained by die pressing or cold isostatic pressing (CIP, cold isostatic pressing) and molding at a pressure of, for example, 1.2 ton/cm 2 or more.

(2)對成形體進行燒結之步驟 (2) Step of sintering the formed body

可將所獲得之成形物於1200~1650℃之燒結溫度燒結10~50小時而獲得燒結體。 The obtained molded article can be sintered at a sintering temperature of 1200 to 1650 ° C for 10 to 50 hours to obtain a sintered body.

燒結溫度較佳為1300~1600℃,更佳為1350~1550℃,進而佳為1400~1500℃。燒結時間較佳為12~40小時,更佳為13~30小時。 The sintering temperature is preferably 1300 to 1600 ° C, more preferably 1350 to 1550 ° C, and further preferably 1400 to 1500 ° C. The sintering time is preferably from 12 to 40 hours, more preferably from 13 to 30 hours.

若燒結溫度為1200℃以上,燒結時間為10小時以上,則可製成不易於靶內部形成氧化鋅或氧化鎂且不易引起異常放電之靶。另一方面,若燒結溫度為1650℃以下,燒結時間為50小時以下,則可抑制由明顯之晶粒成長所導致的平均晶體粒徑之增大或粗大空孔之產生等,不易引起燒結體強度之降低或異常放電。 When the sintering temperature is 1200 ° C or higher and the sintering time is 10 hours or longer, a target which does not easily form zinc oxide or magnesium oxide in the target and is less likely to cause abnormal discharge can be obtained. On the other hand, when the sintering temperature is 1650 ° C or less and the sintering time is 50 hours or less, it is possible to suppress an increase in the average crystal grain size or the generation of coarse pores due to the apparent grain growth, and it is difficult to cause the sintered body. Reduced strength or abnormal discharge.

另外,於使成形體升溫至上述燒結溫度之過程中,300~500℃之溫度範圍內之平均升溫速度為2℃/分鐘鐘以下(較佳為0.05~1℃/分 鐘,更佳為0.05~0.5℃/分鐘)。 Further, in the process of raising the temperature of the formed body to the above-mentioned sintering temperature, the average temperature increase rate in the temperature range of 300 to 500 ° C is 2 ° C / min or less (preferably 0.05 to 1 ° C / min) The clock is more preferably 0.05 to 0.5 ° C / min).

氧化鎂具有吸濕性且於300℃以上引起脫水反應。藉由將300~500℃之溫度範圍內之平均升溫速度設為2℃/分鐘鐘以下,可製成能防止引起急遽之脫水反應且不易產生孔之靶。 Magnesium oxide is hygroscopic and causes a dehydration reaction above 300 °C. By setting the average temperature increase rate in the temperature range of 300 to 500 ° C to 2 ° C / min or less, it is possible to produce a target which is capable of preventing a rapid dehydration reaction and which is less likely to cause pores.

作為本發明中所使用之燒結方法,除常壓燒結法以外,亦可採用熱壓、氧加壓、熱均壓加壓等加壓燒結法。其中,就製造成本之降低、大量生產之可能性、可容易地製造大型燒結體等觀點而言,較佳為採用常壓燒結法。 As the sintering method used in the present invention, in addition to the normal pressure sintering method, a pressure sintering method such as hot pressing, oxygen pressurization, or hot pressurization pressurization may be employed. Among them, from the viewpoints of reduction in manufacturing cost, possibility of mass production, and easy production of a large sintered body, a normal pressure sintering method is preferably employed.

常壓燒結法係於大氣環境或氧化性氣體環境、較佳為氧化性氣體環境下對成形體進行燒結。所謂氧化性氣體環境,較佳為氧氣環境。氧氣環境較佳為氧氣濃度為例如10~100體積%之環境。於本發明之濺鍍靶之製造方法中,可藉由在升溫過程中導入氧氣環境而進一步提高燒結體密度。 The normal pressure sintering method sinters the formed body in an atmosphere or an oxidizing gas atmosphere, preferably an oxidizing gas atmosphere. The oxidizing gas environment is preferably an oxygen atmosphere. The oxygen atmosphere is preferably an environment having an oxygen concentration of, for example, 10 to 100% by volume. In the method for producing a sputtering target of the present invention, the density of the sintered body can be further increased by introducing an oxygen atmosphere during the temperature increase.

為了使上述燒結步驟中所獲得之燒結體之體電阻於靶整體中均勻化,亦可視需要設置還原步驟。 In order to homogenize the bulk resistance of the sintered body obtained in the above sintering step in the entire target, a reduction step may be provided as needed.

作為還原方法,例如可列舉利用還原性氣體之方法、或者利用真空煅燒或惰性氣體之還原等。於為利用還原性氣體之還原處理之情形時,可使用氫氣、甲烷、一氧化碳、或該等氣體與氧氣之混合氣體等。於為藉由於惰性氣體中進行煅燒之還原處理之情形時,可使用氮氣、氬氣、或該等氣體與氧氣之混合氣體等。 Examples of the reduction method include a method using a reducing gas, or a method using vacuum calcination or reduction of an inert gas. In the case of reduction treatment using a reducing gas, hydrogen, methane, carbon monoxide, or a mixed gas of such a gas and oxygen may be used. In the case of a reduction treatment by calcination in an inert gas, nitrogen gas, argon gas, or a mixed gas of such gas and oxygen or the like can be used.

還原處理時之溫度通常為100~800℃,較佳為200~800℃。另外,還原處理之時間通常為0.01~10小時,較佳為0.05~5小時。 The temperature during the reduction treatment is usually from 100 to 800 ° C, preferably from 200 to 800 ° C. Further, the time of the reduction treatment is usually from 0.01 to 10 hours, preferably from 0.05 to 5 hours.

若總結以上,則例如可藉由如下方式獲得燒結體:於包含氧化銦粉末、氧化錫粉末、氧化鋅粉末及氧化鎂粉末之混合粉末之原料粉末中調配水系溶劑,將所獲得之漿料混合12小時以上,其後進行固液分離‧乾燥‧造粒,繼而,將該造粒物加入至模框中而進行成形,其 後,於氧氣環境中、將300~500℃之溫度範圍內之升溫速度設為2℃/分鐘鐘以下、在1200~1650℃下將所獲得之成形物煅燒10~50小時。 In summary, for example, a sintered body can be obtained by disposing an aqueous solvent in a raw material powder containing a mixed powder of indium oxide powder, tin oxide powder, zinc oxide powder, and magnesium oxide powder, and mixing the obtained slurry. 12 hours or more, followed by solid-liquid separation, drying, granulation, and then the granules are added to the mold frame for forming. Thereafter, the temperature increase rate in the temperature range of 300 to 500 ° C is set to 2 ° C / min or less in an oxygen atmosphere, and the obtained molded product is calcined at 1200 to 1650 ° C for 10 to 50 hours.

可藉由對上述中所獲得之燒結體進行加工而製成本發明之濺鍍靶。具體而言,可藉由將燒結體切削加工成適合向濺鍍裝置上安裝之形狀而製成濺鍍靶材,藉由將該靶材接著於襯板上而製成濺鍍靶。 The sputtering target of the present invention can be produced by processing the sintered body obtained as described above. Specifically, the sintered target can be formed into a sputtering target by cutting the sintered body into a shape suitable for mounting on a sputtering apparatus, and then adhering the target to the backing plate.

為了將燒結體製成靶材,利用例如平面磨削盤對燒結體進行削刮而製成表面粗糙度Ra為0.5μm以下之素材。此處,亦可進而對靶材之濺鍍面進行鏡面加工而使平均表面粗糙度Ra成為1000埃以下。 In order to form the sintered body into a target, the sintered body is shaved by, for example, a surface grinding disc to obtain a material having a surface roughness Ra of 0.5 μm or less. Here, the sputter surface of the target may be mirror-finished to have an average surface roughness Ra of 1000 angstroms or less.

鏡面加工(研磨)可利用機械研磨、化學研磨、機械化學研磨(機械研磨與化學研磨之併用)等公知之研磨技術。例如可藉由利用固定研磨粒拋光儀(拋光液:水)拋光成#2000以上、或利用游離研磨粒拋光(研磨材料:SiC膏等)進行摩擦後將研磨材料變更為金剛石膏進行研磨而獲得。上述研磨方法並無特別限定。 The mirror processing (polishing) can be performed by a known grinding technique such as mechanical polishing, chemical polishing, or mechanical chemical polishing (combination of mechanical polishing and chemical polishing). For example, it can be obtained by polishing with a fixed abrasive grain polisher (polishing liquid: water) to #2000 or more, or by using free abrasive grain polishing (abrasive material: SiC paste, etc.), and then grinding the abrasive material into a diamond paste for grinding. . The polishing method is not particularly limited.

靶材之表面較佳為利用200~10,000號金剛石磨輪進行最後加工,尤佳為利用400~5,000號金剛石磨輪進行最後加工。若使用大於200號且小於10,000號之金剛石磨輪,靶材變得不易破裂。 The surface of the target is preferably processed by a diamond grinding wheel of 200 to 10,000, and is preferably processed by a diamond grinding wheel of 400 to 5,000. If a diamond grinding wheel larger than 200 and smaller than 10,000 is used, the target becomes less susceptible to cracking.

較佳為靶材之表面粗糙度Ra為0.5μm以下且具備無方向性之研磨面。若Ra為0.5μm以下且於研磨面無方向性,則不易引起異常放電或產生微粒。 It is preferable that the target has a surface roughness Ra of 0.5 μm or less and a non-directional polishing surface. When Ra is 0.5 μm or less and there is no directionality on the polished surface, abnormal discharge or generation of fine particles is less likely to occur.

其次,對所獲得之靶材進行淨化處理。淨化處理可使用鼓風或流水清洗等。於利用鼓風去除異物時,若利用集塵機自噴嘴之對向側進行吸氣,則可更有效地去除。 Next, the obtained target is subjected to purification treatment. The purification treatment can be performed by using blast or running water. When the foreign matter is removed by air blowing, if the dust collector is used to inhale from the opposite side of the nozzle, it can be removed more effectively.

再者,以上之鼓風或流水清洗存在極限,因此亦可進一步進行超音波清洗等。對於該超音波清洗,較為有效的是於頻率25~300kHz之間以多重振動方式進行之方法。例如較佳為於頻率25~300kHz之間以每25kHz使12種頻率多重振動之方式進行超音波清洗。 Furthermore, there is a limit to the above blast or running water cleaning, so that ultrasonic cleaning or the like can be further performed. For this ultrasonic cleaning, it is more effective to perform the method of multiple vibrations at a frequency of 25 to 300 kHz. For example, ultrasonic cleaning is preferably performed at a frequency of 25 to 300 kHz with 12 types of frequencies per 25 kHz.

靶材之厚度通常為2~20mm,較佳為3~12mm,尤佳為4~6mm。 The thickness of the target is usually 2 to 20 mm, preferably 3 to 12 mm, and more preferably 4 to 6 mm.

可藉由將如上所述般獲得之靶材接合於襯板上而獲得濺鍍靶。另外,亦可將複數之靶材安裝於1個襯板上而製成實質上為1個之靶。 The sputtering target can be obtained by bonding the target obtained as described above to the liner. Alternatively, a plurality of targets may be mounted on one of the liners to form substantially one target.

本發明之氧化物半導體薄膜係藉由使用上述所說明之本發明之濺鍍靶並利用濺鍍法進行成膜而獲得。 The oxide semiconductor thin film of the present invention is obtained by forming a film by a sputtering method using the sputtering target of the present invention described above.

本發明之氧化物半導體薄膜包含銦、錫、鋅、鎂、氧,通常原子比係如(1)~(4)般:0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1) The oxide semiconductor thin film of the present invention contains indium, tin, zinc, magnesium, and oxygen, and generally has an atomic ratio of (1) to (4): 0.05 ≦ In / (In + Sn + Zn + Mg) ≦ 0.70 (1)

0.015≦Sn/(In+Sn+Zn+Mg)≦0.35 (2) 0.015≦Sn/(In+Sn+Zn+Mg)≦0.35 (2)

0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3) 0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3)

0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4) 0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4)

(式中,In、Sn、Zn及Mg分別表示氧化物半導體薄膜中之各元素之原子比)。 (In the formula, In, Sn, Zn, and Mg respectively represent the atomic ratio of each element in the oxide semiconductor thin film).

上述式(1)中,若In元素之量為0.05以上,則於將成膜之膜應用於TFT之通道層時移動度容易提昇。另一方面,若In元素之量為0.70以下,則於將成膜之膜應用於TFT之通道層時,不易成為常導通之特性,作為TFT容易顯示良好之特性。 In the above formula (1), when the amount of the In element is 0.05 or more, the degree of mobility is easily improved when the film formed film is applied to the channel layer of the TFT. On the other hand, when the amount of the In element is 0.70 or less, when the film to be formed is applied to the channel layer of the TFT, it is difficult to be a characteristic of constant conduction, and it is easy to exhibit good characteristics as a TFT.

上述式(2)中,若Sn元素之量為0.01以上,則所獲得之薄膜相對於濕式蝕刻之溶解速度不會過快而容易進行濕式蝕刻。另一方面,若Sn元素之量為0.35以下,則即便於濕式蝕刻後,殘渣亦不易殘存。 In the above formula (2), when the amount of the Sn element is 0.01 or more, the obtained film is not excessively fast in dissolution rate with respect to wet etching, and is easily subjected to wet etching. On the other hand, when the amount of the Sn element is 0.35 or less, the residue does not easily remain even after the wet etching.

上述式(3)中,若Zn元素之量為0.01以上,則所獲得之膜作為非晶質膜而變得容易穩定。另一方面,若Zn元素之量為0.90以下,則所獲得之薄膜相對於濕式蝕刻之溶解速度不會過快而容易進行濕式蝕刻。 In the above formula (3), when the amount of the Zn element is 0.01 or more, the obtained film is easily stabilized as an amorphous film. On the other hand, when the amount of the Zn element is 0.90 or less, the obtained film is not excessively fast in dissolution rate with respect to wet etching, and is easily subjected to wet etching.

上述式(4)中,若Mg元素之量為0.01以上,則膜中之載子濃度不 會變得過高,可防止TFT特性成為常導通。另一方面,若Mg元素之量為0.30以下,則移動度不易降低。 In the above formula (4), if the amount of the Mg element is 0.01 or more, the carrier concentration in the film is not It will become too high to prevent the TFT characteristics from becoming a constant conduction. On the other hand, when the amount of the Mg element is 0.30 or less, the mobility is not easily lowered.

本發明之濺鍍靶具有較高之導電性,因此可使用成膜速度較快之DC濺鍍法。 The sputtering target of the present invention has high conductivity, so that a DC sputtering method with a faster film formation speed can be used.

本發明之濺鍍靶除應用於上述DC濺鍍法以外,亦可應用於RF(Radio Frequency,射頻)濺鍍法、AC(Alternating Current,交流)濺鍍法、脈衝DC濺鍍法,可進行無異常放電之濺鍍。 In addition to the above-mentioned DC sputtering method, the sputtering target of the present invention can also be applied to RF (Radio Frequency) sputtering, AC (Alternating Current) sputtering, and pulsed DC sputtering. Sputter without abnormal discharge.

氧化物半導體薄膜亦可使用上述濺鍍靶並利用蒸鍍法、離子鍍著法、脈衝雷射蒸鍍法等而製作。 The oxide semiconductor thin film can also be produced by a vapor deposition method, an ion plating method, a pulsed laser vapor deposition method, or the like using the above-described sputtering target.

作為濺鍍氣體(環境),可使用氬氣等稀有氣體與氧化性氣體之混合氣體。所謂氧化性氣體,可列舉O2、CO2、O3、水蒸氣(H2O)、N2O等。濺鍍氣體較佳為含有稀有氣體與選自水蒸氣、氧氣及一氧化二氮氣體中之一種以上的混合氣體,更佳為至少含有稀有氣體與水蒸氣之混合氣體。 As the sputtering gas (environment), a mixed gas of a rare gas such as argon gas and an oxidizing gas can be used. Examples of the oxidizing gas include O 2 , CO 2 , O 3 , water vapor (H 2 O), and N 2 O. The sputtering gas is preferably a mixed gas containing a rare gas and one or more selected from the group consisting of water vapor, oxygen, and nitrous oxide gas, and more preferably a mixed gas containing at least a rare gas and water vapor.

氧化物半導體薄膜之載子濃度通常為1019cm-3以下,較佳為1013~1018cm-3,進而佳為1014~1018cm-3,尤佳為1015~1018cm-3The carrier concentration of the oxide semiconductor film is usually 10 19 cm -3 or less, preferably 10 13 to 10 18 cm -3 , more preferably 10 14 to 10 18 cm -3 , and particularly preferably 10 15 to 10 18 cm - 3 .

若氧化物層之載子濃度為1019cm-3以下,則於構成薄膜電晶體等元件時,可防止漏電之產生或TFT特性成為常導通。進而,若載子濃度為1013cm-3以上,則容易作為TFT顯示良好之特性。 When the carrier concentration of the oxide layer is 10 19 cm -3 or less, when an element such as a thin film transistor is formed, occurrence of electric leakage or TFT characteristics can be prevented from being normally conducted. Further, when the carrier concentration is 10 13 cm -3 or more, it is easy to exhibit good characteristics as a TFT.

氧化物半導體薄膜之載子濃度可藉由霍爾效應測定方法而測定。 The carrier concentration of the oxide semiconductor film can be measured by a Hall effect measurement method.

濺鍍成膜時之氧分壓比較佳為設為0.1%~30%。於氧分壓比為30%以上之條件下製作之薄膜有載子濃度大幅降低而載子濃度成為未達1013cm-3之虞。 The oxygen partial pressure at the time of sputtering film formation is preferably set to 0.1% to 30%. When the oxygen partial pressure ratio is 30% or more, the carrier concentration of the film is greatly lowered and the carrier concentration is less than 10 13 cm -3 .

更佳為0.1%~20%。 More preferably 0.1% to 20%.

本發明之氧化物薄膜堆積時之濺鍍氣體(環境)所含之水蒸氣(水 分子)之分壓比、即[水蒸氣(H2O)]/([水蒸氣(H2O)]+[稀有氣體]+[其他氣體分子])較佳為0.1~25%。 The partial pressure ratio of water vapor (water molecules) contained in the sputtering gas (environment) when the oxide film of the present invention is deposited, that is, [water vapor (H 2 O)] / ([water vapor (H 2 O)] +[rare gas]+[other gas molecules]) is preferably 0.1 to 25%.

另外,若水之分壓比為25%以下,則可防止膜密度之降低,In於5 s軌道上之重複不會變小,因此移動度不易降低。濺鍍時之環境中之水之分壓比更佳為0.7~13%,尤佳為1~6%。 Further, when the partial pressure ratio of water is 25% or less, the decrease in the film density can be prevented, and the repetition of In on the 5 s orbit does not become small, so that the mobility is not easily lowered. The partial pressure ratio of water in the environment at the time of sputtering is preferably 0.7 to 13%, particularly preferably 1 to 6%.

利用濺鍍進行成膜時之基板溫度較佳為25~120℃,進而佳為25~100℃,尤佳為25~90℃。若成膜時之基板溫度為120℃以下,則成膜時導入之氧氣等之吸收不易減少,即便於加熱後,薄膜之載子濃度亦容易成為1019cm-3以下。另外,若成膜時之基板溫度高於25℃,則薄膜之膜密度提昇,TFT之移動度不易降低。 The substrate temperature at the time of film formation by sputtering is preferably 25 to 120 ° C, more preferably 25 to 100 ° C, and particularly preferably 25 to 90 ° C. When the substrate temperature at the time of film formation is 120 ° C or less, the absorption of oxygen or the like introduced during film formation is not easily reduced, and even after heating, the carrier concentration of the film is likely to be 10 19 cm -3 or less. Further, if the substrate temperature at the time of film formation is higher than 25 ° C, the film density of the film is increased, and the mobility of the TFT is not easily lowered.

較佳為使由濺鍍所獲得之氧化物薄膜進而於150~500℃保持15分鐘~5小時而實施退火處理。成膜後之退火處理溫度更佳為200℃以上450℃以下,進而佳為250℃以上350℃以下。藉由實施上述退火而獲得半導體特性。 Preferably, the oxide film obtained by sputtering is further subjected to an annealing treatment at 150 to 500 ° C for 15 minutes to 5 hours. The annealing treatment temperature after film formation is more preferably 200 ° C or more and 450 ° C or less, and further preferably 250 ° C or more and 350 ° C or less. Semiconductor characteristics are obtained by performing the above annealing.

另外,加熱時之環境並無特別限定,就載子控制性之觀點而言,較佳為大氣環境、氧氣流通環境。 Further, the environment at the time of heating is not particularly limited, and from the viewpoint of carrier controllability, it is preferably an atmospheric environment or an oxygen circulation environment.

於氧化物薄膜之後處理退火步驟中,可於氧氣之存在下或不存在下使用燈退火裝置、雷射退火裝置、熱電漿裝置、熱風加熱裝置、接觸加熱裝置等。 In the post-treatment annealing step of the oxide film, a lamp annealing device, a laser annealing device, a thermal plasma device, a hot air heating device, a contact heating device, or the like can be used in the presence or absence of oxygen.

濺鍍時之靶與基板之間的距離相對於基板之成膜面而於垂直方向上較佳為1~15cm,進而佳為2~8cm。若該距離為1cm以上,則到達基板之靶構成元素之粒子之運動能量不會過度變大,故而不易引起膜厚或電氣特性之面內分佈。另一方面,若靶與基板之間隔為15cm以下,則到達基板之靶構成元素之粒子之運動能量不會過度變小,膜密度不易降低,容易獲得良好之半導體特性。 The distance between the target and the substrate at the time of sputtering is preferably 1 to 15 cm in the vertical direction with respect to the film formation surface of the substrate, and more preferably 2 to 8 cm. When the distance is 1 cm or more, the kinetic energy of the particles reaching the target constituent elements of the substrate does not become excessively large, so that it is less likely to cause an in-plane distribution of film thickness or electrical characteristics. On the other hand, when the distance between the target and the substrate is 15 cm or less, the kinetic energy of the particles reaching the target constituent elements of the substrate does not become excessively small, the film density is not easily lowered, and good semiconductor characteristics are easily obtained.

氧化物薄膜之成膜較理想為於磁場強度為300~1500高斯之環境 下進行濺鍍。若磁場強度為300高斯以上,則可提高電漿密度,故而即便為高電阻濺鍍靶,亦可無問題地進行濺鍍。另一方面,若為1500高斯以下,則容易控制膜厚及膜中之電氣特性。 The film formation of the oxide film is preferably in the environment of a magnetic field strength of 300 to 1500 gauss. Sputtering is performed. When the magnetic field strength is 300 gauss or more, the plasma density can be increased, and even if it is a high-resistance sputtering target, sputtering can be performed without any problem. On the other hand, when it is 1500 gauss or less, it is easy to control the film thickness and the electrical characteristics in a film.

氣體環境之壓力(濺鍍壓力)只要為電漿可穩定地放電之範圍,則並無特別限定,較佳為0.1~3.0Pa,進而佳為0.1~1.5Pa,尤佳為0.1~1.0Pa。若濺鍍壓力為3.0Pa以下,則可延長濺鍍粒子之平均自由步驟,容易提昇薄膜之密度。另外,若濺鍍壓力為0.1Pa以上,則容易防止成膜時於膜中生成微晶體。再者,所謂濺鍍壓力,係指導入氬氣等稀有氣體、水蒸氣、氧氣等後之濺鍍開始時之系統內總壓。 The pressure of the gas atmosphere (sputtering pressure) is not particularly limited as long as it is a range in which the plasma can be stably discharged, and is preferably 0.1 to 3.0 Pa, more preferably 0.1 to 1.5 Pa, and particularly preferably 0.1 to 1.0 Pa. If the sputtering pressure is 3.0 Pa or less, the average free step of the sputtered particles can be lengthened, and the density of the film can be easily increased. Further, when the sputtering pressure is 0.1 Pa or more, it is easy to prevent the formation of microcrystals in the film during film formation. In addition, the sputtering pressure is a system-controlled total pressure at the start of sputtering after introduction of a rare gas such as argon gas, water vapor, or oxygen.

另外,亦可利用如下交流濺鍍進行氧化物半導體薄膜之成膜。 Further, film formation of the oxide semiconductor thin film can also be carried out by the following alternating current sputtering.

將基板依序搬送至與隔開特定間隔並排設置於真空腔室內之3片以上的靶對向之位置,自交流電源對於各靶交替施加負電位及正電位,於靶上產生電漿而於基板表面上成膜。 The substrate is sequentially transported to a position opposite to three or more targets placed in a vacuum chamber at a predetermined interval, and a negative potential and a positive potential are alternately applied to the respective targets from the AC power source to generate plasma on the target. Film formation on the surface of the substrate.

此時,分支而於連接之2片以上之靶間一面進行施加電位之靶的切換一面進行源自交流電源之輸出之至少1者。即,將來自上述交流電源之輸出之至少1者分支地連接於2片以上之靶上,一面對鄰接之靶施加不同之電位一面進行成膜。 At this time, at least one of the outputs from the AC power source is branched while switching between the two or more connected targets. In other words, at least one of the outputs from the AC power source is branched and connected to two or more targets, and a film is formed while applying a different potential to the adjacent targets.

再者,於利用交流濺鍍使氧化物半導體薄膜成膜之情形時,例如亦較佳為於含有稀有氣體與選自水蒸氣、氧氣及一氧化二氮氣體中之一種以上的混合氣體之環境下進行濺鍍,尤佳為於至少含有稀有氣體與水蒸氣之混合氣體之環境下進行濺鍍。 Further, in the case of forming an oxide semiconductor thin film by alternating current sputtering, for example, it is preferably an environment containing a mixed gas of a rare gas and one or more selected from the group consisting of water vapor, oxygen, and nitrous oxide gas. Sputtering is carried out, and it is particularly preferable to perform sputtering in an environment containing at least a mixed gas of a rare gas and water vapor.

於利用AC濺鍍進行成膜之情形時,獲得工業上大面積均勻性優異之氧化物層,並且可期待靶之利用效率之提昇。 In the case of film formation by AC sputtering, an oxide layer excellent in industrial area uniformity is obtained, and an improvement in utilization efficiency of the target can be expected.

另外,於1邊超過1m之大面積基板上進行濺鍍成膜之情形時,例如較佳為使用如日本專利特開2005-290550號公報記載之大面積生產用AC濺鍍裝置。 In the case of performing sputtering on a large-area substrate having a side of more than 1 m, for example, an AC sputtering apparatus for large-area production as described in JP-A-2005-290550 is preferably used.

日本專利特開2005-290550號公報記載之AC濺鍍裝置具體而言具有真空槽、配置於真空槽內部之基板固持器、及配置於與該基板固持器對向之位置之濺鍍源。於圖4中表示AC濺鍍裝置之濺鍍源之主要部分。濺鍍源具有複數之濺鍍部,分別具有板狀之靶31a~31f,若將各靶31a~3tf之濺鍍之面設為濺鍍面,則以濺鍍面位於相同平面上之方式配置各濺鍍部。各靶31a~31f係形成為具有長度方向之細長形狀,各靶為同一形狀,濺鍍面之長度方向之邊緣部分(側面)相互隔開特定間隔而平行地配置。因此,鄰接之靶31a~31f之側面變得平行。 The AC sputtering apparatus described in Japanese Laid-Open Patent Publication No. 2005-290550 specifically includes a vacuum chamber, a substrate holder disposed inside the vacuum chamber, and a sputtering source disposed at a position facing the substrate holder. The main part of the sputtering source of the AC sputtering apparatus is shown in FIG. The sputtering source has a plurality of sputtering portions each having a plate-shaped target 31a to 31f. When the sputtering surface of each of the targets 31a to 3tf is a sputtering surface, the sputtering surface is disposed on the same plane. Each sputter part. Each of the targets 31a to 31f is formed to have an elongated shape in the longitudinal direction, and each of the targets has the same shape, and the edge portions (side surfaces) in the longitudinal direction of the sputtering surface are arranged in parallel with each other at a predetermined interval. Therefore, the side faces of the adjacent targets 31a to 31f become parallel.

於真空槽之外部配置有交流電源17a~17c,於各交流電源17a~17c之二個端子中,一端子與鄰接之二個電極中之一電極連接,另一端子與另一電極連接。各交流電源17a~17c之2個端子輸出正負不同之極性之電壓,以與電極密接之方式安裝有靶31a~31f,因此對於鄰接之2個靶31a~31f,自交流電源17a~17c施加相互不同之極性之交流電壓。因此,成為相互鄰接之靶31a~31f中之一者位於正電位時另一者位於負電位之狀態。 The AC power sources 17a to 17c are disposed outside the vacuum chamber, and one of the two terminals of the AC power sources 17a to 17c is connected to one of the adjacent two electrodes, and the other terminal is connected to the other electrode. The two terminals of the AC power supplies 17a to 17c output voltages of different positive and negative polarities, and the targets 31a to 31f are attached so as to be in close contact with the electrodes. Therefore, the adjacent two targets 31a to 31f are mutually applied from the AC power sources 17a to 17c. AC voltages of different polarities. Therefore, one of the targets 31a to 31f adjacent to each other is at a positive potential and the other is at a negative potential.

所謂電極之靶31a~31f,係指於相反側之面配置有磁場形成機構40a~40f。各磁場形成機構40a~40f分別具有外周之大小與靶31a~31f之外周大致相等的細長之環狀磁石、及長度短於環狀磁石之較短之棒狀磁石。 The electrode targets 31a to 31f mean that the magnetic field forming mechanisms 40a to 40f are disposed on the opposite side. Each of the magnetic field forming mechanisms 40a to 40f has an elongated annular magnet having an outer circumference substantially equal to the outer circumference of the targets 31a to 31f, and a shorter rod-shaped magnet having a shorter length than the annular magnet.

各環狀磁石係相對於靶31a~31f之長度方向而平行地配置於對應之1個靶31a~31f之正背側位置。 Each of the annular magnets is disposed in parallel with the longitudinal direction of the targets 31a to 31f at the front and back sides of the corresponding one of the targets 31a to 31f.

如上所述,靶31a~31f係隔開特定間隔而平行配置,因此環狀磁石亦隔開與靶31a~31f相同之間隔而配置。 As described above, since the targets 31a to 31f are arranged in parallel at a predetermined interval, the annular magnets are also disposed at the same interval as the targets 31a to 31f.

於AC濺鍍中使用氧化物靶之情形時之交流功率密度較佳為3W/cm2以上且20W/cm2以下。若功率密度為3W/cm2以上,則可加快成膜速度,於生產上較為經濟。若為20W/cm2以下,則可防止靶破 損。更佳之功率密度為3W/cm2~15W/cm2The AC power density in the case where an oxide target is used in AC sputtering is preferably 3 W/cm 2 or more and 20 W/cm 2 or less. If the power density is 3 W/cm 2 or more, the film formation speed can be increased, which is economical in production. When it is 20 W/cm<2> or less, damage of a target can be prevented. More preferably, the power density is from 3 W/cm 2 to 15 W/cm 2 .

AC濺鍍之頻率較佳為10kHz~1MHz之範圍。藉由超過10kHz,不易產生噪音之問題。若不超過1MHz,則可防止電漿過度擴展並於所需之靶位置以外進行濺鍍而損害均勻性。更佳之AC濺鍍之頻率為20kHz~500kHz。 The frequency of AC sputtering is preferably in the range of 10 kHz to 1 MHz. With more than 10 kHz, noise is less likely to occur. If it does not exceed 1 MHz, it is possible to prevent the plasma from excessively expanding and sputtering outside the desired target position to impair uniformity. The better AC sputtering frequency is 20kHz~500kHz.

上述以外之濺鍍時之條件等只要根據如上所述者而適當選擇即可。 The conditions and the like at the time of sputtering other than the above may be appropriately selected in accordance with the above.

本發明氧化物半導體薄膜不溶於磷酸系蝕刻液,且可溶於草酸系蝕刻液。如此,對於蝕刻液具有選擇性,藉此可利用草酸系蝕刻進行氧化物薄膜之蝕刻,進而,可使用磷酸系蝕刻液使形成於該氧化物薄膜上之電極圖案化。 The oxide semiconductor film of the present invention is insoluble in a phosphoric acid-based etching liquid and is soluble in an oxalic acid-based etching liquid. As described above, the etching liquid is selective, whereby the oxide film can be etched by oxalic acid etching, and the electrode formed on the oxide film can be patterned by using a phosphoric acid etching solution.

較佳為利用上述磷酸系蝕刻液之於35℃之蝕刻速度為10nm/分鐘以下,且藉由上述草酸系蝕刻液之35℃下之蝕刻速度為20nm/分鐘以上。藉由蝕刻速度於上述範圍內,可發揮蝕刻液之選擇性,可利用後通道蝕刻製作TFT。 Preferably, the etching rate of the phosphoric acid-based etching solution at 35 ° C is 10 nm/min or less, and the etching rate at 35 ° C of the oxalic acid-based etching liquid is 20 nm/min or more. When the etching rate is within the above range, the selectivity of the etching liquid can be exhibited, and the TFT can be formed by post-channel etching.

作為草酸系蝕刻液,可列舉ITO-06N(關東化學股份有限公司製造)。較佳為含有草酸0.5~10wt%者。但是,除草酸以外,亦可含有丙二酸或琥珀酸、乙酸等羧酸或其他酸,並非必需含有草酸。 ITO-06N (manufactured by Kanto Chemical Co., Ltd.) is exemplified as the oxalic acid-based etching liquid. It is preferably 0.5 to 10% by weight of oxalic acid. However, in addition to oxalic acid, carboxylic acid or other acid such as malonic acid or succinic acid or acetic acid may be contained, and oxalic acid is not necessarily contained.

作為磷酸系蝕刻液,例如可列舉包含磷酸、乙酸、硝酸之PAN(Polyacrylonitrile,聚丙烯腈)系蝕刻液。PAN系蝕刻液較佳為於磷酸45~95wt%、乙酸3~50wt%、硝酸0.5~5wt%之範圍內者。 Examples of the phosphoric acid-based etching liquid include a PAN (Polyacrylonitrile)-based etching liquid containing phosphoric acid, acetic acid, and nitric acid. The PAN-based etching liquid is preferably in the range of 45 to 95% by weight of phosphoric acid, 3 to 50% by weight of acetic acid, and 0.5 to 5% by weight of nitric acid.

本發明之氧化物半導體薄膜可用於薄膜電晶體,尤其是可較佳地用作通道層。 The oxide semiconductor film of the present invention can be used for a thin film transistor, and particularly preferably used as a channel layer.

本發明之薄膜電晶體只要具有上述所說明之本發明之氧化半導體薄膜作為通道層,則其元件構成並無特別限定,可採用公知之各種元件構成。 The thin film transistor of the present invention is not particularly limited as long as it has the above-described oxidized semiconductor thin film of the present invention as a channel layer, and can be formed by various known elements.

本發明之薄膜電晶體中之通道層之膜厚通常為10~300nm,較佳為20~250nm,更佳為30~200nm,進而佳為35~120nm,尤佳為40~80nm。若通道層之膜厚為10nm以上,則可降低大面積地成膜時之膜厚之不均勻性,可防止所製作之TFT之特性於面內變得不均勻。另一方面,若膜厚為300nm以下,則成膜時間不會過度延長,於工業上變得有利。 The film thickness of the channel layer in the thin film transistor of the present invention is usually 10 to 300 nm, preferably 20 to 250 nm, more preferably 30 to 200 nm, still more preferably 35 to 120 nm, and particularly preferably 40 to 80 nm. When the film thickness of the channel layer is 10 nm or more, the unevenness of the film thickness at the time of film formation in a large area can be reduced, and the characteristics of the produced TFT can be prevented from becoming uneven in the plane. On the other hand, when the film thickness is 300 nm or less, the film formation time is not excessively extended, which is industrially advantageous.

本發明之薄膜電晶體中之通道層通常用於N型區域,亦可與P型Si系半導體、P型氧化物半導體、P型有機半導體等各種P型半導體組合而用於PN接合型電晶體等各種半導體裝置。 The channel layer in the thin film transistor of the present invention is generally used in an N-type region, and may be used in combination with various P-type semiconductors such as a P-type Si-based semiconductor, a P-type oxide semiconductor, and a P-type organic semiconductor for a PN junction type transistor. Various semiconductor devices.

本發明之薄膜電晶體之場效移動度較佳為10cm2/Vs以上,更佳為11m2/Vs以上。 The field effect mobility of the thin film transistor of the present invention is preferably 10 cm 2 /Vs or more, more preferably 11 m 2 /Vs or more.

本發明之薄膜電晶體較佳為於上述通道層上具備保護膜。本發明之薄膜電晶體中之保護膜較佳為至少含有SiNx。SiNx由於與SiO2相比可形成更細密之膜,故而具有TFT之劣化抑制效果較高之優點。 The thin film transistor of the present invention preferably has a protective film on the channel layer. The protective film in the thin film transistor of the present invention preferably contains at least SiN x . Since SiN x can form a finer film than SiO 2 , it has an advantage that the deterioration suppression effect of the TFT is high.

再者,x為任意數,SiNx之化學計量比亦可不固定。 Furthermore, x is an arbitrary number, and the stoichiometric ratio of SiN x may not be fixed.

保護膜除包含SiNx以外,例如亦可包含SiO2、Al2O3、Ta2O5、TiO2、MgO、ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、Sc2O3、Y2O3、HfO2、CaHfO3、PbTiO3、BaTa2O6、Sm2O3、SrTiO3或AlN等氧化物等。 The protective film may contain, for example, SiO 2 , Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, Rb 2 in addition to SiN x . An oxide such as O, Sc 2 O 3 , Y 2 O 3 , HfO 2 , CaHfO 3 , PbTiO 3 , BaTa 2 O 6 , Sm 2 O 3 , SrTiO 3 or AlN.

本發明之含有銦元素(In)錫元素(Sn)、鋅元素(Zn)及鎂元素(Mg)之氧化物半導體薄膜由於含有Mg元素,故而CVD(Chemical Vapor Deposition,化學氧相成長)製程之耐還原性提昇,不易藉由製作保護膜之製程而使後通道側還原,可使用SiNx作為保護膜。 The oxide semiconductor thin film containing the indium element (In) tin element (Sn), the zinc element (Zn), and the magnesium element (Mg) of the present invention contains a Mg element, so the CVD (Chemical Vapor Deposition) process The reduction resistance is improved, and it is not easy to reduce the back channel side by the process of producing a protective film, and SiN x can be used as a protective film.

於形成保護膜前,較佳為對於通道層實施臭氧處理、氧電漿處理、二氧化氮電漿處理或一氧化二氮電漿處理。若上述處理於形成通道層後且形成保護膜前,則可以任一時序進行,但較理想為於即將形 成保護膜前進行。藉由進行上述前處理,可抑制通道層中之氧缺陷之產生。 Before forming the protective film, it is preferred to perform ozone treatment, oxygen plasma treatment, nitrogen dioxide plasma treatment or nitrous oxide plasma treatment on the channel layer. If the above treatment is performed after the formation of the channel layer and before the formation of the protective film, it may be performed at any timing, but it is preferably formed immediately. It is carried out before the protective film. By performing the above pretreatment, the generation of oxygen defects in the channel layer can be suppressed.

另外,若氧化物半導體膜中之氫於TFT驅動中擴散,則有引起閾值電壓之漂移而降低TFT之可靠性之虞。藉由對通道層實施臭氧處理、氧電漿處理或一氧化二氮電漿處理,可於薄膜結構中使In-OH之鍵結穩定化而抑制氧化物半導體膜中之氫之擴散。 Further, when hydrogen in the oxide semiconductor film is diffused during driving of the TFT, there is a possibility that the threshold voltage is shifted to lower the reliability of the TFT. By performing ozone treatment, oxygen plasma treatment, or nitrous oxide plasma treatment on the channel layer, the bonding of the In-OH can be stabilized in the thin film structure to suppress the diffusion of hydrogen in the oxide semiconductor film.

薄膜電晶體通常具備基板、閘極電極、閘極絕緣層、有機半導體層(通道層)、源極電極及汲極電極。通道層係如上所述,基板可使用公知之材料。 The thin film transistor generally includes a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer (channel layer), a source electrode, and a drain electrode. The channel layer is as described above, and a known material can be used for the substrate.

形成本發明之薄膜電晶體中之閘極絕緣膜之材料亦無特別限定,可任意地選擇通常使用之材料。具體而言,例如可使用SiO2、SiNx、Al2O3、Ta2O5、TiO2、MgO、ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、Sc2O3、Y2O3、HfO2、CaHfO3、PbTiO3、BaTa2O6、SrTiO3、Sm2O3或AlN等化合物。該等之中,較佳為SiO2、SiNx、Al2O3、Y2O3、HfO2、CaHfO3,更佳為SiO2、SiNx、HfO2、Al2O3The material for forming the gate insulating film in the thin film transistor of the present invention is not particularly limited, and a material which is usually used can be arbitrarily selected. Specifically, for example, SiO 2 , SiN x , Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, Rb 2 O, or the like can be used. Compounds such as Sc 2 O 3 , Y 2 O 3 , HfO 2 , CaHfO 3 , PbTiO 3 , BaTa 2 O 6 , SrTiO 3 , Sm 2 O 3 or AlN. Among these, SiO 2 , SiN x , Al 2 O 3 , Y 2 O 3 , HfO 2 , and CaHfO 3 are preferable, and SiO 2 , SiN x , HfO 2 , and Al 2 O 3 are more preferable.

閘極絕緣膜例如可藉由電漿CVD(Chemical VaPor Deposttion:化學氣相成長)法而形成。 The gate insulating film can be formed, for example, by a plasma CVD (Chemical VaPor Deposttion) method.

於利用電漿CVD法形成閘極絕緣膜並使通道層於其上成膜之情形時,有閘極絕緣膜中之氫擴散至通道層而導致通道層之膜質降低或TFT之可靠性降低之虞。為了防止通道層之膜質降低或TFT之可靠性降低,較佳為於使通道層成膜前對閘極絕緣膜實施臭氧處理、氧電漿處理、二氧化氮電漿處理或一氧化二氮電漿處理。藉由進行上述前處理,可防止通道層之膜質之降低或TFT之可靠性降低。 When a gate insulating film is formed by a plasma CVD method and a channel layer is formed thereon, hydrogen in the gate insulating film is diffused to the channel layer, resulting in a decrease in film quality of the channel layer or a decrease in reliability of the TFT. Hey. In order to prevent the film quality of the channel layer from decreasing or the reliability of the TFT from being lowered, it is preferred to perform ozone treatment, oxygen plasma treatment, nitrogen dioxide plasma treatment or nitrous oxide on the gate insulating film before film formation of the channel layer. Slurry treatment. By performing the above pretreatment, the film quality of the channel layer can be prevented from being lowered or the reliability of the TFT can be lowered.

再者,上述之氧化物之氧數並非必需與化學計量比一致,例如可為SiO2,亦可為SiOxFurther, the oxygen number of the above oxide is not necessarily the same as the stoichiometric ratio, and may be, for example, SiO 2 or SiO x .

閘極絕緣膜亦可為積層有包含不同材料之2層以上之絕緣膜之結 構。另外,閘極絕緣膜可為晶質、多晶質、非晶質之任一者,但較佳為工業上容易製造之多晶質或非晶質。 The gate insulating film may also be a junction of an insulating film containing two or more layers of different materials. Structure. Further, the gate insulating film may be any of crystalline, polycrystalline, and amorphous, but is preferably polycrystalline or amorphous which is industrially easy to manufacture.

形成本發明之薄膜電晶體中之汲極電極、源極電極及閘極電極之各電極的材料並無特別限定,可任意地選擇通常使用之材料。例如可使用銦錫氧化物(ITO)、銦鋅氧化物、ZnO、SnO2等之透明電極、或Al、Ag、Cu、Cr、Ni、Mo、Au、Ti、Ta等之金屬電極、或包含該等之合金之金屬電極。 The material for forming the electrodes of the drain electrode, the source electrode, and the gate electrode in the thin film transistor of the present invention is not particularly limited, and a material which is generally used can be arbitrarily selected. For example, a transparent electrode such as indium tin oxide (ITO), indium zinc oxide, ZnO, or SnO 2 or a metal electrode such as Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, or Ta, or the like may be used. Metal electrodes of these alloys.

本發明之薄膜電晶體可利用氧化物薄膜之蝕刻液選擇性,不於作為活性層之氧化物薄膜上形成蝕刻終止層,而藉由後通道蝕刻而製作。 The thin film transistor of the present invention can be produced by etching an etchant of an oxide film without forming an etch stop layer on the oxide film as an active layer, and etching by a back channel.

關於將IGZO系等通常之氧化物半導體薄膜用於活性層之薄膜電晶體,就對電極進行蝕刻時之蝕刻液而言,亦可對氧化物半導體薄膜進行蝕刻,故而必需形成用以於氧化物半導體薄膜上防止蝕刻之例如SiOx等之蝕刻終止層。因包括形成蝕刻終止層之步驟而降低了生產性。 When a thin film transistor in which a normal oxide semiconductor thin film such as IGZO is used for the active layer is used, the etching liquid for etching the electrode can also etch the oxide semiconductor thin film, so that it is necessary to form an oxide for the oxide. An etch stop layer such as SiO x or the like which is prevented from being etched on the semiconductor film. Productivity is reduced due to the step of forming an etch stop layer.

但是,本發明之氧化物半導體薄膜藉由於製作薄膜電晶體時適當地選擇使半導體薄膜與電極圖案化時之蝕刻液,可不形成蝕刻終止層即能完成,故而生產性提昇。 However, the oxide semiconductor thin film of the present invention can be formed by appropriately selecting an etching liquid for patterning a semiconductor thin film and an electrode when a thin film transistor is formed, and can be completed without forming an etch stop layer, so that productivity is improved.

即,使用本發明之氧化物半導體薄膜作為半導體活性層之薄膜電晶體可藉由包括如下步驟之製造方法而製造,該步驟係不於半導體薄膜上積層蝕刻終止層,而使用不同蝕刻液使半導體薄膜與電極圖案化,於使電極圖案化時使蝕刻液直接與半導體薄膜接觸。 That is, the thin film transistor using the oxide semiconductor thin film of the present invention as the semiconductor active layer can be produced by a manufacturing method including the step of laminating an etch stop layer on the semiconductor thin film and using a different etching liquid to make the semiconductor The film and the electrode are patterned to directly contact the semiconductor film with the etching liquid when patterning the electrode.

具體而言,於使氧化物半導體薄膜圖案化時,使用草酸系蝕刻液等可進行蝕刻之溶液,另一方面,於使電極圖案化時,使用可對銦鋅氧化物、ZnO、SnO2等透明導電氧化物、或Al、Ag、Cu、Cr、Ni、Mo、Ti、Ta等金屬、或者包含該等之合金等電極材料進行蝕刻 且不易對氧化物半導體薄膜進行蝕刻的例如磷酸系蝕刻,藉此即便電極之蝕刻液直接與半導體薄膜接觸,亦不會對半導體薄膜進行蝕刻,故而無需形成蝕刻終止層。 Specifically, when the oxide semiconductor thin film is patterned, an etching solution such as an oxalic acid etching solution or the like is used, and when the electrode is patterned, indium zinc oxide, ZnO, SnO 2 or the like is used. a transparent conductive oxide or a metal such as Al, Ag, Cu, Cr, Ni, Mo, Ti, or Ta, or an electrode material such as an alloy thereof, which is etched and is not easily etched by the oxide semiconductor film, for example, a phosphoric acid type etching. Thereby, even if the etching liquid of the electrode is directly in contact with the semiconductor film, the semiconductor film is not etched, so that it is not necessary to form an etch stop layer.

汲極電極、源極電極及閘極電極之各電極亦可形成為積層有不同之2層以上之導電層的多層結構。尤其是源極‧汲極電極由於對低電阻配線之要求較強,故而亦可利用Ti或Mo等密接性優異之金屬對Al或Cu等良導體進行夾層而使用。 Each of the electrodes of the drain electrode, the source electrode, and the gate electrode may be formed in a multilayer structure in which two or more different conductive layers are laminated. In particular, the source ‧thole electrode has a strong requirement for low-resistance wiring, and can be used by laminating a good conductor such as Al or Cu with a metal having excellent adhesion such as Ti or Mo.

本發明之薄膜電晶體亦可用於場效型電晶體、邏輯電路、記憶體電路、差動放大電路等各種積體電路。進而,除場效型電晶體以外,亦可用於靜電感應型電晶體、肖特基能障型電晶體、肖特基二極體、電阻元件。 The thin film transistor of the present invention can also be used in various integrated circuits such as field effect type transistors, logic circuits, memory circuits, and differential amplifier circuits. Further, in addition to the field effect type transistor, it can also be used for an electrostatic induction type transistor, a Schottky barrier type transistor, a Schottky diode, and a resistance element.

本發明之薄膜電晶體之構成可無限制地採用底部閘極、底部接觸、頂部接觸等公知之構成。 The composition of the thin film transistor of the present invention can be made without any limitation by a known configuration such as a bottom gate, a bottom contact, and a top contact.

尤其是底部閘極構成可獲得與非晶矽或ZnO之薄膜電晶體相比較高之性能,因此較為有利。底部閘極構成容易減少製造時之掩膜片數,且容易降低大型顯示器等用途之製造成本,故而較佳。 In particular, the bottom gate constitutes a higher performance than a thin film transistor of amorphous germanium or ZnO, and thus is advantageous. The bottom gate structure is preferable because it is easy to reduce the number of masks at the time of manufacture and to easily reduce the manufacturing cost of a large-sized display or the like.

本發明之薄膜電晶體可較佳地用於顯示裝置。 The thin film transistor of the present invention can be preferably used for a display device.

作為大面積顯示器用途,尤佳為溝道蝕刻型底部閘極構成之薄膜電晶體。溝道蝕刻型底部閘極構成之薄膜電晶體係光微影步驟時之光罩之數量較少,可以低成本製造顯示器用面板。其中,溝道蝕刻型之底部閘極構成及頂部接觸構成之薄膜電晶體由於移動度等特性良好且易於工業化,故而尤其較佳。 As a large-area display application, a thin film transistor composed of a channel-etched bottom gate is particularly preferable. The channel etching type bottom gate constitutes a thin film electro-crystal system. In the photolithography step, the number of masks is small, and the panel for display can be manufactured at low cost. Among them, the thin film transistor composed of the bottom gate structure and the top contact of the channel etching type is particularly preferable because of good characteristics such as mobility and ease of industrialization.

實施例 Example 實施例1~3 Example 1~3

[燒結體之製造] [Manufacture of sintered body]

作為原料粉體,使用下述氧化物粉末。再者,氧化物粉末之平 均粒徑係利用雷射折射式粒度分佈測定裝置SALD-300V(島津製作所製造)進行測定,平均粒徑係採用中值徑D50。 As the raw material powder, the following oxide powder was used. Furthermore, the oxide powder level The average particle diameter was measured by a laser refractive particle size distribution measuring apparatus SALD-300V (manufactured by Shimadzu Corporation), and the average particle diameter was a median diameter D50.

氧化銦粉末:平均粒徑0.98μm Indium oxide powder: average particle size 0.98μm

氧化錫粉:平均粒徑0.96μm Tin oxide powder: average particle size 0.96μm

氧化鋅粉末:平均粒徑0.98μm Zinc oxide powder: average particle size 0.98μm

氧化鎂粉:平均粒徑0.98μm Magnesium oxide powder: average particle size 0.98μm

以成為表1所示之原子比(百分率)之方式秤量上述粉體,均勻地微粉碎混合後,添加成形用黏合劑而進行造粒。其次,將該原料顆粒均勻地填充於模具中,利用冷壓機以加壓壓力140MPa進行加壓成形。 The powder was weighed so as to have an atomic ratio (percentage) shown in Table 1, uniformly finely pulverized and mixed, and then a molding binder was added thereto to carry out granulation. Next, the raw material pellets were uniformly filled in a mold, and subjected to press molding at a press pressure of 140 MPa by a cold press.

對以此種方式獲得之成形體進行燒結。首先,將成形體載置於燒結爐內,以該燒結爐內之每0.1m3容積為5升/分之比率流入氧氣。於該環境中,在表1所記載之條件(300~500℃之升溫速度、燒結保持溫度、燒結時間)下進行燒結。再者,500℃~100℃之升溫速度係設為0.5℃/分鐘,自800℃至燒結保持溫度之升溫速度係設為1℃/分鐘。 The formed body obtained in this manner is sintered. First, the formed body was placed in a sintering furnace, and oxygen gas was introduced at a rate of 5 liters per minute per 0.1 m 3 of the inside of the sintering furnace. In this environment, sintering was carried out under the conditions described in Table 1 (temperature rising rate of 300 to 500 ° C, sintering holding temperature, and sintering time). Further, the temperature increase rate from 500 ° C to 100 ° C was set to 0.5 ° C / min, and the temperature increase rate from 800 ° C to the sintering hold temperature was set to 1 ° C / min.

根據藉由阿基米德法測得之實測密度及理論密度而算出所獲得之燒結體之相對密度。關於實施例1~3之燒結體,確認相對密度為97%以上。 The relative density of the obtained sintered body was calculated from the measured density and the theoretical density measured by the Archimedes method. With respect to the sintered bodies of Examples 1 to 3, it was confirmed that the relative density was 97% or more.

另外,使用電阻率計(三菱化學股份有限公司製造、Loresta)並基於四探針法(JIS R 1637)而測定所獲得之燒結體之體比電阻(導電性)。將結果示於表1。如表1所示,實施例1~3之燒結體之體比電阻為10mΩcm以下。 Further, the specific resistance (electrical conductivity) of the obtained sintered body was measured using a resistivity meter (manufactured by Mitsubishi Chemical Corporation, Loresta) and based on a four-probe method (JIS R 1637). The results are shown in Table 1. As shown in Table 1, the specific electrical resistance of the sintered bodies of Examples 1 to 3 was 10 mΩcm or less.

[燒結體之分析] [Analysis of sintered body]

對於所獲得之燒結體進行ICP-AES分析,確認為表1所示之原子比。 The obtained sintered body was subjected to ICP-AES analysis and confirmed to have the atomic ratio shown in Table 1.

另外,對於所獲得之燒結體,利用X射線折射測定裝置(XRD)檢 查晶體結構。XRD之測定條件如下所述。 In addition, the obtained sintered body is examined by an X-ray refraction measuring device (XRD). Check the crystal structure. The measurement conditions of XRD are as follows.

‧裝置:Rigaku股份有限公司製造之Ultima-III ‧Device: Ultima-III manufactured by Rigaku Co., Ltd.

‧X射線:Cu-Kα射線(波長1.5406Å、利用石墨單色器使其單色化) ‧X-ray: Cu-Kα ray (wavelength 1.5406Å, monochromated with graphite monochromator)

‧2θ-θ反射法、連續掃描(1.0°/分) ‧2θ-θ reflection method, continuous scanning (1.0°/min)

‧取樣間隔:0.02° ‧Sampling interval: 0.02°

‧狹縫DS、SS:2/3°、RS:0.6mm ‧Slit DS, SS: 2/3°, RS: 0.6mm

將實施例1~3中所獲得之燒結體之X射線折射圖表示於圖1~3。對圖表進行分析,結果於實施例1之燒結體中觀測到In2Zn4O7之同源結構與Zn2SnO4之尖晶石結構。 The X-ray refraction diagrams of the sintered bodies obtained in Examples 1 to 3 are shown in Figs. 1 to 3. The chart was analyzed, and as a result, the homologous structure of In 2 Zn 4 O 7 and the spinel structure of Zn 2 SnO 4 were observed in the sintered body of Example 1.

晶體結構可藉由JCPDS卡或ICSD而確認。 The crystal structure can be confirmed by a JCPDS card or ICSD.

In2Zn4O7之同源結構為ICSD#162451,Zn2SnO4之尖晶石結構為JCPDS卡No.24-1470。 The homologous structure of In 2 Zn 4 O 7 is ICSD #162451, and the spinel structure of Zn 2 SnO 4 is JCPDS card No. 24-1470.

關於實施例2~3,亦如表1所示觀測到In2O3(ZnO)m之同源結構與Zn2SnO4之尖晶石結構。 With respect to Examples 2 to 3, the homology structure of In 2 O 3 (ZnO) m and the spinel structure of Zn 2 SnO 4 were also observed as shown in Table 1.

於實施例2~3中,In2Zn7O10之同源結構為ICSD#162453,In2Zn3O6之同源結構為ICSD#162450,Zn2SnO4之尖晶石結構為JCPDS卡No.24-1470。 In Examples 2 to 3, the homologous structure of In 2 Zn 7 O 10 is ICSD #162453, the homologous structure of In 2 Zn 3 O 6 is ICSD #162450, and the spinel structure of Zn 2 SnO 4 is JCPDS card. No.24-1470.

[濺鍍靶之製造] [Manufacture of sputtering target]

利用平面磨削盤對實施例1~3中所獲得之燒結體之表面進行削刮,使用金剛石切割器將側邊切斷並貼合於襯板上,分別製作直徑4英吋之濺鍍靶。 The surfaces of the sintered bodies obtained in Examples 1 to 3 were shaved by a flat grinding disc, and the side edges were cut and attached to the backing plate using a diamond cutter to prepare a sputtering target having a diameter of 4 inches. .

另外,分別製作用於AC濺鍍成膜之寬度200mm、長度1700mm、厚度10mm之6片靶。 Further, six targets having a width of 200 mm, a length of 1,700 mm, and a thickness of 10 mm for AC sputtering were separately prepared.

[有無異常放電之確認] [Confirmation of abnormal discharge]

將所獲得之直徑4英吋之濺鍍靶安裝於DC濺鍍裝置中,作為環 境,使用於氬氣中以2%之分壓比添加有水蒸氣之混合氣體,於濺鍍壓力0.4Pa、將基板溫度設為室溫、DC輸出400W之條件下進行10kWh連續濺鍍。將濺鍍中之電壓變動儲存於資料記錄器中,確認有無異常放電。將結果示於表1。 The obtained 4 inch diameter sputtering target is mounted in a DC sputtering device as a ring In a argon gas, a mixed gas of water vapor was added at a partial pressure ratio of 2%, and continuous sputtering was performed at a sputtering temperature of 0.4 Pa, a substrate temperature of room temperature, and a DC output of 400 W. Store the voltage fluctuations during sputtering in the data logger to check for abnormal discharge. The results are shown in Table 1.

再者,上述有無異常放電係藉由觀察電壓變動並檢測異常放電而確認。具體而言,將5分鐘之測定時間中所產生之電壓變動為濺鍍運轉過程中之恆定電壓的10%以上之情形設為異常放電。尤其是於濺鍍運轉過程中之恆定電壓於0.1秒鐘內變動±10%之情形時,有產生濺鍍放電之異常放電即微電弧,元件之良率降低,不適於量產化之虞。 In addition, the presence or absence of the abnormal discharge is confirmed by observing the voltage fluctuation and detecting the abnormal discharge. Specifically, the case where the voltage generated in the measurement time of 5 minutes is changed to 10% or more of the constant voltage during the sputtering operation is assumed to be abnormal discharge. In particular, when the constant voltage during the sputtering operation is changed by ±10% within 0.1 second, there is a micro-arc which causes abnormal discharge of the sputtering discharge, and the yield of the element is lowered, which is not suitable for mass production.

[是否產生結核之確認] [Is there a confirmation of tuberculosis]

另外,使用所獲得之直徑4英吋之濺鍍靶,作為環境,使用於氬氣中以3%之分壓比添加有氫氣之混合氣體,連續進行40小時濺鍍,確認是否產生結核。 In addition, a sputtering target having a diameter of 4 inches was used, and a mixed gas containing hydrogen gas at a partial pressure of 3% in argon was used as an environment, and sputtering was continuously performed for 40 hours to confirm whether or not nodules were generated.

其結果,於實施例1~3之濺鍍靶表面未觀測到結核。 As a result, no nodules were observed on the surface of the sputtering target of Examples 1 to 3.

再者,濺鍍條件係設為濺鍍壓0.4Pa、DC輸出100W,基板溫度係設為室溫。為了促進結核之產生而於環境氣體中添加氫氣。 Further, the sputtering conditions were set to a sputtering pressure of 0.4 Pa, a DC output of 100 W, and a substrate temperature of room temperature. Hydrogen is added to the ambient gas to promote the production of nodules.

結核係採用如下方法:該方法係於圓形濺鍍靶之中心點(1個部位)、及於該中心點正交之2條中心線上之中心點與周緣部的中間點(4個部位)之合計5個部位,利用實體顯微鏡放大至50倍而觀察濺鍍後之靶表面之變化,對於9mm2視野中產生之長徑20μm以上的結核測定數平均。將所產生之結核數示於表1。 The tuberculosis system adopts the following method: the method is at the center point (one part) of the circular sputtering target, and the intermediate point (four parts) between the center point and the peripheral portion on the two center lines orthogonal to the center point The total of the five sites was magnified to 50 times by a stereoscopic microscope to observe the change in the target surface after sputtering, and the number of tuberculosis measurements having a long diameter of 20 μm or more generated in a field of 9 mm 2 was averaged. The number of tuberculosis produced is shown in Table 1.

比較例1~2 Comparative example 1~2

以表1所示之原子比(百分率)將原料粉末混合,以與實施例1相同之方式製造燒結體及濺鍍靶並進行評價。將結果示於表1。 The raw material powders were mixed at an atomic ratio (percentage) shown in Table 1, and a sintered body and a sputtering target were produced and evaluated in the same manner as in Example 1. The results are shown in Table 1.

於比較例1、2中,未同時觀測到In2O3(ZnO)m之同源結構與Zn2SnO4之尖晶石結構。 In Comparative Examples 1 and 2, the homologous structure of In 2 O 3 (ZnO) m and the spinel structure of Zn 2 SnO 4 were not observed at the same time.

MgIn2O4之尖晶石結構對應於ICSD#24992,MgO之石鹽型結構對應於JCPDS卡No.45-0946,SnO2之金紅石型結構對應於JCPDS卡No.00-1024。 The spinel structure of MgIn 2 O 4 corresponds to ICSD #24992, the rock salt type structure of MgO corresponds to JCPDS card No. 45-0946, and the rutile structure of SnO 2 corresponds to JCPDS card No. 00-1024.

比較例1、2係密度為90%以下而為低密度。可認為其原因在於,300℃~500℃下之升溫速度為2.5℃/分鐘以上而較快,故而MgO所吸濕之水分快速地脫離,生成多個孔。 In Comparative Examples 1 and 2, the density was 90% or less and the density was low. The reason for this is considered to be that the temperature increase rate at 300 ° C to 500 ° C is faster than 2.5 ° C / min or more, so that moisture absorbed by MgO rapidly desorbs to form a plurality of pores.

於比較例1之濺鍍靶中,濺鍍時產生異常放電,於靶表面觀測到結核。比較例2係電阻較高而無法放電。 In the sputtering target of Comparative Example 1, abnormal discharge occurred during sputtering, and nodules were observed on the surface of the target. In Comparative Example 2, the electric resistance was high and it was impossible to discharge.

實施例4~6 Example 4~6

[氧化物半導體薄膜之製造] [Manufacture of oxide semiconductor film]

於磁控濺鍍裝置上安裝實施例1~3中所製作之表2所示之組成的4英吋靶,作為基板,分別安裝載玻片(康寧公司製造之#1737)。藉由DC磁控濺鍍法而使膜厚50nm之非晶質膜於載玻片上成膜。成膜時,以表2所示之分壓比(%)導入氬氣、氧氣及水蒸氣。 A 4 inch target having the composition shown in Table 2 prepared in Examples 1 to 3 was attached to the magnetron sputtering apparatus, and a glass slide (#1737 manufactured by Corning Incorporated) was attached as a substrate. An amorphous film having a film thickness of 50 nm was formed on a glass slide by DC magnetron sputtering. At the time of film formation, argon gas, oxygen gas, and water vapor were introduced at a partial pressure ratio (%) shown in Table 2.

濺鍍條件如下所述。 The sputtering conditions are as follows.

‧基板溫度:25℃(其中,實施例6為100℃) ‧ substrate temperature: 25 ° C (where example 6 is 100 ° C)

‧到達壓力:8.5×10-5Pa ‧ Arrival pressure: 8.5×10 -5 Pa

‧環境氣體:氬氣、氧氣、水蒸氣(分壓比參照表2) ‧Environmental gases: argon, oxygen, water vapor (partition ratio is shown in Table 2)

‧濺鍍壓力(總壓):0.4Pa ‧ Sputtering pressure (total pressure): 0.4Pa

‧投入電力:DC100W ‧Input power: DC100W

‧S(基板)-T(靶)距離:70mm ‧S (substrate)-T (target) distance: 70mm

對於玻璃基板上成膜之薄膜,利用X射線折射(XRD)測定裝置(Rigaku製造之Ultima-III)檢查晶體結構。 The film structure was examined by an X-ray refraction (XRD) measuring apparatus (Ultima-III manufactured by Rigaku) on a film formed on a glass substrate.

於實施例4~6中,確認於薄膜堆積後未觀測到折射峰而為非晶質。 In Examples 4 to 6, it was confirmed that no refractive index was observed after the film was deposited, and it was amorphous.

XRD之測定條件如下所述。 The measurement conditions of XRD are as follows.

‧裝置:Rigaku股份有限公司製造之Ultima-III ‧Device: Ultima-III manufactured by Rigaku Co., Ltd.

‧X射線:Cu-Kα射線(波長1.5406Å、利用石墨單色器使其單色化) ‧X-ray: Cu-Kα ray (wavelength 1.5406Å, monochromated with graphite monochromator)

‧2θ-θ反射法、連續掃描(1.0°/分) ‧2θ-θ reflection method, continuous scanning (1.0°/min)

‧取樣間隔:0.02° ‧Sampling interval: 0.02°

‧狹縫DS、SS:2/3°、RS:0.6mm ‧Slit DS, SS: 2/3°, RS: 0.6mm

其次,於大氣中、在表2所示之退火溫度下、於退火時間內,對形成有非晶質膜之基板進行加熱而形成氧化物半導體膜。使用於該玻 璃基板上成膜之基板作為霍爾效應測定用元件,設置於Resi Test8300型(東陽技術公司製造)上而於室溫下評價霍爾效應。 Next, the substrate on which the amorphous film was formed was heated in the atmosphere at the annealing temperature shown in Table 2 during the annealing time to form an oxide semiconductor film. Used in the glass The substrate on which the film was formed on the glass substrate was used as a Hall effect measuring element, and was placed on a Resi Test 8300 (manufactured by Toyo Denki Co., Ltd.) to evaluate the Hall effect at room temperature.

另外,藉由ICP-AES分析而確認氧化物半導體薄膜所含之各元素之原子比與濺鍍靶相同。 Further, it was confirmed by ICP-AES analysis that the atomic ratio of each element contained in the oxide semiconductor thin film was the same as that of the sputtering target.

[薄膜電晶體之製造] [Manufacture of thin film transistor]

作為基板,使用附有膜厚100nm之熱氧化膜之導電性矽基板。熱氧化膜作為閘極絕緣膜發揮功能,導電性矽部作為閘極電極發揮功能。 As the substrate, a conductive germanium substrate to which a thermal oxide film having a film thickness of 100 nm was attached was used. The thermal oxide film functions as a gate insulating film, and the conductive crotch functions as a gate electrode.

於閘極絕緣膜上進行濺鍍成膜而製作膜厚50nm之非晶質薄膜。使用OFPR#800(東京應化工業股份有限公司製造)作為抗蝕劑而進行塗佈、預烤(80℃、5分)、曝光。顯像後進行後烘烤(120℃、5分)並利用草酸進行蝕刻而按照所需之形狀圖案化。其後,於熱風加熱爐內、在表2所示之退火溫度下、於退火時間內進行加熱處理(退火處理)。 A sputtering film was formed on the gate insulating film to form an amorphous film having a film thickness of 50 nm. Coating, prebaking (80 ° C, 5 minutes), and exposure were carried out using OFPR #800 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) as a resist. After development, post-baking (120 ° C, 5 minutes) was carried out and etched with oxalic acid to pattern according to the desired shape. Thereafter, heat treatment (annealing treatment) was performed in the hot air heating furnace at the annealing temperature shown in Table 2 during the annealing time.

其後,根據剝離法,利用濺鍍成膜使Mo(100nm)成膜,使源極/汲極電極按照所需之形狀圖案化。進而,作為形成保護膜之前階段之處理,對氧化物半導體膜實施一氧化二氮電漿處理。其後,利用電漿CVD法(PECVD)使SiOx成膜而形成保護膜。使用氟酸對接觸孔進行開口而製作薄膜電晶體。 Thereafter, Mo (100 nm) was formed into a film by sputtering, and the source/drain electrodes were patterned in a desired shape according to the lift-off method. Further, as the treatment in the stage before the formation of the protective film, the oxide semiconductor film is subjected to nitrous oxide plasma treatment. Thereafter, SiO x is formed into a film by a plasma CVD method (PECVD) to form a protective film. A thin film transistor was formed by opening a contact hole with hydrofluoric acid.

[蝕刻速度之評價] [Evaluation of etching speed]

使用除將非晶質膜之膜厚設為100nm以外於相同之條件下進行成膜之實施例4~6之氧化物半導體薄膜評價蝕刻速度。 The etching rate of the oxide semiconductor thin films of Examples 4 to 6 which were formed under the same conditions except that the film thickness of the amorphous film was changed to 100 nm was used.

將作為草酸系蝕刻液之ITO-06N(關東化學股份有限公司)設為35℃並浸漬氧化物半導體薄膜,根據浸漬時間及浸漬前後之膜厚而算出蝕刻速度。 ITO-06N (Kanto Chemical Co., Ltd.) as an oxalic acid-based etching liquid was placed at 35 ° C, and an oxide semiconductor thin film was immersed, and the etching rate was calculated from the immersion time and the film thickness before and after immersion.

另外,將作為磷酸系蝕刻液之PAN蝕刻液(磷酸91.4wt%、硝酸3.3wt%、乙酸5.3wt%)設為35℃並浸漬氧化物半導體薄膜,根據浸漬 時間及浸漬前後之膜厚而算出蝕刻速度。 In addition, a PAN etching solution (91.4 wt% of phosphoric acid, 3.3 wt% of nitric acid, and 5.3 wt% of acetic acid) as a phosphoric acid-based etching liquid was set to 35 ° C, and an oxide semiconductor thin film was immersed in accordance with the impregnation. The etching rate was calculated by the film thickness before and after the immersion.

[薄膜電晶體之評價] [Evaluation of Thin Film Transistors]

對於實施例4~6中所製作之薄膜電晶體,評價場效移動度(μ)、S值及閾值電壓(Vth)。該等之特性值係使用半導體參數分析儀(Keithley Instruments股份有限公司製造之4200SCS)於室溫、遮光環境下(屏蔽盒)進行測定。Vth係設為汲極電流(Id)為1nA時之閘極電壓(Vg)。 For the thin film transistors produced in Examples 4 to 6, the field effect mobility (μ), the S value, and the threshold voltage (Vth) were evaluated. These characteristic values were measured using a semiconductor parameter analyzer (4200SCS manufactured by Keithley Instruments Co., Ltd.) at room temperature under a light-shielding environment (shield box). The Vth is a gate voltage (Vg) at which the drain current (Id) is 1 nA.

另外,對於所製造之電晶體,將汲極電壓(Vd)設為5V並將閘極電壓(Vg)設為-15~25V而評價傳遞特性。將結果示於表2。再者,場效移動度(μ)係根據線形移動度而算出,以Vg-μ之最大值進行定義。 Further, with respect to the manufactured transistor, the transfer characteristics were evaluated by setting the gate voltage (Vd) to 5 V and the gate voltage (Vg) to -15 to 25 V. The results are shown in Table 2. Further, the field effect mobility (μ) is calculated based on the linear mobility and is defined by the maximum value of Vg-μ.

其次,對於實施例4~6之TFT進行DC偏壓應力試驗。於表2中表示施加Vg=15V、Vd=15V之DC應力(應力溫度80℃下)10000秒前後的Vth之變化量△Vth。關於本發明之TFT,已知閾值電壓之變動非常小,不易受DC應力之影響。 Next, DC bias stress tests were performed on the TFTs of Examples 4 to 6. Table 2 shows the amount of change ΔVth of Vth before and after applying a DC stress of Vg = 15 V and Vd = 15 V (at a stress temperature of 80 ° C) for 10,000 seconds. Regarding the TFT of the present invention, it is known that the variation of the threshold voltage is extremely small and is not easily affected by the DC stress.

比較例3 Comparative example 3

除使用比較例1中所製作之4英吋靶以外,以與實施例4相同之方式製作氧化物半導體薄膜及薄膜電晶體並進行評價。將成膜條件、退火條件及結果示於表2。 An oxide semiconductor thin film and a thin film transistor were produced and evaluated in the same manner as in Example 4 except that the 4 inch target produced in Comparative Example 1 was used. The film formation conditions, annealing conditions, and results are shown in Table 2.

如表2所示,可知比較例3之元件係場效移動度未達10cm2/Vs,與實施例4~6相比大幅降低。 As shown in Table 2, it was found that the field effect mobility of the element system of Comparative Example 3 was less than 10 cm 2 /Vs, which was significantly lower than that of Examples 4 to 6.

另外,對比較例3之TFT進行DC偏壓應力試驗。於表2中表示施加Vg=15V、Vd=15V之DC應力(應力溫度80℃下)10000秒前後的Vth之變化量△Vth。 Further, the TFT of Comparative Example 3 was subjected to a DC bias stress test. Table 2 shows the amount of change ΔVth of Vth before and after applying a DC stress of Vg = 15 V and Vd = 15 V (at a stress temperature of 80 ° C) for 10,000 seconds.

實施例7~9 Examples 7-9

使用日本專利特開2005-290550號公報中所揭示之成膜裝置,對實施例1~3中所製作之表3所示之組成的4英吋靶進行AC濺鍍而製作薄膜電晶體。成膜條件、非晶質膜之加熱(退火)條件係如表3所示。除利用乾式蝕刻進行源極‧汲極圖案化以外,以與實施例4相同之方式製作薄膜電晶體並進行評價。將結果示於表3。 A thin film transistor was produced by subjecting a 4-inch target having the composition shown in Table 3 produced in Examples 1 to 3 to AC sputtering using a film forming apparatus disclosed in Japanese Laid-Open Patent Publication No. 2005-290550. The film formation conditions and the heating (annealing) conditions of the amorphous film are shown in Table 3. A thin film transistor was produced and evaluated in the same manner as in Example 4 except that the source ‧ drain pattern was patterned by dry etching. The results are shown in Table 3.

另外,藉由ICP-AES分析而確認氧化物薄膜所含之各元素之原子比與濺鍍靶相同。 Further, it was confirmed by ICP-AES analysis that the atomic ratio of each element contained in the oxide film was the same as that of the sputtering target.

使用圖4所示之裝置進行AC濺鍍。 AC sputtering was performed using the apparatus shown in FIG.

如圖4所示般以各自之長度方向平行之方式按照2mm之間隔配置實施例1~3中所製作之寬度200mm、長度1700mm、厚度10mm之6片靶31a~31f。磁場形成機構40a~40f之寬度與靶31a~31f相同而為200mm。自氣體供給系統將作為濺鍍氣體之Ar及水蒸氣及/或O2分別 導入至系統內。 As shown in Fig. 4, six targets 31a to 31f having a width of 200 mm, a length of 1,700 mm, and a thickness of 10 mm, which were produced in Examples 1 to 3, were arranged at intervals of 2 mm so as to be parallel to each other in the longitudinal direction. The widths of the magnetic field forming mechanisms 40a to 40f are the same as those of the targets 31a to 31f and are 200 mm. From the gas supply system, Ar as a sputtering gas, water vapor, and/or O 2 are introduced into the system, respectively.

例如於實施例7中,成膜環境係設為0.5Pa,交流電源之功率係設為3W/cm2(=10.2kW/3400cm2),頻率係設為10kHz。 For example, in the seventh embodiment, the film formation environment is set to 0.5 Pa, the power of the alternating current power source is set to 3 W/cm 2 (= 10.2 kW / 3400 cm 2 ), and the frequency is set to 10 kHz.

於以上之條件下成膜速度為54nm/分鐘而為高速,適合於量產。 Under the above conditions, the film formation rate is 54 nm/min and it is high speed, which is suitable for mass production.

比較例4 Comparative example 4

使用比較例1中所製作之寬度200mm、長度1700mm、厚度10mm之6片靶,將濺鍍條件變更為表3中所記載者,除此以外,以與實施例7相同之方式製作氧化物半導體薄膜及薄膜電晶體並進行評價。將結果示於表3。 An oxide semiconductor was produced in the same manner as in Example 7 except that six sputtering targets having a width of 200 mm, a length of 1,700 mm, and a thickness of 10 mm, which were produced in Comparative Example 1, were used, and the sputtering conditions were changed to those shown in Table 3. Films and thin film transistors were evaluated. The results are shown in Table 3.

如表3所示,可知比較例4之元件係場移動度未達10cm2/Vs,與實施例7~9相比,場效移動度大幅降低。 As shown in Table 3, it was found that the field mobility of the element of Comparative Example 4 was less than 10 cm 2 /Vs, and the field effect mobility was significantly lower than that of Examples 7 to 9.

實施例10~12 Example 10~12

除使用利用PAN(磷酸91.4wt%、硝酸3.3wt%、乙酸5.3wt%)蝕刻液之後通道蝕刻進行Mo之圖案化以外,於與實施例4~6相同之條件下製作TFT,將該TFT特性之結果示於表4。 A TFT was fabricated under the same conditions as in Examples 4 to 6 except that patterning of Mo was performed by channel etching using an etching solution of PAN (91.4 wt% of phosphoric acid, 3.3 wt% of nitric acid, and 5.3 wt% of acetic acid). The results are shown in Table 4.

可知藉由後通道蝕刻,亦可獲得良好之TFT特性。 It can be seen that good TFT characteristics can also be obtained by etching through the back channel.

[產業上之可利用性] [Industrial availability]

本發明之濺鍍靶可用於氧化物半導體或透明導電膜等氧化物薄膜之製作。另外,本發明之氧化物薄膜可用於透明電極、薄膜電晶體之半導體層、氧化物薄膜層等。 The sputtering target of the present invention can be used for the production of an oxide film such as an oxide semiconductor or a transparent conductive film. Further, the oxide film of the present invention can be used for a transparent electrode, a semiconductor layer of a thin film transistor, an oxide thin film layer, or the like.

上述中對本發明之若干個實施形態及/或實施例進行了詳細地說明,業者容易於不偏離本發明之新穎之教示及效果之情況下對作為該等例示之實施形態及/或實施例進行多種變更。因此,該等多種變更包含於本發明之範圍內。 The embodiments and/or the embodiments of the present invention are described in detail hereinabove, and the embodiments and/or embodiments of the present invention are susceptible to the embodiments and/or embodiments of the present invention. A variety of changes. Accordingly, such various modifications are intended to be included within the scope of the present invention.

將成為本案之優先權之基礎之日本申請案說明書之內容全部引用於此。 The contents of the Japanese application specification which is the basis of the priority of the present application are all incorporated herein.

Claims (19)

一種濺鍍靶,其包含含有氧化物,且以In2O3(ZnO)m(m為0.1~20)表示之同源結構化合物、及以Zn2SnO4表示之尖晶石結構化合物,該氧化物含有銦元素(In)、錫元素(Sn)、鋅元素(Zn)及鎂元素(Mg)。 A sputtering target comprising a homologous structural compound containing an oxide and having In 2 O 3 (ZnO) m (m is 0.1 to 20), and a spinel structure compound represented by Zn 2 SnO 4 , The oxide contains an indium element (In), a tin element (Sn), a zinc element (Zn), and a magnesium element (Mg). 如請求項1之濺鍍靶,其中上述銦元素、錫元素、鋅元素及鎂元素之原子比滿足下述式(1)~(4):0.05≦In/(In+Sn+Zn+Mg)≦0.70 (1) 0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2) 0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3) 0.01≦Mg/(In+Sn+Zn+Mg)≦0.30 (4)(式中,In、Sn、Zn及Mg分別表示濺鍍靶中之各元素之原子比)。 The sputtering target according to claim 1, wherein the atomic ratio of the indium element, the tin element, the zinc element, and the magnesium element satisfies the following formula (1) to (4): 0.05 ≦ In / (In + Sn + Zn + Mg) ≦0.70 (1) 0.01≦Sn/(In+Sn+Zn+Mg)≦0.35 (2) 0.01≦Zn/(In+Sn+Zn+Mg)≦0.90 (3) 0.01≦Mg/(In+Sn+ Zn + Mg) ≦ 0.30 (4) (wherein, In, Sn, Zn, and Mg respectively represent the atomic ratio of each element in the sputtering target). 如請求項1或2之濺鍍靶,其中相對密度為97%以上,體比電阻為10mΩcm以下。 The sputtering target according to claim 1 or 2, wherein the relative density is 97% or more, and the volume specific resistance is 10 m Ωcm or less. 一種如請求項1至3中任一項之濺鍍靶之製造方法,其包括如下步驟:於300℃~500℃之溫度範圍內以2℃/分鐘鐘以下之升溫速度使成形體升溫,且以1200℃~1650℃保持10~50小時而對上述成形體進行燒結。 A method for producing a sputtering target according to any one of claims 1 to 3, comprising the steps of: heating a molded body at a temperature increase rate of 2 ° C /min or less in a temperature range of 300 ° C to 500 ° C, and The formed body was sintered at 1200 ° C to 1650 ° C for 10 to 50 hours. 一種氧化物半導體薄膜,其係使用如請求項1至3中任一項之濺鍍靶且藉由濺鍍法進行成膜而成。 An oxide semiconductor thin film formed by sputtering using a sputtering target according to any one of claims 1 to 3. 如請求項5之氧化物半導體薄膜,其不溶於磷酸系蝕刻液,且可溶於草酸系蝕刻液。 The oxide semiconductor thin film according to claim 5, which is insoluble in the phosphoric acid-based etching liquid and soluble in the oxalic acid-based etching liquid. 如請求項6之氧化物半導體薄膜,其中利用上述磷酸系蝕刻液之於35℃之蝕刻速度為10nm/分鐘以下,且利用上述草酸蝕刻液之 於35℃之蝕刻速度為20nm/分鐘以上。 The oxide semiconductor thin film according to claim 6, wherein the etching rate of the phosphoric acid-based etching solution at 35 ° C is 10 nm/min or less, and the oxalic acid etching solution is used. The etching rate at 35 ° C is 20 nm / min or more. 一種氧化物半導體薄膜之製造方法,其係於含有選自水蒸氣、氧氣及一氧化二氮氣體中之1種以上與稀有氣體之混合氣體之環境下,使用如請求項1至3中任一項之濺鍍靶藉濺鍍法進行成膜。 A method for producing an oxide semiconductor thin film, which is used in an environment containing a mixed gas of one or more selected from the group consisting of water vapor, oxygen, and nitrous oxide gas and a rare gas, using any one of claims 1 to 3 The sputtering target of the item is formed by sputtering. 如請求項8之氧化物半導體薄膜之製造方法,其於至少含有水蒸氣及稀有氣體之混合氣體的環境下進行上述氧化物半導體薄膜之成膜。 The method for producing an oxide semiconductor thin film according to claim 8, wherein the oxide semiconductor thin film is formed in an atmosphere containing at least a mixed gas of water vapor and a rare gas. 如請求項8或9之氧化物半導體薄膜之製造方法,其中上述混合氣體中所含之水蒸氣之比率以分壓比計為0.1%~25%。 The method for producing an oxide semiconductor thin film according to claim 8 or 9, wherein the ratio of the water vapor contained in the mixed gas is 0.1% to 25% in terms of a partial pressure ratio. 如請求項8之氧化物半導體薄膜之製造方法,其中上述混合氣體中所含之氧氣之比率以分壓比計為0.1%~30%。 The method for producing an oxide semiconductor thin film according to claim 8, wherein the ratio of the oxygen contained in the mixed gas is 0.1% to 30% in terms of a partial pressure ratio. 如請求項8之氧化物半導體薄膜之製造方法,其中藉由如下濺鍍方法而進行上述氧化物半導體薄膜之成膜,該濺鍍方法係將基板依序搬送至與隔開特定間隔而並排設置於真空腔室內之3片以上之靶對向之位置,於自交流電源對上述各靶交替施加負電位及正電位之情形時,一面將來自上述交流電源之輸出之至少1者分支而於連接之2片以上之靶間進行施加電位之靶之切換,一面於靶上產生電漿而於基板表面成膜。 The method for producing an oxide semiconductor thin film according to claim 8, wherein the film formation of the oxide semiconductor thin film is carried out by a sputtering method in which the substrates are sequentially transferred to a predetermined interval and arranged side by side. When three or more targets in the vacuum chamber are opposed to each other, when a negative potential and a positive potential are alternately applied to the respective targets from the AC power source, at least one of the outputs from the AC power source is branched and connected. When two or more targets are switched between the targets to which the potential is applied, plasma is generated on the target to form a film on the surface of the substrate. 如請求項12之氧化物半導體薄膜之製造方法,其中上述交流電源之交流功率密度為3W/cm2以上且20W/cm2以下。 The method of producing an oxide semiconductor thin film according to claim 12, wherein the AC power source has an AC power density of 3 W/cm 2 or more and 20 W/cm 2 or less. 如請求項12或13之氧化物半導體薄膜之製造方法,其中上述交流電源之頻率為10kHz~1MHz。 The method of manufacturing an oxide semiconductor thin film according to claim 12 or 13, wherein the frequency of the alternating current power source is 10 kHz to 1 MHz. 一種薄膜電晶體,其具有如請求項5至7中任一項之氧化物半導體薄膜作為通道層。 A thin film transistor having the oxide semiconductor film according to any one of claims 5 to 7 as a channel layer. 如請求項15之薄膜電晶體,其中場效移動度為10cm2/Vs以上。 The thin film transistor of claim 15, wherein the field effect mobility is 10 cm 2 /Vs or more. 一種薄膜電晶體,其於如請求項5至7中任一項之氧化物半導體薄膜上具有至少含有SiNx(x為任意數)之保護膜。 A thin film transistor having a protective film containing at least SiN x (x is an arbitrary number) on the oxide semiconductor thin film according to any one of claims 5 to 7. 一種薄膜電晶體之製造方法,其係使用如請求項5至7中任一項之氧化物半導體薄膜作為半導體活性層之薄膜電晶體之製造方法,且包括如下步驟:不於上述半導體薄膜上積層蝕刻終止層,而使用不同之蝕刻液使上述半導體薄膜及電極圖案化,且於使電極圖案化時蝕刻液直接接觸於上述半導體薄膜。 A method of producing a thin film transistor using the oxide semiconductor thin film according to any one of claims 5 to 7 as a method of manufacturing a thin film transistor of a semiconductor active layer, comprising the steps of: laminating no layer on the semiconductor thin film The termination layer is etched, and the semiconductor thin film and the electrode are patterned using different etching liquids, and the etching liquid directly contacts the semiconductor thin film when the electrode is patterned. 一種顯示裝置,其具備如請求項15至17中任一項之薄膜電晶體。 A display device comprising the thin film transistor according to any one of claims 15 to 17.
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US11309181B2 (en) 2016-06-06 2022-04-19 Semiconductor Energy Laboratory Co., Ltd. Sputtering apparatus, sputtering target, and method for forming semiconductor film with the sputtering apparatus

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TWI760539B (en) * 2017-08-01 2022-04-11 日本商出光興產股份有限公司 Sputtering targets, oxide semiconductor thin films, thin film transistors and electronic equipment

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