WO2014073210A1 - Sputtering target, oxide semiconductor thin film, and methods for producing these products - Google Patents

Sputtering target, oxide semiconductor thin film, and methods for producing these products Download PDF

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WO2014073210A1
WO2014073210A1 PCT/JP2013/006573 JP2013006573W WO2014073210A1 WO 2014073210 A1 WO2014073210 A1 WO 2014073210A1 JP 2013006573 W JP2013006573 W JP 2013006573W WO 2014073210 A1 WO2014073210 A1 WO 2014073210A1
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thin film
oxide semiconductor
semiconductor thin
sputtering
sputtering target
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PCT/JP2013/006573
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French (fr)
Japanese (ja)
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望 但馬
一晃 江端
麻美 西村
美佐 砂川
将之 糸瀬
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出光興産株式会社
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    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34Sputtering
    • C23C14/3407Cathode assembly for sputtering apparatus, e.g. Target
    • C23C14/3414Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
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    • C04B35/01Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
    • C04B35/453Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on zinc, tin, or bismuth oxides or solid solutions thereof with other oxides, e.g. zincates, stannates or bismuthates
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    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Definitions

  • the present invention relates to a sputtering target for producing an oxide thin film such as an oxide semiconductor or a transparent conductive film, a thin film produced using the target, a thin film transistor including the thin film, and a method for producing them.
  • TFTs thin film transistors
  • LCD liquid crystal display devices
  • EL electroluminescence display devices
  • FED field emission displays
  • a silicon semiconductor compound As a material for a semiconductor layer (channel layer) which is a main member of a field effect transistor, a silicon semiconductor compound is most widely used.
  • a silicon single crystal is used for a high-frequency amplifying element or an integrated circuit element that requires high-speed operation.
  • an amorphous silicon semiconductor (amorphous silicon) is used for a liquid crystal driving element or the like because of a demand for a large area.
  • an amorphous silicon thin film can be formed at a relatively low temperature, its switching speed is slower than that of a crystalline thin film, so when used as a switching element for driving a display device, it may not be able to follow the display of high-speed movies. is there.
  • amorphous silicon having a mobility of 0.5 to 1 cm 2 / Vs could be used, but when the resolution is SXGA, UXGA, QXGA or higher, 2 cm 2 / Mobility greater than Vs is required.
  • the driving frequency is increased in order to improve the image quality, higher mobility is required.
  • the crystalline silicon-based thin film has a high mobility
  • problems such as requiring a large amount of energy and the number of processes for manufacturing, and a problem that it is difficult to increase the area.
  • laser annealing using a high temperature of 800 ° C. or higher and expensive equipment is necessary.
  • a crystalline silicon-based thin film is difficult to reduce costs such as a reduction in the number of masks because the element configuration of a TFT is usually limited to a top gate configuration.
  • Patent Documents 1 to 3 a thin film transistor using an oxide semiconductor thin film containing indium oxide, tin oxide, and zinc oxide has been studied (for example, Patent Documents 1 to 3). It has been reported that this thin film has selective etching properties (for example, Patent Document 1).
  • the electrode can be patterned by wet etching (back channel etching) without stacking an etching stopper on the oxide semiconductor thin film, thereby reducing the mask process when manufacturing the thin film transistor. In addition, the cost can be reduced and the productivity can be improved.
  • the oxide semiconductor thin film containing indium oxide, tin oxide, and zinc oxide of the prior art is likely to be crystallized when the amount of indium is increased, and the etching rate with the oxalic acid-based etching solution is slow, and the residue is likely to remain. For this reason, it was necessary to limit the amount of In to a limited range. For this reason, it was difficult to improve mobility.
  • An object of the present invention is to provide a sputtering target that contains indium oxide, tin oxide, and zinc oxide and realizes good TFT characteristics in a wide range of In amount. Furthermore, it aims at providing the sputtering target which can manufacture TFT which has a favorable characteristic by a back channel etching method.
  • a bixbite structure composed of an oxide containing at least one element X selected from indium element (In), tin element (Sn), zinc element (Zn), and the following group X, and represented by In 2 O 3
  • a sputtering target comprising a compound and a spinel structure compound.
  • X group Mg, Al, Ga, Si, Sc, Ti, Y, Zr, Hf, Ta, La, Nd, Sm 2.
  • the oxide semiconductor thin film according to 8 which is insoluble in a phosphoric acid etching solution and is soluble in an oxalic acid etching solution. 10. 10. The oxide semiconductor thin film according to 9, wherein an etching rate at 35 ° C. with the phosphoric acid-based etching solution is 10 nm / min or less and an etching rate at 35 ° C. with the oxalic acid etching solution is 20 nm / min or more. 11. Oxidation formed by sputtering using a sputtering target according to any one of 1 to 7 in an atmosphere of a mixed gas containing one or more selected from water vapor, oxygen gas and nitrous oxide gas and a rare gas Method for manufacturing a semiconductor thin film. 12 12.
  • At least one of the outputs from the AC power supply is switched between two or more targets that are branched and connected while switching the target to which the potential is applied.
  • 15. The method for producing an oxide semiconductor thin film according to any one of 11 to 14, which is performed by a sputtering method in which plasma is generated on a target to form a film on a substrate surface. 16. 16.
  • 16. The method for producing an oxide semiconductor thin film according to 15, wherein the AC power density of the AC power source is 3 W / cm 2 or more and 20 W / cm 2 or less.
  • 17. 17 The method for producing an oxide semiconductor thin film according to 15 or 16, wherein the frequency of the AC power source is 10 kHz to 1 MHz.
  • a method of manufacturing a thin film transistor comprising a step of patterning using an etching solution, and the step of contacting the semiconductor thin film directly with the etching solution when patterning an electrode. 22.
  • a display device comprising the thin film transistor according to any one of 18.18 to 20.
  • a sputtering target that includes indium oxide, tin oxide, and zinc oxide and realizes good TFT characteristics in a wide range of In amount.
  • a sputtering target capable of manufacturing a TFT having favorable characteristics by a back channel etching method.
  • Example 2 is an X-ray chart of a sintered body obtained in Example 1.
  • 3 is an X-ray chart of a sintered body obtained in Example 2.
  • 4 is an X-ray chart of a sintered body obtained in Example 3.
  • 6 is an X-ray chart of a sintered body obtained in Example 4.
  • 6 is an X-ray chart of a sintered body obtained in Example 5.
  • 6 is an X-ray chart of a sintered body obtained in Example 6.
  • 6 is an X-ray chart of a sintered body obtained in Example 7.
  • 6 is an X-ray chart of a sintered body obtained in Example 8.
  • 10 is an X-ray chart of a sintered body obtained in Example 9. It is a figure which shows the sputtering device used for one Embodiment of this invention.
  • the present invention is not limited to the following embodiments and examples.
  • the sputtering target of the present invention is composed of an oxide containing indium element (In), tin element, (Sn), zinc element (Zn), and one or more elements X selected from the following group X, and includes In 2 O 3.
  • the bixbite structure compound represented by these and a spinel structure compound are included.
  • X group Mg, Al, Ga, Si, Sc, Ti, Y, Zr, Hf, Ta, La, Nd, Sm
  • the presence or absence of the bixbite structure compound and the spinel structure compound can be confirmed by X-ray diffraction.
  • the atomic ratio of indium element, tin element, zinc element and element X preferably satisfies the following formulas (1) to (4). 0.20 ⁇ In / (In + Sn + Zn + X) ⁇ 0.85 (1) 0.01 ⁇ Sn / (In + Sn + Zn + X) ⁇ 0.35 (2) 0.01 ⁇ Zn / (In + Sn + Zn + X) ⁇ 0.70 (3) 0.01 ⁇ X / (In + Sn + Zn + X) ⁇ 0.30 (4) (In the formula, In, Sn, Zn, and X each represent an atomic ratio of each element in the sputtering target.)
  • the amount of In element is 0.20 or more, the bulk resistance value of the sputtering target is hardly increased, and DC sputtering is possible.
  • the amount of In element is 0.85 or less, it is difficult to form a conductor due to an increase in carrier concentration of a thin film produced using the target, and it can be used as a semiconductor thin film.
  • the In concentration is preferably 0.20 ⁇ In / (In + Sn + Zn + X) ⁇ 0.85.
  • the amount of In element [In / (In + Sn + Zn + X)] is preferably 0.20 to 0.75, and more preferably 0.25 to 0.60.
  • the Sn concentration is preferably 0.01 ⁇ Sn / (In + Sn + Zn + X) ⁇ 0.35.
  • the amount of Sn element [Sn / (In + Sn + Zn + X)] is preferably 0.03 to 0.30, and more preferably 0.05 to 0.25.
  • the amount of Zn element is 0.01 or more, the target density is improved and the target resistance is easily lowered, so that DC sputtering can be performed.
  • the amount of Zn element is 0.70 or less, the dissolution rate of the obtained thin film in the etching solution is too fast, and wet etching is not difficult.
  • the Zn concentration is preferably 0.01 ⁇ Zn / (In + Sn + Zn + X) ⁇ 0.70.
  • the amount of Zn element [Zn / (In + Sn + Zn + X)] is preferably 0.03 to 0.60, and more preferably 0.05 to 0.60.
  • the concentration of X is preferably 0.01 ⁇ X / (In + Sn + Zn + X) ⁇ 0.30.
  • the amount of the element X [X / (In + Sn + Zn + X)] is preferably 0.02 to 0.27, and more preferably 0.02 to 0.25.
  • the bixbite structure means that the X-ray diffraction pattern of the sintered body matches the crystal structure of the bixbital diffraction pattern obtained from JCPDS (Joint Committee of Powder Diffraction Standards) card or The Inorganic Crystal Structure Database (ICSD). Can be confirmed.
  • Examples of the compound having a bixbite structure include In 2 O 3 .
  • Bixbyte is also referred to as rare earth oxide C-type or Mn 2 O 3 (I) -type oxide.
  • the stoichiometric ratio is M 2 X 3 (M is a cation, X is an anion, usually an oxygen ion), and one unit cell is composed of 16 molecules of M 2 X 3 , a total of 80 atoms (M is 32, X is 48) Yes.
  • the bixbite structure is X-ray diffraction, and is No. of JCPDS database. A peak pattern of 06-0416 or a similar (shifted) pattern is shown.
  • the bixbite structure compound also includes a substitutional solid solution in which atoms and ions in the crystal structure are partially substituted with other atoms, and an interstitial solid solution in which other atoms are added to interstitial positions.
  • the spinel structure can be confirmed by observing the peak of the spinel structure compound as a result of X-ray diffraction measurement of the sintered body.
  • the spinel structure is described in detail in “Introduction to West Solid Chemistry” (Kodansha Scientific). According to this, the spinel structure is as follows.
  • Spinel has a composition formula of AB 2 O 4 and is classified into a normal spinel structure, a reverse spinel structure, and an intermediate structure between the two when classified according to the coordination state of A ions and B ions.
  • the regular spinel has a structure in which A is filled in one-eighth of the tetrahedral gap of the solid face-centered lattice formed by O 2 ⁇ and B is filled in one-half of the octahedral gap.
  • the reverse spinel structure has a structure in which one-eighth of the tetrahedral gap is filled with B and half of the octahedral gap is filled with A and B.
  • it is a cubic crystal, but some of the cubic crystals are distorted.
  • the spinel structure compound also included in the spinel structure compound are substituted solid solutions in which atoms and ions in the crystal structure are partially substituted with other atoms, and interstitial solid solutions in which other atoms are added to interstitial positions.
  • the spinel structure compound include ZnAl 2 O 4 , Zn 2 SnO 4 , MgIn 2 O 4 , Zn 2 TiO 4 , ZnGa 2 O 4 , Zn 2 SiO 4 and the like.
  • the spinel structure of ZnAl 2 O 4 is X-ray diffraction, and the JCPDS database No. It shows a peak pattern of 05-0669 or a similar (shifted) pattern.
  • other spinel structures show an X-ray pattern obtained from JCPDS or ICSD by X-ray diffraction or a similar (shifted) pattern.
  • the sputtering target of the present invention contains a bixbite structure compound represented by In 2 O 3 , the element X can easily form a bixbite structure and a substitutional solid solution or an interstitial solid solution, thereby increasing the resistance of the target. It is possible to prevent the oxide of the element X from appearing alone.
  • the inclusion of the spinel structure compound makes it easier for the element X to form a spinel structure and a substitutional solid solution or an interstitial solid solution, and the oxide of the element X that may increase the resistance of the target appears alone. Can be prevented.
  • the element X hardly forms a crystal structure with In, Sn, Zn, and even if the oxide of the element X tends to appear alone,
  • the resistance of the target can be lowered.
  • the amount of element X added can be increased, and an excellent semiconductor thin film can be produced without increasing the oxygen partial pressure during film formation.
  • the element X further constitutes a spinel structure such as XIn 2 O 4 , ZnX 2 O 4 , Zn 2 XO 4 , that is, the spinel structure compound is XIn 2 O. 4 , ZnX 2 O 4 , or Zn 2 XO 4 , which makes it difficult for an oxide of element X to appear alone, and makes a high-density, low-resistance target even if the amount of element X is large. Can do.
  • a spinel structure such as XIn 2 O 4 , ZnX 2 O 4 , Zn 2 XO 4 , that is, the spinel structure compound is XIn 2 O. 4 , ZnX 2 O 4 , or Zn 2 XO 4 , which makes it difficult for an oxide of element X to appear alone, and makes a high-density, low-resistance target even if the amount of element X is large. Can do.
  • the element X is preferably Mg, Al, Ti, Si, or Ga. Thereby, it can be set as a high-density and low-resistance target. This is presumably because the element X is likely to form a bixbite or spinel structure compound and a substitutional solid solution or an interstitial solid solution, or the element X is likely to form a spinel structure.
  • the element X is Al and the spinel structure compound is ZnAl 2 O 4 .
  • the target of the present invention may also include a well if it contains bixbyite structure compound and spinel structural compound represented by an In 2 O 3, other crystalline phases.
  • the atomic ratio of each element contained in the sputtering target can be determined by quantitative analysis of the contained elements using an inductively coupled plasma emission spectrometer (ICP-AES). Specifically, when a solution sample is atomized with a nebulizer and introduced into an argon plasma (about 6000 to 8000 ° C.), the elements in the sample are excited by absorbing thermal energy, and orbital electrons have a high energy from the ground state. Move to the level orbit. These orbital electrons move to a lower energy level orbit in about 10 ⁇ 7 to 10 ⁇ 8 seconds. At this time, the energy difference is emitted as light to emit light. Since this light shows a wavelength (spectral line) unique to the element, the presence of the element can be confirmed by the presence or absence of the spectral line (qualitative analysis).
  • ICP-AES inductively coupled plasma emission spectrometer
  • the sample concentration can be obtained by comparing with a standard solution having a known concentration (quantitative analysis). After identifying the elements contained in the qualitative analysis, the content is obtained by quantitative analysis, and the atomic ratio of each element is obtained from the result.
  • the metal element contained in the sputtering target is substantially composed of In, Sn, Zn, and metal X, and may contain other inevitable impurities as long as the effects of the present invention are not impaired.
  • “substantially” means that the effect as a sputtering target is caused by the above In, Sn, Zn and element X, or 95% by weight to 100% by weight (preferably 98% by weight) of the metal element of the sputtering target. % Or more and 100% by weight or less) means In, Sn, Zn, and element X.
  • the sputtering target used in the present invention preferably has a relative density of 98% or more.
  • the relative density is preferably 98% or more.
  • the relative density is a density calculated relative to the theoretical density calculated from the weighted average.
  • the density calculated from the weighted average of the density of each raw material is the theoretical density, which is defined as 100%.
  • the relative density is 98% or more, a stable sputtering state is maintained.
  • the target surface may be blackened or abnormal discharge may occur if the relative density is less than 98%.
  • the relative density is preferably 98.5% or more, more preferably 99% or more.
  • the relative density can be measured by Archimedes method.
  • the relative density is preferably 100% or less. If it is 100% or less, metal particles are less likely to be generated in the sintered body and lower oxides are less likely to be produced, and it is not necessary to strictly adjust the oxygen supply amount during film formation.
  • the density can be adjusted by performing a post-treatment step such as a heat treatment operation under a reducing atmosphere.
  • a post-treatment step such as a heat treatment operation under a reducing atmosphere.
  • a reducing atmosphere an atmosphere of argon, nitrogen, hydrogen, or a mixed gas atmosphere thereof is used.
  • the sputtering target of the present invention has a relative density of 98% or more and a bulk specific resistance of 10 m ⁇ cm or less.
  • the sputtering target of the present invention can form a high-quality oxide semiconductor thin film efficiently, inexpensively and with energy saving.
  • a bulk specific resistance can be measured by the method as described in an Example, for example.
  • the bulk specific resistance is preferably 5 m ⁇ cm or less.
  • the maximum crystal grain size in the sputtering target of the present invention is 8 ⁇ m or less. Generation of nodules can be prevented if the crystal has a particle size of 8 ⁇ m or less.
  • the cutting speed varies depending on the direction of the crystal plane, and irregularities are generated on the target surface.
  • the size of the unevenness depends on the crystal grain size present in the sputtering target. In the target having a large crystal grain size, the unevenness is increased, and it is considered that nodules are generated from the convex portion.
  • the maximum grain size of these sputtering target crystals is the center point (one place) of the circle and the center point and the peripheral part on two center lines orthogonal to the center point.
  • the central point (one location) and the intermediate point (4) between the central point and the corner on the diagonal of the quadrangle is measured, and is expressed as an average value of the particle sizes of the maximum particles present in each of these five locations.
  • the particle size is measured for the major axis of the crystal grains.
  • the crystal grains can be observed with a scanning electron microscope (SEM).
  • the manufacturing method of the sputtering target of the present invention includes the following two steps. (1) Step of mixing raw material compounds and molding to form a molded body (2) Step of sintering the molded body
  • the raw material compound is not particularly limited, and is a compound containing In, Sn, Zn and element X, and the sintered body has the following atomic ratio.
  • a compound that can be used may be used.
  • a combination of indium oxide, tin oxide, zinc oxide and a single element X, a combination of indium oxide, tin oxide, zinc oxide and an oxide of element X, or the like can be given.
  • the raw material is preferably a powder, and more preferably a mixed powder of indium oxide, tin oxide, zinc oxide and an oxide of element X.
  • a single metal is used as a raw material
  • a combination of indium oxide, tin oxide, zinc oxide and a single element X is used as a raw material powder
  • grains of the single element X exist in the obtained sintered body
  • the metal particles on the target surface may melt and not be released from the target, and the composition of the resulting film and the composition of the sintered body may differ greatly.
  • the average particle diameter of the raw material powder is preferably 0.1 ⁇ m to 1.2 ⁇ m, more preferably 0.1 ⁇ m to 1.0 ⁇ m or less.
  • the average particle diameter of the raw material powder can be measured with a laser diffraction type particle size distribution apparatus or the like.
  • an oxide containing an element X oxide powder having an average particle diameter of 0.1 ⁇ m to 1.2 ⁇ m is used as a raw material powder, and these are prepared at a ratio satisfying the above formulas (1) to (4).
  • the mixing and forming method in step (1) is not particularly limited, and can be performed using a known method.
  • an aqueous solvent is blended into a raw material powder containing a mixed powder of oxide containing indium oxide powder, tin oxide, zinc oxide and oxide powder of element X, and the resulting slurry is mixed for 12 hours or more. Solid-liquid separation, drying, and granulation are performed, and then this granulated product is put into a mold and molded.
  • a wet or dry ball mill, vibration mill, bead mill, or the like can be used.
  • a bead mill mixing method is most preferable because the crushing efficiency of the agglomerates is high in a short time and the additive is well dispersed.
  • the mixing time by the ball mill is preferably 15 hours or more, more preferably 19 hours or more. This is because if the mixing time is insufficient, a high resistance compound such as an oxide of metal X may be formed in the finally obtained sintered body.
  • the pulverization and mixing time by the bead mill varies depending on the size of the apparatus and the amount of slurry to be processed, but is appropriately adjusted so that the particle size distribution in the slurry is all uniform at 1 ⁇ m or less.
  • binder polyvinyl alcohol, vinyl acetate, or the like can be used.
  • granulated powder is obtained from the raw material powder slurry.
  • rapid drying granulation it is preferable to perform rapid drying granulation.
  • a spray dryer is widely used as an apparatus for rapid drying granulation. Since specific drying conditions are determined by various conditions such as the slurry concentration of the slurry to be dried, the temperature of hot air used for drying, and the amount of air, it is necessary to obtain optimum conditions in advance.
  • the sedimentation speed varies depending on the specific gravity difference of the raw material powder, so that separation of In 2 O 3 powder, Sn 2 O 2 powder, ZnO powder and metal X oxide powder occurs, and uniform granulated powder is formed. There is a risk that it will not be obtained.
  • an oxide of element X or the like is present inside the sintered body, which may cause abnormal discharge in sputtering.
  • the granulated powder is usually molded by a die press or cold isostatic press (CIP) at a pressure of, for example, 1.2 ton / cm 2 or more to obtain a molded body. The pressure may be greater than this value.
  • the obtained molded product can be sintered at a sintering temperature of 1200 to 1650 ° C. for 10 to 50 hours to obtain a sintered body.
  • the sintering temperature is preferably 1300 to 1600 ° C, more preferably 1350 to 1550 ° C, and still more preferably 1400 to 1500 ° C.
  • the sintering time is preferably 12 to 40 hours, more preferably 13 to 30 hours.
  • the sintering temperature is 1200 ° C. or more and the sintering time is 10 hours or more, the oxide of the element X or the like is hardly formed inside the target, and an abnormal discharge hardly occurs.
  • the firing temperature is 1650 ° C. or less and the firing time is 50 hours or less, the increase in the average crystal grain size due to remarkable crystal grain growth, the generation of coarse pores, etc. can be suppressed, and the strength of the sintered body is reduced or abnormal. Discharge can be made difficult to occur.
  • a pressure sintering method such as hot press, oxygen pressurization, hot isostatic pressurization and the like can be employed in addition to the atmospheric pressure sintering method.
  • a normal pressure sintering method from the viewpoints of reducing manufacturing costs, possibility of mass production, and easy production of large sintered bodies.
  • the compact is sintered in an air atmosphere or an oxidizing gas atmosphere, preferably an oxidizing gas atmosphere.
  • the oxidizing gas atmosphere is preferably an oxygen gas atmosphere.
  • the oxygen gas atmosphere is preferably an atmosphere having an oxygen concentration of, for example, 10 to 100% by volume.
  • the density of the sintered body can be further increased by introducing an oxygen gas atmosphere in the temperature raising process.
  • the heating rate during sintering is from 800 ° C. to a sintering temperature (1200 to 1650 ° C.) of 0.1 to 2 ° C./min.
  • the temperature range above 800 ° C. is the range where the sintering proceeds most.
  • the rate of temperature rise in this temperature range is faster than 0.1 ° C./min, it becomes easy to prevent significant crystal grain growth and to increase the density.
  • the temperature increase rate slower than 2 ° C./min, it becomes easy to prevent the oxide of element X and the like from being precipitated inside the target, and the target resistance is likely to be lowered.
  • the heating rate from 800 ° C. to the sintering temperature is preferably 0.1 to 1.3 ° C./min, more preferably 0.1 to 1.1 ° C./min. Furthermore, it is preferable to add a calcining step of maintaining the temperature in the temperature range of 700 to 900 ° C. for 1 to 5 hours before raising the temperature to the sintering temperature (1200 to 1650 ° C.). Since heat shrinkage proceeds rapidly from around 800 ° C., maintaining the temperature in the temperature range of 700 to 900 ° C. for 1 to 5 hours can suppress the generation of pores, and the target resistance tends to decrease.
  • a reduction step may be provided as necessary.
  • the reduction method include a method using a reducing gas, vacuum firing, or reduction using an inert gas.
  • hydrogen, methane, carbon monoxide, a mixed gas of these gases and oxygen, or the like can be used.
  • the temperature during the reduction treatment is usually 100 to 800 ° C, preferably 200 to 800 ° C.
  • the reduction treatment time is usually 0.01 to 10 hours, preferably 0.05 to 5 hours.
  • an aqueous solvent is blended with a raw material powder containing a mixed powder of indium oxide powder, tin oxide powder, zinc oxide powder and oxide of element X, and the resulting slurry is mixed for 12 hours or more. Thereafter, solid-liquid separation, drying, and granulation are performed, and then this granulated product is put into a mold and molded. Thereafter, the obtained molded product is heated in an oxygen atmosphere from 800 ° C. to a sintering temperature.
  • the sintered body used in the present invention can be obtained by firing at 1200 to 1650 ° C. for 10 to 50 hours at 0.1 to 2 ° C./min. Further, it is preferable to add a calcining step for maintaining the temperature in the temperature range of 700 to 900 ° C. for 1 to 5 hours.
  • the sputtering target of the present invention can be obtained by processing the sintered body obtained above.
  • a sputtering target material can be obtained by cutting the sintered body into a shape suitable for mounting on a sputtering apparatus, and a sputtering target can be obtained by bonding the target material to a backing plate.
  • the sintered body is ground with, for example, a surface grinder to obtain a material having a surface roughness Ra of 0.5 ⁇ m or less.
  • the sputter surface of the target material may be further mirror-finished so that the average surface roughness Ra may be 1000 angstroms or less.
  • Mirror surface processing can be performed using a known polishing technique such as mechanical polishing, chemical polishing, mechanochemical polishing (a combination of mechanical polishing and chemical polishing). For example, polishing to # 2000 or more with a fixed abrasive polisher (polishing liquid: water), or lapping with loose abrasive lapping (abrasive: SiC paste, etc.), and then lapping by changing the abrasive to diamond paste Can be obtained.
  • a polishing method is not particularly limited.
  • the surface of the target material is preferably finished with a diamond grindstone of No. 200 to 10,000, and particularly preferably finished with a diamond grindstone of No. 400 to 5,000. If a diamond grindstone smaller than 200 or larger than 10,000 is used, the target material may be easily broken.
  • the target material has a surface roughness Ra of 0.5 ⁇ m or less and has a non-directional ground surface. If Ra is 0.5 ⁇ m or less and a non-directional polished surface is provided, there is little risk of abnormal discharge or generation of particles.
  • the obtained target material is cleaned. Air blow or running water washing can be used for the cleaning treatment. When removing foreign matter by air blow, it is possible to remove the foreign matter more effectively by suctioning with a dust collector from the opposite side of the nozzle.
  • ultrasonic cleaning and the like can also be performed.
  • This ultrasonic cleaning is effective by performing multiple oscillations at a frequency of 25 to 300 KHz.
  • the thickness of the target material is usually 2 to 20 mm, preferably 3 to 12 mm, particularly preferably 4 to 6 mm.
  • a sputtering target can be obtained by bonding the target material obtained as described above to a backing plate. Further, a plurality of target materials may be attached to one backing plate to substantially serve as one target.
  • the oxide semiconductor thin film of the present invention is formed by a sputtering method using the above-described sputtering target of the present invention.
  • the oxide semiconductor thin film of the present invention contains indium, tin, zinc, element X, and oxygen, and usually has an atomic ratio of (1) to (4).
  • the amount of In element is 0.20 or more, the mobility can be increased when the formed film is applied to the channel layer of the TFT.
  • the amount of In element is 0.85 or less, when the formed film is applied to the channel layer of the TFT, it becomes difficult to conduct and the TFT can be operated.
  • the amount of the element X when the amount of the element X is 0.01 or more, the carrier concentration in the film can be suppressed and the TFT can be easily operated. On the other hand, when the amount of the element X is 0.30 or less, the mobility is not lowered and good TFT characteristics can be obtained. Since the sputtering target of the present invention has high conductivity, a DC sputtering method having a high deposition rate can be applied.
  • the sputtering target of the present invention can be applied to an RF sputtering method, an AC sputtering method, and a pulsed DC sputtering method in addition to the DC sputtering method, and enables sputtering without abnormal discharge.
  • the oxide semiconductor thin film can also be manufactured by a vapor deposition method, an ion plating method, a pulse laser vapor deposition method, or the like using the above sputtering target.
  • a mixed gas of a rare gas such as argon and an oxidizing gas can be used.
  • the oxidizing gas include O 2 , CO 2 , O 3 , water vapor (H 2 O), and N 2 O.
  • the sputtering gas is preferably a mixed gas containing a rare gas and one or more selected from water vapor, oxygen gas and nitrous oxide gas, and more preferably a mixed gas containing at least a rare gas and water vapor.
  • the carrier concentration of the oxide semiconductor thin film is usually 10 19 cm ⁇ 3 or less, preferably 10 13 to 10 18 cm ⁇ 3 , more preferably 10 14 to 10 18 cm ⁇ 3 , and particularly preferably 10 13 cm ⁇ 3. 15 to 10 18 cm ⁇ 3 .
  • the carrier concentration of the oxide layer is 10 19 cm ⁇ 3 or less, generation of leakage current can be suppressed when an element such as a thin film transistor is formed. Further, it is possible to prevent the normally-on state and the on-off ratio from becoming small. Further, when the carrier concentration is 10 13 cm ⁇ 3 or more, the number of carriers is sufficient and the TFT can be driven.
  • the carrier concentration of the oxide semiconductor thin film can be measured by a Hall effect measurement method.
  • the oxygen partial pressure ratio during sputtering film formation is preferably 0% or more and 30% or less.
  • a thin film manufactured under a condition where the oxygen partial pressure ratio exceeds 30% may significantly reduce the carrier concentration and the carrier concentration may be less than 10 13 cm ⁇ 3 .
  • the oxygen partial pressure ratio is preferably 0% to 30%, particularly preferably 0% to 20%.
  • the partial pressure ratio of water molecules contained in the sputtering gas (atmosphere) during oxide thin film deposition in the present invention are preferably 0.1 to 25%. Also, if the water partial pressure ratio is 25% or less, the film density can be prevented from decreasing, and the overlap of the 5s orbitals of In will not be reduced, so that the mobility is unlikely to decrease.
  • the partial pressure ratio of water in the atmosphere during sputtering is more preferably 0.7 to 13%, particularly preferably 1 to 6%.
  • the substrate temperature when forming a film by sputtering is preferably 25 to 120 ° C., more preferably 25 to 100 ° C., and particularly preferably 25 to 90 ° C. If the substrate temperature at the time of film formation is 120 ° C. or lower, it is possible to prevent the intake of oxygen or the like introduced at the time of film formation from being reduced, and the carrier concentration of the thin film after heating is easily reduced to 10 19 cm ⁇ 3 or lower. Further, if the substrate temperature during film formation is 25 ° C. or higher, the film density of the thin film does not decrease, and the mobility of the TFT is difficult to decrease.
  • the oxide thin film obtained by sputtering is preferably further annealed by holding at 150 to 500 ° C. for 15 minutes to 5 hours.
  • the annealing temperature after film formation is more preferably 200 ° C. or higher and 450 ° C. or lower, and further preferably 250 ° C. or higher and 350 ° C. or lower.
  • the atmosphere during heating is not particularly limited, but from the viewpoint of carrier controllability, an air atmosphere or an oxygen circulation atmosphere is preferable.
  • a lamp annealing device, a laser annealing device, a thermal plasma device, a hot air heating device, a contact heating device, or the like can be used in the presence or absence of oxygen.
  • the distance between the target and the substrate at the time of sputtering is preferably 1 to 15 cm, more preferably 2 to 8 cm in the direction perpendicular to the film formation surface of the substrate. If this distance is 1 cm or more, the kinetic energy of the target constituent element particles reaching the substrate does not become too large, and good film characteristics can be obtained, and the in-plane distribution of film thickness and electrical characteristics can be made uniform easily. Become. On the other hand, when the distance between the target and the substrate is 15 cm or less, the kinetic energy of the target constituent particles reaching the substrate is not too small, and a dense film can be obtained and good semiconductor characteristics can be obtained. .
  • the oxide thin film is preferably formed by sputtering in an atmosphere having a magnetic field strength of 300 to 1500 gauss.
  • the magnetic field strength is 300 gauss or more, the plasma density can be increased, so that even a high resistance sputtering target can be sputtered without problems.
  • the film thickness and the electrical characteristics in the film can be easily controlled.
  • the pressure in the gas atmosphere is not particularly limited as long as the plasma can be stably discharged, but is preferably 0.1 to 3.0 Pa, more preferably 0.1 to 1.5 Pa. Particularly preferred is 0.1 to 1.0 Pa. If the sputtering pressure is 3.0 Pa or less, the mean free path of sputtered particles can be lengthened and the density of the thin film can be easily improved. Moreover, when the sputtering pressure is 0.1 Pa or more, it becomes easy to prevent the formation of microcrystals in the film during film formation.
  • the sputtering pressure refers to the total pressure in the system at the start of sputtering after introducing a rare gas atom such as argon, water vapor, oxygen gas or the like.
  • the oxide semiconductor thin film may be formed by AC sputtering as described below.
  • the substrate is sequentially transported to a position facing three or more targets arranged in parallel at a predetermined interval in the vacuum chamber, and negative and positive potentials are alternately applied to each target from an AC power source. Then, plasma is generated on the target to form a film on the substrate surface.
  • an oxide semiconductor thin film is formed by AC sputtering
  • sputtering is performed in an atmosphere of a mixed gas containing a rare gas atom and one or more selected from water vapor, oxygen gas, and nitrous oxide gas. It is preferable to perform sputtering in a mixed gas atmosphere containing at least a rare gas and water vapor.
  • the AC sputtering apparatus described in Japanese Patent Laid-Open No. 2005-290550 includes a vacuum chamber, a substrate holder disposed inside the vacuum chamber, and a sputtering source disposed at a position facing the substrate holder. .
  • FIG. 10 shows a main part of the sputtering source of the AC sputtering apparatus.
  • the sputter source has a plurality of sputter units, each of which has plate-like targets 31a to 31f, and the surfaces to be sputtered of the targets 31a to 31f are sputter surfaces. It arrange
  • Each target 31a to 31f is formed in an elongated shape having a longitudinal direction, each target has the same shape, and edge portions (side surfaces) in the longitudinal direction of the sputtering surface are arranged in parallel with a predetermined interval therebetween. Therefore, the side surfaces of the adjacent targets 31a to 31f are parallel.
  • AC power supplies 17a to 17c are arranged outside the vacuum chamber, and one of the two terminals of each AC power supply 17a to 17c is connected to one of the two adjacent electrodes. The other terminal is connected to the other electrode.
  • Two terminals of each of the AC power supplies 17a to 17c output voltages of positive and negative different polarities, and the targets 31a to 31f are attached in close contact with the electrodes, so that the two adjacent targets 31a to 31f are adjacent to each other.
  • AC voltages having different polarities are applied from the AC power sources 17a to 17c. Therefore, when one of the targets 31a to 31f adjacent to each other is placed at a positive potential, the other is placed at a negative potential.
  • Magnetic field forming means 40a to 40f are disposed on the surface of the electrode opposite to the targets 31a to 31f.
  • Each of the magnetic field forming means 40a to 40f has an elongated ring-shaped magnet whose outer periphery is substantially equal to the outer periphery of the targets 31a to 31f, and a bar-shaped magnet shorter than the length of the ring-shaped magnet.
  • Each ring-shaped magnet is arranged in parallel with the longitudinal direction of the targets 31a to 31f at the position directly behind the corresponding one of the targets 31a to 31f. As described above, since the targets 31a to 31f are arranged in parallel at a predetermined interval, the ring magnets are also arranged at the same interval as the targets 31a to 31f.
  • the AC power density when an oxide target is used in AC sputtering is preferably 3 W / cm 2 or more and 20 W / cm 2 or less.
  • the power density is 3 W / cm 2 or more, the deposition rate can be increased, which is economical in production. It can prevent that a target breaks that it is 20 W / cm ⁇ 2 > or less.
  • a more preferable power density is 3 W / cm 2 to 15 W / cm 2 .
  • the frequency of AC sputtering is preferably in the range of 10 kHz to 1 MHz.
  • the frequency is 10 kHz or more, the problem of noise hardly occurs. If it does not exceed 1 MHz, it is possible to prevent the plasma from spreading too much, and it is possible to prevent the sputtering from being performed at a position other than the desired target position and the uniformity to be lost.
  • a more preferable frequency of AC sputtering is 20 kHz to 500 kHz. What is necessary is just to select suitably the conditions at the time of sputtering other than the above from what was mentioned above.
  • the oxide semiconductor thin film of the present invention is preferably insoluble in a phosphoric acid etching solution and soluble in an oxalic acid etching solution.
  • the oxide thin film is etched by oxalic acid-based etching because it has selectivity with respect to the etching liquid, and the electrode formed in this oxide thin film shape is further used with a phosphoric acid-based etching liquid. Patterning becomes possible.
  • “Insoluble in the etching solution” means that the etching rate at 35 ° C. is 10 nm / min or less, and “soluble in the etching solution” means that the etching rate at 35 ° C. is larger than 10 nm / min.
  • the etching rate at 35 ° C. with a phosphoric acid etching solution is less than 10 nm / min, more preferably 5 nm / min or less, and further preferably 1 nm / min or less, and 35 with the oxalic acid etching solution.
  • the etching solution at 20 ° C. is 20 nm / min or more, preferably 30 nm / min or more.
  • oxalic acid-based etching solution examples include ITO-06N (manufactured by Kanto Chemical Co., Inc.). Preferably, it contains 0.5 to 10 wt% oxalic acid. However, in addition to oxalic acid, carboxylic acid such as malonic acid, succinic acid, and acetic acid and other acids may be included, and oxalic acid is not necessarily included.
  • Examples of the phosphoric acid-based etching solution include PAN-based etching solutions containing phosphoric acid, acetic acid, and nitric acid.
  • the PAN-based etching solution is preferably in the range of 45 to 95 wt% phosphoric acid, 3 to 50 wt% acetic acid, and 0.5 to 5 wt% nitric acid.
  • the oxide semiconductor thin film of the present invention can be used for a thin film transistor, and can be particularly suitably used as a channel layer.
  • the element structure of the thin film transistor of the present invention is not particularly limited as long as it includes the above-described oxide semiconductor thin film of the present invention as a channel layer, and various known element structures can be employed.
  • the thickness of the channel layer in the thin film transistor of the present invention is usually 10 to 300 nm, preferably 20 to 250 nm, more preferably 30 to 200 nm, still more preferably 35 to 120 nm, and particularly preferably 40 to 80 nm.
  • the thickness of the channel layer is 10 nm or more, the non-uniformity of the film thickness when the film is formed in a large area can be reduced, and the characteristics of the manufactured TFT can be prevented from becoming non-uniform in the plane.
  • the film thickness is 300 nm or less, the film formation time does not become too long, which is industrially advantageous.
  • the channel layer in the thin film transistor of the present invention is usually used in an N-type region, but a PN junction transistor or the like in combination with various P-type semiconductors such as a P-type Si-based semiconductor, a P-type oxide semiconductor, and a P-type organic semiconductor. It can be used for various semiconductor devices.
  • the channel layer of the thin film transistor of the present invention may have any crystal composition. That is, it may be amorphous or crystalline. Further, at least part of the region overlapping with the gate electrode may be crystallized after the annealing treatment.
  • crystallization means that crystal nuclei are generated from an amorphous state or crystal grains are grown from a state where crystal nuclei are generated.
  • CVD process plasma process or the like
  • the crystallized region can be confirmed from, for example, an electron beam diffraction image of a transmission electron microscope (TEM).
  • the thin film transistor of the present invention preferably includes a protective film on the channel layer.
  • the protective film in the thin film transistor of the present invention preferably contains at least SiN x . Since SiN x can form a dense film as compared with SiO 2 , it has an advantage of a high TFT deterioration suppressing effect. Note that x is an arbitrary number, and the stoichiometric ratio of SiN x may not be constant.
  • the protective film may be, for example, SiO 2 , Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3 , Y 2 O 3 , HfO 2 , CaHfO 3 , PbTiO 3 , BaTa 2 O 6 , Sm 2 O 3 , SrTiO 3, or an oxide such as AlN can be included.
  • the oxide semiconductor thin film containing indium element (In) tin element (Sn), zinc element (Zn), and element X of the present invention contains element X, so that the reduction resistance by the CVD process is improved, and protection is achieved.
  • the back channel side is not easily reduced by the process of forming the film, and SiN x can be used as the protective film.
  • the channel layer is preferably subjected to ozone treatment, oxygen plasma treatment, nitrogen dioxide plasma treatment or nitrous oxide plasma treatment.
  • ozone treatment oxygen plasma treatment, nitrogen dioxide plasma treatment or nitrous oxide plasma treatment.
  • Such treatment may be performed at any timing after the channel layer is formed and before the protective film is formed, but is preferably performed immediately before the protective film is formed. By performing such pretreatment, generation of oxygen defects in the channel layer can be suppressed.
  • the threshold voltage may shift and the reliability of the TFT may be reduced.
  • a thin film transistor usually includes a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer (channel layer), a source electrode, and a drain electrode.
  • the channel layer is as described above, and a known material can be used for the substrate.
  • the material for forming the gate insulating film in the thin film transistor of the present invention is not particularly limited, and a commonly used material can be arbitrarily selected. Specifically, for example, SiO 2, SiN x, Al 2 O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Compounds such as Sc 2 O 3 , Y 2 O 3 , HfO 2 , CaHfO 3 , PbTiO 3 , BaTa 2 O 6 , SrTiO 3 , Sm 2 O 3 , and AlN can be used.
  • SiO 2 , SiN x , Al 2 O 3 , Y 2 O 3 , HfO 2 and CaHfO 3 are preferable, and SiO 2 , SiN x , HfO 2 and Al 2 O 3 are more preferable.
  • the gate insulating film can be formed by, for example, a plasma CVD (Chemical Vapor Deposition) method.
  • a gate insulating film is formed by plasma CVD and a channel layer is formed on the gate insulating film, hydrogen in the gate insulating film may diffuse into the channel layer, leading to deterioration in channel layer quality and TFT reliability. is there.
  • the gate insulating film may be subjected to ozone treatment, oxygen plasma treatment, nitrogen dioxide plasma treatment or nitrous oxide plasma treatment before forming the channel layer. preferable. By performing such pretreatment, it is possible to prevent deterioration of the channel layer film quality and TFT reliability.
  • the gate insulating film may have a structure in which two or more insulating films made of different materials are stacked.
  • the gate insulating film may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that can be easily manufactured industrially.
  • each of the drain electrode, the source electrode, and the gate electrode in the thin film transistor of the present invention there are no particular limitations on the material for forming each of the drain electrode, the source electrode, and the gate electrode in the thin film transistor of the present invention, and a commonly used material can be arbitrarily selected.
  • a transparent electrode such as ITO, IZO, ZnO, or SnO 2
  • a metal electrode such as Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, or Ta, or a metal electrode made of an alloy including these electrodes may be used. it can.
  • the thin film transistor of the present invention can be manufactured by back channel etching without forming an etching stopper on the oxide thin film which is an active layer by utilizing the etching solution selectivity of the oxide thin film.
  • Thin-film transistors using an active layer of a normal oxide semiconductor thin film such as an IGZO system prevent etching on the oxide semiconductor thin film because the oxide semiconductor thin film is also etched against the etchant used to etch the electrodes.
  • a normal oxide semiconductor thin film such as an IGZO system
  • Productivity has been reduced by including a step of forming an etching stopper.
  • the oxide semiconductor thin film of the present invention has a high productivity because it is not necessary to form an etching stopper by appropriately selecting an etching solution for patterning the semiconductor thin film and the electrode when a thin film transistor is manufactured. improves.
  • the semiconductor thin film and the electrode are patterned using different etching solutions without stacking the etching stopper on the semiconductor thin film, and the electrode is patterned.
  • it can be manufactured by a manufacturing method including a step in which the etching solution directly contacts the semiconductor thin film.
  • a solution capable of etching such as an oxalic acid-based etching solution is used for patterning the oxide thin film, while a transparent conductive material such as IZO, ZnO, SnO 2 is used for patterning the electrode.
  • Etching is possible for electrode materials such as oxides, metals such as Al, Ag, Cu, Cr, Ni, Mo, Ti, Ta, or alloys containing them, and etching is performed for the oxide thin films.
  • phosphoric acid etching it is not necessary to form an etching stopper because the semiconductor thin film is not etched even when the electrode etchant directly contacts the semiconductor thin film.
  • the drain electrode, the source electrode, and the gate electrode may have a multilayer structure in which two or more different conductive layers are stacked.
  • a good conductor such as Al or Cu may be sandwiched with a metal having excellent adhesion such as Ti or Mo.
  • the thin film transistor of the present invention preferably has an S value of 0.8 V / dec or less, more preferably 0.5 V / dec or less, further preferably 0.3 V / dec or less, and particularly preferably 0.2 V / dec or less. If it is 0.8 V / dec or less, the drive voltage becomes small and there is a possibility that power consumption can be reduced. In particular, when used in an organic EL display, it is preferable to set the S value to 0.3 V / dec or less because of direct current drive because power consumption can be greatly reduced.
  • the S value is a value indicating the steepness of the drain current that rises sharply from the off state to the on state when the gate voltage is increased from the off state.
  • S value dVg / dlog (Ids)
  • the smaller the S value, the sharper the rise (All about Thin Film Transistor Technology", Ikuhiro Ukai, 2007, Industrial Research Committee).
  • the S value is large, it is necessary to apply a high gate voltage when switching from on to off, and power consumption may increase.
  • the S value can be derived from the reciprocal of this slope by creating a Log (Id) -Vg graph from the result of the transfer characteristics.
  • the unit of the S value is V / decade and is preferably a small value.
  • the thin film transistor of the present invention preferably has a field effect mobility of 10 cm 2 / Vs or more, more preferably 15 cm 2 / Vs or more.
  • the field effect mobility can be measured by the method described in the examples.
  • the thin film transistor of the present invention can be applied to various integrated circuits such as a field effect transistor, a logic circuit, a memory circuit, and a differential amplifier circuit. Further, in addition to the field effect transistor, it can be applied to an electrostatic induction transistor, a Schottky barrier transistor, a Schottky diode, and a resistance element.
  • the structure of the thin film transistor of the present invention known structures such as a bottom gate, a bottom contact, and a top contact can be adopted without limitation.
  • the bottom gate structure is advantageous because high performance can be obtained as compared with thin film transistors of amorphous silicon or ZnO.
  • the bottom gate configuration is preferable because it is easy to reduce the number of masks at the time of manufacturing, and it is easy to reduce the manufacturing cost for uses such as a large display.
  • the thin film transistor of the present invention can be suitably used for a display device.
  • a channel-etched bottom-gate thin film transistor is particularly preferable.
  • a channel-etched bottom-gate thin film transistor has a small number of photomasks in the photolithography process, and can be manufactured at a low cost.
  • channel-etched bottom gate and top contact thin film transistors are particularly preferable because they have favorable characteristics such as mobility and are easily industrialized.
  • Examples 1 to 39 [Production of sintered body] The following powder was used as a raw material powder.
  • the average particle size of each powder was measured with a laser diffraction particle size distribution analyzer SALD-300V (manufactured by Shimadzu Corporation), and the median particle size was a median diameter D50.
  • Tin oxide powder average particle size 0.96 ⁇ m
  • Zinc oxide powder Average particle size 0.98 ⁇ m
  • Element X oxide powder average particle size 0.90 to 1.00 ⁇ m
  • Each of the above powders was weighed so as to have the atomic ratio (percentage) shown in Table 1, and was uniformly pulverized and mixed, and then granulated by adding a molding binder.
  • the raw material grains were uniformly filled in a mold and subjected to pressure molding with a cold press machine at a press pressure of 140 MPa.
  • the obtained molded body was sintered as follows. First, the compact was placed in a sintering furnace, and oxygen was introduced at a rate of 5 liters / minute per volume of 0.1 m 3 in the sintering furnace. The molded body was sintered at 1400 ° C. for 24 hours in this atmosphere.
  • the temperature in the sintering furnace was increased to 1 ° C./min up to 800 ° C., held at 800 ° C. for 3 hours, and then increased from 800 ° C. to 1400 ° C. at 1 ° C./min. Thereafter, after sintering at 1400 ° C. for 24 hours, the temperature lowering rate was 5 ° C./min.
  • An oxygen atmosphere was used during the temperature rise and the sintering temperature maintenance, and the atmosphere (atmosphere) was used during the temperature fall.
  • the relative density of the obtained sintered body was measured by the Archimedes method. It was confirmed that the sintered bodies of Examples 1 to 39 had a relative density of 98% or more. Further, the bulk specific resistance (conductivity) of the obtained sintered body was measured based on the four-probe method (JIS R 1637) using a resistivity meter (Made by Mitsubishi Chemical Corporation, Loresta). The results are shown in Table 1. As shown in Table 1, the bulk specific resistance of the sintered bodies of Examples 1 to 39 was 10 m ⁇ cm or less.
  • FIGS. The X-ray diffraction charts of the sintered bodies obtained in Examples 1 to 9 are shown in FIGS.
  • a bixbite structure of In 2 O 3 and a spinel structure of ZnAl 2 O 4 and a homologous structure of InAlZn 2 O 5 and InAlZnO 4 were observed in the sintered body of Example 1.
  • the crystal structure can be confirmed with a JCPDS (Joint Committee of Powder Diffraction Standards) card.
  • In 2 O 3 has a big byte structure of JCPDS card no.
  • the spinel structure of ZnAl 2 O 4 is JCPDS card no. 05-0669
  • the homologous structure of InAlZn 2 O 5 is JCPDS card no. 40-0259
  • the homologous structure of InAlZnO 4 is JCPDS card no. 40-0258.
  • Table 1 a bixbite structure and a spinel structure of In 2 O 3 were observed.
  • the bibyte structure of In 2 O 3 is JCPDS card no.
  • ZnAl 2 O 4 is JCPDS card no. 05-0669
  • Zn 2 SnO 4 is JCPDS card no. 24-1470
  • ZnGa 2 O 4 is JCPDS card no. No. 38-1240
  • MgIn 2 O 4 is JCPDS card No. 40-1402
  • Zn 2 SiO 4 is ICSD # 161024
  • Zn 2 TiO 4 is ICSD # 80849.
  • InAlZnO 4 is JCPDS card no. 40-0258
  • InAlZn 2 O 5 is JCPDS card no. 40-0259
  • In 2 Zn 2 O 5 is JCPDS card no. 20-1442
  • In 2 Zn 3 O 6 is JCPDS card no. 00-1140 or ICSD # 162450
  • In 2 Zn 4 O 7 is ICSD # 162451
  • InGaZnO 4 is ICSD # 9003
  • InGaZn 2 O 5 is ICSD # 380305
  • the pyrochlore structure of JCPDS card no. 20-1418, and the ZnSnO 3 ilmenite structure is JCPDS card no. 00-1197
  • In 2 TiO 4 is JCPDS card no. 30-0640.
  • SnO 2 is JCPDS card no. 00-1024
  • Al 2 O 3 is ICSD # 9770
  • MgO is JCPDS card no. Is 45-0946
  • Ga 2 O 3 is ICSD # 603563
  • TiO 2 is ICSD # 603563
  • SiO 2 is JCPDS card No. Is 33-1161
  • ZnO is ICSD # 57156
  • Sc 2 O 3 is ICSD # 24200
  • HfO 2 is ICSD # 27313
  • ZrO 2 is an ICSD # 66781.
  • the obtained sputtering target having a diameter of 4 inches was mounted on a DC sputtering apparatus, a mixed gas in which water vapor was added to argon gas at a partial pressure ratio of 2% as an atmosphere, a sputtering pressure of 0.4 Pa, a substrate temperature of room temperature, DC 10 kWh continuous sputtering was performed at an output of 400 W. Voltage fluctuations during sputtering were accumulated in a data logger, and the presence or absence of abnormal discharge was confirmed. The results are shown in Table 1.
  • the presence or absence of the abnormal discharge was performed by monitoring the voltage fluctuation and detecting the abnormal discharge.
  • the abnormal discharge was determined when the voltage fluctuation generated during the measurement time of 5 minutes was 10% or more of the steady voltage during the sputtering operation.
  • the steady-state voltage during sputtering operation varies by ⁇ 10% in 0.1 second, a micro arc, which is an abnormal discharge of the sputter discharge, has occurred, and the device yield may decrease, making it unsuitable for mass production. is there.
  • the sputtering conditions were a sputtering pressure of 0.4 Pa, a DC output of 100 W, and a substrate temperature of room temperature. Hydrogen gas was added to the atmospheric gas to promote the generation of nodules.
  • nodules For the nodules, a change in the target surface after sputtering was observed by magnifying it 50 times with a stereomicroscope, and a method of measuring the number average of nodules having a size of 20 ⁇ m or more generated in a visual field of 9 mm 2 was adopted. Table 1 shows the number of nodules generated.
  • Comparative Examples 1-11 Raw material powders were mixed at an atomic ratio (percentage) shown in Table 1, and a sintered body and a sputtering target were produced and evaluated in the same manner as in Example 1. The results are shown in Table 1. In the target of Comparative Example 1, a homologous structure of InAlZnO 4 , a corundum structure of Al 2 O 3 , and a rutile structure of SnO 2 were observed. The comparative examples 2 to 11 are also as shown in Table 1.
  • Comparative Examples 1 to 6 In the sputtering targets of Comparative Examples 1 to 6, abnormal discharge occurred during sputtering, and nodules were observed on the target surface. Comparative Examples 7 to 11 had high resistance and could not be discharged.
  • Examples 40-80 [Preparation of oxide semiconductor thin film] A 4-inch target having the composition shown in Table 2 prepared in Examples 1 to 39 was mounted on a magnetron sputtering apparatus, and a slide glass (# 1737 manufactured by Corning) was mounted as a substrate. An amorphous film having a thickness of 50 nm was formed on the slide glass by a DC magnetron sputtering method. As an atmosphere during film formation, a mixed gas in which O 2 gas and / or water vapor was introduced into Ar gas at a partial pressure ratio (%) shown in Table 2 was used.
  • the sputtering conditions are as follows. -Substrate temperature: 25 ° C -Ultimate pressure: 8.5 ⁇ 10 ⁇ 5 Pa Atmosphere gas: Ar gas, O 2 gas, water vapor mixed gas (see Table 2 for partial pressure ratio of O 2 gas and water vapor, Ar gas partial pressure ratio is the remainder) ⁇ Sputtering pressure (total pressure): 0.4 Pa -Input power: DC100W ⁇ S (substrate) -T (target) distance: 70 mm
  • XRD X-ray diffraction measurement
  • the substrate over which the amorphous film was formed was heated in the atmosphere at 300 ° C. for 60 minutes to form an oxide semiconductor film.
  • the substrate formed on this glass substrate was used as a Hall effect measurement element and set in ResiTest 8300 type (manufactured by Toyo Technica Co., Ltd.), and the Hall effect (Hall mobility) was evaluated at room temperature. ICP-AES analysis confirmed that the atomic ratio of each element contained in the oxide semiconductor thin film was the same as that of the sputtering target.
  • a conductive silicon substrate with a thermal oxide film having a thickness of 100 nm was used as the substrate.
  • the thermal oxide film functions as a gate insulating film
  • the conductive silicon portion functions as a gate electrode.
  • a 50 nm-thick amorphous thin film was formed by sputtering on the gate insulating film.
  • OFPR # 800 manufactured by Tokyo Ohka Kogyo Co., Ltd.
  • pre-baking 80 ° C., 5 minutes
  • exposure were performed. After development, it was post-baked (120 ° C., 5 minutes), etched with oxalic acid, and patterned into a desired shape. Thereafter, heat treatment (annealing treatment) was performed at 300 ° C. for 60 minutes in a hot air heating furnace.
  • Mo 100 nm
  • SiOx was formed into a protective film by plasma CVD method (PECVD). A contact hole was opened using hydrofluoric acid to produce a thin film transistor.
  • the etching rate was evaluated using the oxide semiconductor thin films of Examples 40 to 80 formed under the same conditions except that the thickness of the amorphous film was 100 nm.
  • An oxide semiconductor thin film was immersed in ITO-06N (Kanto Chemical Co., Ltd.), which is an oxalic acid-based etching solution, at 35 ° C., and the etching rate was calculated from the immersion time and the film thickness before and after the immersion.
  • a PAN etching solution (phosphoric acid 91.4 wt%, nitric acid 3.3 wt%, acetic acid 5.3 wt%) is set to 35 ° C., and the oxide semiconductor thin film is immersed, and the immersion time is as follows: The etching rate was calculated from the film thickness before and after the immersion.
  • Vth is the gate voltage (Vg) when the drain current (Id) is 1 nA.
  • the transfer characteristics of the mounted transistors were evaluated with a drain voltage (Vd) of 5 V and a gate voltage (Vg) of ⁇ 15 to 25 V. The results are shown in Table 2.
  • the field effect mobility ( ⁇ ) was calculated from the linear mobility and defined as the maximum value of Vg ⁇ .
  • the crystallinity of the channel layer of the thin film transistor was evaluated by an electron beam diffraction pattern using a cross-sectional TEM (Transmission Electron Microscope).
  • a cross-sectional TEM Transmission Electron Microscope
  • Hitachi field emission type transmission electron microscope HF-2100 was used.
  • the front channel side was amorphous from the observed diffraction pattern, but the diffraction pattern was partially observed on the back channel side, It was found to have a crystallized region.
  • the elements of Examples 40, 42 and 44 to 50 no diffraction pattern was observed on the front channel side and the back channel side, and it was confirmed that the elements were amorphous.
  • Comparative Examples 12-14 Each of the 4-inch targets prepared in Comparative Examples 1, 3, and 5 was used, except that the atmosphere during sputtering film formation was changed to a mixed gas of Ar gas and a gas having a partial pressure ratio shown in Table 2.
  • Example 40 Similarly, an oxide semiconductor thin film and a thin film transistor were manufactured and evaluated. The results are shown in Table 2.
  • Comparative Examples 12 to 14 have a field effect mobility of less than 10 cm 2 / Vs, which is significantly lower than Examples 40 to 80.
  • Examples 81-95 A thin film transistor was manufactured by performing AC sputtering using the film forming apparatus disclosed in Japanese Patent Laid-Open No. 2005-290550.
  • the atmosphere during AC sputtering is a mixed gas of Ar gas and a gas having a partial pressure ratio shown in Table 3, and the obtained amorphous film is subjected to heat treatment (annealing treatment) under the conditions shown in Table 3.
  • a thin film transistor was fabricated and evaluated in the same manner as in Examples 40-80 except that the drain patterning was performed by dry etching. The results are shown in Table 3. ICP-AES analysis confirmed that the atomic ratio of each element contained in the oxide thin film was the same as that of the sputtering target.
  • the six targets 31a to 31f having a width of 200 mm, a length of 1700 mm, and a thickness of 10 mm produced in Examples 1 to 11, 14, 22, 24, and 25 are parallel to each other as shown in FIG. They were arranged at intervals of 2 mm.
  • the width of the magnetic field forming means 40a to 40f was 200 mm, which is the same as that of the targets 31a to 31f.
  • Ar, water vapor and / or O 2 as sputtering gases were introduced into the system from the gas supply system.
  • the film forming atmosphere was 0.5 Pa
  • the frequency was 10 kHz.
  • the film formation rate was as high as 66 nm / min, which was suitable for mass production.
  • Comparative Examples 15-17 Using the six targets having a width of 200 mm, a length of 1700 mm, and a thickness of 10 mm prepared for Comparative Examples 1, 3, and 5, the sputtering conditions were changed to those shown in Table 3 and the same as in Example 81. An oxide semiconductor thin film and a thin film transistor were fabricated and evaluated. The results are shown in Table 3. As shown in Table 3, it can be seen that Comparative Examples 15 to 17 have a field effect mobility of less than 10 cm 2 / Vs, which is significantly lower than that of Examples 81 to 95.
  • PAN phosphoric acid 91.4 wt%, nitric acid 3.3 wt%, acetic acid 5.3 wt%
  • the sputtering target of the present invention can be used for production of oxide thin films such as oxide semiconductors and transparent conductive films.
  • the oxide thin film of the present invention can be used for a transparent electrode, a semiconductor layer of a thin film transistor, an oxide thin film layer, and the like.

Abstract

A sputtering target which comprises an oxide containing an indium element (In), a tin element (Sn), a zinc element (Zn) and at least one element (X) selected from the group (X) mentioned below, and contains a bixbyite structure compound represented by In2O3 and a spinel structure compound. Group (X): Mg, Al, Ga, Si, Sc, Ti, Y, Zr, Hf, Ta, La, Nd and Sm.

Description

スパッタリングターゲット、酸化物半導体薄膜及びそれらの製造方法Sputtering target, oxide semiconductor thin film, and manufacturing method thereof
 本発明は、酸化物半導体や透明導電膜等の酸化物薄膜作製用のスパッタリングターゲット、そのターゲットを用いて作製される薄膜、その薄膜を含む薄膜トランジスタ及びそれらの製造方法に関する。 The present invention relates to a sputtering target for producing an oxide thin film such as an oxide semiconductor or a transparent conductive film, a thin film produced using the target, a thin film transistor including the thin film, and a method for producing them.
 薄膜トランジスタ(TFT)等の電界効果型トランジスタは、半導体メモリ集積回路の単位電子素子、高周波信号増幅素子、液晶駆動用素子等として広く用いられており、現在、最も多く実用されている電子デバイスである。なかでも、近年における表示装置のめざましい発展に伴い、液晶表示装置(LCD)、エレクトロルミネッセンス表示装置(EL)、フィールドエミッションディスプレイ(FED)等の各種の表示装置において、表示素子に駆動電圧を印加して表示装置を駆動させるスイッチング素子として、TFTが多用されている。 Field effect transistors such as thin film transistors (TFTs) are widely used as unit electronic elements, high frequency signal amplifying elements, liquid crystal driving elements, etc. for semiconductor memory integrated circuits, and are currently the most widely used electronic devices. . In particular, with the remarkable development of display devices in recent years, in various display devices such as liquid crystal display devices (LCD), electroluminescence display devices (EL), and field emission displays (FED), a driving voltage is applied to the display elements. TFTs are often used as switching elements for driving display devices.
 電界効果型トランジスタの主要部材である半導体層(チャネル層)の材料としては、シリコン半導体化合物が最も広く用いられている。一般に、高速動作が必要な高周波増幅素子や集積回路用素子等には、シリコン単結晶が用いられている。一方、液晶駆動用素子等には、大面積化の要求から非晶質性シリコン半導体(アモルファスシリコン)が用いられている。 As a material for a semiconductor layer (channel layer) which is a main member of a field effect transistor, a silicon semiconductor compound is most widely used. In general, a silicon single crystal is used for a high-frequency amplifying element or an integrated circuit element that requires high-speed operation. On the other hand, an amorphous silicon semiconductor (amorphous silicon) is used for a liquid crystal driving element or the like because of a demand for a large area.
 アモルファスシリコンの薄膜は、比較的低温で形成できるものの、結晶性の薄膜に比べてスイッチング速度が遅いため、表示装置を駆動するスイッチング素子として使用したときに、高速な動画の表示に追従できない場合がある。具体的に、解像度がVGAである液晶テレビでは、移動度が0.5~1cm/Vsのアモルファスシリコンが使用可能であったが、解像度がSXGA、UXGA、QXGAあるいはそれ以上になると2cm/Vs以上の移動度が要求される。また、画質を向上させるため駆動周波数を上げるとさらに高い移動度が必要となる。 Although an amorphous silicon thin film can be formed at a relatively low temperature, its switching speed is slower than that of a crystalline thin film, so when used as a switching element for driving a display device, it may not be able to follow the display of high-speed movies. is there. Specifically, in a liquid crystal television with a resolution of VGA, amorphous silicon having a mobility of 0.5 to 1 cm 2 / Vs could be used, but when the resolution is SXGA, UXGA, QXGA or higher, 2 cm 2 / Mobility greater than Vs is required. Further, when the driving frequency is increased in order to improve the image quality, higher mobility is required.
 一方、結晶性のシリコン系薄膜は、移動度は高いものの、製造に際して多大なエネルギーと工程数を要する等の問題や、大面積化が困難という問題があった。例えば、シリコン系薄膜を結晶化する際に800℃以上の高温や、高価な設備を使用するレーザーアニールが必要である。また、結晶性のシリコン系薄膜は、通常TFTの素子構成がトップゲート構成に限定されるためマスク枚数の削減等コストダウンが困難であった。 On the other hand, although the crystalline silicon-based thin film has a high mobility, there are problems such as requiring a large amount of energy and the number of processes for manufacturing, and a problem that it is difficult to increase the area. For example, when annealing a silicon-based thin film, laser annealing using a high temperature of 800 ° C. or higher and expensive equipment is necessary. In addition, a crystalline silicon-based thin film is difficult to reduce costs such as a reduction in the number of masks because the element configuration of a TFT is usually limited to a top gate configuration.
 このような問題を解決するために、酸化インジウム、酸化スズ、酸化亜鉛を含む酸化物半導体薄膜を使用した薄膜トランジスタが検討されている(例えば、特許文献1~3)。この薄膜は選択エッチング性があることが報告されている(例えば、特許文献1)。活性層にこの薄膜を用いることで、酸化物半導体薄膜上にエッチングストッパーを積層せずに、ウェットエッチングにより電極をパターニング(バックチャネルエッチング)できることから、薄膜トランジスタを製作する際のマスク工程を削減できるために、コストダウンが可能で生産性を向上させることが可能である。 In order to solve such a problem, a thin film transistor using an oxide semiconductor thin film containing indium oxide, tin oxide, and zinc oxide has been studied (for example, Patent Documents 1 to 3). It has been reported that this thin film has selective etching properties (for example, Patent Document 1). By using this thin film for the active layer, the electrode can be patterned by wet etching (back channel etching) without stacking an etching stopper on the oxide semiconductor thin film, thereby reducing the mask process when manufacturing the thin film transistor. In addition, the cost can be reduced and the productivity can be improved.
 しかし、従来技術の酸化インジウム、酸化スズ、酸化亜鉛を含む酸化物半導体薄膜はインジウム量を多くすると薄膜が結晶化しやすくなり、シュウ酸系エッチング液によるエッチング速度が遅くなったり、残渣が残りやすくなったりするためにIn量が比較的少ない限られた範囲に制限する必要があった。このため、移動度を向上させることが困難であった。 However, the oxide semiconductor thin film containing indium oxide, tin oxide, and zinc oxide of the prior art is likely to be crystallized when the amount of indium is increased, and the etching rate with the oxalic acid-based etching solution is slow, and the residue is likely to remain. For this reason, it was necessary to limit the amount of In to a limited range. For this reason, it was difficult to improve mobility.
国際公開第2008/117810号公報International Publication No. 2008/117810 国際公開第2009/147969号公報International Publication No. 2009/147969 特開2008-66276号公報JP 2008-66276 A
 本発明の目的は、酸化インジウム、酸化スズ、酸化亜鉛を含み、広い範囲のIn量において良好なTFT特性を実現させるスパッタリングターゲットを提供することである。さらに、良好な特性を有するTFTをバックチャネルエッチング法によって製造することが可能なスパッタリングターゲットを提供することを目的とする。 An object of the present invention is to provide a sputtering target that contains indium oxide, tin oxide, and zinc oxide and realizes good TFT characteristics in a wide range of In amount. Furthermore, it aims at providing the sputtering target which can manufacture TFT which has a favorable characteristic by a back channel etching method.
 本発明によれば、以下のスパッタリングターゲット等が提供される。
1.インジウム元素(In)、スズ元素(Sn)、亜鉛元素(Zn)及び下記のX群から選択される1以上の元素Xを含有する酸化物からなり、Inで表されるビックスバイト構造化合物と、スピネル構造化合物とを含むスパッタリングターゲット。
X群:Mg、Al、Ga、Si、Sc、Ti、Y、Zr、Hf、Ta、La、Nd、Sm
2.前記インジウム元素、スズ元素、亜鉛元素及び元素Xの原子比が、下記式(1)~(4)を満たす1に記載のスパッタリングターゲット。
0.20≦In/(In+Sn+Zn+X)≦0.85 (1)
0.01≦Sn/(In+Sn+Zn+X)≦0.35 (2)
0.01≦Zn/(In+Sn+Zn+X)≦0.70 (3)
0.01≦X/(In+Sn+Zn+X)≦0.30  (4)
(式中、In、Sn、Zn及びXは、それぞれ、スパッタリングターゲットにおける各元素の原子比を示す。)
3.前記スピネル構造化合物が、XIn、ZnX、ZnXOのうちいずれかを含む、1又は2に記載のスパッタリングターゲット。
4.前記元素XがMg、Al、Ti、Si、又はGaである、1~3のいずれかに記載のスパッタリングターゲット。
5.前記元素XがAlであり、前記スピネル構造化合物がZnAlを含む1~3のいずれかに記載のスパッタリングターゲット。
6.前記スピネル構造化合物がZnSnOを含む1~5のいずれかに記載のスパッタリングターゲット。
7.相対密度が98%以上であり、バルク比抵抗が10mΩcm以下である1~6のいずれかに記載のスパッタリングターゲット。
8.1~7のいずれかに記載のスパッタリングターゲットを用いて、スパッタリング法により成膜してなる酸化物半導体薄膜。
9.リン酸系エッチング液に対して不溶であり、かつシュウ酸系エッチング液に対して可溶である8に記載の酸化物半導体薄膜。
10.前記リン酸系エッチング液による35℃でのエッチング速度が10nm/分以下であり、かつ前記シュウ酸エッチング液による35℃でのエッチング速度が20nm/分以上である9に記載の酸化物半導体薄膜。
11.水蒸気、酸素ガス及び亜酸化窒素ガスから選択される1以上と希ガスとを含有する混合気体の雰囲気下において、1~7のいずれかに記載のスパッタリングターゲットを用いてスパッタリング法で成膜する酸化物半導体薄膜の製造方法。
12.前記酸化物半導体薄膜の成膜を、少なくとも水蒸気と希ガスとを含有する混合気体の雰囲気下において行う11に記載の酸化物半導体薄膜の製造方法。
13.前記混合気体中に含まれる水蒸気の割合が分圧比で0.1%~25%である11又は12に記載の酸化物半導体薄膜の製造方法。
14.前記混合気体中に含まれる酸素ガスの割合が分圧比で0.1%~30%である11~13のいずれかに記載の酸化物半導体薄膜の製造方法。
15.前記酸化物半導体薄膜の成膜を、真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、前記各ターゲットに対して交流電源から負電位及び正電位を交互に印加する場合に、前記交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら、ターゲット上にプラズマを発生させて基板表面に成膜するスパッタリング方法で行う11~14のいずれかに記載の酸化物半導体薄膜の製造方法。
16.前記交流電源の交流パワー密度が3W/cm以上、20W/cm以下である15に記載の酸化物半導体薄膜の製造方法。
17.前記交流電源の周波数が10kHz~1MHzである15又は16に記載の酸化物半導体薄膜の製造方法。
18.8~10のいずれかに記載の酸化物半導体薄膜をチャネル層として有する薄膜トランジスタ。
19.電界効果移動度が10cm/Vs以上である18に記載の薄膜トランジスタ。
20.8~10のいずれかに記載の酸化物半導体薄膜の上に、少なくともSiNx(xは任意の数)を含有する保護膜を有する薄膜トランジスタ。
21.半導体活性層として、8~10のいずれかに記載された酸化物半導体薄膜を用いた薄膜トランジスタの製造方法であって、前記半導体薄膜上にエッチングストッパーを積層させずに、前記半導体薄膜と電極を異なるエッチング液を用いてパターニングし、電極をパターニングする際に直接エッチング液が前記半導体薄膜に接する工程を含む薄膜トランジスタを製造する方法。
22.18~20のいずれかに記載の薄膜トランジスタを備える表示装置。
According to the present invention, the following sputtering target and the like are provided.
1. A bixbite structure composed of an oxide containing at least one element X selected from indium element (In), tin element (Sn), zinc element (Zn), and the following group X, and represented by In 2 O 3 A sputtering target comprising a compound and a spinel structure compound.
X group: Mg, Al, Ga, Si, Sc, Ti, Y, Zr, Hf, Ta, La, Nd, Sm
2. 2. The sputtering target according to 1, wherein an atomic ratio of the indium element, tin element, zinc element and element X satisfies the following formulas (1) to (4).
0.20 ≦ In / (In + Sn + Zn + X) ≦ 0.85 (1)
0.01 ≦ Sn / (In + Sn + Zn + X) ≦ 0.35 (2)
0.01 ≦ Zn / (In + Sn + Zn + X) ≦ 0.70 (3)
0.01 ≦ X / (In + Sn + Zn + X) ≦ 0.30 (4)
(In the formula, In, Sn, Zn, and X each represent an atomic ratio of each element in the sputtering target.)
3. The sputtering target according to 1 or 2, wherein the spinel structure compound contains any one of XIn 2 O 4 , ZnX 2 O 4 , and Zn 2 XO 4 .
4). 4. The sputtering target according to any one of 1 to 3, wherein the element X is Mg, Al, Ti, Si, or Ga.
5. The sputtering target according to any one of 1 to 3, wherein the element X is Al, and the spinel structure compound contains ZnAl 2 O 4 .
6). The sputtering target according to any one of 1 to 5, wherein the spinel structure compound contains Zn 2 SnO 4 .
7). 7. The sputtering target according to any one of 1 to 6, having a relative density of 98% or more and a bulk specific resistance of 10 mΩcm or less.
8. An oxide semiconductor thin film formed by sputtering using the sputtering target according to any one of 1 to 7.
9. 9. The oxide semiconductor thin film according to 8, which is insoluble in a phosphoric acid etching solution and is soluble in an oxalic acid etching solution.
10. 10. The oxide semiconductor thin film according to 9, wherein an etching rate at 35 ° C. with the phosphoric acid-based etching solution is 10 nm / min or less and an etching rate at 35 ° C. with the oxalic acid etching solution is 20 nm / min or more.
11. Oxidation formed by sputtering using a sputtering target according to any one of 1 to 7 in an atmosphere of a mixed gas containing one or more selected from water vapor, oxygen gas and nitrous oxide gas and a rare gas Method for manufacturing a semiconductor thin film.
12 12. The method for producing an oxide semiconductor thin film according to 11, wherein the oxide semiconductor thin film is formed in an atmosphere of a mixed gas containing at least water vapor and a rare gas.
13. 13. The method for producing an oxide semiconductor thin film according to 11 or 12, wherein a ratio of water vapor contained in the mixed gas is 0.1% to 25% in terms of partial pressure ratio.
14 14. The method for producing an oxide semiconductor thin film according to any one of 11 to 13, wherein a ratio of oxygen gas contained in the mixed gas is 0.1% to 30% in terms of partial pressure ratio.
15. The oxide semiconductor thin film is formed by sequentially transporting the substrate to a position facing three or more targets arranged in parallel in the vacuum chamber at a predetermined interval, and from each AC power source to each target. In the case of alternately applying a negative potential and a positive potential, at least one of the outputs from the AC power supply is switched between two or more targets that are branched and connected while switching the target to which the potential is applied. 15. The method for producing an oxide semiconductor thin film according to any one of 11 to 14, which is performed by a sputtering method in which plasma is generated on a target to form a film on a substrate surface.
16. 16. The method for producing an oxide semiconductor thin film according to 15, wherein the AC power density of the AC power source is 3 W / cm 2 or more and 20 W / cm 2 or less.
17. 17. The method for producing an oxide semiconductor thin film according to 15 or 16, wherein the frequency of the AC power source is 10 kHz to 1 MHz.
A thin film transistor having the oxide semiconductor thin film according to any one of 18.8 to 10 as a channel layer.
19. 19. The thin film transistor according to 18, wherein the field effect mobility is 10 cm 2 / Vs or more.
A thin film transistor having a protective film containing at least SiNx (x is an arbitrary number) on the oxide semiconductor thin film according to any one of 20.8 to 10.
21. A method of manufacturing a thin film transistor using the oxide semiconductor thin film according to any one of 8 to 10 as a semiconductor active layer, wherein the semiconductor thin film and the electrode are different from each other without stacking an etching stopper on the semiconductor thin film. A method of manufacturing a thin film transistor, comprising a step of patterning using an etching solution, and the step of contacting the semiconductor thin film directly with the etching solution when patterning an electrode.
22. A display device comprising the thin film transistor according to any one of 18.18 to 20.
 本発明によれば、酸化インジウム、酸化スズ、酸化亜鉛を含み、広い範囲のIn量において良好なTFT特性を実現させるスパッタリングターゲットを提供できる。
 また、良好な特性を有するTFTをバックチャネルエッチング法によって製造することが可能なスパッタリングターゲットを提供できる。
According to the present invention, it is possible to provide a sputtering target that includes indium oxide, tin oxide, and zinc oxide and realizes good TFT characteristics in a wide range of In amount.
In addition, it is possible to provide a sputtering target capable of manufacturing a TFT having favorable characteristics by a back channel etching method.
実施例1で得た焼結体のX線チャートである。2 is an X-ray chart of a sintered body obtained in Example 1. 実施例2で得た焼結体のX線チャートである。3 is an X-ray chart of a sintered body obtained in Example 2. 実施例3で得た焼結体のX線チャートである。4 is an X-ray chart of a sintered body obtained in Example 3. 実施例4で得た焼結体のX線チャートである。6 is an X-ray chart of a sintered body obtained in Example 4. 実施例5で得た焼結体のX線チャートである。6 is an X-ray chart of a sintered body obtained in Example 5. 実施例6で得た焼結体のX線チャートである。6 is an X-ray chart of a sintered body obtained in Example 6. 実施例7で得た焼結体のX線チャートである。6 is an X-ray chart of a sintered body obtained in Example 7. 実施例8で得た焼結体のX線チャートである。6 is an X-ray chart of a sintered body obtained in Example 8. 実施例9で得た焼結体のX線チャートである。10 is an X-ray chart of a sintered body obtained in Example 9. 本発明の一実施形態に用いるスパッタリング装置を示す図である。It is a figure which shows the sputtering device used for one Embodiment of this invention.
 以下、本発明のスパッタリングターゲット、酸化物半導体薄膜、薄膜トランジスタ、表示装置及びこれらの製造方法について詳細に説明するが、本発明は下記実施態様及び実施例に限定されるものではない。 Hereinafter, the sputtering target, the oxide semiconductor thin film, the thin film transistor, the display device, and the manufacturing method thereof according to the present invention will be described in detail, but the present invention is not limited to the following embodiments and examples.
 本発明のスパッタリングターゲットは、インジウム元素(In)、スズ元素、(Sn)、亜鉛元素(Zn)及び下記のX群から選ばれる1以上の元素Xを含有する酸化物からなり、Inで表されるビックスバイト構造化合物と、スピネル構造化合物とを含む。
X群:Mg、Al、Ga、Si、Sc、Ti、Y、Zr、Hf、Ta、La、Nd、Sm
The sputtering target of the present invention is composed of an oxide containing indium element (In), tin element, (Sn), zinc element (Zn), and one or more elements X selected from the following group X, and includes In 2 O 3. The bixbite structure compound represented by these and a spinel structure compound are included.
X group: Mg, Al, Ga, Si, Sc, Ti, Y, Zr, Hf, Ta, La, Nd, Sm
 ビックスバイト構造化合物及びスピネル構造化合物は、X線回折によりその存在の有無を確認することができる。 The presence or absence of the bixbite structure compound and the spinel structure compound can be confirmed by X-ray diffraction.
 また、本発明のスパッタリングターゲットは、インジウム元素、スズ元素、亜鉛元素及び元素Xの原子比が、下記式(1)~(4)を満たすことが好ましい。
0.20≦In/(In+Sn+Zn+X)≦0.85 (1)
0.01≦Sn/(In+Sn+Zn+X)≦0.35 (2)
0.01≦Zn/(In+Sn+Zn+X)≦0.70 (3)
0.01≦X/(In+Sn+Zn+X)≦0.30  (4)
(式中、In、Sn、Zn及びXは、それぞれ、スパッタリングターゲットにおける各元素の原子比を示す。)
In the sputtering target of the present invention, the atomic ratio of indium element, tin element, zinc element and element X preferably satisfies the following formulas (1) to (4).
0.20 ≦ In / (In + Sn + Zn + X) ≦ 0.85 (1)
0.01 ≦ Sn / (In + Sn + Zn + X) ≦ 0.35 (2)
0.01 ≦ Zn / (In + Sn + Zn + X) ≦ 0.70 (3)
0.01 ≦ X / (In + Sn + Zn + X) ≦ 0.30 (4)
(In the formula, In, Sn, Zn, and X each represent an atomic ratio of each element in the sputtering target.)
 上記式(1)において、In元素の量が0.20以上であれば、スパッタリングターゲットのバルク抵抗値が高くなり難く、DCスパッタリングが可能となる。
 一方、In元素の量が0.85以下であれば、そのターゲットを用いて作製した薄膜のキャリア濃度が増加することによる導体化が起き難く、半導体用薄膜として利用できる。
In the above formula (1), if the amount of In element is 0.20 or more, the bulk resistance value of the sputtering target is hardly increased, and DC sputtering is possible.
On the other hand, if the amount of In element is 0.85 or less, it is difficult to form a conductor due to an increase in carrier concentration of a thin film produced using the target, and it can be used as a semiconductor thin film.
 以上からInの濃度は、0.20≦In/(In+Sn+Zn+X)≦0.85であることが好ましい。In元素の量[In/(In+Sn+Zn+X)]は、好ましくは0.20~0.75であり、さらに好ましくは、0.25~0.60である。 From the above, the In concentration is preferably 0.20 ≦ In / (In + Sn + Zn + X) ≦ 0.85. The amount of In element [In / (In + Sn + Zn + X)] is preferably 0.20 to 0.75, and more preferably 0.25 to 0.60.
 上記式(2)において、Sn元素の量が0.01以上であると、得られる薄膜のエッチング液への選択性が確保でき、バックチャネルエッチングが可能となる。
 一方、Sn元素の量が0.35以下であれば、シュウ酸系エッチング液に対するエッチング性が失われず、面内も均一にしやすくなる。
 以上からSnの濃度は、0.01≦Sn/(In+Sn+Zn+X)≦0.35であることが好ましい。
 Sn元素の量[Sn/(In+Sn+Zn+X)]は、好ましくは0.03~0.30であり、さらに好ましくは、0.05~0.25である。
In the above formula (2), when the amount of Sn element is 0.01 or more, the selectivity of the resulting thin film to the etching solution can be secured, and back channel etching can be performed.
On the other hand, if the amount of Sn element is 0.35 or less, the etching property with respect to the oxalic acid-based etching solution is not lost, and the in-plane is easily made uniform.
Accordingly, the Sn concentration is preferably 0.01 ≦ Sn / (In + Sn + Zn + X) ≦ 0.35.
The amount of Sn element [Sn / (In + Sn + Zn + X)] is preferably 0.03 to 0.30, and more preferably 0.05 to 0.25.
 上記式(3)において、Zn元素の量が0.01以上であれば、ターゲット密度が向上し、ターゲット抵抗を低くしやすくなるためDCスパッタリングを行うことができる。
 一方、Zn元素の量が0.70以下であれば、得られる薄膜のエッチング液への溶解速度が速すぎてウェットエッチングが困難になることがなくなる。
In the above formula (3), if the amount of Zn element is 0.01 or more, the target density is improved and the target resistance is easily lowered, so that DC sputtering can be performed.
On the other hand, if the amount of Zn element is 0.70 or less, the dissolution rate of the obtained thin film in the etching solution is too fast, and wet etching is not difficult.
 以上からZnの濃度は、0.01≦Zn/(In+Sn+Zn+X)≦0.70であることが好ましい。
 Zn元素の量[Zn/(In+Sn+Zn+X)]は、好ましくは0.03~0.60であり、さらに好ましくは、0.05~0.60である。
From the above, the Zn concentration is preferably 0.01 ≦ Zn / (In + Sn + Zn + X) ≦ 0.70.
The amount of Zn element [Zn / (In + Sn + Zn + X)] is preferably 0.03 to 0.60, and more preferably 0.05 to 0.60.
 上記式(4)において、元素Xの量が0.01以上であれば、そのターゲットを用いて作製した薄膜のキャリア濃度を抑制しやすくなり、半導体用薄膜として利用することができる。
 一方、元素Xの量が0.30以下であれば元素Xの酸化物が単独で現れにくくなり、ターゲット抵抗が上がることを防ぐことができる。
 以上からXの濃度は、0.01≦X/(In+Sn+Zn+X)≦0.30であることが好ましい。
 元素Xの量[X/(In+Sn+Zn+X)]は、好ましくは0.02~0.27であり、さらに好ましくは、0.02~0.25である。
In the above formula (4), when the amount of the element X is 0.01 or more, it becomes easy to suppress the carrier concentration of a thin film manufactured using the target, and it can be used as a thin film for a semiconductor.
On the other hand, if the amount of the element X is 0.30 or less, the oxide of the element X is difficult to appear alone, and the target resistance can be prevented from increasing.
From the above, the concentration of X is preferably 0.01 ≦ X / (In + Sn + Zn + X) ≦ 0.30.
The amount of the element X [X / (In + Sn + Zn + X)] is preferably 0.02 to 0.27, and more preferably 0.02 to 0.25.
 ビックスバイト構造は、焼結体のX線回折パターンがJCPDS(Joint Committee of Powder Diffraction Standards)カードやThe Inorganic Crystal Structure Database(ICSD)から得られるビックスバイト相の結晶構造X線回折パターンと一致することから確認することができる。ビックスバイト構造を有する化合物として、Inが挙げられる。 The bixbite structure means that the X-ray diffraction pattern of the sintered body matches the crystal structure of the bixbital diffraction pattern obtained from JCPDS (Joint Committee of Powder Diffraction Standards) card or The Inorganic Crystal Structure Database (ICSD). Can be confirmed. Examples of the compound having a bixbite structure include In 2 O 3 .
 ビックスバイト(bixbyite)は、希土類酸化物C型又はMn(I)型酸化物とも言われる。「透明導電膜の技術」((株)オーム社出版、日本学術振興会、透明酸化物・光電子材料第166委員会編、1999)等に開示されているとおり、化学量論比がM(Mは陽イオン、Xは陰イオンで通常酸素イオン)で、一つの単位胞はM16分子、合計80個の原子(Mが32個、Xが48個)により構成されている。 Bixbyte is also referred to as rare earth oxide C-type or Mn 2 O 3 (I) -type oxide. As disclosed in “Technology of Transparent Conductive Films” (Ohm Publishing Co., Ltd., Japan Society for the Promotion of Science, Transparent Oxide / Optoelectronic Materials 166th Committee, 1999), the stoichiometric ratio is M 2 X 3 (M is a cation, X is an anion, usually an oxygen ion), and one unit cell is composed of 16 molecules of M 2 X 3 , a total of 80 atoms (M is 32, X is 48) Yes.
 ビックスバイト構造は、X線回折で、JCPDSデータベースのNo.06-0416のピークパターンか、又は類似の(シフトした)パターンを示す。
 また、結晶構造中の原子やイオンが一部他の原子で置換された置換型固溶体、他の原子が格子間位置に加えられた侵入型固溶体もビックスバイト構造化合物に含まれる。
The bixbite structure is X-ray diffraction, and is No. of JCPDS database. A peak pattern of 06-0416 or a similar (shifted) pattern is shown.
The bixbite structure compound also includes a substitutional solid solution in which atoms and ions in the crystal structure are partially substituted with other atoms, and an interstitial solid solution in which other atoms are added to interstitial positions.
 スピネル構造であることは、焼結体をX線回折測定した結果、スピネル構造化合物のピークが観察されることにより確認できる。
 スピネル構造については、「ウエスト固体化学入門」(講談社サイエンティフィク)に詳細に記されており、それによればスピネル構造は以下のような構造である。
The spinel structure can be confirmed by observing the peak of the spinel structure compound as a result of X-ray diffraction measurement of the sintered body.
The spinel structure is described in detail in “Introduction to West Solid Chemistry” (Kodansha Scientific). According to this, the spinel structure is as follows.
 スピネルはABの組成式を有し、AイオンとBイオンの配位状態によって分類すると、正スピネル構造、逆スピネル構造、両者の中間の構造に分けられる。
 正スピネルはO2-が形成する立体面心格子の四面体隙間の8分の1にAが充填され、八面体隙間の2分の1にBが充填された構造を有する。逆スピネル構造は、四面体隙間の8分の1にBが充填され八面体隙間の2分の1にA及びBが充填された構造を有する。一般的には立方晶であるが、中には立方晶が歪むものもある。
Spinel has a composition formula of AB 2 O 4 and is classified into a normal spinel structure, a reverse spinel structure, and an intermediate structure between the two when classified according to the coordination state of A ions and B ions.
The regular spinel has a structure in which A is filled in one-eighth of the tetrahedral gap of the solid face-centered lattice formed by O 2− and B is filled in one-half of the octahedral gap. The reverse spinel structure has a structure in which one-eighth of the tetrahedral gap is filled with B and half of the octahedral gap is filled with A and B. Generally, it is a cubic crystal, but some of the cubic crystals are distorted.
 また、結晶構造中の原子やイオンが一部他の原子で置換された置換型固溶体、他の原子が格子間位置に加えられた侵入型固溶体もスピネル構造化合物に含まれる。
 スピネル構造化合物としては、例えばZnAl、ZnSnO、MgIn、ZnTiO、ZnGa、ZnSiO等が挙げられる。
Also included in the spinel structure compound are substituted solid solutions in which atoms and ions in the crystal structure are partially substituted with other atoms, and interstitial solid solutions in which other atoms are added to interstitial positions.
Examples of the spinel structure compound include ZnAl 2 O 4 , Zn 2 SnO 4 , MgIn 2 O 4 , Zn 2 TiO 4 , ZnGa 2 O 4 , Zn 2 SiO 4 and the like.
 例えば、ZnAlのスピネル構造は、X線回折で、JCPDSデータベースのNo.05-0669のピークパターンか、あるいは類似の(シフトした)パターンを示すものである。他のスピネル構造についても同様に、X線回折でJCPDSもしくはICSDから得られるX線パターンかあるいは類似の(シフトした)パターンを示すものである。 For example, the spinel structure of ZnAl 2 O 4 is X-ray diffraction, and the JCPDS database No. It shows a peak pattern of 05-0669 or a similar (shifted) pattern. Similarly, other spinel structures show an X-ray pattern obtained from JCPDS or ICSD by X-ray diffraction or a similar (shifted) pattern.
 本発明のスパッタリングターゲットは、Inで表されるビックスバイト構造化合物を含むことにより、元素Xがビックスバイト構造と置換型固溶体、あるいは侵入型固溶体を形成しやすくなり、ターゲットの高抵抗化を招くおそれがある、元素Xの酸化物が単独で現れることを防ぐことができる。 Since the sputtering target of the present invention contains a bixbite structure compound represented by In 2 O 3 , the element X can easily form a bixbite structure and a substitutional solid solution or an interstitial solid solution, thereby increasing the resistance of the target. It is possible to prevent the oxide of the element X from appearing alone.
 また、スピネル構造化合物を含むことにより、元素Xがスピネル構造と置換型固溶体、あるいは侵入型固溶体を形成しやすくなり、ターゲットの高抵抗化を招くおそれがある、元素Xの酸化物が単独で現れることを防ぐことができる。 In addition, the inclusion of the spinel structure compound makes it easier for the element X to form a spinel structure and a substitutional solid solution or an interstitial solid solution, and the oxide of the element X that may increase the resistance of the target appears alone. Can be prevented.
 本発明の好ましい態様では、スピネル構造化合物としてZnSnOを含むことにより、元素XがIn、Sn、Znと結晶構造を形成しにくく、元素Xの酸化物が単独で現れやすくても、ZnSnOの中に元素Xが固溶することにより、ターゲットの抵抗を低くすることができる。これにより元素Xの添加量を多くすることが可能となり、成膜時の酸素分圧を高くしなくとも良好な半導体薄膜を作製することができる。 In a preferred embodiment of the present invention, by containing Zn 2 SnO 4 as the spinel structure compound, the element X hardly forms a crystal structure with In, Sn, Zn, and even if the oxide of the element X tends to appear alone, When the element X is dissolved in 2 SnO 4 , the resistance of the target can be lowered. As a result, the amount of element X added can be increased, and an excellent semiconductor thin film can be produced without increasing the oxygen partial pressure during film formation.
 本発明の別の好ましい態様では、さらに、元素Xが、XIn、ZnX、ZnXOのようなスピネル構造を構成することにより、即ち、スピネル構造化合物が、XIn、ZnX、ZnXOのうちいずれかを含むことにより、元素Xの酸化物が単独で現れにくくなり、元素Xの量が多くても高密度で低抵抗なターゲットとすることができる。 In another preferred embodiment of the present invention, the element X further constitutes a spinel structure such as XIn 2 O 4 , ZnX 2 O 4 , Zn 2 XO 4 , that is, the spinel structure compound is XIn 2 O. 4 , ZnX 2 O 4 , or Zn 2 XO 4 , which makes it difficult for an oxide of element X to appear alone, and makes a high-density, low-resistance target even if the amount of element X is large. Can do.
 元素Xは、Mg、Al、Ti、Si、又はGaであることが好ましい。これにより、高密度で低抵抗なターゲットとすることができる。これは、上記の元素Xがビックスバイトあるいはスピネル構造化合物と置換型固溶体、あるいは侵入型固溶体を形成しやすかったり、上記の元素Xがスピネル構造を形成しやすかったりするためと考えられる。 The element X is preferably Mg, Al, Ti, Si, or Ga. Thereby, it can be set as a high-density and low-resistance target. This is presumably because the element X is likely to form a bixbite or spinel structure compound and a substitutional solid solution or an interstitial solid solution, or the element X is likely to form a spinel structure.
 特に、元素XがAlであり、スピネル構造化合物がZnAlであることが好ましい。これにより、さらに高密度で低抵抗なターゲットとすることができる。これは、Alは正三価のイオンとなる元素であることから、Inで表されるビックスバイト構造化合物中のInと置換しやすく、さらに、In,Sn,Znと安定的な結晶相を形成しやすいためと考えられる。
 尚、本発明のターゲットはInで表されるビックスバイト構造化合物とスピネル構造化合物が含まれていればよく、その他の結晶相を含んでいても構わない。
In particular, it is preferable that the element X is Al and the spinel structure compound is ZnAl 2 O 4 . Thereby, it can be set as a target with higher density and lower resistance. This is because Al is an element that becomes a positive trivalent ion, so that it can be easily replaced with In in the bixbyite structure compound represented by In 2 O 3 , and moreover, In, Sn, Zn and a stable crystalline phase It is thought that this is easy to form.
Incidentally, the target of the present invention may also include a well if it contains bixbyite structure compound and spinel structural compound represented by an In 2 O 3, other crystalline phases.
 スパッタリングターゲットに含まれる各元素の原子比は、誘導結合プラズマ発光分析装置(ICP-AES)により、含有元素を定量分析して求めることができる。
 具体的には、溶液試料をネブライザーで霧状にして、アルゴンプラズマ(約6000~8000℃)に導入すると、試料中の元素は熱エネルギーを吸収して励起され、軌道電子が基底状態から高いエネルギー準位の軌道に移る。この軌道電子は10-7~10-8秒程度で、より低いエネルギー準位の軌道に移る。この際にエネルギーの差を光として放射し発光する。この光は元素固有の波長(スペクトル線)を示すため、スペクトル線の有無により元素の存在を確認できる(定性分析)。
The atomic ratio of each element contained in the sputtering target can be determined by quantitative analysis of the contained elements using an inductively coupled plasma emission spectrometer (ICP-AES).
Specifically, when a solution sample is atomized with a nebulizer and introduced into an argon plasma (about 6000 to 8000 ° C.), the elements in the sample are excited by absorbing thermal energy, and orbital electrons have a high energy from the ground state. Move to the level orbit. These orbital electrons move to a lower energy level orbit in about 10 −7 to 10 −8 seconds. At this time, the energy difference is emitted as light to emit light. Since this light shows a wavelength (spectral line) unique to the element, the presence of the element can be confirmed by the presence or absence of the spectral line (qualitative analysis).
 また、それぞれのスペクトル線の大きさ(発光強度)は試料中の元素数に比例するため、既知濃度の標準液と比較することで試料濃度を求めることができる(定量分析)。
 定性分析で含有されている元素を特定後、定量分析で含有量を求め、その結果から各元素の原子比を求める。
In addition, since the magnitude (luminescence intensity) of each spectral line is proportional to the number of elements in the sample, the sample concentration can be obtained by comparing with a standard solution having a known concentration (quantitative analysis).
After identifying the elements contained in the qualitative analysis, the content is obtained by quantitative analysis, and the atomic ratio of each element is obtained from the result.
 上記のように、スパッタリングターゲットに含有される金属元素は、実質的にIn、Sn、Zn及び金属Xからなっており、本発明の効果を損なわない範囲で他に不可避不純物を含んでいてもよい。
 本発明において「実質的」とは、スパッタリングターゲットとしての効果が上記In、Sn、Zn及び元素Xに起因すること、又はスパッタリングターゲットの金属元素の95重量%以上100重量%以下(好ましくは98重量%以上100重量%以下)がIn、Sn、Zn及び元素Xであることを意味する。
As described above, the metal element contained in the sputtering target is substantially composed of In, Sn, Zn, and metal X, and may contain other inevitable impurities as long as the effects of the present invention are not impaired. .
In the present invention, “substantially” means that the effect as a sputtering target is caused by the above In, Sn, Zn and element X, or 95% by weight to 100% by weight (preferably 98% by weight) of the metal element of the sputtering target. % Or more and 100% by weight or less) means In, Sn, Zn, and element X.
 本発明に用いるスパッタリングターゲットは、好ましくは相対密度が98%以上である。大型基板(1Gサイズ以上)にスパッタ出力を上げて酸化物半導体を成膜する場合は、相対密度が98%以上であることが好ましい。相対密度とは、加重平均より算出した理論密度に対して相対的に算出した密度である。各原料の密度の加重平均より算出した密度が理論密度であり、これを100%とする。 The sputtering target used in the present invention preferably has a relative density of 98% or more. In the case where an oxide semiconductor film is formed by increasing the sputtering output on a large substrate (1G size or more), the relative density is preferably 98% or more. The relative density is a density calculated relative to the theoretical density calculated from the weighted average. The density calculated from the weighted average of the density of each raw material is the theoretical density, which is defined as 100%.
 相対密度が98%以上であれば、安定したスパッタリング状態が保たれる。大型基板でスパッタ出力を上げて成膜する場合は、相対密度が98%未満ではターゲット表面が黒化したり、異常放電が発生したりする場合がある。相対密度は好ましくは98.5%以上、より好ましくは99%以上である。 If the relative density is 98% or more, a stable sputtering state is maintained. When film formation is performed with a large substrate at an increased sputtering output, the target surface may be blackened or abnormal discharge may occur if the relative density is less than 98%. The relative density is preferably 98.5% or more, more preferably 99% or more.
 相対密度はアルキメデス法により測定できる。相対密度は、好ましくは100%以下である。100%以下であれば、金属粒子が焼結体に発生したり、低級酸化物が生成したりしにくくなり成膜時の酸素供給量を厳密に調整しなくても済む。 The relative density can be measured by Archimedes method. The relative density is preferably 100% or less. If it is 100% or less, metal particles are less likely to be generated in the sintered body and lower oxides are less likely to be produced, and it is not necessary to strictly adjust the oxygen supply amount during film formation.
 また、焼結後に、還元性雰囲気下での熱処理操作等の後処理工程等を行って密度を調整することもできる。還元性雰囲気は、アルゴン、窒素、水素等の雰囲気や、それらの混合気体雰囲気が用いられる。 Further, after sintering, the density can be adjusted by performing a post-treatment step such as a heat treatment operation under a reducing atmosphere. As the reducing atmosphere, an atmosphere of argon, nitrogen, hydrogen, or a mixed gas atmosphere thereof is used.
 本発明のスパッタリングターゲットは、より好ましくは、ターゲットの相対密度が98%以上かつバルク比抵抗が10mΩcm以下である。これにより、ターゲットをスパッタリングする際には、異常放電の発生を抑制することができる。本発明のスパッタリングターゲットは、高品質の酸化物半導体薄膜を、効率的に、安価に、かつ省エネルギーで成膜することができる。
 バルク比抵抗は、例えば、実施例に記載の方法により測定することができる。バルク比抵抗は、好ましくは5mΩcm以下である。
More preferably, the sputtering target of the present invention has a relative density of 98% or more and a bulk specific resistance of 10 mΩcm or less. Thereby, when sputtering a target, generation | occurrence | production of abnormal discharge can be suppressed. The sputtering target of the present invention can form a high-quality oxide semiconductor thin film efficiently, inexpensively and with energy saving.
A bulk specific resistance can be measured by the method as described in an Example, for example. The bulk specific resistance is preferably 5 mΩcm or less.
 本発明のスパッタリングターゲット中の結晶の最大粒径は8μm以下であることが望ましい。結晶が粒径8μm以下であればノジュールの発生を防ぐことができる。 It is desirable that the maximum crystal grain size in the sputtering target of the present invention is 8 μm or less. Generation of nodules can be prevented if the crystal has a particle size of 8 μm or less.
 スパッタによってターゲット表面が削られる場合、その削られる速度が結晶面の方向によって異なり、ターゲット表面に凹凸が発生する。この凹凸の大きさはスパッタリングターゲット中に存在する結晶粒径に依存している。大きい結晶粒径を有するターゲットでは、その凹凸が大きくなり、その凸部分よりノジュールが発生すると考えられる。 When the target surface is cut by sputtering, the cutting speed varies depending on the direction of the crystal plane, and irregularities are generated on the target surface. The size of the unevenness depends on the crystal grain size present in the sputtering target. In the target having a large crystal grain size, the unevenness is increased, and it is considered that nodules are generated from the convex portion.
 これらのスパッタリングターゲットの結晶の最大粒径は、スパッタリングターゲットの形状が円形の場合、円の中心点(1箇所)と、その中心点で直交する2本の中心線上の中心点と周縁部との中間点(4箇所)の合計5箇所において、また、スパッタリングターゲットの形状が四角形の場合には、その中心点(1箇所)と、四角形の対角線上の中心点と角部との中間点(4箇所)の合計5箇所において100μm四方の枠内で観察される最大の粒子についてその最大径を測定し、これらの5箇所の枠内のそれぞれに存在する最大粒子の粒径の平均値で表す。粒径は、結晶粒の長径について測定する。結晶粒は走査型電子顕微鏡(SEM)により観察することができる。 When the shape of the sputtering target is circular, the maximum grain size of these sputtering target crystals is the center point (one place) of the circle and the center point and the peripheral part on two center lines orthogonal to the center point. At a total of five intermediate points (four locations), and when the sputtering target has a quadrangular shape, the central point (one location) and the intermediate point (4) between the central point and the corner on the diagonal of the quadrangle. The maximum diameter of the maximum particles observed in a 100 μm square frame at a total of five locations is measured, and is expressed as an average value of the particle sizes of the maximum particles present in each of these five locations. The particle size is measured for the major axis of the crystal grains. The crystal grains can be observed with a scanning electron microscope (SEM).
 本発明のスパッタリングターゲットの製造方法は以下の2工程を含む。
(1)原料化合物を混合し、成形して成形体とする工程
(2)上記成形体を焼結する工程
The manufacturing method of the sputtering target of the present invention includes the following two steps.
(1) Step of mixing raw material compounds and molding to form a molded body (2) Step of sintering the molded body
 以下、各工程について説明する。
(1)原料化合物を混合し、成形して成形体とする工程
 原料化合物は特に制限されず、In、Sn、Zn及び元素Xを含む化合物であり、焼結体が以下の原子比を有することができる化合物を用いればよい。
Hereinafter, each step will be described.
(1) Process of mixing raw material compounds and molding to form a molded body The raw material compound is not particularly limited, and is a compound containing In, Sn, Zn and element X, and the sintered body has the following atomic ratio. A compound that can be used may be used.
0.20≦In/(In+Sn+Zn+X)≦0.85 (1)
0.01≦Sn/(In+Sn+Zn+X)≦0.35 (2)
0.01≦Zn/(In+Sn+Zn+X)≦0.70 (3)
0.01≦X/(In+Sn+Zn+X)≦0.30  (4)
(式中、In、Sn、Zn及びXは、それぞれ、スパッタリングターゲットにおける各元素の原子比を示す。)
0.20 ≦ In / (In + Sn + Zn + X) ≦ 0.85 (1)
0.01 ≦ Sn / (In + Sn + Zn + X) ≦ 0.35 (2)
0.01 ≦ Zn / (In + Sn + Zn + X) ≦ 0.70 (3)
0.01 ≦ X / (In + Sn + Zn + X) ≦ 0.30 (4)
(In the formula, In, Sn, Zn, and X each represent an atomic ratio of each element in the sputtering target.)
 例えば、酸化インジウム、酸化スズ、酸化亜鉛及び単体の元素Xの組み合わせや、酸化インジウム、酸化スズ、酸化亜鉛及び元素Xの酸化物の組合せ等が挙げられる。
 原料は粉末であることが好ましく、酸化インジウム、酸化スズ、酸化亜鉛及び元素Xの酸化物の混合粉末であることがより好ましい。
 原料に単体金属を用いた場合、例えば、酸化インジウム、酸化スズ、酸化亜鉛及び単体の元素Xの組み合わせを原料粉末として用いると、得られる焼結体中に単体の元素Xの粒が存在し、成膜中にターゲット表面の金属粒が溶融してターゲットから放出されないことがあり、得られる膜の組成と焼結体の組成が大きく異なってしまうことがある。
For example, a combination of indium oxide, tin oxide, zinc oxide and a single element X, a combination of indium oxide, tin oxide, zinc oxide and an oxide of element X, or the like can be given.
The raw material is preferably a powder, and more preferably a mixed powder of indium oxide, tin oxide, zinc oxide and an oxide of element X.
When a single metal is used as a raw material, for example, when a combination of indium oxide, tin oxide, zinc oxide and a single element X is used as a raw material powder, grains of the single element X exist in the obtained sintered body, During the film formation, the metal particles on the target surface may melt and not be released from the target, and the composition of the resulting film and the composition of the sintered body may differ greatly.
 原料粉末の平均粒径は、好ましくは0.1μm~1.2μmであり、より好ましくは0.1μm~1.0μm以下である。原料粉末の平均粒径はレーザー回折式粒度分布装置等で測定することができる。 The average particle diameter of the raw material powder is preferably 0.1 μm to 1.2 μm, more preferably 0.1 μm to 1.0 μm or less. The average particle diameter of the raw material powder can be measured with a laser diffraction type particle size distribution apparatus or the like.
 例えば、平均粒径が0.1μm~1.2μmのIn粉末、平均粒径が0.1μm~1.2μmのSnO粉末、平均粒径が0.1μm~1.2μmのZnO粉末及び平均粒径が0.1μm~1.2μmの元素Xの酸化物粉末を含んだ酸化物を原料粉末とし、これらを、上記式(1)~(4)を満たす割合で調合する。 For example, In 2 O 3 powder with an average particle size of 0.1 μm to 1.2 μm, SnO 2 powder with an average particle size of 0.1 μm to 1.2 μm, ZnO powder with an average particle size of 0.1 μm to 1.2 μm In addition, an oxide containing an element X oxide powder having an average particle diameter of 0.1 μm to 1.2 μm is used as a raw material powder, and these are prepared at a ratio satisfying the above formulas (1) to (4).
 工程(1)の混合、成形方法は特に限定されず、公知の方法を用いて行うことができる。例えば、酸化インジウム粉、酸化スズ、酸化亜鉛及び元素Xの酸化物粉を含んだ酸化物の混合粉を含む原料粉末に、水系溶媒を配合し、得られたスラリーを12時間以上混合した後、固液分離・乾燥・造粒し、引き続き、この造粒物を型枠に入れて成形する。 The mixing and forming method in step (1) is not particularly limited, and can be performed using a known method. For example, an aqueous solvent is blended into a raw material powder containing a mixed powder of oxide containing indium oxide powder, tin oxide, zinc oxide and oxide powder of element X, and the resulting slurry is mixed for 12 hours or more. Solid-liquid separation, drying, and granulation are performed, and then this granulated product is put into a mold and molded.
 混合については、湿式又は乾式によるボールミル、振動ミル、ビーズミル等を用いることができる。均一で微細な結晶粒及び空孔を得るには、短時間で凝集体の解砕効率が高く、添加物の分散状態も良好となるビーズミル混合法が最も好ましい。 For mixing, a wet or dry ball mill, vibration mill, bead mill, or the like can be used. In order to obtain uniform and fine crystal grains and vacancies, a bead mill mixing method is most preferable because the crushing efficiency of the agglomerates is high in a short time and the additive is well dispersed.
 ボールミルによる混合時間は、好ましくは15時間以上、より好ましくは19時間以上とする。混合時間が不足すると最終的に得られる焼結体中に金属Xの酸化物等の高抵抗の化合物が生成するおそれがあるからである。
 ビーズミルによる粉砕、混合時間は、装置の大きさ、処理するスラリー量によって異なるが、スラリー中の粒度分布がすべて1μm以下と均一になるように適宜調整する。
The mixing time by the ball mill is preferably 15 hours or more, more preferably 19 hours or more. This is because if the mixing time is insufficient, a high resistance compound such as an oxide of metal X may be formed in the finally obtained sintered body.
The pulverization and mixing time by the bead mill varies depending on the size of the apparatus and the amount of slurry to be processed, but is appropriately adjusted so that the particle size distribution in the slurry is all uniform at 1 μm or less.
 また、混合する際にはバインダーを任意量だけ添加し、同時に混合を行うと好ましい。バインダーには、ポリビニルアルコール、酢酸ビニル等を用いることができる。 Also, when mixing, it is preferable to add an arbitrary amount of a binder and mix them at the same time. As the binder, polyvinyl alcohol, vinyl acetate, or the like can be used.
 次に、原料粉末スラリーから造粒粉を得る。造粒に際しては、急速乾燥造粒を行うことが好ましい。急速乾燥造粒するための装置としては、スプレードライヤが広く用いられている。具体的な乾燥条件は、乾燥するスラリーのスラリー濃度、乾燥に用いる熱風温度、風量等の諸条件により決定されるため、実施に際しては、予め最適条件を求めておくことが必要となる。 Next, granulated powder is obtained from the raw material powder slurry. In granulation, it is preferable to perform rapid drying granulation. As an apparatus for rapid drying granulation, a spray dryer is widely used. Since specific drying conditions are determined by various conditions such as the slurry concentration of the slurry to be dried, the temperature of hot air used for drying, and the amount of air, it is necessary to obtain optimum conditions in advance.
 自然乾燥を行うと、原料粉末の比重差によって沈降速度が異なるため、In粉末、Sn粉末、ZnO粉末及び金属Xの酸化物粉末の分離が起こり、均一な造粒粉が得られなくなるおそれがある。この不均一な造粒粉を用いて焼結体を作製すると、焼結体内部に元素Xの酸化物等が存在して、スパッタリングにおける異常放電の原因となる場合がある。
 造粒粉に対して、通常、金型プレス又は冷間静水圧プレス(CIP)により、例えば1.2ton/cm以上の圧力で成形を施して成形体を得る。圧力は、この値より大きくてもよい。
When natural drying is performed, the sedimentation speed varies depending on the specific gravity difference of the raw material powder, so that separation of In 2 O 3 powder, Sn 2 O 2 powder, ZnO powder and metal X oxide powder occurs, and uniform granulated powder is formed. There is a risk that it will not be obtained. When a sintered body is produced using this non-uniform granulated powder, an oxide of element X or the like is present inside the sintered body, which may cause abnormal discharge in sputtering.
The granulated powder is usually molded by a die press or cold isostatic press (CIP) at a pressure of, for example, 1.2 ton / cm 2 or more to obtain a molded body. The pressure may be greater than this value.
(2)成形体を焼結する工程
 得られた成形物を1200~1650℃の焼結温度で10~50時間焼結して焼結体を得ることができる。
 焼結温度は好ましくは1300~1600℃、より好ましくは1350~1550℃、さらに好ましくは1400~1500℃である。焼結時間は好ましくは12~40時間、より好ましくは13~30時間である。
(2) Step of Sintering Molded Body The obtained molded product can be sintered at a sintering temperature of 1200 to 1650 ° C. for 10 to 50 hours to obtain a sintered body.
The sintering temperature is preferably 1300 to 1600 ° C, more preferably 1350 to 1550 ° C, and still more preferably 1400 to 1500 ° C. The sintering time is preferably 12 to 40 hours, more preferably 13 to 30 hours.
 焼結温度が1200℃以上で焼結時間が10時間以上であると、元素Xの酸化物等がターゲット内部に形成されにくく、異常放電が起こりにくいターゲットとすることができる。一方、焼成温度が1650℃以下で焼成時間が50時間以下であれば、著しい結晶粒成長による平均結晶粒径の増大や、粗大空孔の発生等が抑えられ、焼結体強度の低下や異常放電が起こりにくくすることができる。 When the sintering temperature is 1200 ° C. or more and the sintering time is 10 hours or more, the oxide of the element X or the like is hardly formed inside the target, and an abnormal discharge hardly occurs. On the other hand, if the firing temperature is 1650 ° C. or less and the firing time is 50 hours or less, the increase in the average crystal grain size due to remarkable crystal grain growth, the generation of coarse pores, etc. can be suppressed, and the strength of the sintered body is reduced or abnormal. Discharge can be made difficult to occur.
 本発明で用いる焼結方法としては、常圧焼結法の他、ホットプレス、酸素加圧、熱間等方圧加圧等の加圧焼結法も採用することができる。ただし、製造コストの低減、大量生産の可能性、容易に大型の焼結体を製造できるといった観点から、常圧焼結法を採用することが好ましい。 As a sintering method used in the present invention, a pressure sintering method such as hot press, oxygen pressurization, hot isostatic pressurization and the like can be employed in addition to the atmospheric pressure sintering method. However, it is preferable to employ a normal pressure sintering method from the viewpoints of reducing manufacturing costs, possibility of mass production, and easy production of large sintered bodies.
 常圧焼結法では、成形体を大気雰囲気、又は酸化性ガス雰囲気、好ましくは酸化性ガス雰囲気にて焼結する。酸化性ガス雰囲気とは、好ましくは酸素ガス雰囲気である。酸素ガス雰囲気は、酸素濃度が、例えば10~100体積%の雰囲気であることが好ましい。上記焼結体の製造方法においては、昇温過程にて酸素ガス雰囲気を導入することで、焼結体密度をより高くすることができる。 In the normal pressure sintering method, the compact is sintered in an air atmosphere or an oxidizing gas atmosphere, preferably an oxidizing gas atmosphere. The oxidizing gas atmosphere is preferably an oxygen gas atmosphere. The oxygen gas atmosphere is preferably an atmosphere having an oxygen concentration of, for example, 10 to 100% by volume. In the method for producing a sintered body, the density of the sintered body can be further increased by introducing an oxygen gas atmosphere in the temperature raising process.
 さらに、焼結に際しての昇温速度は、800℃から焼結温度(1200~1650℃)までを0.1~2℃/分とすることが好ましい。
 インジウム元素(In)、酸化スズ(Sn)、亜鉛元素(Zn)及び元素Xを含有する酸化物のスパッタリングターゲットにおいて800℃から上の温度範囲は、焼結が最も進行する範囲である。この温度範囲での昇温速度を0.1℃/分より速くすると、著しい結晶粒成長を防ぎやすくなり、高密度化しやすくなる。一方、昇温速度を2℃/分より遅くすることで、元素Xの酸化物等がターゲット内部に析出することを防ぎやすくなり、ターゲット抵抗が下がりやすくなる。
Further, it is preferable that the heating rate during sintering is from 800 ° C. to a sintering temperature (1200 to 1650 ° C.) of 0.1 to 2 ° C./min.
In the sputtering target of oxide containing indium element (In), tin oxide (Sn), zinc element (Zn) and element X, the temperature range above 800 ° C. is the range where the sintering proceeds most. When the rate of temperature rise in this temperature range is faster than 0.1 ° C./min, it becomes easy to prevent significant crystal grain growth and to increase the density. On the other hand, by making the temperature increase rate slower than 2 ° C./min, it becomes easy to prevent the oxide of element X and the like from being precipitated inside the target, and the target resistance is likely to be lowered.
 800℃から焼結温度における昇温速度は、好ましくは0.1~1.3℃/分、より好ましくは0.1~1.1℃/分である。
 さらに、焼結温度(1200~1650℃)まで昇温させる前に、700~900℃の温度範囲で1~5時間、温度を保持する仮焼き工程を加えると好ましい。800℃付近から熱収縮が急激に進むため、700~900℃の温度範囲で1~5時間、保温することにより、ポアの生成を抑えることができ、ターゲット抵抗が下がりやすくなる。
The heating rate from 800 ° C. to the sintering temperature is preferably 0.1 to 1.3 ° C./min, more preferably 0.1 to 1.1 ° C./min.
Furthermore, it is preferable to add a calcining step of maintaining the temperature in the temperature range of 700 to 900 ° C. for 1 to 5 hours before raising the temperature to the sintering temperature (1200 to 1650 ° C.). Since heat shrinkage proceeds rapidly from around 800 ° C., maintaining the temperature in the temperature range of 700 to 900 ° C. for 1 to 5 hours can suppress the generation of pores, and the target resistance tends to decrease.
 上記焼成工程で得られた焼結体のバルク抵抗をターゲット全体で均一化するために、必要に応じて還元工程を設けてもよい。
 還元方法としては、例えば、還元性ガスによる方法や真空焼成又は不活性ガスによる還元等が挙げられる。
 還元性ガスによる還元処理の場合、水素、メタン、一酸化炭素、又はこれらのガスと酸素との混合ガス等を用いることができる。
In order to make the bulk resistance of the sintered body obtained in the firing step uniform over the entire target, a reduction step may be provided as necessary.
Examples of the reduction method include a method using a reducing gas, vacuum firing, or reduction using an inert gas.
In the case of reduction treatment with a reducing gas, hydrogen, methane, carbon monoxide, a mixed gas of these gases and oxygen, or the like can be used.
 不活性ガス中での焼成による還元処理の場合、窒素、アルゴン、又はこれらのガスと酸素との混合ガス等を用いることができる。
 還元処理時の温度は、通常100~800℃、好ましくは200~800℃である。また、還元処理の時間は、通常0.01~10時間、好ましくは0.05~5時間である。
In the case of reduction treatment by firing in an inert gas, nitrogen, argon, a mixed gas of these gases and oxygen, or the like can be used.
The temperature during the reduction treatment is usually 100 to 800 ° C, preferably 200 to 800 ° C. The reduction treatment time is usually 0.01 to 10 hours, preferably 0.05 to 5 hours.
 以上をまとめると、例えば、酸化インジウム粉と酸化スズ粉と酸化亜鉛粉及び元素Xの酸化物との混合粉を含む原料粉末に、水系溶媒を配合し、得られたスラリーを12時間以上混合した後、固液分離・乾燥・造粒し、引き続き、この造粒物を型枠に入れて成形し、その後、得られた成形物を酸素雰囲気中、800℃から焼結温度までの昇温速度を0.1~2℃/分とし、1200~1650℃で10~50時間焼成することで本発明に用いる焼結体を得ることができる。さらに700~900℃の温度範囲で1~5時間、温度を保持する仮焼き工程を加えると好ましい。 To summarize the above, for example, an aqueous solvent is blended with a raw material powder containing a mixed powder of indium oxide powder, tin oxide powder, zinc oxide powder and oxide of element X, and the resulting slurry is mixed for 12 hours or more. Thereafter, solid-liquid separation, drying, and granulation are performed, and then this granulated product is put into a mold and molded. Thereafter, the obtained molded product is heated in an oxygen atmosphere from 800 ° C. to a sintering temperature. The sintered body used in the present invention can be obtained by firing at 1200 to 1650 ° C. for 10 to 50 hours at 0.1 to 2 ° C./min. Further, it is preferable to add a calcining step for maintaining the temperature in the temperature range of 700 to 900 ° C. for 1 to 5 hours.
 上記で得られた焼結体を加工することにより本発明のスパッタリングターゲットとすることができる。具体的には、焼結体をスパッタリング装置への装着に適した形状に切削加工することでスパッタリングターゲット素材とし、該ターゲット素材をバッキングプレートに接着することでスパッタリングターゲットとすることができる。 The sputtering target of the present invention can be obtained by processing the sintered body obtained above. Specifically, a sputtering target material can be obtained by cutting the sintered body into a shape suitable for mounting on a sputtering apparatus, and a sputtering target can be obtained by bonding the target material to a backing plate.
 焼結体をターゲット素材とするには、焼結体を、例えば平面研削盤で研削して表面粗さRaが0.5μm以下の素材とする。ここで、さらにターゲット素材のスパッタ面に鏡面加工を施して、平均表面粗さRaが1000オングストローム以下としてもよい。 In order to use the sintered body as a target material, the sintered body is ground with, for example, a surface grinder to obtain a material having a surface roughness Ra of 0.5 μm or less. Here, the sputter surface of the target material may be further mirror-finished so that the average surface roughness Ra may be 1000 angstroms or less.
 鏡面加工(研磨)は、機械的な研磨、化学研磨、メカノケミカル研磨(機械的な研磨と化学研磨の併用)等の、公知の研磨技術を用いることができる。例えば、固定砥粒ポリッシャー(ポリッシュ液:水)で#2000以上にポリッシングしたり、又は遊離砥粒ラップ(研磨材:SiCペースト等)にてラッピング後、研磨材をダイヤモンドペーストに換えてラッピングしたりすることによって得ることができる。このような研磨方法には特に制限はない。 Mirror surface processing (polishing) can be performed using a known polishing technique such as mechanical polishing, chemical polishing, mechanochemical polishing (a combination of mechanical polishing and chemical polishing). For example, polishing to # 2000 or more with a fixed abrasive polisher (polishing liquid: water), or lapping with loose abrasive lapping (abrasive: SiC paste, etc.), and then lapping by changing the abrasive to diamond paste Can be obtained. Such a polishing method is not particularly limited.
 ターゲット素材の表面は200~10,000番のダイヤモンド砥石により仕上げを行うことが好ましく、400~5,000番のダイヤモンド砥石により仕上げを行うことが特に好ましい。200番より小さい、又は10,000番より大きいダイヤモンド砥石を使用するとターゲット素材が割れやすくなるおそれがある。 The surface of the target material is preferably finished with a diamond grindstone of No. 200 to 10,000, and particularly preferably finished with a diamond grindstone of No. 400 to 5,000. If a diamond grindstone smaller than 200 or larger than 10,000 is used, the target material may be easily broken.
 ターゲット素材の表面粗さRaが0.5μm以下であり、方向性のない研削面を備えていることが好ましい。Raが0.5μm以下であり、方向性のない研磨面を備えていれば、異常放電が起きたり、パーティクルが発生したりするおそれが少ない。
 次に、得られたターゲット素材を清浄処理する。清浄処理にはエアーブロー又は流水洗浄等を使用できる。エアーブローで異物を除去する際には、ノズルの向い側から集塵機で吸気を行なうとより有効に除去できる。
It is preferable that the target material has a surface roughness Ra of 0.5 μm or less and has a non-directional ground surface. If Ra is 0.5 μm or less and a non-directional polished surface is provided, there is little risk of abnormal discharge or generation of particles.
Next, the obtained target material is cleaned. Air blow or running water washing can be used for the cleaning treatment. When removing foreign matter by air blow, it is possible to remove the foreign matter more effectively by suctioning with a dust collector from the opposite side of the nozzle.
 尚、以上のエアーブローや流水洗浄では限界があるので、さらに超音波洗浄等を行なうこともできる。この超音波洗浄は周波数25~300KHzの間で多重発振させて行なう方法が有効である。例えば周波数25~300KHzの間で、25kHz刻みに12種類の周波数を多重発振させて超音波洗浄を行なうのが好ましい。 In addition, since there is a limit in the above air blow and running water cleaning, ultrasonic cleaning and the like can also be performed. This ultrasonic cleaning is effective by performing multiple oscillations at a frequency of 25 to 300 KHz. For example, it is preferable to perform ultrasonic cleaning by oscillating 12 types of frequencies in 25 kHz increments between frequencies of 25 to 300 KHz.
 ターゲット素材の厚みは通常2~20mm、好ましくは3~12mm、特に好ましくは4~6mmである。
 上記のようにして得られたターゲット素材をバッキングプレートへボンディングすることによって、スパッタリングターゲットを得ることができる。また、複数のターゲット素材を1つのバッキングプレートに取り付け、実質1つのターゲットとしてもよい。
The thickness of the target material is usually 2 to 20 mm, preferably 3 to 12 mm, particularly preferably 4 to 6 mm.
A sputtering target can be obtained by bonding the target material obtained as described above to a backing plate. Further, a plurality of target materials may be attached to one backing plate to substantially serve as one target.
 本発明の酸化物半導体薄膜は、上記説明した本発明のスパッタリングターゲットを用いて、スパッタリング法により成膜することを特徴とする。
 本発明の酸化物半導体薄膜は、インジウム、スズ、亜鉛、元素X、酸素を含み、通常、原子比は(1)~(4)のとおりである。
The oxide semiconductor thin film of the present invention is formed by a sputtering method using the above-described sputtering target of the present invention.
The oxide semiconductor thin film of the present invention contains indium, tin, zinc, element X, and oxygen, and usually has an atomic ratio of (1) to (4).
0.20≦In/(In+Sn+Zn+X)≦0.85 (1)
0.01≦Sn/(In+Sn+Zn+X)≦0.35 (2)
0.01≦Zn/(In+Sn+Zn+X)≦0.70 (3)
0.01≦X/(In+Sn+Zn+X)≦0.30  (4)
(式中、In、Sn、Zn及びXは、それぞれ、スパッタリングターゲットにおける各元素の原子比を示す。)
0.20 ≦ In / (In + Sn + Zn + X) ≦ 0.85 (1)
0.01 ≦ Sn / (In + Sn + Zn + X) ≦ 0.35 (2)
0.01 ≦ Zn / (In + Sn + Zn + X) ≦ 0.70 (3)
0.01 ≦ X / (In + Sn + Zn + X) ≦ 0.30 (4)
(In the formula, In, Sn, Zn, and X each represent an atomic ratio of each element in the sputtering target.)
 上記式(1)において、In元素の量が0.20以上であれば、成膜した膜をTFTのチャネル層に適用したときに移動度を高くすることができる。
 一方、In元素の量が0.85以下であれば、成膜した膜をTFTのチャネル層に適用したときに、導電化しにくくなりTFTを動作させることができる。
In the above formula (1), if the amount of In element is 0.20 or more, the mobility can be increased when the formed film is applied to the channel layer of the TFT.
On the other hand, when the amount of In element is 0.85 or less, when the formed film is applied to the channel layer of the TFT, it becomes difficult to conduct and the TFT can be operated.
 上記式(2)において、Sn元素の量が0.01以上であれば、得られる薄膜のエッチング液への選択性が確保できる。
 一方、Sn元素の量が0.35以下であれば、シュウ酸系エッチング液に対するエッチング性が確保でき面内均一性が失われにくくなる。
In the above formula (2), if the amount of Sn element is 0.01 or more, the selectivity of the resulting thin film to the etching solution can be ensured.
On the other hand, if the amount of Sn element is 0.35 or less, the etching property with respect to the oxalic acid-based etching solution can be secured and the in-plane uniformity is hardly lost.
 上記式(3)において、Zn元素の量が0.01以上であれば、得られる膜が非晶質膜として安定しやすくなる。一方、Zn元素の量が0.70以下であれば、得られる薄膜のエッチング液への溶解速度が高すぎてウェットエッチングが困難になることがなくなる。 In the above formula (3), if the amount of Zn element is 0.01 or more, the obtained film is easily stabilized as an amorphous film. On the other hand, if the amount of Zn element is 0.70 or less, the dissolution rate of the resulting thin film in the etching solution is too high, and wet etching does not become difficult.
 上記式(4)において、元素Xの量が0.01以上であれば、膜中のキャリア濃度を抑えることができ、TFTを動作させやすくなる。一方、元素Xの量が0.30以下であれば、移動度が低下せず、良好なTFT特性が得られる。
 本発明のスパッタリングターゲットは、高い導電性を有することから成膜速度の速いDCスパッタリング法を適用することができる。
In the above formula (4), when the amount of the element X is 0.01 or more, the carrier concentration in the film can be suppressed and the TFT can be easily operated. On the other hand, when the amount of the element X is 0.30 or less, the mobility is not lowered and good TFT characteristics can be obtained.
Since the sputtering target of the present invention has high conductivity, a DC sputtering method having a high deposition rate can be applied.
 本発明のスパッタリングターゲットは、上記DCスパッタリング法に加えて、RFスパッタリング法、ACスパッタリング法、パルスDCスパッタリング法にも適用することができ、異常放電のないスパッタリングが可能である。
 酸化物半導体薄膜は、上記スパッタリングターゲットを用いて、蒸着法、イオンプレーティング法、パルスレーザー蒸着法等により作製することもできる。
The sputtering target of the present invention can be applied to an RF sputtering method, an AC sputtering method, and a pulsed DC sputtering method in addition to the DC sputtering method, and enables sputtering without abnormal discharge.
The oxide semiconductor thin film can also be manufactured by a vapor deposition method, an ion plating method, a pulse laser vapor deposition method, or the like using the above sputtering target.
 スパッタリングガス(雰囲気)としては、アルゴン等の希ガスと酸化性ガスとの混合ガスを用いることができる。酸化性ガスとはO、CO、O、水蒸気(HO)、NO等が挙げられる。スパッタリングガスは、希ガスと、水蒸気、酸素ガス及び亜酸化窒素ガスから選ばれる一種以上を含有する混合気体が好ましく、少なくとも希ガスと水蒸気とを含有する混合気体であることがより好ましい。
 酸化物半導体薄膜のキャリア濃度は、通常1019cm-3以下であり、好ましくは1013~1018cm-3であり、さらに好ましくは1014~1018cm-3であり、特に好ましくは1015~1018cm-3である。
As the sputtering gas (atmosphere), a mixed gas of a rare gas such as argon and an oxidizing gas can be used. Examples of the oxidizing gas include O 2 , CO 2 , O 3 , water vapor (H 2 O), and N 2 O. The sputtering gas is preferably a mixed gas containing a rare gas and one or more selected from water vapor, oxygen gas and nitrous oxide gas, and more preferably a mixed gas containing at least a rare gas and water vapor.
The carrier concentration of the oxide semiconductor thin film is usually 10 19 cm −3 or less, preferably 10 13 to 10 18 cm −3 , more preferably 10 14 to 10 18 cm −3 , and particularly preferably 10 13 cm −3. 15 to 10 18 cm −3 .
 酸化物層のキャリア濃度が1019cm-3以下であれば、薄膜トランジスタ等の素子を構成した際に、漏れ電流の発生を抑えることができる。また、ノーマリーオンになってしまったり、on-off比が小さくなってしまったりすることを防ぐことができる。さらに、キャリア濃度が1013cm-3以上であればキャリア数が十分であり、TFTとして駆動させることができる。
 酸化物半導体薄膜のキャリア濃度は、ホール効果測定方法により測定することができる。
When the carrier concentration of the oxide layer is 10 19 cm −3 or less, generation of leakage current can be suppressed when an element such as a thin film transistor is formed. Further, it is possible to prevent the normally-on state and the on-off ratio from becoming small. Further, when the carrier concentration is 10 13 cm −3 or more, the number of carriers is sufficient and the TFT can be driven.
The carrier concentration of the oxide semiconductor thin film can be measured by a Hall effect measurement method.
 スパッタリング成膜時の酸素分圧比は0%以上30%以下とすることが好ましい。酸素分圧比が30%超の条件で作製した薄膜は、大幅にキャリア濃度が低減しキャリア濃度が1013cm-3未満となるおそれがある。
 好ましくは、酸素分圧比は0%~30%、特に好ましくは0%~20%である。
The oxygen partial pressure ratio during sputtering film formation is preferably 0% or more and 30% or less. A thin film manufactured under a condition where the oxygen partial pressure ratio exceeds 30% may significantly reduce the carrier concentration and the carrier concentration may be less than 10 13 cm −3 .
The oxygen partial pressure ratio is preferably 0% to 30%, particularly preferably 0% to 20%.
 本発明における酸化物薄膜堆積時のスパッタガス(雰囲気)に含まれる水分子の分圧比、即ち、[水蒸気(HO)]/([水蒸気(HO)]+[希ガス]+[その他のガス分子])は、0.1~25%であることが好ましい。
 また、水の分圧比が25%以下であれば、膜密度の低下を防ぐことができ、Inの5s軌道の重なりが小さくなることがないので、移動度が低下しにくくなる。スパッタリング時の雰囲気中の水の分圧比は0.7~13%がより好ましく、1~6%が特に好ましい。
The partial pressure ratio of water molecules contained in the sputtering gas (atmosphere) during oxide thin film deposition in the present invention, that is, [water vapor (H 2 O)] / ([water vapor (H 2 O)] + [rare gas] + [ The other gas molecules]) are preferably 0.1 to 25%.
Also, if the water partial pressure ratio is 25% or less, the film density can be prevented from decreasing, and the overlap of the 5s orbitals of In will not be reduced, so that the mobility is unlikely to decrease. The partial pressure ratio of water in the atmosphere during sputtering is more preferably 0.7 to 13%, particularly preferably 1 to 6%.
 スパッタリングにより成膜する際の基板温度は、25~120℃であることが好ましく、さらに好ましくは25~100℃、特に好ましくは25~90℃である。成膜時の基板温度が120℃以下であれば成膜時に導入する酸素等の取り込みが減少することを防ぐことができ、加熱後の薄膜のキャリア濃度を1019cm-3以下にしやすくなる。また、成膜時の基板温度が25℃以上であれば薄膜の膜密度が低下することがなく、TFTの移動度が低下しにくくなる。 The substrate temperature when forming a film by sputtering is preferably 25 to 120 ° C., more preferably 25 to 100 ° C., and particularly preferably 25 to 90 ° C. If the substrate temperature at the time of film formation is 120 ° C. or lower, it is possible to prevent the intake of oxygen or the like introduced at the time of film formation from being reduced, and the carrier concentration of the thin film after heating is easily reduced to 10 19 cm −3 or lower. Further, if the substrate temperature during film formation is 25 ° C. or higher, the film density of the thin film does not decrease, and the mobility of the TFT is difficult to decrease.
 スパッタリングによって得られた酸化物薄膜を、さらに150~500℃に15分~5時間保持してアニール処理を施すことが好ましい。成膜後のアニール処理温度は200℃以上450℃以下であることがより好ましく、250℃以上350℃以下であることがさらに好ましい。上記アニールを施すことにより、半導体特性が得られる。 The oxide thin film obtained by sputtering is preferably further annealed by holding at 150 to 500 ° C. for 15 minutes to 5 hours. The annealing temperature after film formation is more preferably 200 ° C. or higher and 450 ° C. or lower, and further preferably 250 ° C. or higher and 350 ° C. or lower. By performing the annealing, semiconductor characteristics can be obtained.
 また、加熱時の雰囲気は、特に限定されるわけではないが、キャリア制御性の観点から、大気雰囲気、酸素流通雰囲気が好ましい。
 酸化物薄膜の後処理アニール工程においては、酸素の存在下又は不存在下でランプアニール装置、レーザーアニール装置、熱プラズマ装置、熱風加熱装置、接触加熱装置等を用いることができる。
The atmosphere during heating is not particularly limited, but from the viewpoint of carrier controllability, an air atmosphere or an oxygen circulation atmosphere is preferable.
In the post-treatment annealing step of the oxide thin film, a lamp annealing device, a laser annealing device, a thermal plasma device, a hot air heating device, a contact heating device, or the like can be used in the presence or absence of oxygen.
 スパッタリング時におけるターゲットと基板との間の距離は、基板の成膜面に対して垂直方向に好ましくは1~15cmであり、さらに好ましくは2~8cmである。この距離が1cm以上であれば、基板に到達するターゲット構成元素の粒子の運動エネルギーが大きくなりすぎず、良好な膜特性を得ることができ、膜厚及び電気特性の面内分布を均一にしやすくなる。一方、ターゲットと基板との間隔が15cm以下であれば、基板に到達するターゲット構成元素の粒子の運動エネルギーが小さくなりすぎず緻密な膜を得ることができ、良好な半導体特性を得ることができる。 The distance between the target and the substrate at the time of sputtering is preferably 1 to 15 cm, more preferably 2 to 8 cm in the direction perpendicular to the film formation surface of the substrate. If this distance is 1 cm or more, the kinetic energy of the target constituent element particles reaching the substrate does not become too large, and good film characteristics can be obtained, and the in-plane distribution of film thickness and electrical characteristics can be made uniform easily. Become. On the other hand, when the distance between the target and the substrate is 15 cm or less, the kinetic energy of the target constituent particles reaching the substrate is not too small, and a dense film can be obtained and good semiconductor characteristics can be obtained. .
 酸化物薄膜の成膜は、磁場強度が300~1500ガウスの雰囲気下でスパッタリングすることが望ましい。磁場強度が300ガウス以上であると、プラズマ密度を高くすることができるため、高抵抗のスパッタリングターゲットであっても、問題なくスパッタリングができる。一方、1500ガウス以下であると、膜厚及び膜中の電気特性が制御しやすくなる。 The oxide thin film is preferably formed by sputtering in an atmosphere having a magnetic field strength of 300 to 1500 gauss. When the magnetic field strength is 300 gauss or more, the plasma density can be increased, so that even a high resistance sputtering target can be sputtered without problems. On the other hand, when it is 1500 gauss or less, the film thickness and the electrical characteristics in the film can be easily controlled.
 気体雰囲気の圧力(スパッタ圧力)は、プラズマが安定して放電できる範囲であれば特に限定されないが、好ましくは0.1~3.0Paであり、さらに好ましくは0.1~1.5Paであり、特に好ましくは0.1~1.0Paである。スパッタ圧力が3.0Pa以下であれば、スパッタ粒子の平均自由工程を長くすることができ、薄膜の密度を向上させやすくなる。また、スパッタ圧力が0.1Pa以上であると、成膜時に膜中に微結晶が生成するのを防ぎやすくなる。尚、スパッタ圧力とは、アルゴン等の希ガス原子、水蒸気、酸素ガス等を導入した後のスパッタ開始時の系内の全圧をいう。 The pressure in the gas atmosphere (sputtering pressure) is not particularly limited as long as the plasma can be stably discharged, but is preferably 0.1 to 3.0 Pa, more preferably 0.1 to 1.5 Pa. Particularly preferred is 0.1 to 1.0 Pa. If the sputtering pressure is 3.0 Pa or less, the mean free path of sputtered particles can be lengthened and the density of the thin film can be easily improved. Moreover, when the sputtering pressure is 0.1 Pa or more, it becomes easy to prevent the formation of microcrystals in the film during film formation. The sputtering pressure refers to the total pressure in the system at the start of sputtering after introducing a rare gas atom such as argon, water vapor, oxygen gas or the like.
 また、酸化物半導体薄膜の成膜を、次のような交流スパッタリングで行ってもよい。
 真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、各ターゲットに対して交流電源から負電位及び正電位を交互に印加して、ターゲット上にプラズマを発生させて基板表面上に成膜する。
Alternatively, the oxide semiconductor thin film may be formed by AC sputtering as described below.
The substrate is sequentially transported to a position facing three or more targets arranged in parallel at a predetermined interval in the vacuum chamber, and negative and positive potentials are alternately applied to each target from an AC power source. Then, plasma is generated on the target to form a film on the substrate surface.
 このとき、交流電源からの出力の少なくとも1つを、分岐して接続された2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら行う。即ち、上記交流電源からの出力の少なくとも1つを分岐して2枚以上のターゲットに接続し、隣り合うターゲットに異なる電位を印加しながら成膜を行う。 At this time, at least one of the outputs from the AC power supply is performed while switching the target to which the potential is applied between two or more targets that are branched and connected. That is, at least one of the outputs from the AC power supply is branched and connected to two or more targets, and film formation is performed while applying different potentials to adjacent targets.
 尚、交流スパッタリングによって酸化物半導体薄膜を成膜する場合も、例えば、希ガス原子と、水蒸気、酸素ガス及び亜酸化窒素ガスから選ばれる一以上とを含有する混合気体の雰囲気下においてスパッタリングを行うことが好ましく、少なくとも希ガスと水蒸気とを含有する混合気体の雰囲気下においてスパッタリングを行うことが特に好ましい。 Note that when an oxide semiconductor thin film is formed by AC sputtering, for example, sputtering is performed in an atmosphere of a mixed gas containing a rare gas atom and one or more selected from water vapor, oxygen gas, and nitrous oxide gas. It is preferable to perform sputtering in a mixed gas atmosphere containing at least a rare gas and water vapor.
 ACスパッタリングで成膜した場合、工業的に大面積均一性に優れた酸化物層が得られると共に、ターゲットの利用効率の向上が期待できる。
 また、1辺が1mを超える大面積基板にスパッタ成膜する場合には、たとえば特開2005-290550号公報記載のような大面積生産用のACスパッタ装置を使用することが好ましい。
When the film is formed by AC sputtering, an oxide layer having industrially excellent large area uniformity can be obtained, and improvement in the utilization efficiency of the target can be expected.
Further, when sputtering film formation is performed on a large-area substrate having a side exceeding 1 m, it is preferable to use an AC sputtering apparatus for large-area production as described in, for example, Japanese Patent Application Laid-Open No. 2005-290550.
 特開2005-290550号公報記載のACスパッタ装置は、具体的には、真空槽と、真空槽内部に配置された基板ホルダと、この基板ホルダと対向する位置に配置されたスパッタ源とを有する。図10にACスパッタ装置のスパッタ源の要部を示す。スパッタ源は、複数のスパッタ部を有し、板状のターゲット31a~31fをそれぞれ有し、各ターゲット31a~31fのスパッタされる面をスパッタ面とすると、各スパッタ部はスパッタ面が同じ平面上に位置するように配置される。各ターゲット31a~31fは長手方向を有する細長に形成され、各ターゲットは同一形状であり、スパッタ面の長手方向の縁部分(側面)が互いに所定間隔を空けて平行に配置される。従って、隣接するターゲット31a~31fの側面は平行になる。 Specifically, the AC sputtering apparatus described in Japanese Patent Laid-Open No. 2005-290550 includes a vacuum chamber, a substrate holder disposed inside the vacuum chamber, and a sputtering source disposed at a position facing the substrate holder. . FIG. 10 shows a main part of the sputtering source of the AC sputtering apparatus. The sputter source has a plurality of sputter units, each of which has plate-like targets 31a to 31f, and the surfaces to be sputtered of the targets 31a to 31f are sputter surfaces. It arrange | positions so that it may be located in. Each target 31a to 31f is formed in an elongated shape having a longitudinal direction, each target has the same shape, and edge portions (side surfaces) in the longitudinal direction of the sputtering surface are arranged in parallel with a predetermined interval therebetween. Therefore, the side surfaces of the adjacent targets 31a to 31f are parallel.
 真空槽の外部には、交流電源17a~17cが配置されており、各交流電源17a~17cの二つの端子のうち、一方の端子は隣接する二つの電極のうちの一方の電極に接続され、他方の端子は他方の電極に接続されている。各交流電源17a~17cの2つの端子は正負の異なる極性の電圧を出力するようになっており、ターゲット31a~31fは電極に密着して取り付けられているので、隣接する2つのターゲット31a~31fには互いに異なる極性の交流電圧が交流電源17a~17cから印加される。従って、互いに隣接するターゲット31a~31fのうち、一方が正電位に置かれる時には他方が負電位に置かれた状態になる。 AC power supplies 17a to 17c are arranged outside the vacuum chamber, and one of the two terminals of each AC power supply 17a to 17c is connected to one of the two adjacent electrodes. The other terminal is connected to the other electrode. Two terminals of each of the AC power supplies 17a to 17c output voltages of positive and negative different polarities, and the targets 31a to 31f are attached in close contact with the electrodes, so that the two adjacent targets 31a to 31f are adjacent to each other. AC voltages having different polarities are applied from the AC power sources 17a to 17c. Therefore, when one of the targets 31a to 31f adjacent to each other is placed at a positive potential, the other is placed at a negative potential.
 電極のターゲット31a~31fとは反対側の面には磁界形成手段40a~40fが配置されている。各磁界形成手段40a~40fは、外周がターゲット31a~31fの外周と略等しい大きさの細長のリング状磁石と、リング状磁石の長さよりも短い棒状磁石とをそれぞれ有している。 Magnetic field forming means 40a to 40f are disposed on the surface of the electrode opposite to the targets 31a to 31f. Each of the magnetic field forming means 40a to 40f has an elongated ring-shaped magnet whose outer periphery is substantially equal to the outer periphery of the targets 31a to 31f, and a bar-shaped magnet shorter than the length of the ring-shaped magnet.
 各リング状磁石は、対応する1個のターゲット31a~31fの真裏位置で、ターゲット31a~31fの長手方向に対して平行に配置されている。上述したように、ターゲット31a~31fは所定間隔を空けて平行配置されているので、リング状磁石もターゲット31a~31fと同じ間隔を空けて配置されている。 Each ring-shaped magnet is arranged in parallel with the longitudinal direction of the targets 31a to 31f at the position directly behind the corresponding one of the targets 31a to 31f. As described above, since the targets 31a to 31f are arranged in parallel at a predetermined interval, the ring magnets are also arranged at the same interval as the targets 31a to 31f.
 ACスパッタで、酸化物ターゲットを用いる場合の交流パワー密度は、3W/cm以上、20W/cm以下が好ましい。パワー密度が3W/cm以上であると、成膜速度を速くすることができ、生産上経済的である。20W/cm以下であると、ターゲットが破損するのを防ぐことができる。より好ましいパワー密度は3W/cm~15W/cmである。 The AC power density when an oxide target is used in AC sputtering is preferably 3 W / cm 2 or more and 20 W / cm 2 or less. When the power density is 3 W / cm 2 or more, the deposition rate can be increased, which is economical in production. It can prevent that a target breaks that it is 20 W / cm < 2 > or less. A more preferable power density is 3 W / cm 2 to 15 W / cm 2 .
 ACスパッタの周波数は10kHz~1MHzの範囲が好ましい。10kHz以上であると、騒音の問題が発生しにくくなる。1MHzを超えないと、プラズマが広がりすぎるのを防止し、所望のターゲット位置以外でスパッタが行われ、均一性が損なわれることを防ぐことができる。より好ましいACスパッタの周波数は20kHz~500kHzである。
 上記以外のスパッタリング時の条件等は、上述したものから適宜選択すればよい。
The frequency of AC sputtering is preferably in the range of 10 kHz to 1 MHz. When the frequency is 10 kHz or more, the problem of noise hardly occurs. If it does not exceed 1 MHz, it is possible to prevent the plasma from spreading too much, and it is possible to prevent the sputtering from being performed at a position other than the desired target position and the uniformity to be lost. A more preferable frequency of AC sputtering is 20 kHz to 500 kHz.
What is necessary is just to select suitably the conditions at the time of sputtering other than the above from what was mentioned above.
 本発明の酸化物半導体薄膜は、好ましくはリン酸系エッチング液に対して不溶であり、かつ、シュウ酸系エッチング液に対して可溶である。このように、エッチング液に対して、選択性を有することにより、シュウ酸系エッチングによって酸化物薄膜のエッチングを行い、さらに、この酸化物薄膜状に形成した電極を、リン酸系エッチング液を用いてパターニングすることが可能となる。 The oxide semiconductor thin film of the present invention is preferably insoluble in a phosphoric acid etching solution and soluble in an oxalic acid etching solution. As described above, the oxide thin film is etched by oxalic acid-based etching because it has selectivity with respect to the etching liquid, and the electrode formed in this oxide thin film shape is further used with a phosphoric acid-based etching liquid. Patterning becomes possible.
 エッチング液に対して不溶とは、35℃におけるエッチング速度が10nm/分以下であることを指し、エッチング液に対して可溶とは35℃におけるエッチング速度が10nm/分より大きいことを指す。 “Insoluble in the etching solution” means that the etching rate at 35 ° C. is 10 nm / min or less, and “soluble in the etching solution” means that the etching rate at 35 ° C. is larger than 10 nm / min.
 好ましくは、リン酸系エッチング液による35℃におけるエッチング速度が10nm/分未満、より好ましくは5nm/分以下であり、さらに好ましくは1nm/分以下であり、かつ、前記シュウ酸系エッチング液による35℃におけるエッチング液が20nm/分以上、好ましくは30nm/分以上であるとよい。エッチング速度が上記の範囲にあることで、エッチング液の選択性を発揮することができ、バックチャネルエッチングによるTFTの作製が可能となる。 Preferably, the etching rate at 35 ° C. with a phosphoric acid etching solution is less than 10 nm / min, more preferably 5 nm / min or less, and further preferably 1 nm / min or less, and 35 with the oxalic acid etching solution. The etching solution at 20 ° C. is 20 nm / min or more, preferably 30 nm / min or more. When the etching rate is in the above range, the selectivity of the etching solution can be exhibited, and a TFT can be manufactured by back channel etching.
 シュウ酸系エッチング液としては、ITO-06N(関東化学(株)製)が挙げられる。好ましくは、シュウ酸を0.5~10wt%含むものがよい。但し、シュウ酸以外でも、マロン酸やコハク酸、酢酸等のカルボン酸やその他の酸を含んでいてもよく、必ずしもシュウ酸を含む必要はない。 Examples of the oxalic acid-based etching solution include ITO-06N (manufactured by Kanto Chemical Co., Inc.). Preferably, it contains 0.5 to 10 wt% oxalic acid. However, in addition to oxalic acid, carboxylic acid such as malonic acid, succinic acid, and acetic acid and other acids may be included, and oxalic acid is not necessarily included.
 リン酸系エッチング液としては、例えば、リン酸、酢酸、硝酸を含むPAN系エッチング液が挙げられる。PAN系エッチング液は、リン酸45~95wt%、酢酸3~50wt%、硝酸0.5~5wt%の範囲にあるものが好ましい。 Examples of the phosphoric acid-based etching solution include PAN-based etching solutions containing phosphoric acid, acetic acid, and nitric acid. The PAN-based etching solution is preferably in the range of 45 to 95 wt% phosphoric acid, 3 to 50 wt% acetic acid, and 0.5 to 5 wt% nitric acid.
 本発明の酸化物半導体薄膜は、薄膜トランジスタに使用でき、特にチャネル層として好適に使用できる。
 本発明の薄膜トランジスタは、上記説明した本発明の酸化物半導体薄膜をチャネル層として有していれば、その素子構成は特に限定されず、公知の各種の素子構成を採用することができる。
The oxide semiconductor thin film of the present invention can be used for a thin film transistor, and can be particularly suitably used as a channel layer.
The element structure of the thin film transistor of the present invention is not particularly limited as long as it includes the above-described oxide semiconductor thin film of the present invention as a channel layer, and various known element structures can be employed.
 本発明の薄膜トランジスタにおけるチャネル層の膜厚は、通常10~300nm、好ましくは20~250nm、より好ましくは30~200nm、さらに好ましくは35~120nm、特に好ましくは40~80nmである。チャネル層の膜厚が10nm以上であると、大面積に成膜した際の膜厚の不均一性を低減でき、作製したTFTの特性が面内で不均一になることを防ぐことができる。一方、膜厚が300nm以下であれば、成膜時間が長くなりすぎずに工業的に有利となる。 The thickness of the channel layer in the thin film transistor of the present invention is usually 10 to 300 nm, preferably 20 to 250 nm, more preferably 30 to 200 nm, still more preferably 35 to 120 nm, and particularly preferably 40 to 80 nm. When the thickness of the channel layer is 10 nm or more, the non-uniformity of the film thickness when the film is formed in a large area can be reduced, and the characteristics of the manufactured TFT can be prevented from becoming non-uniform in the plane. On the other hand, if the film thickness is 300 nm or less, the film formation time does not become too long, which is industrially advantageous.
 本発明の薄膜トランジスタにおけるチャネル層は、通常、N型領域で用いられるが、P型Si系半導体、P型酸化物半導体、P型有機半導体等の種々のP型半導体と組合せてPN接合型トランジスタ等の各種の半導体デバイスに利用することができる。 The channel layer in the thin film transistor of the present invention is usually used in an N-type region, but a PN junction transistor or the like in combination with various P-type semiconductors such as a P-type Si-based semiconductor, a P-type oxide semiconductor, and a P-type organic semiconductor. It can be used for various semiconductor devices.
 本発明の薄膜トランジスタのチャネル層は、結晶組成を問わない。即ち、アモルファスであっても、結晶であってもよい。さらにアニール処理後に少なくともゲート電極と重なる領域において一部、結晶化していてもよい。ここで結晶化とは、非晶質の状態から結晶核が生成すること、又は結晶核が生成された状態から結晶粒が成長することをいう。特にバックチャネル側の一部を結晶化させたときは、プラズマプロセス(CVDプロセス等)に対して、耐還元性が向上しTFTの信頼性が改善する。
 結晶化した領域は、例えば、透過型電子顕微鏡(TEM:Transmission Electron Microscope)の電子線回折像から確認することができる。
The channel layer of the thin film transistor of the present invention may have any crystal composition. That is, it may be amorphous or crystalline. Further, at least part of the region overlapping with the gate electrode may be crystallized after the annealing treatment. Here, crystallization means that crystal nuclei are generated from an amorphous state or crystal grains are grown from a state where crystal nuclei are generated. In particular, when a part of the back channel side is crystallized, reduction resistance is improved with respect to a plasma process (CVD process or the like), and the reliability of the TFT is improved.
The crystallized region can be confirmed from, for example, an electron beam diffraction image of a transmission electron microscope (TEM).
 本発明の薄膜トランジスタは、上記チャネル層上に保護膜を備えることが好ましい。本発明の薄膜トランジスタにおける保護膜は、少なくともSiNを含有することが好ましい。SiNはSiOと比較して緻密な膜を形成できるため、TFTの劣化抑制効果が高いという利点を有する。
 尚、xは任意の数であり、SiNは化学量論比が一定でなくともよい。
The thin film transistor of the present invention preferably includes a protective film on the channel layer. The protective film in the thin film transistor of the present invention preferably contains at least SiN x . Since SiN x can form a dense film as compared with SiO 2 , it has an advantage of a high TFT deterioration suppressing effect.
Note that x is an arbitrary number, and the stoichiometric ratio of SiN x may not be constant.
 保護膜は、SiNの他に例えばSiO、Al、Ta、TiO、MgO、ZrO、CeO、KO、LiO、NaO、RbO、Sc、Y、HfO、CaHfO、PbTiO、BaTa、Sm、SrTiO又はAlN等の酸化物等を含むことができる。 In addition to SiN x , the protective film may be, for example, SiO 2 , Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3 , Y 2 O 3 , HfO 2 , CaHfO 3 , PbTiO 3 , BaTa 2 O 6 , Sm 2 O 3 , SrTiO 3, or an oxide such as AlN can be included.
 本発明のインジウム元素(In)スズ元素(Sn)、亜鉛元素(Zn)及び元素Xを含有する酸化物半導体薄膜は、元素Xを含有しているためCVDプロセスによる耐還元性が向上し、保護膜を作製するプロセスによりバックチャネル側が還元されにくく、保護膜としてSiNを用いることができる。 The oxide semiconductor thin film containing indium element (In) tin element (Sn), zinc element (Zn), and element X of the present invention contains element X, so that the reduction resistance by the CVD process is improved, and protection is achieved. The back channel side is not easily reduced by the process of forming the film, and SiN x can be used as the protective film.
 保護膜を形成する前に、チャネル層に対し、オゾン処理、酸素プラズマ処理、二酸化窒素プラズマ処理もしくは亜酸化窒素プラズマ処理を施すことが好ましい。このような処理は、チャネル層を形成した後、保護膜を形成する前であれば、どのタイミングで行ってもよいが、保護膜を形成する直前に行うことが望ましい。このような前処理を行うことによって、チャネル層における酸素欠陥の発生を抑制することができる。 Before forming the protective film, the channel layer is preferably subjected to ozone treatment, oxygen plasma treatment, nitrogen dioxide plasma treatment or nitrous oxide plasma treatment. Such treatment may be performed at any timing after the channel layer is formed and before the protective film is formed, but is preferably performed immediately before the protective film is formed. By performing such pretreatment, generation of oxygen defects in the channel layer can be suppressed.
 また、TFT駆動中に酸化物半導体膜中の水素が拡散すると、閾値電圧のシフトが起こりTFTの信頼性が低下するおそれがある。チャネル層に対し、オゾン処理、酸素プラズマ処理もしくは亜酸化窒素プラズマ処理を施すことにより、薄膜構造中においてIn-OHの結合が安定化され酸化物半導体膜中の水素の拡散を抑制することができる。 In addition, if hydrogen in the oxide semiconductor film diffuses during driving of the TFT, the threshold voltage may shift and the reliability of the TFT may be reduced. By performing ozone treatment, oxygen plasma treatment or nitrous oxide plasma treatment on the channel layer, the In—OH bond is stabilized in the thin film structure, and diffusion of hydrogen in the oxide semiconductor film can be suppressed. .
 薄膜トランジスタは、通常、基板、ゲート電極、ゲート絶縁層、有機半導体層(チャネル層)、ソース電極及びドレイン電極を備える。チャネル層については上述したとおりであり、基板については公知の材料を用いることができる。 A thin film transistor usually includes a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer (channel layer), a source electrode, and a drain electrode. The channel layer is as described above, and a known material can be used for the substrate.
 本発明の薄膜トランジスタにおけるゲート絶縁膜を形成する材料にも特に制限はなく、一般に用いられている材料を任意に選択できる。具体的には、例えば、SiO、SiN、Al、Ta、TiO、MgO、ZrO、CeO、KO、LiO、NaO、RbO、Sc、Y、HfO、CaHfO、PbTiO、BaTa、SrTiO、Sm、AlN等の化合物を用いることができる。これらのなかでも、好ましくはSiO、SiN、Al、Y、HfO、CaHfOであり、より好ましくはSiO、SiN、HfO、Alである。 The material for forming the gate insulating film in the thin film transistor of the present invention is not particularly limited, and a commonly used material can be arbitrarily selected. Specifically, for example, SiO 2, SiN x, Al 2 O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Compounds such as Sc 2 O 3 , Y 2 O 3 , HfO 2 , CaHfO 3 , PbTiO 3 , BaTa 2 O 6 , SrTiO 3 , Sm 2 O 3 , and AlN can be used. Among these, SiO 2 , SiN x , Al 2 O 3 , Y 2 O 3 , HfO 2 and CaHfO 3 are preferable, and SiO 2 , SiN x , HfO 2 and Al 2 O 3 are more preferable.
 ゲート絶縁膜は、例えばプラズマCVD(Chemical Vapor Deposition;化学気相成長)法により形成することができる。
 プラズマCVD法によりゲート絶縁膜を形成し、その上にチャネル層を成膜した場合、ゲート絶縁膜中の水素がチャネル層に拡散し、チャネル層の膜質低下やTFTの信頼性低下を招くおそれがある。チャネル層の膜質低下やTFTの信頼性低下を防ぐために、チャネル層を成膜する前にゲート絶縁膜に対してオゾン処理、酸素プラズマ処理、二酸化窒素プラズマ処理もしくは亜酸化窒素プラズマ処理を施すことが好ましい。このような前処理を行うことによって、チャネル層の膜質の低下やTFTの信頼性低下を防ぐことができる。
The gate insulating film can be formed by, for example, a plasma CVD (Chemical Vapor Deposition) method.
When a gate insulating film is formed by plasma CVD and a channel layer is formed on the gate insulating film, hydrogen in the gate insulating film may diffuse into the channel layer, leading to deterioration in channel layer quality and TFT reliability. is there. In order to prevent deterioration in channel layer quality and TFT reliability, the gate insulating film may be subjected to ozone treatment, oxygen plasma treatment, nitrogen dioxide plasma treatment or nitrous oxide plasma treatment before forming the channel layer. preferable. By performing such pretreatment, it is possible to prevent deterioration of the channel layer film quality and TFT reliability.
 尚、上記の酸化物の酸素数は、必ずしも化学量論比と一致していなくともよく、例えば、SiOでもSiOでもよい。
 ゲート絶縁膜は、異なる材料からなる2層以上の絶縁膜を積層した構造でもよい。また、ゲート絶縁膜は、結晶質、多結晶質、非晶質のいずれであってもよいが、工業的に製造しやすい多結晶質又は非晶質であることが好ましい。
Note that the number of oxygen in the oxide does not necessarily match the stoichiometric ratio, and may be, for example, SiO 2 or SiO x .
The gate insulating film may have a structure in which two or more insulating films made of different materials are stacked. The gate insulating film may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that can be easily manufactured industrially.
 本発明の薄膜トランジスタにおけるドレイン電極、ソース電極及びゲート電極の各電極を形成する材料に特に制限はなく、一般に用いられている材料を任意に選択することができる。例えば、ITO、IZO、ZnO、SnO等の透明電極や、Al、Ag、Cu、Cr、Ni、Mo、Au、Ti、Ta等の金属電極、又はこれらを含む合金の金属電極を用いることができる。 There are no particular limitations on the material for forming each of the drain electrode, the source electrode, and the gate electrode in the thin film transistor of the present invention, and a commonly used material can be arbitrarily selected. For example, a transparent electrode such as ITO, IZO, ZnO, or SnO 2 , a metal electrode such as Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, or Ta, or a metal electrode made of an alloy including these electrodes may be used. it can.
 本発明の薄膜トランジスタは、酸化物薄膜のエッチング液選択性を利用して、活性層である酸化物薄膜上にエッチングストッパーを形成することなく、バックチャネルエッチングによって作製することができる。 The thin film transistor of the present invention can be manufactured by back channel etching without forming an etching stopper on the oxide thin film which is an active layer by utilizing the etching solution selectivity of the oxide thin film.
 IGZO系等の通常の酸化物半導体薄膜を活性層に用いた薄膜トランジスタは、電極をエッチングする際のエッチング液に対して、酸化物半導体薄膜もエッチングされるため、酸化物半導体薄膜上にエッチングを防止するための、例えばSiOx等のエッチングストッパーを形成することが必要である。エッチングストッパーを形成する工程を含むことで生産性が低下していた。 Thin-film transistors using an active layer of a normal oxide semiconductor thin film such as an IGZO system prevent etching on the oxide semiconductor thin film because the oxide semiconductor thin film is also etched against the etchant used to etch the electrodes. For this purpose, it is necessary to form an etching stopper such as SiOx. Productivity has been reduced by including a step of forming an etching stopper.
 しかし、本発明の酸化物半導体薄膜は、薄膜トランジスタを作製する際に、半導体薄膜と電極をパターニングする際のエッチング液を適切に選択することによって、エッチングストッパーを形成しなくて済むために生産性が向上する。 However, the oxide semiconductor thin film of the present invention has a high productivity because it is not necessary to form an etching stopper by appropriately selecting an etching solution for patterning the semiconductor thin film and the electrode when a thin film transistor is manufactured. improves.
 即ち、半導体活性層として、本発明の酸化物半導体薄膜を用いた薄膜トランジスタは、半導体薄膜上にエッチングストッパーを積層させずに、半導体薄膜と電極を異なるエッチング液を用いてパターニングし、電極をパターニングする際に直接エッチング液が半導体薄膜に接する工程を含む製造方法により製造できる。 That is, in the thin film transistor using the oxide semiconductor thin film of the present invention as the semiconductor active layer, the semiconductor thin film and the electrode are patterned using different etching solutions without stacking the etching stopper on the semiconductor thin film, and the electrode is patterned. In this case, it can be manufactured by a manufacturing method including a step in which the etching solution directly contacts the semiconductor thin film.
 具体的には、当該酸化物薄膜のパターニングする際にはシュウ酸系エッチング液等のエッチングが可能な溶液を用いる一方で、電極をパターニングする際には、IZO、ZnO、SnO等の透明導電酸化物やAl、Ag、Cu、Cr、Ni、Mo、Ti、Ta等の金属、又はこれらを含む合金等の電極材料に対してはエッチングが可能で、かつ当該酸化物薄膜に対してはエッチングが困難である、例えばリン酸系エッチングを用いることで、電極のエッチング液が直接半導体薄膜に接触しても、半導体薄膜はエッチングさせることがないためにエッチングストッパーを形成する必要がなくなる。 Specifically, a solution capable of etching such as an oxalic acid-based etching solution is used for patterning the oxide thin film, while a transparent conductive material such as IZO, ZnO, SnO 2 is used for patterning the electrode. Etching is possible for electrode materials such as oxides, metals such as Al, Ag, Cu, Cr, Ni, Mo, Ti, Ta, or alloys containing them, and etching is performed for the oxide thin films. For example, by using phosphoric acid etching, it is not necessary to form an etching stopper because the semiconductor thin film is not etched even when the electrode etchant directly contacts the semiconductor thin film.
 ドレイン電極、ソース電極及びゲート電極の各電極は、異なる2層以上の導電層を積層した多層構造とすることもできる。特にソース・ドレイン電極は低抵抗配線への要求が強いため、AlやCu等の良導体をTiやMo等の密着性に優れた金属でサンドイッチして使用してもよい。 The drain electrode, the source electrode, and the gate electrode may have a multilayer structure in which two or more different conductive layers are stacked. In particular, since the source / drain electrodes have a strong demand for low-resistance wiring, a good conductor such as Al or Cu may be sandwiched with a metal having excellent adhesion such as Ti or Mo.
 本発明の薄膜トランジスタは、好ましくはS値が0.8V/dec以下であり、0.5V/dec以下がより好ましく、0.3V/dec以下がさらに好ましく、0.2V/dec以下が特に好ましい。0.8V/dec以下であると駆動電圧が小さくなり消費電力を低減できる可能性がある。特に、有機ELディスプレイで用いる場合は、直流駆動のためS値を0.3V/dec以下にすると消費電力を大幅に低減できるため好ましい。 The thin film transistor of the present invention preferably has an S value of 0.8 V / dec or less, more preferably 0.5 V / dec or less, further preferably 0.3 V / dec or less, and particularly preferably 0.2 V / dec or less. If it is 0.8 V / dec or less, the drive voltage becomes small and there is a possibility that power consumption can be reduced. In particular, when used in an organic EL display, it is preferable to set the S value to 0.3 V / dec or less because of direct current drive because power consumption can be greatly reduced.
 S値(SwingFactor)とは、オフ状態からゲート電圧を増加させた際に、オフ状態からオン状態にかけてドレイン電流が急峻に立ち上がるが、この急峻さを示す値である。下記式で定義されるように、ドレイン電流が1桁(10倍)上昇するときのゲート電圧の増分をS値とする。
S値=dVg/dlog(Ids)
 S値が小さいほど急峻な立ち上がりとなる(「薄膜トランジスタ技術のすべて」、鵜飼育弘著、2007年刊、工業調査会)。S値が大きいと、オンからオフに切り替える際に高いゲート電圧をかける必要があり、消費電力が大きくなるおそれがある。
The S value (Swing Factor) is a value indicating the steepness of the drain current that rises sharply from the off state to the on state when the gate voltage is increased from the off state. As defined by the following equation, an increment of the gate voltage when the drain current increases by one digit (10 times) is defined as an S value.
S value = dVg / dlog (Ids)
The smaller the S value, the sharper the rise ("All about Thin Film Transistor Technology", Ikuhiro Ukai, 2007, Industrial Research Committee). When the S value is large, it is necessary to apply a high gate voltage when switching from on to off, and power consumption may increase.
 S値は、トランスファ特性の結果から、Log(Id)―Vgのグラフを作製し、この傾きの逆数から導出することができる。S値の単位は、V/decadeであり、小さな値であることが好ましい。 The S value can be derived from the reciprocal of this slope by creating a Log (Id) -Vg graph from the result of the transfer characteristics. The unit of the S value is V / decade and is preferably a small value.
 本発明の薄膜トランジスタは、好ましくは電界効果移動度が10cm/Vs以上であり、より好ましくは15cm/Vs以上である。電界効果移動度は実施例に記載の方法で測定できる。 The thin film transistor of the present invention preferably has a field effect mobility of 10 cm 2 / Vs or more, more preferably 15 cm 2 / Vs or more. The field effect mobility can be measured by the method described in the examples.
 本発明の薄膜トランジスタは、電界効果型トランジスタ、論理回路、メモリ回路、差動増幅回路等各種の集積回路にも適用できる。さらに、電界効果型トランジスタ以外にも静電誘起型トランジスタ、ショットキー障壁型トランジスタ、ショットキーダイオード、抵抗素子にも適応できる。 The thin film transistor of the present invention can be applied to various integrated circuits such as a field effect transistor, a logic circuit, a memory circuit, and a differential amplifier circuit. Further, in addition to the field effect transistor, it can be applied to an electrostatic induction transistor, a Schottky barrier transistor, a Schottky diode, and a resistance element.
 本発明の薄膜トランジスタの構成は、ボトムゲート、ボトムコンタクト、トップコンタクト等公知の構成を制限なく採用することができる。
 特にボトムゲート構成が、アモルファスシリコンやZnOの薄膜トランジスタに比べ高い性能が得られるので有利である。ボトムゲート構成は、製造時のマスク枚数を削減しやすく、大型ディスプレイ等の用途の製造コストを低減しやすいため好ましい。
As the structure of the thin film transistor of the present invention, known structures such as a bottom gate, a bottom contact, and a top contact can be adopted without limitation.
In particular, the bottom gate structure is advantageous because high performance can be obtained as compared with thin film transistors of amorphous silicon or ZnO. The bottom gate configuration is preferable because it is easy to reduce the number of masks at the time of manufacturing, and it is easy to reduce the manufacturing cost for uses such as a large display.
 本発明の薄膜トランジスタは、表示装置に好適に用いることができる。大面積のディスプレイ用としては、チャネルエッチ型のボトムゲート構成の薄膜トランジスタが特に好ましい。チャネルエッチ型のボトムゲート構成の薄膜トランジスタは、フォトリソ工程時のフォトマスクの数が少なく低コストでディスプレイ用パネルを製造できる。中でも、チャネルエッチ型のボトムゲート構成及びトップコンタクト構成の薄膜トランジスタが移動度等の特性が良好で工業化しやすいため特に好ましい。 The thin film transistor of the present invention can be suitably used for a display device. For large-area displays, a channel-etched bottom-gate thin film transistor is particularly preferable. A channel-etched bottom-gate thin film transistor has a small number of photomasks in the photolithography process, and can be manufactured at a low cost. Among these, channel-etched bottom gate and top contact thin film transistors are particularly preferable because they have favorable characteristics such as mobility and are easily industrialized.
実施例1~39
[焼結体の製造]
 原料粉体として下記の粉末を使用した。尚、各粉末の平均粒径はレーザー回折式粒度分布測定装置SALD-300V(島津製作所製)で測定し、平均粒径はメジアン径D50を採用した。
Examples 1 to 39
[Production of sintered body]
The following powder was used as a raw material powder. The average particle size of each powder was measured with a laser diffraction particle size distribution analyzer SALD-300V (manufactured by Shimadzu Corporation), and the median particle size was a median diameter D50.
酸化インジウム粉:平均粒径0.98μm
酸化スズ粉:平均粒径0.96μm
酸化亜鉛粉:平均粒径0.98μm
元素Xの酸化物粉:平均粒径0.90~1.00μm
Indium oxide powder: average particle size 0.98 μm
Tin oxide powder: Average particle size 0.96μm
Zinc oxide powder: Average particle size 0.98μm
Element X oxide powder: average particle size 0.90 to 1.00 μm
 上記の各粉末を、表1に示す原子比(百分率)になるように秤量し、均一に微粉砕混合後、成形用バインダーを加えて造粒した。次に、この原料粒を金型へ均一に充填し、コールドプレス機にてプレス圧140MPaで加圧成形した。
 得られた成形体を以下のように焼結した。まず、焼結炉内に成形体を載置し、この焼結炉内の容積0.1m当たり5リットル/分の割合で酸素を流入した。この雰囲気中で上記成形体を1400℃で24時間焼結した。
Each of the above powders was weighed so as to have the atomic ratio (percentage) shown in Table 1, and was uniformly pulverized and mixed, and then granulated by adding a molding binder. Next, the raw material grains were uniformly filled in a mold and subjected to pressure molding with a cold press machine at a press pressure of 140 MPa.
The obtained molded body was sintered as follows. First, the compact was placed in a sintering furnace, and oxygen was introduced at a rate of 5 liters / minute per volume of 0.1 m 3 in the sintering furnace. The molded body was sintered at 1400 ° C. for 24 hours in this atmosphere.
 この時、焼結炉内の温度は、800℃までは1℃/分で昇温し、800℃で3時間保持した後、800℃~1400℃は1℃/分で昇温した。その後、1400℃で24時間焼結した後は、降温速度は5℃/分とした。昇温中及び焼結温度保持中は酸素雰囲気、降温中は大気中(雰囲気)とした。 At this time, the temperature in the sintering furnace was increased to 1 ° C./min up to 800 ° C., held at 800 ° C. for 3 hours, and then increased from 800 ° C. to 1400 ° C. at 1 ° C./min. Thereafter, after sintering at 1400 ° C. for 24 hours, the temperature lowering rate was 5 ° C./min. An oxygen atmosphere was used during the temperature rise and the sintering temperature maintenance, and the atmosphere (atmosphere) was used during the temperature fall.
 得られた焼結体の相対密度をアルキメデス法により測定した。実施例1~39の焼結体は相対密度98%以上であることを確認した。
 また、得られた焼結体のバルク比抵抗(導電性)を抵抗率計(三菱化学(株)製、ロレスタ)を使用して四探針法(JIS R 1637)に基づき測定した。結果を表1に示す。表1に示すように実施例1~39の焼結体のバルク比抵抗は、10mΩcm以下であった。
The relative density of the obtained sintered body was measured by the Archimedes method. It was confirmed that the sintered bodies of Examples 1 to 39 had a relative density of 98% or more.
Further, the bulk specific resistance (conductivity) of the obtained sintered body was measured based on the four-probe method (JIS R 1637) using a resistivity meter (Made by Mitsubishi Chemical Corporation, Loresta). The results are shown in Table 1. As shown in Table 1, the bulk specific resistance of the sintered bodies of Examples 1 to 39 was 10 mΩcm or less.
[焼結体の分析]
 得られた焼結体についてICP-AES分析を行い、表1に示す原子比であることを確認した。
 また、得られた焼結体についてX線回折測定装置(XRD)により結晶構造を調べた。XRDの測定条件は以下のとおりである。
・装置:(株)リガク製Ultima-III
・X線:Cu-Kα線(波長1.5406Å、グラファイトモノクロメータにて単色化)
・2θ-θ反射法、連続スキャン(1.0°/分)
・サンプリング間隔:0.02°
・スリット DS、SS:2/3°、RS:0.6mm
[Analysis of sintered body]
The obtained sintered body was subjected to ICP-AES analysis, and the atomic ratios shown in Table 1 were confirmed.
In addition, the crystal structure of the obtained sintered body was examined using an X-ray diffraction measurement apparatus (XRD). The measurement conditions of XRD are as follows.
・ Equipment: Ultimate-III manufactured by Rigaku Corporation
-X-ray: Cu-Kα ray (wavelength 1.5406mm, monochromatized with graphite monochromator)
・ 2θ-θ reflection method, continuous scan (1.0 ° / min)
・ Sampling interval: 0.02 °
・ Slit DS, SS: 2/3 °, RS: 0.6 mm
 実施例1~9で得られた焼結体のX線回折チャートを図1~9に示す。チャートを分析した結果、実施例1の焼結体では、Inのビックスバイト構造とZnAlのスピネル構造、及びInAlZn,InAlZnOのホモロガス構造が観測された。
 結晶構造はJCPDS(Joint Committee of Powder Diffraction Standards)カードで確認することができる。
The X-ray diffraction charts of the sintered bodies obtained in Examples 1 to 9 are shown in FIGS. As a result of analyzing the chart, a bixbite structure of In 2 O 3 and a spinel structure of ZnAl 2 O 4 and a homologous structure of InAlZn 2 O 5 and InAlZnO 4 were observed in the sintered body of Example 1.
The crystal structure can be confirmed with a JCPDS (Joint Committee of Powder Diffraction Standards) card.
 Inのビックスバイト構造はJCPDSカードNo.06-0416であり、ZnAlのスピネル構造はJCPDSカードNo.05-0669であり、InAlZnのホモロガス構造はJCPDSカードNo.40-0259、InAlZnOのホモロガス構造はJCPDSカードNo.40-0258である。
 実施例2~39についても、表1に示すようにInのビックスバイト構造とスピネル構造が観測された。
In 2 O 3 has a big byte structure of JCPDS card no. The spinel structure of ZnAl 2 O 4 is JCPDS card no. 05-0669, and the homologous structure of InAlZn 2 O 5 is JCPDS card no. 40-0259, the homologous structure of InAlZnO 4 is JCPDS card no. 40-0258.
Also in Examples 2 to 39, as shown in Table 1, a bixbite structure and a spinel structure of In 2 O 3 were observed.
 実施例2~39において、Inのビックスバイト構造はJCPDSカードNo.06-0416であり、スピネル構造については、ZnAlはJCPDSカードNo.05-0669であり、ZnSnOはJCPDSカードNo.24-1470であり、ZnGaはJCPDSカードNo.38-1240であり、MgInはJCPDSカードNo.40-1402であり、ZnSiOはICSD#161024であり、ZnTiOはICSD#80849である。 In Examples 2 to 39, the bibyte structure of In 2 O 3 is JCPDS card no. For the spinel structure, ZnAl 2 O 4 is JCPDS card no. 05-0669, Zn 2 SnO 4 is JCPDS card no. 24-1470, ZnGa 2 O 4 is JCPDS card no. No. 38-1240 and MgIn 2 O 4 is JCPDS card No. 40-1402, Zn 2 SiO 4 is ICSD # 161024, and Zn 2 TiO 4 is ICSD # 80849.
 また、ホモロガス構造については、InAlZnOはJCPDSカードNo.40-0258であり、InAlZnはJCPDSカードNo.40-0259であり、InZnはJCPDSカードNo.20-1442であり、InZnはJCPDSカードNo.00-1140、若しくはICSD#162450であり、InZnはICSD#162451であり、InGaZnOはICSD#9003であり、InGaZnはICSD#380305であり、YSnのパイロクロア構造はJCPDSカードNo.20-1418であり、ZnSnOのイルメナイト構造はJCPDSカードNo.00-1197であり、InTiOはJCPDSカードNo.30-0640である。 For the homologous structure, InAlZnO 4 is JCPDS card no. 40-0258, InAlZn 2 O 5 is JCPDS card no. 40-0259, and In 2 Zn 2 O 5 is JCPDS card no. 20-1442, and In 2 Zn 3 O 6 is JCPDS card no. 00-1140 or ICSD # 162450, In 2 Zn 4 O 7 is ICSD # 162451, InGaZnO 4 is ICSD # 9003, InGaZn 2 O 5 is ICSD # 380305, Y 2 Sn 2 O 7 The pyrochlore structure of JCPDS card no. 20-1418, and the ZnSnO 3 ilmenite structure is JCPDS card no. 00-1197, and In 2 TiO 4 is JCPDS card no. 30-0640.
 元素Xの酸化物については、SnOはJCPDSカードNo.00-1024であり、AlはICSD#9770であり、MgOはJCPDSカードNo.45-0946であり、GaはICSD#603563であり、TiOはICSD#603563であり、SiOはJCPDSカードNo.33-1161であり、ZnOはICSD#57156であり、ScはICSD#24200であり、HfOはICSD#27313であり、ZrOはICSD#66781である。 For the oxide of element X, SnO 2 is JCPDS card no. 00-1024, Al 2 O 3 is ICSD # 9770, and MgO is JCPDS card no. Is 45-0946, Ga 2 O 3 is ICSD # 603563, TiO 2 is ICSD # 603563, SiO 2 is JCPDS card No. Is 33-1161, ZnO is ICSD # 57156, Sc 2 O 3 is ICSD # 24200, HfO 2 is ICSD # 27313, ZrO 2 is an ICSD # 66781.
 実施例1~39の焼結体について、電子線マイクロアナライザ(EPMA)測定により、得られた焼結体における元素Xの分散を調べたところ、元素Xを含む25μm超の集合体は観測されなかった。本発明の焼結体は分散性、均一性が極めて優れている。EPMAの測定条件は以下のとおりである。 Regarding the sintered bodies of Examples 1 to 39, when the dispersion of the element X in the obtained sintered body was examined by electron beam microanalyzer (EPMA) measurement, an aggregate of more than 25 μm containing the element X was not observed. It was. The sintered body of the present invention is extremely excellent in dispersibility and uniformity. The measurement conditions of EPMA are as follows.
・装置名:日本電子株式会社 JXA-8200
・測定条件
  加速電圧:15kV
  照射電流:50nA
  照射時間(1点当りの):50ms
Device name: JEOL Ltd. JXA-8200
・ Measurement conditions Acceleration voltage: 15 kV
Irradiation current: 50 nA
Irradiation time (per point): 50 ms
[スパッタリングターゲットの製造]
 実施例1~39で得られた焼結体の表面を平面研削盤で研削し、側辺をダイヤモンドカッターで切断し、バッキングプレートに貼り合わせ、それぞれ直径4インチのスパッタリングターゲットを作製した。
 また、実施例1~11、14、22、24,25については、さらに、それぞれ幅200mm、長さ1700mm、厚さ10mmの6枚のターゲットをACスパッタリング成膜用に作製した。
[Manufacture of sputtering target]
The surfaces of the sintered bodies obtained in Examples 1 to 39 were ground with a surface grinder, the sides were cut with a diamond cutter, and bonded to a backing plate to produce sputtering targets each having a diameter of 4 inches.
In Examples 1 to 11, 14, 22, 24, and 25, six targets each having a width of 200 mm, a length of 1700 mm, and a thickness of 10 mm were prepared for AC sputtering film formation.
[異常放電の有無の確認]
 得られた直径4インチのスパッタリングターゲットをDCスパッタリング装置に装着し、雰囲気としてアルゴンガスに水蒸気を分圧比で2%添加した混合ガスを使用し、スパッタ圧0.4Pa、基板温度を室温とし、DC出力400Wにて、10kWh連続スパッタを行った。スパッタ中の電圧変動をデータロガーに蓄積し、異常放電の有無を確認した。結果を表1に示す。
[Check for abnormal discharge]
The obtained sputtering target having a diameter of 4 inches was mounted on a DC sputtering apparatus, a mixed gas in which water vapor was added to argon gas at a partial pressure ratio of 2% as an atmosphere, a sputtering pressure of 0.4 Pa, a substrate temperature of room temperature, DC 10 kWh continuous sputtering was performed at an output of 400 W. Voltage fluctuations during sputtering were accumulated in a data logger, and the presence or absence of abnormal discharge was confirmed. The results are shown in Table 1.
 尚、上記異常放電の有無は、電圧変動をモニターして異常放電を検出することにより行った。具体的には、5分間の測定時間中に発生する電圧変動がスパッタ運転中の定常電圧の10%以上あった場合を異常放電とした。特にスパッタ運転中の定常電圧が0.1秒間に±10%変動する場合は、スパッタ放電の異常放電であるマイクロアークが発生しており、素子の歩留まりが低下し、量産化に適さないおそれがある。 Note that the presence or absence of the abnormal discharge was performed by monitoring the voltage fluctuation and detecting the abnormal discharge. Specifically, the abnormal discharge was determined when the voltage fluctuation generated during the measurement time of 5 minutes was 10% or more of the steady voltage during the sputtering operation. In particular, when the steady-state voltage during sputtering operation varies by ± 10% in 0.1 second, a micro arc, which is an abnormal discharge of the sputter discharge, has occurred, and the device yield may decrease, making it unsuitable for mass production. is there.
[ノジュール発生の有無の確認]
 また、得られた直径4インチのスパッタリングターゲットを用いて、雰囲気としてアルゴンガスに水素ガスを分圧比で3%添加した混合ガスを使用し、40時間連続してスパッタリングを行い、ノジュールの発生の有無を確認した。
[Check for nodule occurrence]
In addition, using the obtained sputtering target having a diameter of 4 inches, using a mixed gas obtained by adding 3% of hydrogen gas to argon gas at a partial pressure ratio, sputtering was performed continuously for 40 hours, and no nodules were generated. It was confirmed.
 その結果、実施例1~39のスパッタリングターゲット表面において、ノジュールは観測されなかった。
 尚、スパッタ条件は、スパッタ圧0.4Pa、DC出力100W、基板温度は室温とした。水素ガスは、ノジュールの発生を促進するために雰囲気ガスに添加した。
As a result, no nodules were observed on the surfaces of the sputtering targets of Examples 1 to 39.
The sputtering conditions were a sputtering pressure of 0.4 Pa, a DC output of 100 W, and a substrate temperature of room temperature. Hydrogen gas was added to the atmospheric gas to promote the generation of nodules.
 ノジュールは、スパッタリング後のターゲット表面の変化を実体顕微鏡により50倍に拡大して観察し、視野9mm中に発生した20μm以上のノジュールについて数平均を計測する方法を採用した。発生したノジュール数を表1に示す。 For the nodules, a change in the target surface after sputtering was observed by magnifying it 50 times with a stereomicroscope, and a method of measuring the number average of nodules having a size of 20 μm or more generated in a visual field of 9 mm 2 was adopted. Table 1 shows the number of nodules generated.
比較例1~11
 表1に示す原子比(百分率)で原料粉末を混合し、実施例1と同様に焼結体及びスパッタリングターゲットを製造し、評価した。結果を表1に示す。
 比較例1のターゲットでは、InAlZnOのホモロガス構造、Alのコランダム構造及び、SnOのルチル構造が観測された。比較例2~11についても表1のとおりである。
Comparative Examples 1-11
Raw material powders were mixed at an atomic ratio (percentage) shown in Table 1, and a sintered body and a sputtering target were produced and evaluated in the same manner as in Example 1. The results are shown in Table 1.
In the target of Comparative Example 1, a homologous structure of InAlZnO 4 , a corundum structure of Al 2 O 3 , and a rutile structure of SnO 2 were observed. The comparative examples 2 to 11 are also as shown in Table 1.
 比較例1~6のスパッタリングターゲットにおいて、スパッタ時に異常放電が発生し、ターゲット表面にはノジュールが観測された。比較例7~11は抵抗が高く、放電ができなかった。 In the sputtering targets of Comparative Examples 1 to 6, abnormal discharge occurred during sputtering, and nodules were observed on the target surface. Comparative Examples 7 to 11 had high resistance and could not be discharged.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
実施例40~80
[酸化物半導体薄膜の作製]
 マグネトロンスパッタリング装置に、実施例1~39で作製した表2に示す組成の4インチターゲットを装着し、基板としてスライドガラス(コーニング社製♯1737)をそれぞれ装着した。DCマグネトロンスパッタリング法により、スライドガラス上に膜厚50nmの非晶質膜を成膜した。成膜時の雰囲気は、Arガスに表2に示す分圧比(%)でOガス及び/又は水蒸気を導入した混合ガスを使用した。
Examples 40-80
[Preparation of oxide semiconductor thin film]
A 4-inch target having the composition shown in Table 2 prepared in Examples 1 to 39 was mounted on a magnetron sputtering apparatus, and a slide glass (# 1737 manufactured by Corning) was mounted as a substrate. An amorphous film having a thickness of 50 nm was formed on the slide glass by a DC magnetron sputtering method. As an atmosphere during film formation, a mixed gas in which O 2 gas and / or water vapor was introduced into Ar gas at a partial pressure ratio (%) shown in Table 2 was used.
 スパッタ条件は以下のとおりである。
・基板温度:25℃
・到達圧力:8.5×10-5Pa
・雰囲気ガス:Arガス、Oガス、水蒸気の混合ガス(Oガス、水蒸気の分圧比は表2を参照、Arガスの分圧比は残分)
・スパッタ圧力(全圧):0.4Pa
・投入電力:DC100W
・S(基板)-T(ターゲット)距離:70mm
The sputtering conditions are as follows.
-Substrate temperature: 25 ° C
-Ultimate pressure: 8.5 × 10 −5 Pa
Atmosphere gas: Ar gas, O 2 gas, water vapor mixed gas (see Table 2 for partial pressure ratio of O 2 gas and water vapor, Ar gas partial pressure ratio is the remainder)
・ Sputtering pressure (total pressure): 0.4 Pa
-Input power: DC100W
・ S (substrate) -T (target) distance: 70 mm
 ガラス基板上に成膜した薄膜についてX線回折測定(XRD)装置(リガク製Ultima-III)により結晶構造を調べた。実施例40~80では、薄膜堆積直後は回折ピークが観測されず非晶質であることを確認した。
 XRDの測定条件は以下のとおりである。
・装置:(株)リガク製Ultima-III
・X線:Cu-Kα線(波長1.5406Å、グラファイトモノクロメータにて単色化)
・2θ-θ反射法、連続スキャン(1.0°/分)
・サンプリング間隔:0.02°
・スリット DS、SS:2/3°、RS:0.6mm
The crystal structure of the thin film formed on the glass substrate was examined by an X-ray diffraction measurement (XRD) apparatus (Rigaku Ultimate-III). In Examples 40 to 80, a diffraction peak was not observed immediately after deposition of the thin film, and it was confirmed that the film was amorphous.
The measurement conditions of XRD are as follows.
・ Equipment: Ultimate-III manufactured by Rigaku Corporation
-X-ray: Cu-Kα ray (wavelength 1.5406mm, monochromatized with graphite monochromator)
・ 2θ-θ reflection method, continuous scan (1.0 ° / min)
・ Sampling interval: 0.02 °
・ Slit DS, SS: 2/3 °, RS: 0.6 mm
 次いで、非晶質膜を形成した基板を大気中、300℃で60分加熱して酸化物半導体膜を形成した。このガラス基板上に成膜した基板を、ホール効果測定用素子として用いてResiTest8300型(東陽テクニカ社製)にセットし、室温でホール効果(ホール移動度)を評価した。
 また、ICP-AES分析により、酸化物半導体薄膜に含まれる各元素の原子比がスパッタリングターゲットと同じであることを確認した。
Next, the substrate over which the amorphous film was formed was heated in the atmosphere at 300 ° C. for 60 minutes to form an oxide semiconductor film. The substrate formed on this glass substrate was used as a Hall effect measurement element and set in ResiTest 8300 type (manufactured by Toyo Technica Co., Ltd.), and the Hall effect (Hall mobility) was evaluated at room temperature.
ICP-AES analysis confirmed that the atomic ratio of each element contained in the oxide semiconductor thin film was the same as that of the sputtering target.
[薄膜トランジスタの製造]
 基板として、膜厚100nmの熱酸化膜付きの導電性シリコン基板を使用した。熱酸化膜がゲート絶縁膜として機能し、導電性シリコン部がゲート電極として機能する。
 ゲート絶縁膜上にスパッタ成膜し、膜厚50nmの非晶質薄膜を作製した。レジストとしてOFPR♯800(東京応化工業株式会社製)を使用し、塗布、プレベーク(80℃、5分)、露光した。現像後、ポストベーク(120℃、5分)し、シュウ酸にてエッチングし、所望の形状にパターニングした。その後、熱風加熱炉内にて300℃で60分加熱処理(アニール処理)を行った。
[Manufacture of thin film transistors]
As the substrate, a conductive silicon substrate with a thermal oxide film having a thickness of 100 nm was used. The thermal oxide film functions as a gate insulating film, and the conductive silicon portion functions as a gate electrode.
A 50 nm-thick amorphous thin film was formed by sputtering on the gate insulating film. OFPR # 800 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) was used as a resist, and coating, pre-baking (80 ° C., 5 minutes), and exposure were performed. After development, it was post-baked (120 ° C., 5 minutes), etched with oxalic acid, and patterned into a desired shape. Thereafter, heat treatment (annealing treatment) was performed at 300 ° C. for 60 minutes in a hot air heating furnace.
 その後、リフトオフ法によりMo(100nm)をスパッタ成膜により成膜し、ソース/ドレイン電極を所望の形状にパターニングした。さらに保護膜を形成する前段階の処理として、酸化物半導体膜に対し、亜酸化窒素プラズマ処理を施した。その後、プラズマCVD法(PECVD)にてSiOxを成膜して保護膜とした。フッ酸を用いてコンタクトホールを開口し、薄膜トランジスタを作製した。 Thereafter, Mo (100 nm) was formed by sputtering film formation by the lift-off method, and the source / drain electrodes were patterned into a desired shape. Further, a nitrous oxide plasma treatment was performed on the oxide semiconductor film as a treatment before the formation of the protective film. Then, SiOx was formed into a protective film by plasma CVD method (PECVD). A contact hole was opened using hydrofluoric acid to produce a thin film transistor.
[エッチング速度の評価]
 非晶質膜の膜厚を100nmとした以外は同様の条件で成膜した実施例40~80の酸化物半導体薄膜を用いて、エッチング速度を評価した。
 シュウ酸系エッチング液であるITO-06N(関東化学(株))を35℃にして、酸化物半導体薄膜を浸漬し、浸漬時間と、浸漬の前後の膜厚から、エッチング速度を算出した。
 また、リン酸系エッチング液であるPANエッチング液(リン酸91.4wt%、硝酸3.3wt%、酢酸5.3wt%)を35℃にして、酸化物半導体薄膜を浸漬し、浸漬時間と、浸漬の前後の膜厚から、エッチング速度を算出した。
[Evaluation of etching rate]
The etching rate was evaluated using the oxide semiconductor thin films of Examples 40 to 80 formed under the same conditions except that the thickness of the amorphous film was 100 nm.
An oxide semiconductor thin film was immersed in ITO-06N (Kanto Chemical Co., Ltd.), which is an oxalic acid-based etching solution, at 35 ° C., and the etching rate was calculated from the immersion time and the film thickness before and after the immersion.
Further, a PAN etching solution (phosphoric acid 91.4 wt%, nitric acid 3.3 wt%, acetic acid 5.3 wt%) is set to 35 ° C., and the oxide semiconductor thin film is immersed, and the immersion time is as follows: The etching rate was calculated from the film thickness before and after the immersion.
[薄膜トランジスタの評価]
 実施例40~80で作製した薄膜トランジスタについて、電界効果移動度(μ)及び閾値電圧(Vth)を評価した。これらの特性値は、半導体パラメーターアナライザー(ケースレーインスツルメンツ株式会社製4200SCS)を用い、室温、遮光環境下(シールドボックス内)で測定した。Vthはドレイン電流(Id)が1nAの時のゲート電圧(Vg)とする。
[Evaluation of Thin Film Transistor]
The thin film transistors manufactured in Examples 40 to 80 were evaluated for field effect mobility (μ) and threshold voltage (Vth). These characteristic values were measured using a semiconductor parameter analyzer (4200SCS manufactured by Keithley Instruments Co., Ltd.) at room temperature in a light-shielding environment (in a shield box). Vth is the gate voltage (Vg) when the drain current (Id) is 1 nA.
 また、盛装したトランジスタについて、ドレイン電圧(Vd)を5V及びゲート電圧(Vg)を-15~25Vとして伝達特性を評価した。結果を表2に示す。尚、電界効果移動度(μ)は、線形移動度から算出し、Vg-μの最大値で定義した。 The transfer characteristics of the mounted transistors were evaluated with a drain voltage (Vd) of 5 V and a gate voltage (Vg) of −15 to 25 V. The results are shown in Table 2. The field effect mobility (μ) was calculated from the linear mobility and defined as the maximum value of Vg−μ.
 次に、実施例40~80のTFTに対し、DCバイアスストレス試験を行った。表2に、Vg=15V、Vd=15VのDCストレス(ストレス温度80℃下)を10000秒印加した前後における、Vthの変化量ΔVthを示す。本発明のTFTでは閾値電圧の変動が非常に小さく、DCストレスに対して影響を受けにくいことが分かる。 Next, a DC bias stress test was performed on the TFTs of Examples 40 to 80. Table 2 shows the amount of change ΔVth in Vth before and after the application of DC stress (stress temperature of 80 ° C.) of Vg = 15 V and Vd = 15 V for 10,000 seconds. It can be seen that the threshold voltage variation of the TFT of the present invention is very small and is hardly affected by DC stress.
 また、実施例40~50について、薄膜トランジスタのチャネル層に対して、断面TEM(透過電子顕微鏡;Transmission Electron Microscope)を用いて電子線回折パターンによる結晶性評価を行った。装置は、日立製電界放出型透過電子顕微鏡 HF-2100を利用した。
 実施例41、43の素子のチャネル層について断面TEM解析を行った結果、観察された回折パターンからフロントチャネル側は非晶質であったが、バックチャネル側は一部に回折パターンが観測され、結晶化している領域を有することが分かった。一方、実施例40、42及び44~50の素子については、フロントチャネル側、バックチャネル側ともに回折パターンは観測されず、非晶質であることを確認した。
In addition, in Examples 40 to 50, the crystallinity of the channel layer of the thin film transistor was evaluated by an electron beam diffraction pattern using a cross-sectional TEM (Transmission Electron Microscope). As the apparatus, Hitachi field emission type transmission electron microscope HF-2100 was used.
As a result of cross-sectional TEM analysis of the channel layers of the elements of Examples 41 and 43, the front channel side was amorphous from the observed diffraction pattern, but the diffraction pattern was partially observed on the back channel side, It was found to have a crystallized region. On the other hand, in the elements of Examples 40, 42 and 44 to 50, no diffraction pattern was observed on the front channel side and the back channel side, and it was confirmed that the elements were amorphous.
比較例12~14
 比較例1、3、5で作製した4インチターゲットをそれぞれ用いて、スパッタ成膜時の雰囲気をArガスと表2に記載の分圧比のガスとの混合ガスに変更した他は実施例40と同様にして酸化物半導体薄膜及び薄膜トランジスタを作製し、評価した。結果を表2に示す。
Comparative Examples 12-14
Each of the 4-inch targets prepared in Comparative Examples 1, 3, and 5 was used, except that the atmosphere during sputtering film formation was changed to a mixed gas of Ar gas and a gas having a partial pressure ratio shown in Table 2. Example 40 Similarly, an oxide semiconductor thin film and a thin film transistor were manufactured and evaluated. The results are shown in Table 2.
 表2に示すように、比較例12~14は電界効果移動度が10cm/Vs未満であり、実施例40~80と比べて大幅に低いことが分かる。 As shown in Table 2, it can be seen that Comparative Examples 12 to 14 have a field effect mobility of less than 10 cm 2 / Vs, which is significantly lower than Examples 40 to 80.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
実施例81~95
 特開2005-290550号公報に開示された成膜装置を用い、ACスパッタリングを行い、薄膜トランジスタを作製した。ACスパッタリングの際の雰囲気をArガスと表3に記載の分圧比のガスとの混合ガスとし、得られた非晶質膜を表3に記載の条件で加熱処理(アニール処理)を行い、ソース・ドレインパターニングをドライエッチングで行った他は、実施例40-80と同様にして薄膜トランジスタを作製し、評価した。結果を表3に示す。
 また、ICP-AES分析により、酸化物薄膜に含まれる各元素の原子比がスパッタリングターゲットと同じであることを確認した。
Examples 81-95
A thin film transistor was manufactured by performing AC sputtering using the film forming apparatus disclosed in Japanese Patent Laid-Open No. 2005-290550. The atmosphere during AC sputtering is a mixed gas of Ar gas and a gas having a partial pressure ratio shown in Table 3, and the obtained amorphous film is subjected to heat treatment (annealing treatment) under the conditions shown in Table 3. A thin film transistor was fabricated and evaluated in the same manner as in Examples 40-80 except that the drain patterning was performed by dry etching. The results are shown in Table 3.
ICP-AES analysis confirmed that the atomic ratio of each element contained in the oxide thin film was the same as that of the sputtering target.
 ACスパッタリングは、具体的には、図10に示す装置を用いて行った。
 実施例1~11、14、22、24,25で作製した幅200mm、長さ1700mm、厚さ10mmの6枚のターゲット31a~31fを、図10に示すようにそれぞれの長さ方向が平行となるよう2mmの間隔で配置した。磁界形成手段40a~40fの幅はターゲット31a~31fと同じ200mmであった。ガス供給系からスパッタガスであるAr、水蒸気及び/又はOをそれぞれ系内に導入した。
Specifically, AC sputtering was performed using the apparatus shown in FIG.
The six targets 31a to 31f having a width of 200 mm, a length of 1700 mm, and a thickness of 10 mm produced in Examples 1 to 11, 14, 22, 24, and 25 are parallel to each other as shown in FIG. They were arranged at intervals of 2 mm. The width of the magnetic field forming means 40a to 40f was 200 mm, which is the same as that of the targets 31a to 31f. Ar, water vapor and / or O 2 as sputtering gases were introduced into the system from the gas supply system.
 例えば実施例81では、成膜雰囲気は0.5Pa、交流電源のパワーは3W/cm(=10.2kW/3400cm)とし、周波数は10kHzとした。
 以上の条件で成膜速度は66nm/分と高速であり、量産に適するものであった。
For example, in Example 81, the film forming atmosphere was 0.5 Pa, the power of the AC power source was 3 W / cm 2 (= 10.2 kW / 3400 cm 2 ), and the frequency was 10 kHz.
Under the above conditions, the film formation rate was as high as 66 nm / min, which was suitable for mass production.
比較例15~17
 比較例1、3、5について作製した幅200mm、長さ1700mm、厚さ10mmの6枚のターゲットを用いて、スパッタ条件を表3に記載のものに変更した他は実施例81と同様にして酸化物半導体薄膜及び薄膜トランジスタを作製し、評価した。結果を表3に示す。
 表3に示すように、比較例15~17は電界効果移動度が10cm/Vs未満であり、実施例81~95と比べて大幅に電界効果移動度が低いことが分かる。
Comparative Examples 15-17
Using the six targets having a width of 200 mm, a length of 1700 mm, and a thickness of 10 mm prepared for Comparative Examples 1, 3, and 5, the sputtering conditions were changed to those shown in Table 3 and the same as in Example 81. An oxide semiconductor thin film and a thin film transistor were fabricated and evaluated. The results are shown in Table 3.
As shown in Table 3, it can be seen that Comparative Examples 15 to 17 have a field effect mobility of less than 10 cm 2 / Vs, which is significantly lower than that of Examples 81 to 95.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
実施例96~105
 実施例1~39で作製した表4に記載の組成のスパッタリングターゲットを用い、MoのパターニングをPAN(リン酸91.4wt%、硝酸3.3wt%、酢酸5.3wt%)エッチング液によるバックチャネルエッチングを用いて行った以外は、実施例40~80と同様の条件で作製したTFT特性の結果を表4に示す。
 バックチャネルエッチングによっても、良好なTFT特性が得られることが分かる。
Examples 96-105
Back channel using a PAN (phosphoric acid 91.4 wt%, nitric acid 3.3 wt%, acetic acid 5.3 wt%) etching solution using the sputtering target having the composition shown in Table 4 prepared in Examples 1 to 39 and Mo patterning Table 4 shows the results of TFT characteristics produced under the same conditions as in Examples 40 to 80 except that the etching was performed.
It can be seen that good TFT characteristics can also be obtained by back channel etching.
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
 本発明のスパッタリングターゲットは、酸化物半導体や透明導電膜等の酸化物薄膜の作製に使用できる。また、本発明の酸化物薄膜は、透明電極、薄膜トランジスタの半導体層、酸化物薄膜層等に使用できる。 The sputtering target of the present invention can be used for production of oxide thin films such as oxide semiconductors and transparent conductive films. The oxide thin film of the present invention can be used for a transparent electrode, a semiconductor layer of a thin film transistor, an oxide thin film layer, and the like.
 上記に本発明の実施形態及び/又は実施例を幾つか詳細に説明したが、当業者は、本発明の新規な教示及び効果から実質的に離れることなく、これら例示である実施形態及び/又は実施例に多くの変更を加えることが容易である。従って、これらの多くの変更は本発明の範囲に含まれる。
 本願のパリ優先の基礎となる日本出願明細書の内容を全てここに援用する。
Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will appreciate that these exemplary embodiments and / or embodiments are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many changes to the embodiment. Accordingly, many of these modifications are within the scope of the present invention.
All the contents of the Japanese application specification that is the basis of the priority of Paris in this application are incorporated herein.

Claims (22)

  1.  インジウム元素(In)、スズ元素(Sn)、亜鉛元素(Zn)及び下記のX群から選択される1以上の元素Xを含有する酸化物からなり、Inで表されるビックスバイト構造化合物と、スピネル構造化合物とを含むスパッタリングターゲット。
    X群:Mg、Al、Ga、Si、Sc、Ti、Y、Zr、Hf、Ta、La、Nd、Sm
    A bixbite structure composed of an oxide containing at least one element X selected from indium element (In), tin element (Sn), zinc element (Zn), and the following group X, and represented by In 2 O 3 A sputtering target comprising a compound and a spinel structure compound.
    X group: Mg, Al, Ga, Si, Sc, Ti, Y, Zr, Hf, Ta, La, Nd, Sm
  2.  前記インジウム元素、スズ元素、亜鉛元素及び元素Xの原子比が、下記式(1)~(4)を満たす請求項1に記載のスパッタリングターゲット。
    0.20≦In/(In+Sn+Zn+X)≦0.85 (1)
    0.01≦Sn/(In+Sn+Zn+X)≦0.35 (2)
    0.01≦Zn/(In+Sn+Zn+X)≦0.70 (3)
    0.01≦X/(In+Sn+Zn+X)≦0.30  (4)
    (式中、In、Sn、Zn及びXは、それぞれ、スパッタリングターゲットにおける各元素の原子比を示す。)
    The sputtering target according to claim 1, wherein an atomic ratio of the indium element, tin element, zinc element and element X satisfies the following formulas (1) to (4).
    0.20 ≦ In / (In + Sn + Zn + X) ≦ 0.85 (1)
    0.01 ≦ Sn / (In + Sn + Zn + X) ≦ 0.35 (2)
    0.01 ≦ Zn / (In + Sn + Zn + X) ≦ 0.70 (3)
    0.01 ≦ X / (In + Sn + Zn + X) ≦ 0.30 (4)
    (In the formula, In, Sn, Zn, and X each represent an atomic ratio of each element in the sputtering target.)
  3.  前記スピネル構造化合物が、XIn、ZnX、ZnXOのうちいずれかを含む、請求項1又は2に記載のスパッタリングターゲット。 The spinel structure compound, XIn 2 O 4, ZnX 2 O 4, Zn 2 of XO 4 containing either sputtering target according to claim 1 or 2.
  4.  前記元素XがMg、Al、Ti、Si、又はGaである、請求項1~3のいずれかに記載のスパッタリングターゲット。 The sputtering target according to any one of claims 1 to 3, wherein the element X is Mg, Al, Ti, Si, or Ga.
  5.  前記元素XがAlであり、前記スピネル構造化合物がZnAlを含む請求項1~3のいずれかに記載のスパッタリングターゲット。 The sputtering target according to any one of claims 1 to 3, wherein the element X is Al and the spinel structure compound contains ZnAl 2 O 4 .
  6.  前記スピネル構造化合物がZnSnOを含む請求項1~5のいずれかに記載のスパッタリングターゲット。 The sputtering target according to any one of claims 1 to 5, wherein the spinel structure compound contains Zn 2 SnO 4 .
  7.  相対密度が98%以上であり、バルク比抵抗が10mΩcm以下である請求項1~6のいずれかに記載のスパッタリングターゲット。 The sputtering target according to claim 1, wherein the relative density is 98% or more and the bulk specific resistance is 10 mΩcm or less.
  8.  請求項1~7のいずれかに記載のスパッタリングターゲットを用いて、スパッタリング法により成膜してなる酸化物半導体薄膜。 An oxide semiconductor thin film formed by sputtering using the sputtering target according to any one of claims 1 to 7.
  9.  リン酸系エッチング液に対して不溶であり、かつシュウ酸系エッチング液に対して可溶である請求項8に記載の酸化物半導体薄膜。 The oxide semiconductor thin film according to claim 8, wherein the oxide semiconductor thin film is insoluble in a phosphoric acid etching solution and soluble in an oxalic acid etching solution.
  10.  前記リン酸系エッチング液による35℃でのエッチング速度が10nm/分以下であり、かつ前記シュウ酸エッチング液による35℃でのエッチング速度が20nm/分以上である請求項9に記載の酸化物半導体薄膜。 10. The oxide semiconductor according to claim 9, wherein an etching rate at 35 ° C. with the phosphoric acid-based etching solution is 10 nm / min or less, and an etching rate at 35 ° C. with the oxalic acid etching solution is 20 nm / min or more. Thin film.
  11.  水蒸気、酸素ガス及び亜酸化窒素ガスから選択される1以上と希ガスとを含有する混合気体の雰囲気下において、請求項1~7のいずれかに記載のスパッタリングターゲットを用いてスパッタリング法で成膜する酸化物半導体薄膜の製造方法。 A film is formed by a sputtering method using the sputtering target according to any one of claims 1 to 7 in an atmosphere of a mixed gas containing one or more selected from water vapor, oxygen gas, and nitrous oxide gas and a rare gas. A method for manufacturing an oxide semiconductor thin film.
  12.  前記酸化物半導体薄膜の成膜を、少なくとも水蒸気と希ガスとを含有する混合気体の雰囲気下において行う請求項11に記載の酸化物半導体薄膜の製造方法。 The method for producing an oxide semiconductor thin film according to claim 11, wherein the oxide semiconductor thin film is formed in an atmosphere of a mixed gas containing at least water vapor and a rare gas.
  13.  前記混合気体中に含まれる水蒸気の割合が分圧比で0.1%~25%である請求項11又は12に記載の酸化物半導体薄膜の製造方法。 The method for producing an oxide semiconductor thin film according to claim 11 or 12, wherein a ratio of water vapor contained in the mixed gas is 0.1% to 25% in terms of partial pressure ratio.
  14.  前記混合気体中に含まれる酸素ガスの割合が分圧比で0.1%~30%である請求項11~13のいずれかに記載の酸化物半導体薄膜の製造方法。 14. The method for producing an oxide semiconductor thin film according to claim 11, wherein a ratio of oxygen gas contained in the mixed gas is 0.1% to 30% in terms of partial pressure ratio.
  15.  前記酸化物半導体薄膜の成膜を、真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、前記各ターゲットに対して交流電源から負電位及び正電位を交互に印加する場合に、前記交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら、ターゲット上にプラズマを発生させて基板表面に成膜するスパッタリング方法で行う請求項11~14のいずれかに記載の酸化物半導体薄膜の製造方法。 The oxide semiconductor thin film is formed by sequentially transporting the substrate to a position facing three or more targets arranged in parallel in the vacuum chamber at a predetermined interval, and from each AC power source to each target. In the case of alternately applying a negative potential and a positive potential, at least one of the outputs from the AC power supply is switched between two or more targets that are branched and connected while switching the target to which the potential is applied. The method for producing an oxide semiconductor thin film according to any one of claims 11 to 14, wherein the method is performed by a sputtering method in which plasma is generated on a target to form a film on a substrate surface.
  16.  前記交流電源の交流パワー密度が3W/cm以上、20W/cm以下である請求項15に記載の酸化物半導体薄膜の製造方法。 The method for manufacturing an oxide semiconductor thin film according to claim 15, wherein the AC power density of the AC power source is 3 W / cm 2 or more and 20 W / cm 2 or less.
  17.  前記交流電源の周波数が10kHz~1MHzである請求項15又は16に記載の酸化物半導体薄膜の製造方法。 The method for producing an oxide semiconductor thin film according to claim 15 or 16, wherein the frequency of the AC power source is 10 kHz to 1 MHz.
  18.  請求項8~10のいずれかに記載の酸化物半導体薄膜をチャネル層として有する薄膜トランジスタ。 A thin film transistor comprising the oxide semiconductor thin film according to any one of claims 8 to 10 as a channel layer.
  19.  電界効果移動度が10cm/Vs以上である請求項18に記載の薄膜トランジスタ。 The thin film transistor according to claim 18, wherein the field effect mobility is 10 cm 2 / Vs or more.
  20.  請求項8~10のいずれかに記載の酸化物半導体薄膜の上に、少なくともSiNx(xは任意の数)を含有する保護膜を有する薄膜トランジスタ。 A thin film transistor having a protective film containing at least SiNx (x is an arbitrary number) on the oxide semiconductor thin film according to any one of claims 8 to 10.
  21.  半導体活性層として、請求項8~10のいずれかに記載された酸化物半導体薄膜を用いた薄膜トランジスタの製造方法であって、前記半導体薄膜上にエッチングストッパーを積層させずに、前記半導体薄膜と電極を異なるエッチング液を用いてパターニングし、電極をパターニングする際に直接エッチング液が前記半導体薄膜に接する工程を含む薄膜トランジスタを製造する方法。 A method of manufacturing a thin film transistor using the oxide semiconductor thin film according to any one of claims 8 to 10 as a semiconductor active layer, wherein the semiconductor thin film and the electrode are formed without stacking an etching stopper on the semiconductor thin film. A method of manufacturing a thin film transistor, comprising: a step of patterning with a different etching solution, and the step of contacting the semiconductor thin film directly with the etching solution when patterning the electrode.
  22.  請求項18~20のいずれかに記載の薄膜トランジスタを備える表示装置。 A display device comprising the thin film transistor according to any one of claims 18 to 20.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016173170A1 (en) * 2015-04-30 2016-11-03 京东方科技集团股份有限公司 Oxide semiconductor thin film, thin-film transistor, and preparation method and device
WO2017168283A1 (en) * 2016-04-01 2017-10-05 株式会社半導体エネルギー研究所 Composite oxide semiconductor, semiconductor device using said composite oxide semiconductor, and display device having said semiconductor device
CN107522484A (en) * 2017-06-26 2017-12-29 广西新未来信息产业股份有限公司 A kind of preparation method of AZO target material
JP2019077594A (en) * 2017-10-25 2019-05-23 出光興産株式会社 Oxide sintered body, sputtering target, oxide semiconductor thin film, and thin-film transistor
CN111373514A (en) * 2017-11-20 2020-07-03 株式会社爱发科 Oxide semiconductor thin film
US11078120B2 (en) 2016-04-26 2021-08-03 Idemitsu Kosan Co., Ltd. Oxide sintered body, sputtering target and oxide semiconductor film

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5876172B1 (en) * 2014-10-06 2016-03-02 Jx金属株式会社 Oxide sintered body, oxide sputtering target, conductive oxide thin film, and method for producing oxide sintered body
CN107428616B (en) * 2015-02-27 2020-10-23 捷客斯金属株式会社 Oxide sintered body and sputtering target comprising same
TWI629791B (en) 2015-04-13 2018-07-11 友達光電股份有限公司 Active device structure and fabricating method thereof
JP6144858B1 (en) 2016-04-13 2017-06-07 株式会社コベルコ科研 Oxide sintered body, sputtering target, and production method thereof
KR102461413B1 (en) * 2016-08-03 2022-10-31 가부시키가이샤 니콘 Semiconductor device, pH sensor, biosensor, and method for manufacturing semiconductor device
US11251310B2 (en) 2017-02-22 2022-02-15 Idemitsu Kosan Co., Ltd. Oxide semiconductor film, electronic device comprising thin film transistor, oxide sintered body and sputtering target
JP6343695B2 (en) * 2017-03-01 2018-06-13 Jx金属株式会社 Indium oxide-zinc oxide (IZO) sputtering target and method for producing the same
CN109148592B (en) * 2017-06-27 2022-03-11 乐金显示有限公司 Thin film transistor including oxide semiconductor layer, method of manufacturing the same, and display device including the same
US20200235247A1 (en) * 2017-08-01 2020-07-23 Idemitsu Kosan Co.,Ltd. Sputtering target, oxide semiconductor thin film, thin film transistor, and electronic device
JP7269886B2 (en) * 2017-12-28 2023-05-09 三井金属鉱業株式会社 Oxide sintered body, sputtering target and oxide thin film
CN112262114B (en) * 2018-06-19 2022-06-28 三井金属矿业株式会社 Oxide sintered body and sputtering target
CN114032517A (en) * 2021-10-22 2022-02-11 芜湖映日科技股份有限公司 Preparation method of rare earth ion doped ITO target material

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010058533A1 (en) * 2008-11-20 2010-05-27 出光興産株式会社 ZnO-SnO2-In2O3 BASED SINTERED OXIDE AND AMORPHOUS TRANSPARENT CONDUCTIVE FILM
JP2011108739A (en) * 2009-11-13 2011-06-02 Dainippon Printing Co Ltd Thin film transistor substrate, method of manufacturing the same, and image display device
JP2012153592A (en) * 2011-01-28 2012-08-16 Taiheiyo Cement Corp Method for producing zinc oxide sintered compact
WO2012117695A1 (en) * 2011-02-28 2012-09-07 シャープ株式会社 Semiconductor device and process of producing same, and display device
WO2012127883A1 (en) * 2011-03-24 2012-09-27 出光興産株式会社 Sintered material, and process for producing same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010058533A1 (en) * 2008-11-20 2010-05-27 出光興産株式会社 ZnO-SnO2-In2O3 BASED SINTERED OXIDE AND AMORPHOUS TRANSPARENT CONDUCTIVE FILM
JP2011108739A (en) * 2009-11-13 2011-06-02 Dainippon Printing Co Ltd Thin film transistor substrate, method of manufacturing the same, and image display device
JP2012153592A (en) * 2011-01-28 2012-08-16 Taiheiyo Cement Corp Method for producing zinc oxide sintered compact
WO2012117695A1 (en) * 2011-02-28 2012-09-07 シャープ株式会社 Semiconductor device and process of producing same, and display device
WO2012127883A1 (en) * 2011-03-24 2012-09-27 出光興産株式会社 Sintered material, and process for producing same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016173170A1 (en) * 2015-04-30 2016-11-03 京东方科技集团股份有限公司 Oxide semiconductor thin film, thin-film transistor, and preparation method and device
US9917205B2 (en) 2015-04-30 2018-03-13 Boe Technology Group Co., Ltd. Oxide semiconductor thin film, thin film transistor, manufacturing method and device
WO2017168283A1 (en) * 2016-04-01 2017-10-05 株式会社半導体エネルギー研究所 Composite oxide semiconductor, semiconductor device using said composite oxide semiconductor, and display device having said semiconductor device
US10942408B2 (en) 2016-04-01 2021-03-09 Semiconductor Energy Laboratory Co., Ltd. Composite oxide semiconductor, semiconductor device using the composite oxide semiconductor, and display device including the semiconductor device
US11537019B2 (en) 2016-04-01 2022-12-27 Semiconductor Energy Laboratory Co., Ltd. Composite oxide semiconductor, semiconductor device using the composite oxide semiconductor, and display device including the semiconductor device
US11940702B2 (en) 2016-04-01 2024-03-26 Semiconductor Energy Laboratory Co., Ltd. Composite oxide semiconductor, semiconductor device using the composite oxide semiconductor, and display device including the semiconductor device
US11078120B2 (en) 2016-04-26 2021-08-03 Idemitsu Kosan Co., Ltd. Oxide sintered body, sputtering target and oxide semiconductor film
CN107522484A (en) * 2017-06-26 2017-12-29 广西新未来信息产业股份有限公司 A kind of preparation method of AZO target material
JP2019077594A (en) * 2017-10-25 2019-05-23 出光興産株式会社 Oxide sintered body, sputtering target, oxide semiconductor thin film, and thin-film transistor
CN111373514A (en) * 2017-11-20 2020-07-03 株式会社爱发科 Oxide semiconductor thin film

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