TW201428889A - Method of forming semiconductor structure having contact plug - Google Patents

Abstract

A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Description

Method of forming a semiconductor structure having a contact plug

The present invention relates to a method of forming a semiconductor structure having a contact plug, and more particularly to a method of forming a semiconductor structure, wherein a top surface of the contact plug is higher than a top surface of the gate structure and a cap layer over the gate structure The top surface is coplanar.

In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry has attempted to replace the traditional polysilicon gate with a new gate material, such as a work function metal, as a control electrode for matching a high-k gate dielectric layer. .

In addition, after forming a transistor having a metal gate, it is also formed on the external line to electrically connect the metal gate and the source/drain region of the transistor, respectively, as input/output to the external electronic signal. end. External lines usually contain multiple contact plugs, and in order to define complex and dense patterns, double patterning (DPT) is often used as an exposure technique to overcome the limits of the original machine equipment, that is, It is known that the lithography process is performed multiple times in the contact plug process, and the cleaning solution, etching solution or chemical solvent used in the multiple lithography process will damage or deform the exposed metal gate. Therefore, how to avoid follow-up The process of influencing and maintaining the normal function of the metal gate is a problem that the relevant technicians want to improve.

One of the objects of the present invention is to provide a method of forming a semiconductor structure having contact plugs to improve the electrical performance of the overall semiconductor structure.

A preferred embodiment of the present invention provides a method of forming a semiconductor structure having contact plugs, the steps of which are as follows. First, at least one transistor and an interlevel dielectric layer are formed on a substrate, wherein the transistor comprises a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the transistor and the interlayer dielectric layer. Next, a plurality of openings are formed through the cap layer and the interlayer dielectric layer to the source/drain regions, and a conductive layer is formed to cover the cap layer and fill the openings. Then, a portion of the conductive layer is removed to form a plurality of first contact plugs such that one surface of the remaining conductive layer is coplanar with one of the remaining cap layers, and the remaining cap layer will completely cover one of the tops of the gate structure surface.

When forming the first contact plug electrically connected to the source/drain region, the gate structure is completely covered by the cap layer to ensure that the gate structure is not affected by the process of the first contact plug, such as a gate The structure will not contact the cleaning solution, etchant or chemical solvent used in the multiple lithography processes required to form the plurality of openings to maintain the material properties of the gate structure. In addition, the method for forming a first contact plug of the present invention includes sequentially forming a first opening on a source/drain region on one side of the gate structure and a source/drain region on the other side of the gate structure. Two openings are provided to improve the positioning accuracy of the subsequently formed first contact plug.

100‧‧‧Base

102,104‧‧‧Active area

106‧‧‧Shallow trench isolation

107,109‧‧‧Optoelectronics

108,110‧‧‧ gate structure

112A, 112B, 112C, 112D, 114A, 114B, 114C, 114D‧‧‧ source/bungee area

116,118,116A,118A‧‧‧gate dielectric layer

120,122‧‧‧Metal gate

124,126‧‧‧ 边边子

128‧‧‧Contact hole etch stop layer

130‧‧‧Interlayer dielectric layer

132‧‧‧ first cover

134‧‧‧Second cover

136,136’, 158‧‧ ‧ cover

138,148‧‧‧Organic dielectric layer

140,150‧‧‧矽 hard mask layer

142‧‧‧First mask layer

144‧‧‧First patterned photoresist layer

146‧‧‧ first opening

152‧‧‧second mask layer

154‧‧‧Second patterned photoresist layer

156‧‧‧ second opening

160‧‧‧Advanced patterned material layer

162‧‧‧Anti-reflective dielectric layer

164‧‧‧mask layer

166‧‧‧First bottom anti-reflection layer

168‧‧‧second bottom anti-reflection layer

170‧‧‧metal telluride layer

172‧‧‧Block/adhesive layer

174,174'‧‧‧ Conductive layer

176‧‧‧First contact plug

178‧‧‧ dielectric layer

180‧‧‧Second contact plug

182‧‧‧ Third contact plug

P1, P2‧‧‧ pattern

T1, T2, T3‧‧‧ top

1 through 11 illustrate schematic views of a method of forming a semiconductor structure having a contact plug in accordance with a preferred embodiment of the present invention.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figures 1 to 11. 1 through 11 illustrate schematic views of a method of forming a semiconductor structure having a contact plug in accordance with a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 100 is first provided, and the substrate 100 includes at least two active regions 102/104 and a plurality of shallow trench isolation (STI) 106 in the substrate 100. The substrate 100 may be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (silicon-on-insulator). SOI) A semiconductor substrate composed of a substrate or other semiconductor substrate material, but not limited to the above. The shallow trench isolation 106 may comprise an insulating material such as tantalum oxide, and the method of forming shallow trench isolation is well known to those skilled in the art and will not be repeated here.

Next, at least one transistor 107/109 and an interlayer dielectric layer 130 are formed on the substrate 100. Each of the transistors 107/109 includes a gate structure 108/110 and two source/drain regions 112A/112B/114A/114B, wherein each gate structure 108/110 includes a gate dielectric layer 116/118 And a metal gate 120/122, and two source/drain regions 112A/112B/114A/114B are respectively disposed on both sides of the gate structure 108/110. The invention can be applied to various metal gate processes including a gate first process, a gate last process, a high-k first process, and a gate process after a gate process. Dielectric layer (high-k last) process, etc. In this embodiment, the transistor 107/109 formed by the gate dielectric process after the gate process is taken as an example, wherein the gate dielectric layer 116/118 comprises a high dielectric constant dielectric having a U-shaped profile. a layer comprising a dielectric material having a dielectric constant greater than 4, and optionally also Further comprising a dielectric layer (not shown) such as a tantalum oxide layer disposed between the substrate 100 and the gate dielectric layer 116/118; and the metal gate 120/122 may comprise one or more layers of metal material, for example comprising one A work function metal layer, a barrier layer, and a low resistance metal layer. For example, the process of forming the gate structure 108/110 and the source/drain regions 112A/112B/114A/114B may first form a dummy gate structure (not shown) on the substrate 100, and then sequentially form sidewalls. Sub-124/126, source/drain regions 112A/112B/114A/114B, contact etch stop layer (CESL) 128, and interlayer dielectric layer 130. The interlayer dielectric layer 130 may be formed of a dielectric material formed by a spin-on-coating (SOC) process, a chemical vapor deposition (CVD) process, or other suitable process, and the dielectric material includes a low dielectric. Constant (k) material (dielectric constant value less than 3.9), ultra low dielectric constant (ultra low-k, hereinafter referred to as ULK) material (dielectric constant value less than 2.6), or porous ultra-low dielectric Constant ULK material, but is not limited to this. Next, a planarization process is performed on the interlayer dielectric layer 130 to expose the dummy gate structure, and then a portion of the dummy gate structure is removed to form a trench (not shown), and finally at least one dielectric is filled in the trench. a material layer (not shown) and at least one metal material layer (not shown), and performing a chemical mechanical polishing (CMP) process to remove the dielectric material layer and the metal material layer outside the trench to form a gate The gate dielectric layer 116/118 of the pole structure 108/110 and the metal gate 120/122, and one of the top surfaces of the interlayer dielectric layer 130 will be coplanar with one of the top surfaces of the gate structure 108/110.

In addition, the various components in the transistor can have different implementations depending on the design. For example, the source/drain regions 112A/112B/114A/114B can include selective epitaxial growth (selective epitaxial growth, An epitaxial layer formed by SEG), wherein the epitaxial layer can be formed directly on the substrate 100, as shown by the source/drain regions 112A/112B in the active region 102, or a recess is formed in the gate structure 108/ Both sides of the 110 are filled with an epitaxial layer in the recess, as shown by the source/drain regions 114A/114B in the active region 104 to provide stress to the gate structure. The passage area below 108/110. In the present embodiment, when the transistor 107 is an N-type MOS transistor (NMOS), the epitaxial layer of the source/drain region 112A/112B may be bismuth phosphide (SiP) or tantalum carbide (SiC). The composition is to provide tensile stress to the channel region, and when the transistor 109 is a P-type MOS transistor (PMOS), the epitaxial layer of the source/drain region 114A/114B may be composed of germanium telluride (SiGe). Provide compressive stress to the channel area, but not limited to this. The top surface of one of the epitaxial layers is preferably higher than one of the original surfaces of the substrate 100, that is, the epitaxial layers included in the source/drain regions 112A/112B/114A/114B respectively protrude upward from the substrate 100. And may extend down into the substrate 100 depending on process requirements, or even extend below the sidewalls 124/126 to provide greater stress to the channel region. In addition, a dry and wet etching process can be mixed to form various shapes such as a barrel shape (a straight shape), a hexagonal shape, a polygonal groove, and a protrusion formed in a groove of such a shape in a subsequent process. The seed layer may have a cross-sectional shape of a hexagonal or octagon and has a substantially flat bottom surface to increase the stress provided to the channel region.

In another embodiment, as shown in FIG. 2, the gate dielectric layer 116/118 is a "high-k last process" process in the embodiment different from the first embodiment. Forming (ie, the gate dielectric layer is formed after removing the dummy gate), in the embodiment of FIG. 2, the gate dielectric layer 116A/118A is a "high-k first" process Process formation (ie, the gate dielectric layer is formed before the dummy gate), so the gate dielectric layer has a "-type" profile, and on the other hand, the source/drain region 112C/112D/114C/114D The source/drain doping region may also be formed by ion implantation or the like, and the shape of the source/drain region 112C/112D/114C/114D may also be adjusted according to the stress required for the channel under the gate. In addition, the contact hole etch stop layer 128 may additionally have a stress. The above embodiments are merely examples, and the transistor of the present invention may have various implementations, which are not described herein. The following embodiments will be described in the embodiment of the transistor 107/109 in Fig. 1.

As shown in FIG. 3, a cap layer 136 is formed over the transistor 107/109 and the interlayer dielectric layer 130, and the cap layer 136 simultaneously contacts the interlayer dielectric layer 130 and the gate structure 108/110. The cap layer 136 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon carbide, dopant-containing tantalum carbide, silicon oxynitride or a combination thereof. A single layer structure or a multilayer structure. A method of forming a cap layer includes sequentially forming a first cap layer 132 and a second cap layer 134 on the interlayer dielectric layer 130, wherein a material of the first cap layer 132 is substantially different from that of the second cap layer 134 The material, that is, the first cap layer 132 and the second cap layer 134 will have an etch selectivity ratio, that is, when the first cap layer 132 and the second cap layer 134 are removed using the same etchant or abrasive, The rate of removal of a cap layer 132 will be substantially different than the rate at which the second cap layer 134 is removed. In this embodiment, the first cap layer is composed of nitrogen doped silicon carbide (NDC), silicon nitride (SiN) or silicon carbonitride (SiCN). The second cap layer is composed of an oxide, and the removal speed of the second cap layer 134 is substantially greater than the removal rate of the first cap layer 132, but is not limited thereto.

Subsequently, a plurality of openings are formed through the cap layer 136 and the interlayer dielectric layer 130 to the source/drain regions 112A/112B/114A/114B. A method of forming a plurality of openings, including the following steps. First, please continue to refer to FIG. 3. As shown in FIG. 3, a first mask layer 142 and a first patterned photoresist layer 144 are formed on the cap layer 136, and the first patterned photoresist layer 144 and the first layer are formed. A mask layer 142 can have different options depending on the process technology. For example, the first patterned photoresist layer 144 may be formed of a photoresist material suitable for a wavelength of 248 nanometers (nm) or 193 nanometers (nm), such as a KrF photoresist layer, and the first patterned photoresist A bottom anti-reflective coating (BARC) may be selectively formed under the layer 144 (not shown); the first mask layer 142 may include one or more layers of a masking material, such as nitriding. Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), organic materials containing amorphous carbon (as reported by Applied Materials Inc.) Advanced pattern film APF©) and so on. In this embodiment, the first patterned photoresist layer 144 includes a pattern defining a first opening, and the first mask layer 142 is directly disposed under the first patterned photoresist layer 144. A mask layer 142 includes an organic dielectric layer (ODL) 138 and a silicon-containing hard mask (SHB) layer 140. The organic dielectric layer 138 may be composed of an I-line photoresist material having a wavelength of 365 nanometers (nm) or a novolac resin. The composition of the ruthenium-containing hard mask layer 140 is mainly composed of an organo-silicon polymer or a polysilane, and has at least one chromophore group and one cross. A crosslinkable group, and the ruthenium-containing hard mask layer 140 may further include a crosslinking agent to cause the ruthenium-containing hard mask layer 140 to generate a crosslinking reaction after illumination.

Next, as shown in FIG. 4, using the first patterned photoresist layer 144 as a mask, a first etching process is performed to remove a portion of the first mask layer 142, a portion of the cap layer 136, and a portion of the interlayer dielectric layer 130. Finally, the contact hole etch stop layer 128 is stopped to form at least one first opening 146, wherein the first opening 146 overlaps only the source/drain regions 112A/114A on the side of the gate structure 108/110, and the cap layer 136 The source/drain regions 112B/114B on the other side of the gate structure 108/110 and the gate structure 108/110 are still completely covered. In addition, when an over etch condition occurs, the contact hole etch stop layer 128 will have a partial loss, that is, the thickness of the contact hole etch stop layer 128 at the bottom of the first opening 146 will be less than the contact hole etch stop. The original thickness of layer 128. Subsequently, the first patterned photoresist layer 144 and the first mask layer 142 are removed.

Next, as shown in FIG. 5, a second mask layer 152 and a second patterned photoresist layer 154 are formed on the cap layer 136, and the second patterned photoresist layer 154 and the second mask layer 152 are formed. The composition may have different options depending on the process technology, and is the same as or different from the composition of the first patterned photoresist layer 144 and the first mask layer 142. In this embodiment, the second patterned photoresist layer 154 includes a pattern defining a second opening, and the second mask layer 152 is directly disposed on the first The second mask layer 152 has the same composition as the first mask layer 142, that is, the second mask layer 152 is a multi-layer stack structure, including a A silicon-containing hard mask (SHB) layer 150 and an organic dielectric layer (ODL) 148, wherein the organic dielectric layer 148 of the second mask layer 152 has good hole filling capability. Therefore, it can be effectively filled in the formed first opening 146. Next, as shown in FIG. 6, using the second patterned photoresist layer 154 as a mask, a second etching process is performed to remove a portion of the second mask layer 152, a portion of the cap layer 136, and a portion of the interlayer dielectric layer 130. A portion of the contact hole etch stop layer 128 forms at least one second opening 156, wherein the second opening 156 overlaps only the source/drain regions 112B/114B on the other side of the gate structure 108/110, and the cap layer 136 remains The gate structure 108/110 is completely covered, that is, in both the first etch process and the second etch process, neither the first opening 146 nor the second opening 156 exposes the gate structure 108/110 of the transistor 107/109. Next, the second patterned photoresist layer 154 and the second mask layer 152 are removed. Finally, the contact opening etch stop layer 128 at the bottom of the first opening 146 and the second opening 156 is removed, and thus a method of forming a plurality of openings is completed.

The first opening 146 and the second opening 156 are not limited to a single single port, and may also include a plurality of independent openings or an extended strip, and the extended strips may be along the parallel gate structure. The direction in which the 108/110 extends, that is, the direction perpendicular to the paper, extends over the source/drain regions 112A/112B/114A/114B and preferably extends the entire source/drain region 112A/112B/114A/114B To increase the contact area of the subsequently formed first contact plug with the source/drain regions 112A/112B/114A/114B and reduce the resistance. That is to say, the size, shape, number and layout pattern of the opening can be adjusted according to the process requirements.

The method of forming a plurality of openings through the cap layer and the interlayer dielectric layer to the source/drain regions is not limited to the above embodiment. In other embodiments, when the distance between the plurality of openings is greater than the minimum exposure technology Pattern distance, a single mask layer can be used with a single patterned photoresist The layer is subjected to a lithography process to simultaneously define a plurality of openings without separately forming partial openings. In another embodiment, a method of forming a plurality of openings comprises the following steps. First, as shown in FIG. 7, a mask layer 164, a first bottom anti-reflective coating film (BARC) 166, and a first patterned photoresist layer 144 are formed on the cap layer 158. The cover layer 158 may comprise a single layer structure or a multilayer structure, and the mask layer 164 may include an advanced patterning film (APF) 160 such as an amorphous carbon layer, and an anti-reflective dielectric layer (dielectric anti -reflective coating film (DARC) 162, wherein the advanced patterned material layer (APF) 160 has good high aspect ratio (HAR), low edge line roughness (LER) and ashing resistance. (PR-like ashability), so it is often used in processes with line widths less than 60 nm. Next, using the first patterned photoresist layer 144 as a mask, the pattern of the first patterned photoresist layer 144, that is, the pattern defining the first opening, is transferred to the anti-reflective dielectric layer (DARC) 162 of the mask layer 164. Then, the first patterned photoresist layer 144 and the first bottom anti-reflective layer 166 are removed. Next, as shown in FIG. 8, a second bottom anti-reflective layer 168 and a second patterned photoresist layer 154 are formed on the mask layer 164, and the second patterned photoresist layer 154 is used as a mask. The pattern of the second patterned photoresist layer 154, that is, the pattern defining the second opening, is transferred to the anti-reflective dielectric layer (DARC) 162 of the mask layer 164, and then the second patterned photoresist layer 154 and the second bottom are removed. Anti-reflection layer 168. At this time, the mask layer 164 simultaneously forms the pattern P1 including the first opening and the pattern P2 of the second opening, that is, the pattern of the plurality of openings, in the anti-reflection dielectric layer (DARC) 162, and the patterns of the openings are not The advanced patterned material layer (APF) 160 is exposed, and the distance between the pattern P1 of the first opening and the pattern P2 of the second opening may be smaller than the minimum pattern distance that the exposure technique can expose. Next, at least two patterning processes are performed to transfer the patterns of the openings (the pattern of the first opening P1 and the pattern of the second opening P2) into the cap layer 158 and the interlayer dielectric layer 130 to form a pattern as shown in FIG. The first opening 146 and the second opening 156 are shown. In more detail, the anti-reflective dielectric layer (DARC) 162 is used as a mask, and a first patterning process is performed to transfer the patterns of the openings to the advanced patterned material layer (APF) 160 and expose portions. After the cap layer 158, the anti-reflective dielectric layer (DARC) 162 A second patterning process is performed together with the advanced patterned material layer (APF) 160 as a mask, and a plurality of openings, that is, a first opening 146 and a second opening 156 are formed in the cap layer 158 and the interlayer dielectric layer 130. Similarly, the first opening 146 and the second opening 156 both overlap the source/drain region 112A/112B/114A/114B without exposing the gate structure 108/110, and further, the first opening 146 and the second opening are removed. The exposed contact etch stop layer 128 at the bottom of 156, wherein the gate structure 108/110 is completely covered by the cap layer 158 during the patterning process described above.

As shown in FIG. 9, after forming a plurality of openings, a cleaning process may be selectively performed, for example, cleaning the surfaces of the first opening 146 and the second opening 156 with argon (Ar). Subsequently, a self-aligned metal salicide process can be performed to form a metal telluride on the source/drain regions 112A/112B/114A/114B exposed by the first opening 146 and the second opening 156, respectively. The silicide layer 170 is, for example, a nickel niobide (NiSi) layer. In other embodiments, this step of forming a metal telluride may be omitted if the metal telluride layer has been formed on the source/drain regions prior to forming the opening.

Subsequently, a plurality of first contact plugs are formed in the first opening 146 and the second opening 156. For the method of forming the first contact plug, please continue to refer to FIG. 9. As shown in FIG. 9, for example, a barrier/adhesion layer 172, a seed layer (not shown), and a seed layer (not shown) are sequentially formed on the substrate 100. A conductive layer 174 covers the cap layer 136 and fills the first opening 146 and the second opening 156, wherein the barrier/adhesion layer 172 is conformally filled into the first opening 146 and the second opening 152, and is electrically conductive. Layer 174 completely fills first opening 146 and second opening 156. The barrier/adhesion layer 172 can be used to prevent metal atoms of the conductive layer 174 from diffusing into the surrounding interlayer dielectric layer 130 and to increase adhesion between the conductive layer 174 and the interlayer dielectric layer 130. The material of the barrier/adhesive layer 172 is, for example, tantalum (Ta), titanium (Ti), titanium nitride (TiN), titanium telluride (TaN) or any combination thereof such as titanium/titanium oxide, but not This is limited. The material of the seed layer is preferably the same as the material of the conductive layer 174, and the material of the conductive layer 174 comprises various low resistance metal materials, such as It is aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu) and the like, preferably tungsten or copper, preferably tungsten. A suitable ohmic contact is formed with the metal telluride layer 170 or the underlying source/drain regions 112A/112B/114A/114B.

Then, as shown in FIG. 10, a planarization process such as a chemical mechanical polishing (CMP) process, an etching process, or a combination of the two is performed to remove the resistance of the regions other than the first opening 146 and the second opening 156. The barrier/adhesive layer 172, the seed layer and the conductive layer 174, and the portion of the cap layer 136 are removed such that one surface of the remaining conductive layer 174' is coplanar with one of the remaining cap layers 136', thereby completing a plurality of first The contact plug 176, that is, the source/drain plug, and the remaining cap layer 136' still completely covers one of the top surfaces of the gate structure 108/110. It should be noted that since the material of the first cap layer 132 is substantially different from the material of the second cap layer 134, the first cap layer 132 can serve as a stop layer of the planarization process, so that the second cap layer 134 is completely removed, and The top surface of the formed first contact plug 176 is located in the first cover layer 132. In more detail, one of the top contact pads 176 is substantially higher than the top surface of the gate structure 108/110. Face T2, and the top surface T1 of each of the first contact plugs 176 is coplanar with the top surface T3 of one of the remaining cover layers 136'.

In other embodiments, when the cap layer 136 is a single layer structure composed of a dielectric material, the operating conditions of the planarization process can be adjusted by a time mode, such as adjusting the processing time of the planarization process. To determine the thickness of the removed cap layer 136, the surface of one of the remaining conductive layers 174' is coplanar with the surface of one of the remaining cap layers 136'.

As shown in FIG. 11, after forming a plurality of first contact plugs 176, a dielectric layer 178 is formed on the remaining cap layer 136', and a plurality of second contact plugs 180 are formed thereon. Each of the first contact plugs 176 is electrically connected to the first contact plugs 176, and the at least one third contact plugs 182 are electrically connected to the dielectric layer 178 and the remaining cap layer 136'. Gate structure 108/110. Finally, a metal interconnect process can be performed to form a metal interconnection system (not shown) on the dielectric layer 178, which includes a plurality of inter-metal dielectric layers. , IMD layer) and a plurality of metal layers (so-called metal 1, metal 2...etc.). The metal interconnecting system is electrically connected to the metal gate 120/122 of the transistor 107/109 through the third contact plug 182, and electrically connected to the second contact plug 180 and the first contact plug 176. The source/drain regions 112A/112B/114A/114B of the crystal 107/109 provide input/output of the external signals of the transistor 107/109.

In summary, when the first contact plug is electrically connected to the source/drain region, the gate structure is completely covered by the cap layer to ensure that the gate structure is not protected by the first contact plug. The effect, such as the gate structure, will not contact the cleaning solution, etchant or chemical solvent used in the multiple lithography processes required to form the plurality of openings to maintain the material properties of the gate structure. In addition, the method for forming a first contact plug of the present invention includes sequentially forming a first opening on a source/drain region on one side of the gate structure and a source/drain region on the other side of the gate structure. Two openings are provided to improve the positioning accuracy of the subsequently formed first contact plug.

100‧‧‧Base

102,104‧‧‧Active area

106‧‧‧Shallow trench isolation

107,109‧‧‧Optoelectronics

108,110‧‧‧ gate structure

112A, 112B, 114A, 114B‧‧‧ source/bungee area

116,118‧‧‧gate dielectric layer

120,122‧‧‧Metal gate

124,126‧‧‧ 边边子

128‧‧‧Contact hole etch stop layer

130‧‧‧Interlayer dielectric layer

132‧‧‧ first cover

136’‧‧‧ cover

170‧‧‧metal telluride layer

172‧‧‧Block/adhesive layer

174'‧‧‧ Conductive layer

176‧‧‧First contact plug

T1, T2, T3‧‧‧ top

Claims (17)

A method of forming a semiconductor structure having a contact plug includes: forming at least one transistor and an interlevel dielectric layer on a substrate, wherein the transistor comprises a gate structure and a two source/drain region; forming a a capping layer on the transistor and the interlayer dielectric layer; forming a plurality of openings through the cap layer and the interlayer dielectric layer to the source/drain regions; forming a conductive layer covering the cap layer and filling And removing a portion of the conductive layer to form a plurality of first contact plugs such that a surface of one of the remaining conductive layers is coplanar with a surface of one of the remaining cover layers, and the remaining cover layer is completely Covering one of the top surfaces of the gate structure. A method of forming a semiconductor structure having a contact plug as described in claim 1, wherein the material of the cap layer comprises a dielectric material. A method of forming a semiconductor structure having a contact plug according to claim 1, wherein the method of forming the cap layer comprises sequentially forming a first cap layer and a second cap layer on the interlayer dielectric layer. A method of forming a semiconductor structure having a contact plug as described in claim 3, wherein after removing a portion of the conductive layer, the remaining cap layer includes only the first cap layer. A method of forming a semiconductor structure having a contact plug as described in claim 3, wherein the material of the first cap layer is substantially different from the material of the second cap layer. A method of forming a semiconductor structure having a contact plug as described in claim 1 further comprising forming an etch stop layer before forming the interlayer dielectric layer. The method of forming a semiconductor structure having a contact plug according to claim 1, further comprising performing a planarization process on the interlayer dielectric layer before forming the cap layer. The method for forming a semiconductor structure having a contact plug according to claim 7, wherein after the planarization process is performed on the interlayer dielectric layer, a top surface of the interlayer dielectric layer and the top surface of the gate structure The coplanar layer, and the cap layer simultaneously contacts the interlayer dielectric layer and the gate structure. A method of forming a semiconductor structure having a contact plug as described in claim 1, wherein the openings do not expose the gate structure of the transistor. A method of forming a semiconductor structure having a contact plug as described in claim 1, wherein the method of forming the plurality of openings comprises forming at least one first opening and then forming at least one second opening. A method of forming a semiconductor structure having a contact plug as disclosed in claim 10, wherein the first opening exposes the source/drain region on one side of the gate structure, the second opening exposes the gate structure and another The source/drain region on the side. A method of forming a semiconductor structure having a contact plug according to claim 1, wherein before forming the conductive layer to fill the openings, further comprising performing a self-aligned metal telluride process to form a metal telluride, respectively. Layers are on each of the source/drain regions. A method of forming a semiconductor structure having a contact plug according to claim 1, wherein the gate structure comprises a gate dielectric layer and a metal gate. A method of forming a semiconductor structure having a contact plug according to claim 13, wherein the metal gate comprises a work function metal layer, a barrier layer And a low resistance metal layer. A method of forming a semiconductor structure having a contact plug according to claim 1, wherein a top surface of each of the first contact plugs is substantially higher than the top surface of the gate structure, and each of the first contacts The top surface of the plug is coplanar with a top surface of the cover layer. A method of forming a semiconductor structure having a contact plug according to claim 1, wherein each of the source/drain regions comprises an epitaxial layer, and one of the top layers of the epitaxial layer is higher than one of the substrates surface. The method of forming a semiconductor structure having a contact plug according to claim 1, further comprising: forming a dielectric layer on the remaining cap layer; forming a plurality of second contact plugs in the dielectric layer Electrically connecting each of the first contact plugs; and forming at least one third contact plug in the dielectric layer and the remaining cover layer to electrically connect the gate structure.