TW201426922A - Back-to-back stacked integrated circuit assembly and method of making - Google Patents

Abstract

An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with the second surfaces of each substrate coupled together. A method of fabricating an integrated circuit assembly includes forming active layers on the first surfaces of each of two substrates, and coupling the second surfaces of the substrates together.

Description

Back-to-back stacked integrated circuit assembly and manufacturing method

The present application claims priority to U.S. Patent Application Serial No. 13/725,403, entitled,,,,,,,,,,, Used for all purposes. The present application is related to U.S. Patent Application Serial No. 13/725,245, filed on Dec. 21, 2012, which is incorporated herein by reference in its entirety in U.S. Patent Application Serial No. 13/725,306, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety in the the the the the the the the the the the The manner is incorporated herein.

Electronic devices continue to offer more functionality in smaller packages. This is partially achieved by integrating more capacity, processing power, memory, etc. onto a single integrated circuit chip. However, it is also important in the development of small and powerful devices to be able to mount more integrated circuit chips themselves into smaller packages.

Integrated circuit chips are typically attached to a printed circuit board. These boards contain one or more layers of metal traces and vias that provide electrical connections to the wafer and other components, thus completing the electronic system. The board is made smaller to fit into smaller devices by using an innovative way of attaching its component wafers.

The integrated circuit die can be attached to the printed circuit board in a number of ways. They are typically mounted in a package having a variety of pin configurations that are then inserted into the holes of the printed circuit board and secured in place. For smaller shapes, the packaging step can be omitted and the wafer Can be mounted directly on the board. For wafer mounting in a package and directly on a board, the common wafer mounting techniques are wire bonding. In this method, thin leads connect pads in the package or on the board to pads on the wafer. These bond pads are typically laid flat along the outer edge of the upper surface of the wafer.

The board area required for wire bonding the wafer exceeds the crystal due to the length of the lead The area of the sheet, so other methods can be used instead of wire bonding. In the second method, known as flip chip or C4 (for controlling crashed wafer connections), the bond pads on the wafer are coated by solder bumps and the wafers are mounted face down on the board. In this method, the footprint of the wafer used on the board is not greater than the area of the wafer. Removing long leads can also have performance advantages.

Another way to reduce the size of the board is to stack the wafers on top of each other. It is still electrically connected to the board. Designers generally consider stacking related wafers such as memory chips and their controllers. In this case, the upper wafer is typically directly connected to the lower wafer and is not necessarily connected to the circuit board. Such a stacked wafer assembly will typically require a vertical connection, such as a via, to transmit signals and/or power to at least one of the wafers. This vertical connection, while expensive, can result in a reduction in the substantial package size, especially in the case of this technology combined with flip chip mounting. In such assemblies, the wafer is flip-chip mounted with C4 bumps formed on the lower wafer; or face-to-face with C4 bumps formed directly on the vertical connector.

In some cases, wafer stacking may be beneficial but does not require a vertical connection. Example In this case, a plurality of identical memory chips can be connected to one controller wafer in order to increase the memory capacity. In this case, the memory chips can be stacked separately and bonded to the printed circuit board, connected to the nearby controller wafer. In such cases, the wafers are typically mounted face up and are wire bonded to the board. However, the small area savings provided by the wafer stack is lost due to the area consumed by the large number of wire bonds.

Therefore, there is an increasing need to produce small, complex electricity in a cost-effective manner. Road board.

As used herein and in the scope of the accompanying patent application, circuitry is formed on a substrate The area is called the active layer. The circuit referred to by the term "active layer" need not include any active device; rather, this layer may include circuitry that includes only passive components. Examples of such passive circuits include band pass filters and resistor dividers.

In one embodiment, an integrated circuit assembly includes a substrate having a first surface and a second surface, the first surface having an active layer formed therein. The first active layer includes a first metal pad. Providing a second substrate having a first surface and a second surface, wherein a second active layer is formed in the first surface such that a second surface of the second substrate is coupled to the second substrate surface. The second active layer comprises a second metal pad.

In another embodiment, a method of fabricating an integrated circuit assembly includes providing a first substrate having a first surface and a second surface. A first active layer is formed on the first surface of the first substrate. A second substrate is provided having a first surface and a second surface, and further having a second active layer formed on the first surface thereof. A second surface of the second substrate is coupled to the second surface of the first substrate.

100‧‧‧First substrate

101‧‧‧ first surface

102‧‧‧ second surface

103‧‧‧First active layer

104‧‧‧Metal joint pad

105‧‧‧Lead

107‧‧‧Metal pad

108‧‧‧dick

109‧‧‧ lead

115‧‧‧welding bumps

200‧‧‧second substrate

201‧‧‧ first surface

202‧‧‧ second surface

203‧‧‧Secondary layer

204‧‧‧Metal pad

205‧‧‧welding bumps

206‧‧‧Printed circuit board

207‧‧‧Metal pad

208‧‧‧dick

216‧‧‧Printed circuit board

240‧‧‧Integrated circuit assembly

250a‧‧‧ integrated circuit assembly; bump assembly

250b‧‧‧ integrated circuit assembly

260‧‧‧ third substrate

261‧‧‧ first surface

262‧‧‧ second surface

263‧‧‧Working layer

264‧‧‧ pads

300‧‧‧Semiconductor semiconductor

302‧‧‧ surface

303‧‧‧Working layer

304‧‧‧Metal joint pad

308‧‧‧

310‧‧‧Insulation

311‧‧‧Processing layer

312‧‧‧ temporary carrier

340‧‧‧ integrated circuit assembly

350a‧‧‧ integrated circuit assembly

400‧‧‧ Flowchart

410‧‧‧Steps

415‧‧‧ steps

420‧‧ steps

425‧‧ steps

430‧‧ steps

435‧‧‧Steps

440‧‧‧Steps

445‧‧ steps

1000‧‧‧flow chart

1010‧‧‧Steps

1015‧‧‧Steps

1020‧‧‧Steps

1025‧‧‧Steps

1030‧‧‧Steps

1035‧‧‧Steps

1040‧‧‧Steps

1045‧‧‧Steps

1050‧‧‧Steps

1055‧‧‧Steps

1060‧‧‧Steps

The various aspects and embodiments of the invention described herein can be used alone or in combination with one another. The aspects and embodiments will now be described with reference to the drawings.

1 is a flow diagram of an exemplary method for forming a back-to-back stacked volume circuit.

2a-2f are cross-sectional views showing the steps of forming a back-to-back stacked integrated circuit in accordance with some embodiments.

3 is a cross-sectional view of another embodiment of a back-to-back stacked integrated circuit.

4a through 4b are cross-sectional views of another embodiment of a back-to-back stacked integrated circuit.

5a-5b are cross-sectional views of another embodiment of a back-to-back stacked integrated circuit in which a third integrated circuit is stacked on top of the back-to-back integrated circuit assembly.

6 is a flow diagram of an exemplary method of transferring an SOI active layer to the back side of a bulk CMOS integrated circuit.

7a-7f are cross-sectional views showing the steps of forming a stacked CMOS/SOI integrated circuit in accordance with some embodiments.

An electronic assembly typically includes a plurality of integrated circuit crystals attached to a printed circuit board sheet. The printed circuit board contains leads and connections to the integrated circuitry to form a complete functional system. In order to minimize the footprint of this assembly, integrated circuit chips are typically stacked on top of each other.

A stacked wafer assembly and a method of stacking wafers are disclosed. Place The proposed wafer stacking process is simple and low cost. In an embodiment of the invention, a method in which integrated circuit wafers are stacked back to back on each other and electrically connected to a printed circuit board is described. In this configuration, the bond pads on each wafer are accessible without the need for vertical connections, such as through-holes. Since vertical via diameters are typically less than 5 microns and spaced apart by less than 5 microns, vertical connections between wafers typically require expensive precision alignment (<5 microns) between the wafers. Thus, in the present invention, highly accurate wafer-to-wafer alignment is not required.

In the present invention, one of the wafers can be solder bumps ("Crystal" method) Bond to the board to achieve a minimum wafer outline area. One or two wafers can be thinned to achieve a thinner circuit board assembly that is typically required for small, thin electronic devices. In fact, the first wafer can structurally support the second wafer, so the second wafer can be thinned to 10 microns or less. Alternatively, the second wafer can be a semiconductor-on-insulator (SOI) bonded to the first wafer using layer transfer techniques to achieve an even thinner assembly.

1 illustrates an embodiment of a method of the present disclosure in which a block is formed Two integrated circuits on the semiconductor substrate are coupled back to back and attached to the printed circuit board to electrically connect the two circuits to the circuit board. In the flowchart 1000 of FIG. 1, a first substrate, such as a germanium wafer, having a first surface and a second surface is provided in step 1010. In step 1015, a first active layer is formed on the first surface of the first substrate, for example, via a standard complementary metal oxide semiconductor (CMOS) process. Such a process can, for example, form a transistor, a contact, and an interconnect layer that are connected to form an integrated circuit. In step 1020, a metal bond pad is formed on the first active layer. The pad can be electrically connected to an input node, an output node, a power node, a ground node, or some other node of the integrated circuit formed in step 1015. The pad is physically connectable to a metal interconnect layer formed as part of step 1015.

In step 1025, a second substrate is provided, which has a first surface and a The second surface and further has a second active layer formed on the first surface thereof. For example, the second substrate can be a second germanium wafer, wherein a CMOS process is used similar to step 1015. An active layer is formed on the first surface thereof. In step 1030, a metal bond pad is formed on the second active layer. In one embodiment, the metal bond pad is similar to the bond pad formed on the first active layer in step 1020. In step 1035, one or both of the substrates may be thinned. For example, material can be removed from the second surface of either substrate via grinding. In step 1040, the second surface of the first substrate is bonded to the second surface of the second substrate. Any wafer bonding method that results in permanent bonding can be used; for example, direct splicing or fusion bonding, permanent bonding bonding, intermetallic diffusion, or eutectic bonding. It should be noted that in some embodiments, this step can include an alignment step such that the scribe lines on each substrate are substantially aligned with one another. In some embodiments, an insulating layer (eg, hafnium oxide) can be grown or deposited on the second surface of the first substrate, or on the second surface of the second substrate, or both.

Still referring to FIG. 1, in step 1045, the first gold on the first active layer A solder bump is formed on the bonding pad. For example, this step can include testing the wafer on each substrate prior to forming the solder bumps. In step 1050, the bonded substrate assembly is optionally separated into individual wafers. For example, the separating step can include cutting with a saw. In step 1055, the solder bump is attached to a third metal pad on a printed circuit board. For example, this step can be accomplished by completing the soldering step; that is, by soldering the bumps to adhere to the material of the third metal pad on a printed circuit board. In step 1060, a second metal bond pad on the second active layer is wire bonded to a fourth metal pad on the printed circuit board. The resulting structure has two stacked integrated circuits, both of which are independently electrically connected to a printed circuit board.

2a to 2f illustrate an exemplary stacked integrated body fabricated according to the method of FIG. road. In FIG. 2a, a first substrate 100 having a first surface 101 and a second surface 102 is provided. For example, the substrate can be a single wafer, for example having a thickness of 500 microns to 900 microns. Alternatively, the substrate may comprise a different semiconductor (e.g., germanium, gallium arsenide, or gallium nitride), or it may comprise an insulator (e.g., sapphire or quartz). In FIG. 2b, a first active layer 103 is formed on the first substrate 100. For example, the active layer can include a transistor (eg, including a gate, a source, a drain, and a body region), an isolation region, a contact, and an interconnect layer that form a complete integrated circuit. This active layer can be formed by any of a number of integrated circuit fabrication processes, such as a CMOS process or a CMOS process using a bipolar transistor (BiCMOS) or a process of forming a high power device or optoelectronic device other than a MOS transistor. The active layer 103 can include a line 108 separate multiple integrated circuits. For example, the width of such scribe lines can be 40 microns or 80 microns. FIG. 2B also shows the metal bond pad 104 formed in the first active layer. These metal pads can be made of any metal compatible with solder bumps or wire bonds; for example copper or aluminum. Forming the metal bond pad 104 can also include forming a passivation layer, such as tantalum nitride or hafnium oxynitride, to prevent the circuit from reacting with its environment. Thus, forming the metal bond pad 104 can also include forming a pad opening to access the bond pad 104.

FIG. 2c illustrates a second substrate 200 that can be similar to the first substrate 100, There is a first surface 201 and a second surface 202. For example, the second substrate may be a germanium wafer having a thickness similar to that of the first substrate (ie, 500 micrometers to 900 micrometers), or a wafer of different semiconductors, such as germanium, or an insulator such as sapphire. The second substrate has an active layer 203 formed on the first surface 201; for example, the active layer may be formed using a process similar to that used to form the first active layer 101, or may be formed using different circuits. Different processes of components. The active layer 203 may also include a plurality of integrated circuits separated by scribe lines 208. The thickness of the scribe lines may be the same as the thickness of the scribe lines 108 on the first active layer 103. Also shown in Figure 2c is a second set of metal pads 204 formed in the second active layer 203. These metal pads 204 may be formed of a material similar to the first metal bond pads 104, or the like may be formed of different metals. Similarly, forming metal pad 204 can include forming a passivation layer. In FIG. 2c, the second surface 102 of the first substrate 100 is bonded to the second surface 202 of the second substrate 200 to form a bonded integrated circuit assembly 240.

Before or during this bonding step, either or both of the substrates 100 and 200 can be Thinning, for example, to a final thickness of 150 microns, or 100 microns, or 80 microns, or 50 microns, or 30 microns, or 10 microns. If one substrate is not thinned to a point where the structure is unstable (eg, for a germanium wafer, the substrate is greater than about 100 microns), the other substrate can be sufficiently thinned; for example, to a 30 micron or 10 position. In any event, the thinning step can include, for example, first attaching the first surface 101 or 201 of the substrate to the back grinding tape, or to the rigid processing wafer coated with the adhesive. The second surface 102 or 202 of the substrate can then be subjected to a mechanical or chemical mechanical polishing step, or a purification polishing step or any combination of such steps.

Prior to combining surfaces 102 and 202 for bonding, infrared imaging can be used, for example, to align substrates 100 and 200 with each other. The purpose of this alignment may be to align the scribe lines 108 and 208 with each other. Therefore, the accuracy required for this alignment step depends on, for example, the scribe line 108. And the width of 208; for example, the alignment accuracy may be one quarter of the width of the scribe line, or 10 microns, or 20 microns. This is less critical, for example, than the precision required to align a wafer that must be connected by a bonded via. This alignment may require an accuracy of less than 1 micron. Thus, embodiments of the present invention may use equipment and bonding processes that are less expensive than the equipment and bonding processes required to form other integrated circuit assemblies.

Also prior to bonding, a dielectric layer can be deposited on surface 102, 202 or both On. For example, this may include a layer of hafnium oxide or tantalum nitride. For example, this layer can be formed via plasma enhanced chemical vapor deposition (PECVD). A dielectric layer on either or both of surfaces 102 and 202 can better isolate the circuits formed on substrates 100 and 200 from one another.

The second surfaces 102 and 202 of the two substrates 100 and 200 are then bonded together. Any of a number of joining methods can be used, including but not limited to: bismuth direct or melt bonding, permanent bond bonding (eg, using benzocyclobutene or polyimine), or bonding using intermetallic diffusion or eutectic layers For example, copper, tin or gold. Such bonding techniques can occur in an atmospheric environment or in a vacuum, such as at a temperature of less than 450 degrees Celsius (° C.) or less than 350 ° C or less than 250 ° C, or at room temperature. Some bonding techniques (such as intermetallic diffusion bonding) require relatively high bonding pressures (e.g., 60 kilonewtons); other techniques (e.g., adhesive bonding or fusion bonding) require a small bonding pressure (e.g., less than 5 Newtons). Some bonding methods, such as direct or fusion bonding, may require a surface activation step that renders each surface hydrophilic, allowing for the formation of van der Waals joints. This activation step can include a plasma treatment, a wet chemical treatment, or a combination of these. An annealing step, such as at 400 ° C, may be required to convert the van der Waals bond to a covalent bond. It should be noted that some bonding techniques (such as bonding or intermetallic diffusion bonding) require the use of an intermediate layer (e.g., adhesive or metal) that remains in the assembly (not shown in Figure 2c). After bonding, any tape or rigid handling member used to thin the substrates 100 and 200 is typically removed. For example, this can be accomplished using mechanical, thermal or chemical means, or any combination thereof.

Turning to Figure 2d, the solder bumps 205 are applied to the gold connected to the active layer 203. Is a mat 204. For example, the solder bumps can be composed of lead, tin, copper, germanium, silver, gallium, indium, or some combination thereof. The solder bumps may be 500 microns in diameter, or 100 microns in diameter, or 50 microns in diameter, or 25 microns in diameter, and they may be placed at a pitch of 1 mm, or a pitch of 200 microns, or 100 microns. Distance, or 50 micron pitch. Solder bumps can be made through any of a variety of processes Applied; for example via electroplating, screen printing, evaporation or transfer from a glass mold. The metal pad 204 may have additional metal layers deposited thereon, such as titanium, tin, tungsten, copper, or some combination thereof, prior to attaching the solder bumps. The integrated circuits formed in the active layers 103 and 203 can be electrically tested before the solder bumps 205 are applied.

Figure 2e shows two formed via separate integrated circuit assembly 240 (Figure 2d) The integrated circuit assemblies 250a and 250b are bonded. This separation process can use any of a number of methods to cut bonded wafer pairs, such as mechanical saws, laser cuts, or dry etches. The integrated circuit assembly is separated along scribe lines 108 and 208 (Fig. 2d).

In Figure 2f, the bump assembly 250a is attached to a printed circuit board 206, on which Metal pads 107 and 207 have been formed. These pads may be composed of, for example, copper or aluminum. The assembly 250a is placed such that the solder bumps 205 contact the metal pads 207. The solder bumps are then melted to form an electrical connection between the pads 207 on the printed circuit board 206 and the pads 204 on the active layer 203. For example, this melting can be performed via ultrasonic welding or reflow soldering. For example, the temperature required for this melting can be about 250 ° C, or about 200 ° C, or about 150 ° C. An underfill of the bond assembly 250a can also be performed with a dielectric layer (not shown) interposed between the assembly 250a and the circuit board 206.

The metal of the first active layer 103 to the printed circuit board 206 is also shown in FIG. 2f. The connection of the pads 107. This connection can be accomplished via the use of leads 105. For example, such leads may be composed of aluminum, gold or copper, which may be alloyed with, for example, tantalum or magnesium. To connect the leads 105 to the pads 107 and 104, any of a number of wire bonding processes can be used, including ball or wedge bonding. The leads 105 are soldered to the pads 107 and 104 using heat, supersonic energy, pressure, or some combination thereof.

In Figure 3, an alternative assembly structure is shown. In this structure, the integrated circuit The first active layer 103 of the assembly 250a can be electrically connected to the active layer 103 of the second integrated circuit assembly 250b instead of being connected to the circuit board 206. For example, such a connection can be established by wire bonding pads 104 on assemblies 250a and 250b to each other using leads 109.

In Figures 4a to 4b, another alternative embodiment of an assembled structure is described. A single integrated circuit assembly 250a is shown in FIG. 4a with solder bumps 115 and 205 applied to metal pads 104 and 204, respectively. In Figure 4b, bump assembly 250a is attached to printed circuit boards 206 and 216, on which metal pads 207 and 107 have been formed, respectively. Assembly 250a is placed to weld The bump 205 contacts the metal pad 207, and the solder bump 115 contacts the metal pad 107. The solder bumps are then melted to form an electrical connection between the pads 207 on the printed circuit board 206 and the pads 204 on the active layer 203, and between the pads 107 on the printed circuit board 216 and the pads 104 on the active layer 103. . For example, this melting can be performed via ultrasonic welding or reflow soldering.

In Figures 5a to 5b, another assembly of the structure according to one of the present invention is described. Alternative embodiment. In this embodiment, three integrated circuits are stacked on top of each other and attached to a printed circuit board in such a manner as to provide a circuit to the printed circuit board for all of the circuit elements in each of the three integrated circuits. In FIG. 5a, in addition to the solder bumps 205 applied to the pads 204, solder bumps 115 are applied to some, but not all, of the metal pads 104 of the single integrated circuit assembly 250a. FIG. 5b shows a third substrate 260 having a first surface 261, a second surface 262, and an active layer 263 formed on the first surface 261. A pad 264 is formed in the active layer 263. The third substrate 260 is placed such that the pad 264 contacts the solder bumps 115. Figure 5b also shows a printed circuit board 206 having pads 207 and 107. The assembly 250a is placed such that the solder bumps 205 contact the metal pads 207. The solder bumps are then melted between the pad 207 on the printed circuit board 206 and the pad 204 on the active layer 203, and between the pad 264 on the substrate 260 and some of the pads 104 on the active layer 103. Form an electrical connection. Finally, FIG. 5b also shows one of the leads 105 connecting the other pads 104 to the pads 107 on the printed circuit board 206. In this manner, the circuit elements in the active layer 263 can have circuitry that reaches the printed circuit board 206 through the circuit elements in the active layer 103.

Figure 6 illustrates another embodiment of a method of the present invention in which two integrated bodies are The tracks (one of which is a semiconductor-on-insulator) are bonded back to back and attached to a printed circuit board to electrically connect the two circuits to the circuit board. In the flowchart 400 of FIG. 6, a first substrate, such as a germanium wafer, having a first surface and a second surface is provided in step 410. In step 415, similar to step 1015 in the previous embodiment (FIG. 1), a first effect is formed on the first surface of the first substrate, for example, via using a standard complementary metal oxide semiconductor (CMOS) process. Floor.

In step 420, a semiconductor-on-insulator is provided that includes a handle layer. For example, a semiconductor-on-insulator comprising a handle layer can be composed of a thin tantalum layer and a thick tantalum layer with a thin layer of hafnium disposed therebetween. For example, an active layer is formed in the thin layer using a CMOS process. In step 425, a temporary carrier is bonded to the active semiconductor layer. For example, this can be accomplished by using a wafer coated with one of the decomposable binders. During the next step 430, the temporary carrier provides support for the semiconductor-on-insulator where the supported semiconductor-on-insulator layer is completely or partially removed. If the treatment layer remains sufficiently thick, the joining of the temporary carrier (step 425) may not be necessary. This removal step can include mechanical or chemical polishing. In step 435, the first substrate can be thinned using a similar mechanical or chemical approach. In step 440, the second surface of the first substrate is bonded to the exposed portion of the insulating layer or to the remaining portion of the semiconductor-on-insulator layer. Any wafer bonding method that results in permanent bonding can be used, similar to step 1040 in the previous embodiment (FIG. 1). Again, this step can include an alignment step. In step 445, the temporary carrier supporting the semiconductor on insulator is removed. The resulting integrated circuit assembly can then be raised, separated and attached to a printed circuit board in a manner similar to that described in steps 1045 through 1060 of FIG.

7a to 7f illustrate an exemplary stacked stack fabricated according to the method of FIG. Circuit. In FIG. 7a, a semiconductor-on-insulator 300 is provided that includes an active layer 303 and a handle layer 311 with an insulating layer 310 disposed therebetween. The insulating layer 310 has a surface 302 in contact with the processing layer 311. For example, the processing layer 311 can be a single wafer having a thickness of 500 microns to 900 microns. For example, the insulating layer 310 can be hafnium oxide and can have a thickness of 0.1 micron to 2 microns. For example, the active layer 303 can be a thin layer of germanium in which a transistor (eg, including gate, source, drain, and body regions), isolation regions, contacts, and interconnect layers can be formed. For example, the thickness of the thin layer can be from 0.05 microns to 3 microns. The active layer 303 can form a complete integrated circuit. This active layer can be formed using techniques similar to those described in the previous embodiment (Fig. 2b). Similarly, active layer 303 can include a plurality of integrated circuits separated by scribe lines 308. FIG. 7a also shows the metal bond pad 304 formed in the active layer 303. Furthermore, such metal pads can be made of any metal compatible with solder bumps or wire bonds; for example, copper or aluminum. Forming the bond pad 304 can include forming a passivation layer and a pad opening in the passivation layer.

In FIG. 7b, a temporary carrier 312 is bonded to the active layer 303 of the semiconductor-on-insulator 300. For example, the temporary carrier can be a wafer comprising tantalum, soda lime or borosilicate glass, or sapphire. The temporary carrier may be coated with a bonding adhesive layer (not shown), which may include, for example, an artificial wax, a thermoplastic polymer, or an ultraviolet (UV) curable polymer. For example, the bonding process can include heating the temporary lift and contacting the semiconductor on insulator. For example, a pressure of 1 Newton to 5 Newtons (N/cm ² ) per square centimeter, or 10 N/cm ² to 50 N/cm ² , may be applied during the joining. If a UV curable adhesive is used, the bonding step will involve irradiation with UV light, typically through a transparent temporary carrier.

In Figure 7c, the processing layer 311 is removed. For example, the removal process can include a mechanical or chemical mechanical polishing step, or a purification polishing step or a combination of these. Although not shown in FIG. 7c, a portion of the handle layer 311 may remain on the insulator 310. If sufficient processing layers are left on the insulator 310 such that the semiconductor on insulator is self-supporting (e.g., if a 100 micron processing layer is retained), the above (Fig. 7b) temporary carrier treatment may not be necessary.

Turning to FIG. 7d, the active layer 303 and the insulator 310 supported by the temporary carrier 312 are bonded to the second surface 102 of the substrate 100. The substrate 100 can be a single wafer, or a different semiconductor wafer, such as germanium, or an insulator, such as sapphire. The substrate 100 can be thinned prior to bonding; for example, via one of the methods of attaching to a back grinding tape or a rigid processing member as described above, and then mechanically grinding or chemically treating. Although FIG. 7d illustrates the surface 302 of the insulator 310 bonded to the surface 102 of the substrate 100, some of the remaining processing layers (not shown) may be interposed between the surfaces 302 and 102. The bonding step depicted in Figure 7d can include an alignment step to ensure that the scribe lines 308 and 108 are placed flat on each other. For example, the precision required for this alignment step is one-quarter of the width of the scribe line, or 10 microns, or 20 microns. This is less critical, for example, than the precision required to align a wafer that must be connected by a bonded via. It should be noted that, for example, a transparent temporary carrier 312 (e.g., a glass carrier) may be advantageous for this alignment step.

The joining method used in Figure 7d can be any of the foregoing permanent methods, including but not limited to: 矽 direct or melt bonding, permanent bond bonding, or bonding using intermetallic diffusion or eutectic layers, such as copper, tin or gold. . It should be noted that some bonding techniques (such as bonding or intermetallic diffusion bonding) require the use of an intermediate layer (e.g., adhesive or metal) that remains in the assembly (not shown in Figure 7d).

In Figure 7e, the temporary carrier 512 is removed along with the tape or rigid handling member (if used) used to support the substrate 100 during thinning. For example, this can be accomplished using mechanical, thermal or chemical means, or any combination thereof. The result is a bonded integrated circuit assembly 340.

The assembly 340 is then subjected to the phase synchronization discussed in the description of Figures 2d through 2f above. Steps (not shown): testing, soldering bumps, separating, and soldering and wire bonding individual assemblies to a printed circuit board. 3f shows the final result: the integrated circuit assembly 350a is attached to the printed circuit board 206 having bond pads 107 and 207, wherein the pads 304 of the integrated circuit assembly 350a are connected to the circuit board pads 207 via solder bumps 205, The pad 104 of the integrated circuit assembly 350a is connected to the circuit board pad 107 via leads 105.

Although the specification has been described in detail with reference to the specific embodiments of the present invention, it will be understood that These and other modifications and variations of the present invention can be carried out by the skilled artisan without departing from the spirit and scope of the invention. In addition, those skilled in the art will understand that the foregoing description is by way of example only and is not intended to limit the invention. Accordingly, it is intended that the subject matter of the invention be construed as

104‧‧‧Metal joint pad

105‧‧‧Lead

107‧‧‧Metal pad

204‧‧‧Metal pad

205‧‧‧welding bumps

206‧‧‧Printed circuit board

207‧‧‧Metal pad

250a‧‧‧ integrated circuit assembly

Claims (26)

An integrated circuit assembly, comprising: a first substrate having a first surface and a second surface, a first active layer formed on the first surface of the first substrate, the first The active layer includes a first metal bond pad; a second substrate having a first surface and a second surface, the second surface of the first substrate being coupled to the second surface of the second substrate, and a second active layer formed on the first surface of the second substrate, the second active layer comprising a second metal bond pad. The assembly of claim 1 wherein the thickness of the second substrate is less than 30 microns. The assembly of claim 1, wherein the thickness of the second substrate is less than 10 microns. The assembly of claim 1, wherein the thickness of the first substrate and the second substrate are each less than or equal to 100 micrometers. The assembly of claim 1, wherein the first active layer or the second active layer comprises a passive device. The assembly of claim 1, further comprising: a printed circuit board electrically connected to the first active layer and the second active layer. The assembly of claim 6 wherein the printed circuit board is electrically connected to the first active layer by a solder bump. The assembly of claim 6 wherein the printed circuit board is electrically connected to the second active layer via a wire bond. The assembly of claim 1, further comprising an insulating layer interposed between the second surface of the first substrate and the second surface of the second substrate. The assembly of claim 1, wherein the second substrate is insulated. A method of manufacturing an integrated circuit assembly, the method comprising: providing a first substrate having a first surface and a second surface; forming a first active layer on the first surface of the first substrate; Providing a second substrate having a first surface and a second surface, wherein the second substrate comprises a second active layer formed on the first surface of the second substrate; The second surface of the second substrate is coupled to the second surface of the first substrate. The method of claim 11, wherein the step of providing a second substrate comprises: providing a semiconductor-on-insulator comprising an insulating layer between the active semiconductor layer and a processing layer, and removing the processing layer At least part of it. The method of claim 12, wherein the treatment layer is completely removed. The method of claim 12, further comprising: bonding a temporary carrier to the active semiconductor layer of the semiconductor-on-insulator prior to the step of removing at least a portion of the handle layer; and applying the second substrate After the step of coupling the second surface to the second surface of the first substrate, the temporary carrier is removed. The method of claim 11, further comprising forming a metal bond pad on the first active layer. The method of claim 11, further comprising forming a metal bond pad on the second active layer. The method of claim 11, further comprising thinning the first substrate prior to coupling the second surface of the second substrate to the second surface of the first substrate. The method of claim 11, wherein the first substrate is a semiconductor wafer. The method of claim 18, wherein the step of forming a first active layer on the first surface of the first substrate comprises forming a complementary metal oxide semiconductor circuit. The method of claim 11, wherein the first active layer or the second active layer comprises a passive device. The method of claim 11, further comprising: separating the integrated circuit assembly into individual integrated circuit chips. The method of claim 11, further comprising: electrically connecting a printed circuit board to the first active layer and the second active layer. The method of claim 22, wherein the step of electrically connecting a printed circuit board to the first active layer and the second active layer comprises: forming a first metal bond pad on the first active layer; Forming a second metal bonding pad on the second active layer; Forming a solder bump on the first metal bond pad on the first active layer; attaching the solder bump to a third metal pad on the printed circuit board, and the The second metal bond pad is wire bonded to a fourth metal pad on the printed circuit board. The method of claim 11, wherein the step of coupling the second surface of the second substrate to the second surface of the first substrate comprises: applying an adhesive layer to the second surface of the first substrate And contacting the second surface of the second substrate with the adhesive layer. The method of claim 11, wherein the step of coupling the second surface of the second substrate to the second surface of the first substrate comprises fusion bonding. The method of claim 11, wherein the step of coupling the second surface of the second substrate to the second surface of the first substrate comprises aligning the second substrate with the first substrate to not less than 5 Micron precision.