TW201421754A - Package of optoelectronic device - Google Patents

Abstract

A package of optoelectronic device including a transparent optical substrate, a semiconductor optoelectronic chip, a first patterned conductive layer, a second patterned conductive layer and a dielectric material is provided. The transparent optical substrate has a first surface, a second surface, an accommodating space and a conductive via. The accommodating space extends from the first surface towards the second surface, and the first conductive via extends from the first surface to the second surface. The semiconductor optoelectronic chip is disposed in the accommodating space and has a plurality of terminals. The first patterned conductive layer and the second patterned conductive layer are disposed over the first surface and the second surface respectively. The first patterned conductive layer is electrically connected to the second patterned conductive layer through the first conductive via, and the terminals are electrically connected to the first patterned conductive layer and the second patterned conductive layer.

Description

Photoelectric device package

The present disclosure relates to a semiconductor package, and more particularly to a package of optoelectronic device.

Since the light-emitting diode has the advantages of long life, fast reaction speed, small volume, low power consumption, low pollution, high reliability, and suitable mass production, the light-emitting diode can be applied in a wide range of fields, such as large billboards. Traffic lights, mobile phones, scanners, fax machine light sources and lighting devices. Regardless of the field of application, the LEDs must be properly packaged before they can be used. In general, a light-emitting diode package must take into account both heat dissipation characteristics and optical performance.

In order to effectively improve the heat dissipation performance of the LED package, the conventional technology uses a package substrate with high thermal conductivity, such as a metal core printed circuit board, a ceramic (alumina) substrate, a germanium substrate, etc., to carry the light emitting diode chip. . Although the above-mentioned package substrate can provide good heat dissipation performance of the LED chip, these package substrates only have the functions of carrying the LED chip and providing electrical connection, and the optical performance of the LED package itself is not helpful. .

The present disclosure provides a photovoltaic device package using a transparent substrate The optoelectronic component is packaged for the carrier.

The present disclosure provides a photovoltaic device package including a transparent substrate, a photovoltaic element, a first patterned conductive layer, a second patterned conductive layer, and a dielectric material. The transparent substrate has a first surface and a second surface, and the transparent substrate includes a recess and at least one first conductive via, wherein the recess includes a bottom surface, and the first conductive via extends from the first surface to the first surface Two surfaces. The photovoltaic element is disposed in the recess, and the optoelectronic component has a plurality of conductive terminals. The first patterned conductive layer is disposed on the first surface, and the first patterned conductive layer is electrically connected to the conductive terminal. The second patterned conductive layer is disposed on the second surface, wherein the second patterned conductive layer is electrically connected to the first patterned conductive layer through the first conductive via. In addition, a dielectric material is filled into the recess to encapsulate the photovoltaic element.

The above and other objects and features of the present invention will become more apparent from the following description.

[First Embodiment]

1 is a schematic cross-sectional view showing a photovoltaic element package of a first embodiment of the present application. Referring to FIG. 1 , the photovoltaic device package 100 of the present embodiment includes a transparent substrate 110 , a photovoltaic element 120 , a first patterned conductive layer 130 , a second patterned conductive layer 140 , and a dielectric material 150 . The transparent substrate 110 has a first surface 110a, a second surface 110b, and a recess 112 in the transparent substrate 110, and the transparent substrate 110 includes one or more first conductive vias 114, wherein the recess 112 is oriented from the first surface 110a Second surface The 110b extends and the first conductive via 114 extends from the first surface 110a to the second surface 110b. The optoelectronic component 120 is disposed within the recess 112 and the optoelectronic component 120 has a plurality of conductive terminals 122. The first patterned conductive layer 130 is disposed on the first surface 110a, and the second patterned conductive layer 140 is disposed on the second surface 110b, wherein the first patterned conductive layer 130 passes through the first conductive via 114 and the second pattern The conductive layer 140 is electrically connected, and the conductive terminal 122 is electrically connected to the first patterned conductive layer 130 and the second patterned conductive layer 140. In addition, a dielectric material 150 is filled into the recess 112 to encapsulate the optoelectronic component 120. In the present embodiment, the transparent substrate 110 is, for example, a glass substrate, a sapphire substrate, or other optical substrate having light transmissivity.

As shown in FIG. 1, the groove 112 of the present embodiment has a bottom surface 112a, and the depth d1 of the groove 112 is smaller than the shortest distance d2 between the first surface 110a and the second surface 110b. For example, the depth d1 is about 50% to 80% of the shortest distance d2. It should be noted that the side wall 112b of the groove 112 may be a vertical surface perpendicular to the bottom surface 112a, or may be an inclined surface having an acute or obtuse angle with the bottom surface 112a. In addition, the angle between the side wall 112b and the bottom surface 112a can be appropriately changed depending on the optical design of the photovoltaic element package 100.

When the photo-electric component 120 is a LED chip, and the optoelectronic device package 100 is designed to emit light upward, the angle between the sidewall 112b and the bottom surface 112a can be designed to be an acute angle, so that the sidewall 112b can be used for the photo-electric component 120. The emitted lateral light is reflected upward; when the photovoltaic element 120 is a light-emitting diode wafer, and the photovoltaic device package 100 is designed to emit light downward, the angle between the sidewall 112b and the bottom surface 112a can be designed as an obtuse angle to The side wall 112b is configured to reflect the lateral light emitted by the photovoltaic element 120 downward; when the photovoltaic element 120 is a photo-sensing chip, and the photovoltaic element package 100 is adapted to receive light from above, The angle between the sidewall 112b and the bottom surface 112a can be designed to be an acute angle so that the light from the upper side of the sidewall 112b can be reflected to the photovoltaic element 120 and absorbed by the photovoltaic element 120. When the photo-electric component 120 is a photo-sensing wafer, and the optoelectronic component package 100 is adapted to receive light from below, the angle between the sidewall 112b and the bottom surface 112a can be designed to be an acute angle so that the sidewall 112b can be reflected from the light below. The photovoltaic element 120 is further absorbed by the photovoltaic element 120.

In addition, in order to increase the ability of the sidewall 112b to reflect light, the embodiment may selectively form a reflective coating or a reflective sheet on the sidewall 112b.

As shown in FIG. 1, the height of the first conductive via 114 is substantially the same as the shortest distance d2 of the first surface 110a and the second surface 110b. In the embodiment, the first conductive vias 114 are solid conductive posts penetrating the transparent substrate 110. In another embodiment, the first conductive vias 114 are hollow conductive posts extending through the transparent substrate 110, such as the photovoltaic device package 100a shown in FIG.

As shown in FIG. 1, a plurality of conductive terminals 122 of the photovoltaic element 120 are distributed over a single surface thereof. In order to enable the conductive terminal 122 of the photovoltaic element 120 to be electrically connected to the second patterned conductive layer 140, the transparent substrate 110 of the embodiment has a plurality of second conductive vias 116, wherein the second conductive vias 116 correspond to the conductive terminals. 122 distribution, and each of the second conductive vias 116 The bottom surface 112a extends from the bottom surface 112a to the second surface 110b, so that the respective conductive terminals 122 are electrically connected to the second patterned conductive layer 140 on the second surface 110b through the corresponding second conductive vias 116, respectively. Further, the height of the second conductive via 116 is substantially the same as the shortest distance d3 between the bottom surface 112a and the second surface 110b. In the present embodiment, the shortest distance d3 is about 50% to 80% of the shortest distance d2.

In this embodiment, the materials of the first patterned conductive layer 130 and the second patterned conductive layer 140 are both metal, and the materials of the first patterned conductive layer 130 and the second patterned conductive layer 140 are the same as the first The conductive vias 114 are made of the same or different materials. In addition, since the conductive terminal 122 is electrically connected to the first patterned conductive layer 130, the second patterned conductive layer 140, and the first conductive via 114, the electrical signal to be input to the conductive terminal 122 can directly pass through the second patterning. The conductive layer 140 is provided or provided through the first patterned conductive layer 130, the first conductive vias 114, and the second patterned conductive layer 140.

In the present embodiment, the dielectric material 150 is, for example, a transparent dielectric material, and the dielectric material 150 is mainly used to fix the photovoltaic element 120 in the recess 112.

It is to be noted that since the transparent substrate 110 is designed with the recess 112, the photovoltaic device package 100 of the present embodiment does not need to further provide a lens portion on the transparent substrate 110. Of course, in order to further optimize the optical performance of the photovoltaic device package 100, the present embodiment can still provide an appropriate lens portion on the transparent substrate 110.

As shown in FIG. 1, the photovoltaic device package 100 of the present embodiment can be further The step includes a phosphor layer 160 disposed in the recess 112, wherein the phosphor layer 160 is disposed on the bottom surface 112a, and the phosphor layer 160 is disposed between the photovoltaic element 120 and the bottom surface 112a. In the present embodiment, the photo-electric element 120 is, for example, a blue light-emitting diode wafer, and the phosphor layer 160 is, for example, a yellow phosphor layer. In other embodiments, the photovoltaic element 120 is, for example, an ultraviolet light emitting diode wafer, and the phosphor layer 160 is, for example, a red, green, and/or blue phosphor layer.

It should be noted that although the phosphor layer 160 in FIG. 1 is distributed between the photovoltaic element 120 and the bottom surface 112a, the present embodiment does not limit the distribution position of the phosphor material. In a possible embodiment, the phosphor material (first phosphor material) may be distributed on the second surface 110b of the transparent substrate 110 and above the photovoltaic element 120. In other embodiments, the phosphor material (second phosphor material) may be distributed among the dielectric material 150.

The fabrication flow of the photovoltaic device package of the present embodiment will be described below with reference to FIGS. 3A to 3F.

3A to 3F are schematic views showing a manufacturing process of the photovoltaic device package of the first embodiment. Referring to FIG. 3A, first, a transparent substrate 110 is provided. The transparent substrate 110 has a first surface 110a, a second surface 110b, and a recess 112 in the transparent substrate 110. The recess 112 is from the first surface 110a toward the second surface. The surface 110b extends. In the present embodiment, the groove 112 is formed by, for example, laser processing, machining, or etching. Here, the groove 112 has a bottom surface 112a and a side wall 112b. The side wall 112b of the groove 112 may be a vertical surface perpendicular to the bottom surface 112a, or may be an inclined surface having an acute or obtuse angle with the bottom surface 112a. The angle between the sidewall 112b and the bottom surface 112a can be regarded as the optical design of the photovoltaic device package 100. And make appropriate changes.

Referring to FIG. 3B, a phosphor layer 160 is applied on the bottom surface 112a of the recess 112. The phosphor layer 160 is, for example, a yellow phosphor layer, a red phosphor layer, a green phosphor layer, and/or a blue phosphor layer. . In other embodiments, the coating of the phosphor layer 160 is a step that can be omitted.

Referring next to Figure 3C, a photovoltaic element 120 is provided having a plurality of conductive terminals 122 distributed over a single surface thereof. Next, the photovoltaic element 120 is disposed on the bottom surface 112a of the recess 112 such that the phosphor layer 160 is positioned between the photovoltaic element 120 and the bottom surface 112a, and the conductive terminal 122 is in contact with the bottom surface 112a of the recess 112. Thereafter, dielectric material 150 is filled into recess 112 to encapsulate photovoltaic element 120 to secure photovoltaic element 120 in recess 112.

Referring to FIG. 3D, the transparent substrate 110 carrying the photovoltaic element 120 is inverted, and a plurality of second conductive vias 116 are formed in the transparent substrate 110. The second conductive vias 116 are distributed corresponding to the conductive terminals 122, and each The second conductive vias 116 extend from the bottom surface 112a to the second surface 110b to be electrically connected to the corresponding conductive terminals 122, respectively.

Next, referring to FIG. 3E, one or more through holes TGV are formed in the transparent substrate 110, wherein the through holes TGV extend from the first surface 110a to the second surface 110b. In the present embodiment, the through hole TGV is formed by, for example, laser processing, machining, or etching.

Referring to FIG. 3F, the first conductive via 114, the first patterned conductive layer 130 and the second patterned conductive layer are formed through electroplating (or other conductor deposition processes) and a lithography process (or other patterning process). 140, wherein the first conductive via 114 is located in the through hole TGV, the first patterned conductive layer 130 is located on the first surface 110a, and the second patterned conductive layer 140 is located on the second surface 110b. As shown in FIG. 3F , the conductive terminals 122 are electrically connected to the first patterned conductive layer 130 through the corresponding second conductive vias 116 , the second patterned conductive layer 140 , and the corresponding first conductive vias 114 .

[Second embodiment]

4 is a cross-sectional view showing a photovoltaic element package of a second embodiment of the present application. Referring to FIG. 1 and FIG. 4 simultaneously, the photovoltaic device package 100' of the present embodiment is similar to the photovoltaic device package 100 of the first embodiment, but the main difference between the two is that the transparent substrate 110' of the embodiment is The groove 112' extends further to the second surface 110b to form a receiving through hole, and the depth of the receiving through hole 112' is substantially the same as the shortest distance d2 of the first surface 110a and the second surface 110b.

In addition to the above differences, the photovoltaic device package 100' of the present embodiment may further include a dielectric layer 170 between the transparent substrate 110' and the second patterned conductive layer 140, wherein the dielectric layer The 170 has a plurality of third conductive vias 172 , and the conductive terminals 122 are electrically connected to the second patterned conductive layer 140 through the third conductive vias 172 . Furthermore, the photovoltaic device package 100' of the present embodiment may further include a lens portion 180, wherein the lens portion 180 covers the second surface 110b of the transparent substrate 110', the second patterned conductive layer 140, and the photovoltaic element 120.

Similar to the first embodiment, the side wall 112b' of the receiving through hole 112' can be It is a vertical plane perpendicular to the first surface 110a, and may also be an inclined surface having an acute or obtuse angle with the first surface 110a. Further, the angle between the side wall 112b' and the first surface 110a can be appropriately changed depending on the optical design of the photovoltaic element package 100'.

In addition, the first conductive via 114 may be a solid conductive pillar penetrating through the transparent substrate 110 (as shown in FIG. 4 ) or a hollow conductive pillar penetrating through the transparent substrate 110 (the photovoltaic device package 100 a as shown in FIG. 5 ) ').

The fabrication flow of the photovoltaic device package of the present embodiment will be described below with reference to FIGS. 6A to 6F.

6A to 6G are schematic views showing the manufacturing process of the photovoltaic device package of the second embodiment. Referring to FIG. 6A, first, a transparent substrate 110' having a first surface 110a, a second surface 110b, and a receiving through hole 112' in the transparent substrate 110 is provided. In the present embodiment, the receiving through hole 112' is formed by, for example, laser processing, machining, or etching. Here, the receiving through hole 112' has a side wall 112b', wherein the side wall 112b' of the receiving through hole 112' may be a vertical surface perpendicular to the bottom surface 112a, or may be an inclined surface having an acute or obtuse angle with the first surface 110a. The angle between the side wall 112b' and the first surface 110a can be appropriately changed depending on the optical design of the photovoltaic element package 100'.

Next, the transparent substrate 110' having the through-holes 112' is disposed on a carrier C, wherein the second surface 110b of the transparent substrate 110' is in contact with the carrier C. In this embodiment, the carrier C is, for example, a substrate, a release film or other suitable carrier.

Referring next to FIG. 6B, a photovoltaic element 120 is provided. The photovoltaic element 120 The plurality of conductive terminals 122 are distributed over a single surface thereof. Next, the photovoltaic element 120 is placed in the receiving through hole 112' so that the photovoltaic element 120 is carried by the carrier C. Then, a dielectric material 150 is filled into the receiving through hole 112' to cover the photovoltaic element 120 to fix the photovoltaic element 120 in the receiving through hole 112'. In the present embodiment, the filling of the dielectric material 150 is based on the principle of not covering the conductive terminals 122. Thereafter, the carrier C is removed to expose the second surface 110b of the transparent substrate 110'.

Referring to FIG. 6C and FIG. 6D, a dielectric layer 170 is formed on the first surface 110a' of the transparent substrate 110', and a plurality of third conductive vias 172 are formed in the dielectric layer 170, wherein the conductive terminals 122 are Corresponding third conductive vias 172 are electrically connected.

Next, referring to FIG. 6E, one or more through holes TGV are formed in the transparent substrate 110, wherein the through holes TGV extend from the first surface 110a to the second surface 110b. In the present embodiment, the through hole TGV is formed by, for example, laser processing, machining, or etching.

Referring to FIG. 6F, the first conductive via 114, the first patterned conductive layer 130 and the second patterned conductive layer are formed through electroplating (or other conductor deposition processes) and a lithography process (or other patterning process). 140, wherein the first conductive via 114 is located in the through hole TGV, the first patterned conductive layer 130 is located on the first surface 110a, and the second patterned conductive layer 140 is located on the second surface 110b. As shown in FIG. 6F , the conductive terminals 122 are electrically connected to the first patterned conductive layer 130 through the corresponding second conductive vias 116 , the second patterned conductive layer 140 , and the corresponding first conductive vias 114 .

Referring to FIG. 6G, a lens portion 180 is formed on the second surface 110b of the transparent substrate 110' such that the lens portion 180 covers the dielectric layer 170, the second patterned conductive layer 140, and the photovoltaic element 120.

[Third embodiment]

Figure 7 is a cross-sectional view showing a photovoltaic element package of a third embodiment of the present application. Referring to FIG. 7, the photovoltaic device package 200 of the present embodiment is similar to the photovoltaic device package 100' of the second embodiment, but the main difference is that the photovoltaic device 220 in the photovoltaic device package 200 has multiple The conductive terminals 222a, 222b, and the conductive terminals 222a, 222b are respectively located on the opposite surfaces of the photovoltaic element 220, wherein the conductive terminal 222a is electrically connected to the second patterned conductive layer 140 through the third conductive via 172, and the conductive terminal 222b For example, it is electrically connected to the first patterned conductive layer 130.

Fourth Embodiment

Figure 8 is a cross-sectional view showing a photovoltaic element package of a fourth embodiment of the present application. Referring to FIG. 8, the photovoltaic device package 300 of the present embodiment is similar to the photovoltaic device package 100' of the second embodiment, but the main difference is that the photovoltaic device 320 in the photovoltaic device package 300 has a plurality of The conductive terminals 322a, 322b, and the conductive terminals 222a, 222b are respectively located on a single surface of the photovoltaic element 220, wherein the conductive terminal 322a and the conductive terminal 322b are electrically connected to the first patterned conductive layer 130. In this embodiment, the conductive terminals 322a and the conductive terminals 322b are, for example, conductive bumps.

In addition, the photovoltaic device package 300 of the present embodiment may further include a phosphor material 190, wherein the phosphor material 190 is distributed on the surface of the dielectric layer 170. However, the present embodiment does not limit the distribution position of the fluorescent material, and the fluorescent material may be distributed in the dielectric material 150 or the lens portion 180.

[Fifth Embodiment]

Figure 9 is a cross-sectional view showing a photovoltaic element package of a fifth embodiment of the present application. Referring to FIG. 9 , the photovoltaic device package 400 of the present embodiment is similar to the photovoltaic device package 200 of the third embodiment, but the main difference between the two is that the photovoltaic device package 400 further includes a recess 112. The heat sink block HS is disposed on the heat sink block HS. In this embodiment, the photovoltaic element 220 is adhered to the heat sink block HS through the thermal conductive adhesive AD, for example. For example, the aforementioned thermal conductive adhesive AD is, for example, a silver paste having good electrical and thermal conductivity properties.

[Sixth embodiment]

Figure 10 is a cross-sectional view showing a photovoltaic element package of a sixth embodiment of the present application. Referring to FIG. 10, the photovoltaic device package 500 of the present embodiment is similar to the photovoltaic device package 100' of the second embodiment, but the main difference between the two is that the photovoltaic device package 500 further includes a recess disposed in the recess. The heat sink block HS in the 112, wherein the photovoltaic element 120 is disposed on the heat sink block HS. In this embodiment, the photovoltaic element 120 is adhered to the heat sink block HS through the thermal conductive adhesive AD, for example. For example, the aforementioned thermal conductive adhesive AD is, for example, silver paste or other adhesive material having good thermal conductivity.

Based on the above, since the photovoltaic device package of the present invention encapsulates the photovoltaic element using the transparent substrate as a carrier, the photovoltaic device package of the present disclosure can have good reliability and heat dissipation characteristics.

The present disclosure has been disclosed in the above embodiments, and is not intended to limit the scope of the disclosure, and the present disclosure may be modified and modified without departing from the spirit and scope of the disclosure. The scope of protection is subject to the definition of the scope of the patent application.

100, 100a, 100', 100a', 200‧‧‧ photoelectric component package

110, 110'‧‧‧ Transparent substrate

110a‧‧‧ first surface

110b‧‧‧ second surface

112‧‧‧ Groove

112’‧‧‧ accommodated through holes

112a‧‧‧ bottom

112b, 112b’‧‧‧ side wall

114‧‧‧First conductive via

116‧‧‧Second conductive via

120, 220‧‧‧Optoelectronic components

122, 222a, 222b‧‧‧ conductive terminals

130‧‧‧First patterned conductive layer

140‧‧‧Second patterned conductive layer

150‧‧‧ dielectric materials

160‧‧‧Fluorescent layer

170‧‧‧ dielectric layer

172‧‧‧ Third conductive via

180‧‧‧Lens Department

190‧‧‧Fluorescent materials

D1‧‧ depth

D2, d3‧‧‧ distance

TGV‧‧‧through hole

C‧‧‧ Carrier

HS‧‧‧Heat block

AD‧‧‧thermal adhesive

1 is a schematic cross-sectional view showing a photovoltaic element package of a first embodiment of the present application.

2 is a cross-sectional view showing another photovoltaic element package of the first embodiment of the present application.

3A to 3F are schematic views showing a manufacturing process of the photovoltaic device package of the first embodiment.

4 is a cross-sectional view showing a photovoltaic element package of a second embodiment of the present application.

FIG. 5 is a cross-sectional view showing another photovoltaic element package according to a second embodiment of the present application.

6A to 6G are schematic views showing the manufacturing process of the photovoltaic device package of the second embodiment.

Figure 7 is a cross-sectional view showing a photovoltaic element package of a third embodiment of the present application.

Figure 8 is a cross-sectional view showing a photovoltaic element package of a fourth embodiment of the present application.

Figure 9 is a cross-sectional view showing a photovoltaic element package of a fifth embodiment of the present application.

Figure 10 is a cross-sectional view showing a photovoltaic element package of a sixth embodiment of the present application.

100‧‧‧Photoelectric component package

110‧‧‧Transparent substrate

110a‧‧‧ first surface

110b‧‧‧ second surface

112‧‧‧ Groove

112a‧‧‧ bottom

112b‧‧‧ Sidewall

114‧‧‧First conductive via

116‧‧‧Second conductive via

120‧‧‧Optoelectronic components

122‧‧‧Electrical terminals

130‧‧‧First patterned conductive layer

140‧‧‧Second patterned conductive layer

150‧‧‧ dielectric materials

160‧‧‧Fluorescent layer

D1‧‧ depth

D2, d3‧‧‧ distance

Claims (11)

A photovoltaic device package comprising: a transparent substrate having a first surface and a second surface, wherein the first surface has a recess, the transparent substrate comprising: at least one first conductive via, from the first a surface extending to the second surface; a photovoltaic element disposed in the recess, the photovoltaic element having a plurality of conductive terminals; a first patterned conductive layer disposed on the first surface, the first pattern The conductive layer is electrically connected to the conductive terminals; a second patterned conductive layer is disposed on the second surface, and the second patterned conductive layer is electrically connected to the first through the first conductive via A patterned conductive layer; and a dielectric material positioned in the recess to encapsulate the photovoltaic element. The photovoltaic device package according to claim 1, wherein the transparent substrate is a glass substrate or a sapphire substrate. The photovoltaic device package of claim 1, wherein the transparent substrate further comprises a phosphor layer disposed on a bottom surface of the recess. The photovoltaic device package of claim 1, wherein the transparent substrate has a plurality of second conductive vias extending from the bottom surface to the second surface, and at least a portion thereof The conductive terminals are electrically connected to the second patterned conductive layer through the second conductive vias. The photovoltaic device package according to claim 1, wherein The recess extends further through the second surface to form a receiving through hole, and the dielectric material is located in the receiving through hole to cover and fix the photovoltaic element. The photovoltaic device package of claim 5, further comprising a dielectric layer between the transparent substrate and the second patterned conductive layer, the dielectric layer having a plurality of third conductive vias, And at least a portion of the conductive terminals are electrically connected to the second patterned conductive layer through the third conductive vias. The photovoltaic device package of claim 6, further comprising a first phosphor material, wherein the first phosphor material is distributed on a surface of the dielectric layer. The photovoltaic element package of claim 1, wherein the photovoltaic element comprises a light emitting diode chip or a light sensing wafer. The photovoltaic device package of claim 1, further comprising a second phosphor material, wherein the second phosphor material is distributed in the dielectric material. The photovoltaic device package of claim 1, further comprising a lens portion, wherein the lens portion covers the second surface of the transparent substrate, the second patterned conductive layer, and the photovoltaic element. The photovoltaic device package of claim 1, further comprising a heat dissipating block, wherein the heat dissipating block is disposed in the recess, and the photo component is disposed on the heat dissipating block.