TWI720972B - Chip package structure and method of manufacturing the same - Google Patents

Abstract

A chip package structure and method of manufacturing the same.  A chip package includes a substrate with a mounting surface, a chip having a first surface and a second surface positioned oppositely and a side surface connecting the first surface and the second surface, an encapsulation layer and a fluorescent layer.  The second surface of the chip is disposed on the mounting surface of the substrate.  The fluorescent layer fully covers the first surface of the chip. The encapsulation layer covers the mounting surface of the substrate and the side surface of the chip, wherein the encapsulation layer has a high reflectivity of 90% at least.

Description

Chip packaging structure and manufacturing method thereof

The present invention relates to a chip package structure and a manufacturing method thereof, and more particularly to a light emitting diode chip package structure and a manufacturing method thereof with improved light conversion and extraction efficiency.

Energy-saving and environmentally friendly light-emitting diodes are widely used, except for products that can be seen everywhere in daily life, which may be equipped with light-emitting diodes, such as general lighting, computer or portable electronic product screen displays, signage, artwork and applications, etc. .

Generally speaking, the traditional light-emitting diode chip packaging structure is to arrange the light-emitting diode chip on a concave cup-shaped carrier base formed of ceramic or metal material, and then package the light-emitting diode chip with a colloid. To form a package structure. At this time, the electrode of the light-emitting diode chip is located above the supporting base and in the concave cup. However, the concave-cup type supporting base has a certain shape and thickness, and the thickness of the light-emitting diode chip packaging structure cannot be effectively reduced. Furthermore, in response to the needs of many different applications, such as the emission of light to achieve different color temperatures, it is necessary to use different concave cup-shaped supporting bases, such as varying base thicknesses, to meet the needs of the application. So traditional light-emitting diodes The application flexibility of the chip package structure is very small.

The present invention provides a chip package structure and a manufacturing method thereof, which can improve the optical properties of the chip package structure, for example, can improve the efficiency of light conversion and extraction.

The chip package structure of the present invention includes a substrate having a bearing surface, a chip having a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface, a colloid layer, and a chip Fluorescent layer. The second surface of the chip is arranged on the carrying surface of the substrate. The fluorescent layer completely covers the first surface of the chip. The colloid layer covers the bearing surface of the substrate and the side surface of the chip, wherein the reflectivity of the colloid layer is at least greater than 90%.

The manufacturing method of the chip package structure of the present invention includes providing a substrate, and separately arranging a plurality of chips on a supporting surface of the substrate, wherein each of the chips has a first surface and a second surface opposite to each other and a connection to the first surface. Surface and the side surface of the second surface, and the second surfaces are arranged on the carrying surface of the substrate; forming a fluorescent layer to completely cover the first surface of the chip; forming a colloid layer to cover the carrying surface of the substrate And the side surface of the chip, wherein the reflectivity of the colloid layer is at least greater than 90%; and cutting the colloid layer and the substrate to form a plurality of chip package structures.

Based on the above, the present invention provides a chip packaging structure and a manufacturing method thereof. First, a chip is placed on a substrate and packaged with a colloid layer, and then one surface of the chip is exposed, and then a fluorescent layer is formed on the exposed surface of the chip. The design of the example can improve the optical properties of the chip package structure, for example, can improve the efficiency of light conversion and extraction. in In other embodiments, a light-transmitting layer can also be selectively provided on the fluorescent layer to serve as a light-transmitting protective layer to increase the water vapor transmission path and effectively prevent water vapor from penetrating. Of course, the structure of different light-transmitting layer structures, such as a lens-type light-transmitting layer, can effectively improve the light extraction efficiency.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10, 70, 80: substrate

100a, 100b, 100c, 100d: chip package structure

101, 701, 801: bearing surface

102, 702, 802: bottom surface

103: Edge

111a, 111b: extension electrode

112a, 112b: pad

113a, 113b: pilot hole

75a, 75b, 85a, 85b: heat sink

20: chip

201: First Surface

202: second surface

203: side surface

222a, 222b: electrodes

30, 30a: colloidal materials

31, 34, 35, 36: colloidal layer

311: top surface

313, 314, 315, 316: side edge

40: Mask

401: open

41, 42, 43, 44, 45: Fluorescent layer

44a, 45a: side edges

51, 52, 54: light-transmitting layer

511, 521, 541: upper surface

513, 514: Side edge

515: Extension

515a: side edge

C: Depressed

L1: Side length of the fluorescent layer

Lm: side length of colloid layer

Lc: side length of the chip

d1: first spacing

d2: second spacing

M: Mo Ren

1A to 1D are schematic diagrams illustrating the manufacturing method of a chip package structure according to the first embodiment of the disclosure.

2A to 2E illustrate the manufacturing method of the multiple chip package structure according to the first embodiment of the disclosure.

FIG. 3 is a schematic diagram showing a chip package structure of the second embodiment of the disclosure.

4 is a schematic diagram showing a chip package structure of the third embodiment of the disclosure.

FIG. 5 is a schematic diagram showing a chip package structure of the fourth embodiment of the disclosure.

FIG. 6 is a schematic diagram showing a chip package structure of the fifth embodiment of the disclosure.

7A to 7C are schematic diagrams of one of the in-line light source layouts using the chip package structure of the embodiment on the substrate.

8A to 8C are schematic diagrams of a matrix light source layout in which the chip package structure of the embodiment is applied to the substrate.

9A to 9C illustrate the manufacturing method of the chip package structure of the sixth embodiment of the disclosure Schematic diagram of the partial steps of the method.

10A to 10C are schematic diagrams showing partial steps of the manufacturing method of the chip package structure of the seventh embodiment of the disclosure.

11A to 11E are schematic diagrams showing partial steps of the manufacturing method of the chip package structure of the eighth embodiment of the disclosure.

12A to 12D are schematic diagrams showing partial steps of the manufacturing method of the chip package structure of the ninth embodiment of the disclosure.

The embodiment of the disclosure proposes a chip packaging structure and a manufacturing method thereof, which can improve the efficiency of light conversion and extraction. The following is a detailed description of multiple implementation aspects of the present disclosure with reference to the accompanying drawings. It should be noted that the structure and content proposed in the embodiments are for illustrative purposes only, and the scope to be protected by the present disclosure is not limited to the above-mentioned aspects. In the embodiments, the same or similar reference numerals are used to indicate the same or similar parts. It should be noted that this disclosure does not show all possible embodiments. The structure can be changed and modified without departing from the spirit and scope of this disclosure to meet actual application requirements. Therefore, other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the drawings have been simplified to clearly illustrate the content of the embodiments, and the size ratios on the drawings are not drawn in proportion to the actual product. Therefore, the contents of the description and the illustrations are only used to describe the embodiments, rather than to limit the protection scope of this disclosure.

<First embodiment>

Figures 1A~1D show the fabrication of a chip package structure according to the first embodiment of the disclosure. Schematic diagram of manufacturing method. In FIGS. 1A to 1D, a cross-sectional diagram of a single chip package structure is used to illustrate the manufacturing method to facilitate a clear description of the related details of each component. As shown in FIG. 1A, a substrate 10 is provided, and a chip 20 is placed on the carrying surface 101 of the substrate 10. The chip 20, for example, a light-emitting diode chip, has a first surface 201 and a second surface 202 opposite to each other. The second surface 202 is disposed on the carrying surface 101 of the substrate 10, and the first surface 201 is a part of the chip 20. Glossy surface.

In one embodiment, the chip 20 is a UV light-emitting diode chip with an emission wavelength between 315 nm and 412 nm. In another embodiment, the chip 20 is a blue light emitting diode chip with a light emitting wavelength between 440 nm and 470 nm. However, light-emitting diode chips in other light-emitting wavelength ranges can also be applied, and the present disclosure is not limited to this.

As shown in FIG. 1B, a colloidal material 30 is formed on the supporting surface 101 of the substrate 10 and covers the supporting surface 101 and the chip 20, wherein the reflectance of the colloidal material 30 is at least greater than 90%. In one embodiment, the material of the colloidal material 30 is, for example, a polymer material, such as a white epoxy resin sealant or a silicon resin sealant (epoxy/silicon) (but not limited to this), and its high reflectivity can be The side light is shielded to improve the efficiency of light emitting from the chip 20 in the forward direction.

Then, as shown in FIG. 1C, a portion of the colloidal material 30 is removed to form a colloidal layer 31. A top surface 311 of the colloidal layer 31 exposes the first surface 201 of the chip 20, and the top surface 311 is cut in line with the chip 20. First surface 201. In the embodiment, for example, part of the colloidal material 30 is removed by polishing.

In addition, in one embodiment, in the step of forming the colloidal layer, when a part of the colloidal material 30 is removed by grinding, it touches the first surface of the wafer 20 After the surface 201, the first surface 201 is also polished, so that the top surface 311 of the high-reflectivity colloidal layer 31 is aligned with the first surface 201 of the wafer 20, and the first surface 201 of the wafer 20 (such as sapphire (Transparent surface of sapphire) is a roughened surface with scratches to increase light extraction. In one embodiment, the first surface 201 of the wafer 20 after grinding has a surface roughness Ra greater than 0.01 μm.

In addition, through the support of the substrate 10 with high mechanical strength, when a part of the colloidal material 30 is removed by grinding, in addition to roughening the first surface 201 of the wafer 20, it can also make the transparent substrate of the wafer 20 (ex : The sapphire substrate) is thinner, so that the total reflection path is reduced, thereby increasing the illuminance and strengthening the forward light intensity. Taking a 2-inch wafer as an example, with the manufacturing method proposed in the embodiment, the thickness of the wafer 20 after grinding and thinning can reach about 100 μm. Of course, the thickness of the thinned chip 20 depends on the actual application conditions (ex: wafer size, mechanical strength of the substrate 10, etc.), and it may be less than 100 μm without breaking the chip. This disclosure does not No restrictions.

After the top surface 311 of the colloid layer 31 is aligned with the first surface 201 of the chip 20, a phosphor layer 41 is formed on the top surface 311 of the colloid layer 31, and the phosphor layer 41 at least completely shields the chip 20. The first surface 201, for example, covers the first surface 201 of the wafer 20 but is smaller than the length of one side of the colloidal layer 31. In one embodiment, except for completely covering the first surface 201 of the chip 20, the four side lengths of the phosphor layer 41 are smaller than the four side lengths of the colloidal layer 31, respectively. The fluorescent layer 41 can be formed, for example, by using a mask having a plurality of spaced openings, through which the fluorescent layer 41 is coated, such as spraying. In the actual manufacturing process, after the phosphor layer 41 is formed, a plurality of separate single chip packages can be formed by dicing the colloid layer 31 and the substrate 10 The structure is shown in Figure 1D. In one embodiment, the fluorescent layer 41 is, for example, doped with a plurality of fluorescent particles with a particle size ranging from 3 μm to 50 μm.

Furthermore, according to the embodiment, in addition to the top surface 311 of the colloidal layer 31 being aligned with the first surface 201 of the chip 20, as shown in FIG. 1D, the substrate 10 in the single chip package structure also has two edges 103 and a carrying surface 101 respectively. For connection, the gel layer 31 also has two side edges 313 connected to the top surface 311 respectively. After the colloid layer 31 and the substrate 10 are cut, the two side edges 313 of the colloid layer 31 are aligned with the two edges 103 of the substrate 10.

In addition, it is worth noting that the fluorescent layer 41 can be directly formed on the top surface 311 of the colloidal layer 31 (FIG. 1D), or a light-transmitting layer can be formed first (the light-transmitting material is not limited to the glue). On the top surface 311 of the colloidal layer 31, a fluorescent layer 41 is formed on the light-transmitting layer (as described in the fifth embodiment below). This disclosure is not limited, as long as the fluorescent layer 41 can at least completely cover the chip 20. The first surface 201 is an implementation aspect of this disclosure.

In the single chip package structure of the embodiment, the phosphor layer 41 directly formed on the top surface 311 of the colloidal layer 31 has an area substantially equal to or greater than the area of the chip 20 but smaller than the area of the top surface 311 of the colloidal layer 31. In one embodiment, as shown in FIG. 1D, the side length L1 of the phosphor layer 41 that can completely cover the first surface 201 of the chip 20 is greater than the side length Lc of the chip 20 but less than the side length Lm of the colloidal layer 31. Of course, the present disclosure is not limited to this. In another embodiment, the area of the phosphor layer 41 may be substantially equal to or slightly larger than the area of the chip 20, that is, the side length L1 of the phosphor layer 41 may be substantially equal to or slightly larger than the area of the chip 20. If the upper part is equal to or slightly larger than the side length Lc of the chip 20, the blue/yellow circle phenomenon can be reduced, which is an implementation aspect of the present disclosure.

Since the chip 20 is repeatedly heated and cooled during the packaging process, or the chip 20 is in operation after packaging, thermal stress will be generated at the interface of the various construction material layers with different thermal expansion coefficients, which will cause the construction material layer to deform, Delamination, chipping, and even wafer damage. Therefore, in this embodiment, the substrate 10 used to set the chip 20 (ex: flip-chip type) and the colloid layer 31 covering the substrate 10 in direct contact with the substrate have a higher coefficient of thermal expansion (CTE). The smaller the better, and the smaller the difference in coefficient of thermal expansion between the two, the better, so as to avoid undue damage to the structure caused by thermal stress. In one embodiment, the thermal expansion coefficients of the colloidal layer 31 and the substrate 10 are both less than 15 ppm/°C. In one embodiment, the difference in thermal expansion coefficient between the colloidal layer 31 and the substrate 10 is less than 10 ppm/°C. In one embodiment, the substrate 10 is, for example, a ceramic substrate, which has a low thermal expansion coefficient of about 6 ppm/°C; and the gel layer 31 is, for example, a white epoxy resin sealant or a silicone resin sealant with a low thermal expansion coefficient ( epoxy or silicon), silicone resin encapsulant has a thermal expansion coefficient of about 14ppm/°C. In addition, the ceramic substrate has high flexural strength, can protect the wafer from stress pulling, and has the function of a stress barrier.

Furthermore, the special design of the substrate 10 can reduce the short circuit risk of the chip package structure of the embodiment, and when used as surface-mount devices (SMD), the surface adhesion area can be increased, thereby improving the assembly with external circuits. Time alignment accuracy and assembly efficiency. 1A to 1D, the substrate 10 of the embodiment has a bottom surface 102 opposite to the carrying surface 101, and the substrate 10 includes: a plurality of extending electrodes (extending electrodes) 111a, 111b are separately provided on the carrying surface 101, and a plurality of connections Solder pads 112a and 112b are separately arranged on the bottom surface 102, and a plurality of vias 113a, 113b are vertically formed in the substrate 10, wherein the pads 112a, 112b and the extension electrodes 111a, 111b are electrically connected through the vias 113a, 113b to reach the bottom surface 102 and the carrying surface 101. . For example, the pad 112a and the extension electrode 111a are electrically connected by a via 113a, and the pad 112b and the extension electrode 111b are electrically connected by a via 113b.

The wafer 20 includes a plurality of electrodes 222 a and 222 b disposed on the second surface 202 separately from each other. When the chip 20 is placed on the carrying surface 101 of the substrate 10, the electrodes 222a and 222b of the chip 20 are contacted with the extended electrodes 111a and 111b of the substrate 10, respectively. Wherein, the extension electrodes 111a and 111b can be completely or partially overlapped with the electrodes 222a and 222b of the wafer 20, as long as the extension electrodes 111a and 111b are structurally and electrically connected to the electrodes 222a and 222b of the wafer 20. The effect is the mode in which this disclosure can be implemented.

As shown in FIGS. 1A to 1D, the extension electrodes 111 a and 111 b of the substrate 10 are separated from each other and expose a part of the second surface 202 of the wafer 20. Furthermore, the pads 112 a and 112 b on the bottom surface 102 of the substrate 10 are separated from each other and extend toward the edge 103 of the substrate 10. The design of the extension electrodes 111a, 111b and the pads 112a, 112b of the substrate 10 can enlarge the distance between the electrodes 222a, 222b of the original chip 20 and reduce the risk of short circuit. As shown in FIG. 1C, the two adjacent electrodes 222a, 222b of the chip 20 have a first distance d1, and the two adjacent pads 112a, 112b of the substrate 10 have a second distance d2, and the second distance d2 is greater than the first distance. d1. Furthermore, the area of the extended pad 112a, 112b is larger than the area of the electrode 222a, 222b of the chip 20. When assembling with an external circuit, for example, surface adhesion is performed. The surface of the entire chip package structure is adhered. The area is increased, and the alignment accuracy can be increased and the assembly efficiency can be improved. Especially when the size of the package structure is very small, the design of the embodiment can significantly improve the product yield, electrical performance, and structural strength and stability of the package structure.

In addition, during the coating process of the phosphor layer 41, the ratio of the phosphor to the colloid can be selected in an appropriate ratio range according to different color temperatures to obtain the best light conversion and extraction efficiency. For example, the fluorescent layer corresponding to a higher color temperature has a first thickness, and the corresponding fluorescent layer at a lower color temperature has a second thickness, and the first thickness is smaller than the second thickness (a fluorescent layer with a higher color temperature is less than a lower color temperature). The thickness of the phosphor layer should be thin). In one embodiment, in the color temperature range of 4500K~9000K, the thickness of the phosphor layer 41 is 40μm~100μm, and the phosphor layer 41 includes a polymer colloid and a weight percentage of 40wt%~60wt% of phosphors distributed in high Molecular colloid inside. In one embodiment, in the color temperature range of 2200K~4000K, the thickness of the phosphor layer 41 is 100μm~250μm, and the phosphor layer 41 includes a polymer colloid and a weight percentage of 40wt%~70wt% of phosphors distributed in high Molecular colloid inside. These numerical values are for illustrative purposes only, and are not intended to limit the present invention. Compared with the traditional chip package structure where the chip is arranged on a carrier base of a concave cup type with a certain thickness, the thickness variation of the phosphor layer is also restricted. In the structural design of the embodiment of the present disclosure, the thickness of the phosphor layer 41 can be adjusted and changed according to the different requirements of the desired color temperature to obtain the best light conversion and extraction efficiency. Therefore, the design of the embodiment varies in application Compared with the traditional chip package structure, the above has more flexibility to choose from.

2A to 2E illustrate the manufacturing method of the multiple chip package structure according to the first embodiment of the disclosure. Please refer to the figure for the detailed structure and related description of each construction material layer 1A~1D and the above description, some details will not be repeated here. As shown in FIG. 2A, a substrate 10 is provided, and a plurality of wafers 20 are separately arranged on the supporting surface 101 of the substrate 10, wherein each wafer 20 has a first surface (light emitting surface) 201 and a second surface 202 (with electrodes) opposite to each other. 222a, 222b), and the second surface 202 is disposed on the carrying surface 101 (having extended electrodes 111a, 111b) of the substrate 10. As shown in FIG. 2B, a colloidal material 30 is formed on the supporting surface 101 of the substrate 10 to cover the supporting surface 101 and the chips 20, wherein the reflectance of the colloidal material 30 is at least greater than 90%. Then, as shown in FIG. 2C, for example, a part of the colloidal material 30 is removed by grinding to form a colloidal layer 31. The grinding may further include the steps of roughening the surface (first surface 201) of the wafer 20 and thinning the wafer. After the grinding is completed, the top surface 311 of the colloidal layer 31 exposes the first surface 201 of the wafer 20 and is aligned with the first surface 201 of the 20. As shown in FIG. 2D, a mask 40 is provided above the colloid layer 31, and the mask 40 has a plurality of openings 401 spaced apart corresponding to the positions of the chips 20, wherein the area 401 of the openings is substantially equal to or larger than that of the chip 20 Area: Through the opening 401 of the mask 40, a phosphor layer 41 is coated on the top surface 311 of the colloid layer 31, and the phosphor layer 41 at least completely covers the first surface 201 of the chip 20 but is smaller than a side length of the colloid layer 31. Then, as shown in FIG. 2E, the colloidal layer 31 and the substrate 10 are cut to form a plurality of chip package structures. The area of the phosphor layer 41 of each chip package structure (same as shown in FIG. 1D) is substantially equal to or larger than that of the chip. The area of 20 is smaller than the area of the top surface 311 of the colloidal layer 31. As shown in FIG. 1D, the side length L1 of the phosphor layer 41 that completely covers the chip 20 is greater than the side length Lc of the chip 20 and smaller than the side length Lm of the colloidal layer 31. After the cutting step, the side edges 313 of the colloid layer 31 are aligned with the base. The two edges 103 of the board 10.

The following are the designs of several chip package structures disclosed in this disclosure for illustrative purposes. It should be noted that this disclosure is not limited to the exemplified aspects, and other implementation aspects not mentioned in this disclosure can also be applied without departing from the scope of protection intended by this disclosure. In addition, in the second to fifth embodiments, elements that are the same or similar to those in the first embodiment use the same or similar reference numerals, and the details that have been clearly described above will not be repeated.

<Second Embodiment>

FIG. 3 is a schematic diagram showing a chip package structure of the second embodiment of the disclosure. The difference between the second embodiment and the first embodiment is that a light-transmitting layer 51 is further formed on the chip package structure as shown in FIG. 1D. In the second embodiment, the light-transmitting layer 51 is a flat transparent plastic material. As shown in FIG. 3, the phosphor layer 41 of the second embodiment is directly formed on the top surface 311 of the colloidal layer 31 and at least completely covers the first surface 201 of the chip 20, and the chip package structure further includes a transparent layer 51 formed on the colloid The top surface 311 of the layer 31 is on and completely covers the phosphor layer 41. The thickness of the transparent layer 51 is greater than the thickness of the fluorescent layer 41. Furthermore, in the second embodiment, the light-transmitting layer 51 has two side edges 513 respectively connected to the upper surface 511, and the two side edges 513 of the light-transmitting layer 51, the two side edges 313 of the colloid layer 31, and the two edges of the substrate 10 103 are all aligned.

<Third Embodiment>

4 is a schematic diagram showing a chip package structure of the third embodiment of the disclosure. In the third embodiment, a light-transmitting layer 52 is also formed on the chip package structure as shown in FIG. 1D, but the difference from the second embodiment is that the light-transmitting layer 52 of the third embodiment is It is a lens type transparent plastic material. As shown in FIG. 4, the light-transmitting layer 52 of the third embodiment is formed on the top surface 311 of the colloidal layer 31 and completely covers the fluorescent layer 41, and the upper surface 521 of the light-transmitting layer 52 extends to both sides of the colloidal layer 31边边313.

Either the planar light-transmitting layer 51 (the second embodiment) or the lens-type light-transmitting layer 52 (the third embodiment) can increase the water vapor transmission path and effectively prevent the penetration of water vapor. The lenticular light-transmitting layer 52 (the third embodiment) can increase the light extraction efficiency.

<Fourth Embodiment>

FIG. 5 is a schematic diagram showing a chip package structure of the fourth embodiment of the disclosure. The difference from the first embodiment is that the fluorescent layer 42 of the first embodiment is a planar fluorescent layer, while the fluorescent layer 42 of the fourth embodiment is a lens-type fluorescent layer, which can increase the light extraction efficiency . In one embodiment, the fluorescent layer 42 contains fluorescent particles with a particle size of 3 μm-50 μm.

<Fifth Embodiment>

FIG. 6 is a schematic diagram showing a chip package structure of the fifth embodiment of the disclosure. In the fifth embodiment, a lenticular light-transmitting layer 52 is first formed on the top surface 311 of the colloidal layer 31 and at least completely covering the first surface 201 of the wafer 20, and then a fluorescent layer 43 is coated on the lenticular light-transmitting layer 52 on. The lens-type light-transmitting layer 52 can not only increase the water vapor transmission path, effectively prevent the penetration of water vapor, but also increase the light extraction efficiency.

In addition, in practical applications, the chips 20 of multiple embodiments may be arranged on a substrate to form the chip package structure of the embodiments, and there may be many different layouts, depending on the requirements of the application. The following is an example of an in-line light source layout and a matrix light source layout, but this disclosure is not limited to this.

7A to 7C are schematic diagrams of one of the in-line light source layouts using the chip package structure of the embodiment on the substrate. The bottom surface 702 of the substrate 70 has a heat-dissipating pad. Through a special heat-dissipating pad design, the entire chip-level package structure can achieve the effect of thermoelectric separation. FIG. 7A shows that a plurality of (five) wafers 20 are arranged on the substrate 70 at a distance from each other, and their arrangement is also the same as 1×5 in-line. FIG. 7B shows the positions of the wafer 20 (the area of the frame is the area of the phosphor layer 41 in the above embodiment) and the heat dissipation pads disposed on the bottom surface 702 respectively disposed on the carrying surface 701 of the substrate 70. The carrying surface 701 and the bottom surface 702 of the substrate 70 are connected up and down through the via hole. FIG. 7C is a schematic diagram showing the design of thermal pads 75a and 75b located on the bottom surface 702 of the substrate 70. As shown in FIG. The large-area heat-dissipating pad 75a can overlap with the corresponding positions of all the chips 20, and the corresponding two heat-dissipating pads 75b have via holes (filled with conductive materials such as metal) through the substrate 70 to achieve up and down conduction. The opposite voltage is applied to the two heat dissipation pads 75b. Since the heat dissipation pad 75a and the two heat dissipation pads 75b are arranged separately (in terms of heat dissipation), this design can achieve thermoelectric separation and prolong the service life of the entire package structure.

2,n

2，m，n為正整數)之排列方式亦可應用。圖8B繪示分別設置於基板80之承載表面801的晶片20與設置於底面802的散熱墊之位置。 其中基板80之承載表面801與底面802係透過導通孔上下導通。圖8C繪示位於基板80之底面802的散熱墊85a、85b之設計示意圖。其中大面積之散熱墊85a與相應所有晶片20的位置有重疊部分，對應兩散熱墊85b處有導通孔(其內部填充有導電材料如金屬)貫穿基板80以達到上下導通，操作時係施以相反電壓於兩散熱墊85b，由於散熱墊85a與兩散熱墊85b分隔設置(散熱上彼此獨立)，如此設計可以達到熱電分離，延長封裝結構整體之使用壽命。 8A to 8C are schematic diagrams of one matrix light source layout in which the chip package structure of the embodiment is applied to the substrate. Similar to FIGS. 7A to 7C, FIG. 8A shows a plurality of (four) wafers disposed on the substrate 80 at a distance from each other, and their arrangement is also the same as a 2×2 matrix. Of course, this disclosure is not limited to this, other m×n matrices (m

2,n

2. The arrangement of m and n is a positive integer) can also be applied. FIG. 8B shows the positions of the chip 20 disposed on the carrying surface 801 of the substrate 80 and the heat dissipation pad disposed on the bottom surface 802 respectively. The carrying surface 801 and the bottom surface 802 of the substrate 80 are connected up and down through the via holes. FIG. 8C is a schematic diagram showing the design of the heat dissipation pads 85a and 85b located on the bottom surface 802 of the substrate 80. The large-area heat-dissipating pad 85a overlaps the positions of all the corresponding chips 20, and the corresponding two heat-dissipating pads 85b have through holes (filled with conductive materials such as metal) through the substrate 80 to achieve up and down conduction. The opposite voltage is the two heat dissipation pads 85b. Since the heat dissipation pad 85a and the two heat dissipation pads 85b are arranged separately (in terms of heat dissipation), this design can achieve thermoelectric separation and prolong the service life of the package structure as a whole.

In summary, in the light-emitting diode chip package structure of the embodiment (as shown in FIG. 1D), the top surface 311 of the colloidal layer 31 exposes the first surface 201 of the chip 20 and cuts the first surface 201 of the chip 20 (light emitting surface). ), and the two side edges 313 of the colloid layer 31 are aligned with the two edges 103 of the substrate 10, and the phosphor layer 41 located above the top surface 311 of the colloid layer 31 at least completely covers the first surface 201 of the chip 20 but is smaller than the colloid layer 31 One side is long, the area of the phosphor layer 41 is substantially equal to or larger than the area of the chip 20 but smaller than the area of the top surface 311 of the colloidal layer 31, which can reduce the blue/yellow circle phenomenon. In an embodiment, the reflectivity of the colloidal layer 31 (ex: silicon+titanium dioxide) is at least greater than 90%, which can guide the side light of the chip 20 to the positive direction, thereby improving the efficiency of light emission in the forward direction and increasing the illuminance. Furthermore, in one embodiment, the substrate 10 is, for example, a ceramic substrate (about 6ppm/°C) with a low thermal expansion coefficient, and the material of the colloid layer 31 (such as white epoxy resin or silicone resin). , Silicone resin sealant has a thermal expansion coefficient of about 14ppm/℃) It also has a low thermal expansion coefficient, which can avoid improper damage to the structure caused by thermal stress. And the ceramic substrate has high bending strength, which can protect the chip from stress pulling, It has the function of a stress barrier. Furthermore, the special design of the substrate 10 (the extended electrodes 111a, 111b and the pads 112a, 112b that are connected up and down) can reduce the short circuit risk of the chip package structure of the embodiment, and increase the surface adhesion ( SMD) area to improve the alignment accuracy and assembly efficiency of adhesion. In addition, during the coating process of the phosphor layer 41, the ratio of the phosphor to the colloid can be selected in an appropriate ratio range according to different color temperatures to obtain the best light conversion and extraction efficiency. In the structural design of the embodiment of the present disclosure, the thickness of the phosphor layer 41 can be adjusted and changed according to the different requirements of the desired color temperature to obtain the best light conversion and extraction efficiency. Therefore, the design of the embodiment varies in application Compared with the traditional chip package structure, the above has more flexibility to choose from. In addition, the manufacturing method proposed according to the embodiment can also be used in the step of forming the colloidal layer 31 (for example, a grinding method is used to remove part of the colloidal material 30), and the first surface 201 of the wafer 20 can be polished together to make The top surface 311 of the colloidal layer 31 with high reflectivity and the first surface 201 of the wafer 20 are not only aligned with the same height, but also make the first surface 201 of the wafer 20 form a roughened surface (for example, the surface roughness Ra is greater than 0.01 μm). Increase light extraction efficiency. Furthermore, under the support of the substrate 10 with high mechanical strength, in the step of roughening the first surface 201 of the wafer 20, the wafer 20 can be thinned to reduce the total reflection path, thereby increasing the illuminance and enhancing the forward light intensity.

It must be noted here that the following embodiments use the element numbers and part of the content of the foregoing embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

<Sixth Embodiment>

9A to 9C are schematic diagrams showing partial steps of the manufacturing method of the chip package structure of the sixth embodiment of the disclosure. The manufacturing method of the chip package structure of this embodiment is similar to the manufacturing method of the chip package structure of FIG. 2A to FIG. 2E. The only difference is that after the step of FIG. 2A, a substrate 10 is provided, and a plurality of chips 20 are separately arranged. After being placed on the bearing surface 101 of the substrate 10, referring to FIG. 9A, a phosphor layer 44 is formed by spraying, and the phosphor layer 44 directly covers the first surface 201 and the side surface 203 of the wafer 20 and the substrate 10 Bearing surface 101. Then, a light-transmitting layer 54 is formed on the fluorescent layer 44 by spraying, wherein the light-transmitting layer 54 and the fluorescent layer 44 are conformally arranged, and the light-transmitting layer 54 has an upper surface 541 and a plurality of side edges 514, respectively It is connected to the upper surface 541 and the plurality of extension portions 515 are connected to the side edge 514. Next, referring to FIG. 9B, a glue layer 34 is formed by dispensing glue, wherein the glue layer 34 extends along the extension 515 and the side edge 514 of the transparent layer 54 on the upper surface 541 of the transparent layer 54 and is exposed出Part of the upper surface 541. Here, the colloid layer 34 directly covers the side edge 514 and the extension portion 515 of the light-transmitting layer 54. In particular, the gel layer 34 covers the side edge 514 and the extension portion 515 of the light-transmitting layer 54 through capillary action, and also extends to the upper surface 541 of the light-transmitting layer 54 because of the capillary function. Preferably, the extension length of the colloid layer 34 on the upper surface 541 of the light-transmitting layer 54 is less than or equal to 10% of the length of the wafer 20. However, the colloidal layer 34 may also be concave between two adjacent wafers 20 due to surface tension. After that, referring to FIGS. 9B and 9C at the same time, the colloidal layer 34, the light-transmitting layer 54, the fluorescent layer 44, and the substrate 10 are cut to form a plurality of chip package structures. For the convenience of description, FIG. 9C only schematically illustrates a chip package structure. Please refer to Figure 9C, The side edges 314 of the colloid layer 34 of the chip package structure, the side edges 515a of the extension 515 of the light-transmitting layer 54, the side edges 44a of the phosphor layer 44, and the edges 103 of the substrate 10 are all aligned. So far, the fabrication of the chip package structure 100a has been completed.

<Seventh Embodiment>

10A to 10C are schematic diagrams showing partial steps of the manufacturing method of the chip package structure of the seventh embodiment of the disclosure. The manufacturing method of the chip package structure of this embodiment is similar to the manufacturing method of the chip package structure of FIGS. 9A to 9C. The only difference is: after the step of FIG. 9A, that is, after the light-transmitting layer 54 is formed, please refer to FIG. 10A , Turn over the overall structure, and press a mold core M and the colloidal material 30a disposed on the mold core M on the light-transmitting layer 54 by heating and pressing. Since both the light-transmitting layer 54 and the fluorescent layer 44 are arranged conformally to the outer contour of the wafer 20, there is a recess C between two adjacent wafers 20, and the colloidal material 30a is filled here due to the thermal compression. Next, referring to FIG. 10B, the mold core M is removed, and the overall structure is turned over to form the colloid layer 35. At this time, the colloid layer 35 completely exposes the upper surface 541 of the light-transmitting layer 54, and the concentration of the colloid layer 35 in the recess C is greater than the concentration on the upper surface 541 of the light-transmitting layer 54. After that, referring to FIGS. 10B and 10C at the same time, the colloidal layer 35, the light-transmitting layer 54, the fluorescent layer 44 and the substrate 10 are cut to form a plurality of chip package structures. For the convenience of description, FIG. 10C only schematically illustrates a chip package structure. 10C, the side edges 315 of the colloidal layer 35 of the chip package structure, the side edges 515a of the extension 515 of the light-transmitting layer 54, the side edges 44a of the phosphor layer 44, and the edge 103 of the substrate 10 are all aligned. So far, the fabrication of the chip package structure 100b has been completed.

<Eighth Embodiment>

11A to 11E are schematic diagrams showing partial steps of the manufacturing method of the chip package structure of the eighth embodiment of the disclosure. The manufacturing method of the chip package structure of this embodiment is similar to the manufacturing method of the chip package structure of FIGS. 2A to 2E. The only difference is that after the step of FIG. 2C, a part of the colloidal material 30 is removed by grinding. A colloidal layer 31 is formed. The polishing process may further include the steps of roughening the surface (first surface 201) of the wafer 20 and thinning the wafer; after the polishing is completed, the top surface 311 of the colloidal layer 31 exposes the first surface of the wafer 20 After the surface 201 is aligned with the first surface 201 of 20, please refer to FIG. 11A to remove the colloidal layer 31. Here, the purpose of the steps of roughening the first surface 201 and thinning the wafer 20 on the wafer 20 during grinding is to make the used wafer 20 have the same height to facilitate subsequent manufacturing steps. Next, referring to FIG. 11B, a fluorescent layer 44 is formed by spraying, and the fluorescent layer 44 directly covers the first surface 201 and the side surface 203 of the wafer 20 and the supporting surface 101 of the substrate 10. Then, a light-transmitting layer 54 is formed on the fluorescent layer 44 by spraying, wherein the light-transmitting layer 54 and the fluorescent layer 44 are conformally arranged, and the light-transmitting layer 54 has an upper surface 541 and a plurality of side edges 514, respectively It is connected to the upper surface 541 and the plurality of extension portions 515 are connected to the side edge 514. Next, referring to FIG. 11C, the overall structure is turned over, and a mold core M and the colloidal material 30a disposed on the mold core M are pressed onto the light-transmitting layer 54 by heating and pressing. Since the light-transmitting layer 54 and the fluorescent layer 44 are arranged conformally to the outer contour of the wafer 20, there is a recess C between two adjacent wafers 20, and the colloidal material 30a is filled here due to the thermal compression bonding. And the concentration of the colloidal material 30a in the recess C is greater than that on the upper surface 541 of the light-transmitting layer 54 On the concentration. Next, referring to FIG. 11D, the mold core M is removed, and the overall structure is turned over to form the colloid layer 35. At this time, the colloid layer 35 completely exposes the upper surface 541 of the light-transmitting layer 54. After that, referring to FIGS. 11D and 11E at the same time, the colloidal layer 35, the light-transmitting layer 54, the fluorescent layer 44 and the substrate 10 are cut to form a plurality of chip package structures. For the convenience of description, FIG. 11E only schematically illustrates a chip package structure. 11E, the side edges 315 of the colloidal layer 35 of the chip package structure, the side edges 515a of the extension 515 of the light-transmitting layer 54, the side edges 44a of the phosphor layer 44, and the edge 103 of the substrate 10 are all aligned. So far, the fabrication of the chip package structure 100c has been completed.

<Ninth Embodiment>

12A to 12D are schematic diagrams showing partial steps of the manufacturing method of the chip package structure of the ninth embodiment of the disclosure. The manufacturing method of the chip package structure of this embodiment is similar to the manufacturing method of the chip package structure of FIG. 2A to FIG. 2E. The only difference is that after the step of FIG. 2A, a substrate 10 is provided, and a plurality of chips 20 are separately arranged. After being placed on the supporting surface 101 of the substrate 10, referring to FIG. 12A, a colloidal layer 36 is formed by dispensing glue, wherein the colloidal layer 36 extends along the side surface 203 of the chip 20 to the supporting surface 101 of the substrate 10. Next, referring to FIG. 12B, a pre-cutting process is performed on the colloidal layer 36 and the substrate 10 to form a plurality of grooves V. Next, referring to FIG. 12C, a phosphor layer 45 is formed on the first surface 201 of the chip 20 by dispensing and extends to cover the gel layer 36. Here, the fluorescent layer 45 is a lens type fluorescent layer. After that, referring to FIG. 12D, the substrate 10 is cut along the groove V to form a plurality of chip package structures. For the convenience of description, FIG. 12D only schematically illustrates a chip package structure. Please refer to Figure 12D, chip package The side edge 316 of the colloidal layer 36, the side edge 45a of the phosphor layer 45, and the edge 103 of the substrate 10 are all aligned. So far, the fabrication of the chip package structure 100d has been completed.

In summary, the present invention provides a chip packaging structure and a manufacturing method thereof. The chip is first placed on a substrate and packaged with a colloid layer, then one surface of the chip is exposed, and then a phosphor layer is formed on the exposed surface of the chip. Through the design of the embodiment, the optical properties of the chip package structure can be improved, for example, the light conversion and extraction efficiency can be improved. In other embodiments, a light-transmitting layer can also be selectively provided on the fluorescent layer to serve as a light-transmitting protective layer to increase the water vapor transmission path and effectively prevent water vapor from penetrating. Of course, the structure of different light-transmitting layer structures, such as a lens-type light-transmitting layer, can effectively improve the light extraction efficiency.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧Substrate

101‧‧‧Loading surface

102‧‧‧Bottom

103‧‧‧Edge

111a、111b‧‧‧Extension electrode

112a, 112b‧‧‧Pad

113a, 113b‧‧‧Guide hole

20‧‧‧Chip

201‧‧‧First surface

202‧‧‧Second Surface

222a, 222b‧‧‧electrode

31‧‧‧Colloid layer

311‧‧‧Top surface

313‧‧‧Side edge

41‧‧‧Fluorescent layer

L1‧‧‧Side length of fluorescent layer

Lm‧‧‧Side length of colloid layer

Lc‧‧‧Side length of chip

Claims (12)

A chip packaging structure includes: a substrate with a flat plate structure; a chip arranged on the substrate and electrically connected to the substrate; a reflective colloid layer arranged on the substrate to encapsulate the chip and expose the An upper surface of the chip; and a fluorescent layer covering the upper surface of the chip and at least part of an upper surface of the reflective colloid layer, wherein the chip package structure has a flat side surface, and the flat side surface at least includes The reflective colloid layer and the substrate, wherein the reflective colloid layer has a concave upper surface. A chip packaging structure includes: a substrate with a flat plate structure; a chip arranged on the substrate and electrically connected to the substrate; a fluorescent layer covering an upper surface and a side surface of the chip and a surface of the substrate At least a part of an upper surface; and a reflective colloid layer disposed on the substrate to encapsulate the chip and expose a portion of the phosphor layer on the upper surface of the chip, wherein the chip packaging structure has a flat side Surface, the flat side surface at least includes the reflective colloid layer and the substrate, wherein the reflective colloid layer has a concave upper surface. A chip packaging structure includes: a substrate with a flat plate structure; A chip is arranged on the substrate and is electrically connected to the substrate; a reflective colloid layer is arranged on the substrate to encapsulate the chip and expose an upper surface of the chip; a fluorescent layer covering the upper surface of the chip The upper surface and an upper surface of at least part of the reflective colloid layer, wherein the chip package structure has a flat side surface, and the flat side surface includes at least the reflective colloid layer and the substrate; and a lens-type light-transmitting layer , Wherein the lenticular transparent layer completely covers the fluorescent layer. A chip packaging structure includes: a substrate with a flat plate structure; a chip arranged on the substrate and electrically connected to the substrate; a reflective colloid layer arranged on the substrate to encapsulate the chip and expose the An upper surface of the chip; and a fluorescent layer covering the upper surface of the chip and at least part of an upper surface of the reflective colloid layer, wherein the chip package structure has a flat side surface, and the flat side surface at least includes The reflective colloid layer and the substrate, wherein the fluorescent layer includes a lens type fluorescent layer. The chip package structure described in item 1 or 2 or 4 of the scope of the patent application further includes a light-transmitting layer, wherein the light-transmitting layer completely covers the fluorescent layer. According to the chip package structure described in item 5 of the scope of patent application, the flat side surface of the chip package structure further includes the light-transmitting layer. The chip package structure according to item 6 of the scope of patent application, wherein the flat side surface of the chip package structure further includes the phosphor layer. The chip package structure according to item 1 or 2 or 3 or 4 of the scope of patent application, wherein the flat side surface of the chip package structure further includes the phosphor layer. The chip package structure described in item 1 of the scope of patent application further includes a lens-type light-transmitting layer, wherein the lens-type light-transmitting layer completely covers the fluorescent layer. According to the chip package structure described in claim 1, wherein the phosphor layer includes a lens-type phosphor layer. According to the chip package structure described in item 1 or 2 or 3 or 4 of the scope of patent application, the reflective colloid layer has a flat upper surface. According to the chip package structure described in item 3 or 4 of the scope of patent application, the reflective colloid layer has a concave upper surface.

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