TW201419529A - A novel low voltage structure ESD bipolar junction transistor (BJT) for bi-direction high voltage ESD protection based on EPI process - Google Patents

Abstract

A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates and one or more P+ doped plates.

Description

EPI process uses a new low-voltage architecture for bidirectional high-voltage ESD protection of dual-carrier transistors

Embodiments of the present invention are generally related to semiconductor devices and, more particularly, to Bipolar Junction Transistors (BJT) for bidirectional high voltage ESD (Electrostatic Discharge) protection.

Almost as far as various aspects of electronic device manufacturing are concerned, there is currently a tendency to continue to shrink toward device size. Smaller electronic devices tend to be popular with larger, heavier devices when both devices have substantially equal performance. Therefore, the ability to manufacture smaller components will obviously help to produce smaller devices that are assembled with those components. However, many modern electronic devices require electronic circuitry to perform both drive functions (eg, turning the device on or off) and data processing or other decision functions. For these two functions, the use of Complementary Metal-Oxide-Semiconductor (CMOS) technology may not always be feasible. Therefore, high voltage (or high power) devices have also been developed to handle many applications where low voltage operation is not possible.

The electrostatic discharge (ESD) performance of a typical high voltage device often depends on the overall width and surface or lateral rules of the respective device. Therefore, for smaller devices, ESD performance may often be more important. High voltage devices typically have characteristics including low on-state resistance (Rdson), high breakdown voltage (Breakdown Voltage), and low holding voltage (Holding Voltage). During an ESD event, low on-state resistance may tend to make ESD currents more easily concentrated at the surface or drain edge of the device. High currents and high electric fields can cause physical damage in a surface junction area of such devices. Surface or lateral rules may not increase based on typical requirements for low on-state resistance. Therefore, ESD protection can be a challenge.

The high breakdown voltage characteristic of the high voltage device typically means that the breakdown voltage is above the operating voltage and the trigger voltage (Vt1) is above the breakdown voltage. Therefore, during an ESD event, the internal circuitry of the high voltage device may be at risk of damage before the high voltage device is turned on for ESD protection. The low sustain voltage characteristics of the high voltage device also preserve the possibility of triggering unwanted noise associated with the Power-On peak voltage or Surge Voltage, or may occur during normal operation. Latch-Up possibility. Due to the fact that the electric field distribution may be sensitive to routing, high voltage devices may also experience a Field Plate Effect such that the ESD current may concentrate on the surface or drain edge during an ESD event.

In order to improve the performance of high voltage devices for ESD events, an already implemented technique involves the use of masks and other processes to create a larger size diode within the components of a bi-carrier transistor (BJT), And/or increase the surface or lateral rules of the MOS transistor. Silicone Controlled Rectifiers (SCRs) have also been developed to protect circuits during ESD events. However, while the low sustain voltage of the SCR means that they can perform well during an ESD event, this feature also increases the occurrence of latch-up during normal operation.

Motor Driver Circuits can be particularly tricky to protect against ESD events using current solutions. This is because when the motor is turned off, it may continue to rotate for a period of time, thus acting as an inductor to feed back a high negative voltage. If the motor drive circuit is to include a PMOS, the parasitic forward biased diode of the PMOS may be turned on by this negative feedback voltage, which may cause latch-up problems and/or other irregular circuit operations.

Therefore, it may be desirable to develop an improved structure for providing ESD protection, and in particular, to provide bidirectional ESD protection.

Some exemplary embodiments are thus directed to a low voltage structure bipolar transistor (BJT) for bidirectional high voltage electrostatic discharge (ESD) protection. In some cases, ESD protection is based, at least in part, on a BCD (Bipolar Computational Metal-Oxide Semiconductor, BiCMOS) Diffusion Metal-Oxide Semiconductor (DMOS) process. Modifications, the BCD process may involve an Epitaxial Process.

In an exemplary embodiment, a two-way BJT is provided ("exemplary" as used herein refers to "serving as an example, instance, or illustration"). The bidirectional BJT can include a p-type substrate, an N+ doped buried layer, an N-type well region, and two P-type well regions. The N+ doped buried layer can be disposed adjacent to the substrate. The N-type well region may be deposited adjacent to the N+ doped buried layer and surrounding the first and second P-type well regions such that a portion of the N-type well region is between the first and second P-type regions Between the well areas. The P-type well regions may be deposited adjacent to the N+ doped buried layer and each may include one or more N+ doped plates and one or more P+ doped plates, respectively.

According to a further embodiment, the N-doped plates, the two P+ doped plates, and the two gate structures are included in the P-type well regions. For each P-well, the three N+ doped plates, the two P+ doped plates, and the two gate structures can be configured such that a first P+ doped plate is deposited as a phase Adjacent to a first N+ doped plate, a first gate structure is interposed between the first and a second N+ doped plates, and a second gate structure is interposed between the second and a third N+ Between the doped plates, and a second P+ doped plate are deposited adjacent to the third N+ doped plate.

In another exemplary embodiment, a circuit is provided that includes a bidirectional high voltage ESD protection component. The bidirectional high voltage ESD protection component includes a p-type substrate, an N+ doped buried layer, an N-type well region, and two P-type well regions. The N+ doped buried layer can be deposited adjacent to the substrate. The N-type well region may be deposited adjacent to the N+ doped buried layer and surrounding the first and second P-type well regions such that a portion of the N-type well region is interposed between the first and second P-type wells Between the districts. The P-type well regions may be deposited adjacent to the N+ doped buried layer, and each P-type well region may include one or more N+ doped plates and one or more P+ doped plates, respectively. The P-type well regions may include three N+ doped plates, two P+ doped plates, and two gate structures. For each P-well, the three N+ doped plates, the two P+ doped plates, and the two gate structures can be configured such that a first P+ doped plate is deposited as a phase Adjacent to a first N+ doped plate, a first gate structure is interposed between the first and a second N+ doped plates, and a second gate structure is interposed between the second and a third N+ Between the doped plates, and a second P+ doped plate are deposited adjacent to the third N+ doped plate.

According to still another exemplary embodiment, there is provided a semiconductor device including a first isolated low voltage n-channel metal oxide field effect transistor (LVNMOS) and a second isolated LV NMOS, the first and second isolated LV NMOS being shared A common N-well isolation region.

Some exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. In fact, the various exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein; rather, these exemplary embodiments are provided to enable the disclosure. Content meets applicable legal requirements.

Some exemplary embodiments of the present invention may provide a bidirectional BJT that may be used for, for example, bidirectional high voltage ESD protection, such as positive and negative voltage ESD protection. The bidirectional BJT of these exemplary embodiments can combine two isolated low voltage N-channel metal oxide semiconductor transistors (MOS) into an ESD protection device, thereby providing a structure having a total area less than a diode —BJT and MOS, with similar ESD performance in both directions. The exemplary embodiment may also have a breakdown voltage in the vicinity of the high voltage device operating voltage and a trigger voltage below the high voltage device breakdown voltage. In addition, a relatively high sustain voltage can be provided to more easily (as compared to the use of a controlled voltage rectifier (SCR)) to avoid latch-up. For example, these exemplary embodiments may be useful in a motor drive circuit, such as between an I/O connection pad and a power connection pad. In this case, the exemplary embodiment can provide positive and negative high voltage ESD protection without causing irregular behavior during normal operation and without introducing latch problems. In some cases, the exemplary embodiments can also be fabricated using a standard BCD process that does not require an additional reticle or process number. For example, the polysilicon used in some exemplary embodiments can be provided by ion implantation through a hard reticle.

Figure 1a shows a simplified schematic of a conventional SCR 100. As shown, a conventional SCR is comprised of a P+ material 101, an N-material 102, a P-type material 103, and an N+ material 104 adjacent to the N-material 102, the N- Material 102 is then adjacent to the P-type material 103, and the P-type material 103 is itself adjacent to the N+ material 104. An elemental structural equivalent diagram 150 is also shown. As shown in graph 160 of Figure 1b, a conventional SCR provides forward ESD protection as shown by Snap-Back 161 occurring in the forward collapse voltage.

Figure 2a shows a simplified schematic of an embodiment of the invention. As shown in view 200, embodiments of the present invention can operate as two NPN bipolar transistors 201 having coupled N-type regions 202. Thus, as can be seen in views 210 and 220, in both forward 210 and reverse 220, the exemplary embodiment can have a function of being triggered by a forward biased diode 211, followed by opening an NPN BJT 212 to fold back (Snap-Back). Graph 230 illustrates the forward and reverse foldback 231 described above. The exemplary embodiment may have a low on-resistance (Ron) and a high sustain voltage, and the high ESD current may be simultaneously discharged through the forward biased diode and the NPN BJT.

Figures 3a and 3b show simplified circuit diagrams of an embodiment of the invention. As can be seen in Figure 3a, embodiments of the present invention can include two low voltage isolated NMOSs 300a, 300b that share a common isolation region 301. As shown in Figure 3b, the electrical properties of embodiments of the present invention can be modeled as two BJT transistors 310a, 310b having coupled collectors 311. As can be seen in Figures 4a and 4b, the upper BJT transistor 310a is replaced by a forward biased diode 410a under forward ESD stress. As can be seen in Figures 5a and 5b, under negative ESD stress, the lower BJT transistor 310a is replaced by a forward biased diode 510b. Thus, embodiments of the present invention ensure that ESD current is discharged regardless of the application of positive ESD or negative ESD stress, thus providing bidirectional ESD protection. The forward and reverse collapse voltages of the exemplary embodiments can be made the same or different by using isolated NMOS or NPN BJTs having the same or different breakdown voltages.

Although the electronic characteristics and attributes of the exemplary embodiments of the present invention have been generally described, reference will now be made to FIGS. 6 through 8 to describe the structure of the exemplary embodiments.

FIG. 6 shows a cross-sectional view of an exemplary embodiment for providing bidirectional high voltage ESD protection. As can be seen from FIG. 6, a P-type material substrate 600 or an epitaxially-grown P-layer (P-epi) may be provided adjacent to the N+ buried layer 601. An N-type well 602a-c can be deposited adjacent to the N+ buried layer 601 and surrounding the first and second P-type wells 603a, 603b such that a portion 602b of the N-type well above is deposited in the Between the first and second P-wells 603a, 603b. According to some embodiments, the N-wells 602a-c can be a single continuous N-type well 602a-c, or according to another embodiment, can include two or more separate N-type wells. According to an exemplary embodiment, the outer portions 602a and 602c of the N-type well may be in contact with the P-type substrate 600. The first and second P-type wells 603a and 603b may include at least one P+ doped plate 604 and at least one N+ doped plate 605.

For example, according to the exemplary embodiment shown in FIG. 6, each of the first and second P-type wells 603a and 603b may each include two P+ doped plates 604, three N+ doped plates 605, and two Gate structure 606. Thus, as shown, the first P-well 603a may include a first P+ doped plate 604 that may be deposited adjacent to a first N+ doped plate 605, which may be interposed between the first and a first gate structure 606 between a second N+ doped plate 605, a second gate structure 606 between the second and a third N+ doped plate 605, and a deposition Is a second P+ doped plate adjacent to a third N+ doped plate. Similarly, the second P-type well 603b may include a third P+ doped plate 604 deposited adjacent to a fourth N+ doped plate 605, interposed between the fourth and a fifth N+ doped plates. a third gate structure between 605, a fourth gate structure between the fifth and a sixth N+ doped plate 605, and a deposition adjacent to the sixth N+ A fourth P+ doped plate 604 of the miscellaneous board. According to another exemplary embodiment, an anode 607 can be operatively coupled to a P+ doped plate 604, a plurality of N+ doped plates 605, and a plurality of gate structures 606 of one of the P-type wells 603a. And a cathode 608 can be operatively coupled to a plurality of P+ doped plates 604, a plurality of N+ doped plates 605, and a plurality of gate structures 606 of the other 603b of the P-type well.

The gate structure 606, which may be formed between the N+ doped plates 605, may include a gate oxide layer and a polysilicon layer, wherein the polysilicon may be provided as a hard mask during ion implantation. The gate 606 can enable a Collective Operation of the distributed N+ doped plate 605. A Field-Oxide Film (FOX) portion 609 can be deposited adjacent to the surface of portions 602a-c of the N-type well and adjacent to each of the P+ doped plates 604. A distal end. As can be seen from FIG. 6, a plurality of BJT transistors 610a, 610b can be equivalently formed by the provided structure (in this example, there are four BJT transistors, two on the anode side, 610a, and two in 610b) on the cathode side. As shown, according to the structure described, the collector of the BJT transistor 610a on the anode side and the collector (shown as "C" in Fig. 6) of the BJT transistor 610b on the cathode side are equivalently connected. Further, the base of the anode side BJT electric transistor 610a and the cathode side BJT transistor 610b (denoted as "B" in Fig. 6) are equivalently connected to the radiation of their respective P+ plates and BJT transistors 610a on the anode side. The poles (denoted "E" in Figure 6) and the cathode side BJT transistors 610b are equivalently connected to their respective N+ plates.

It will be understood that the configuration shown in FIG. 6 and, even, according to the configuration of other embodiments not shown, may serve as two isolated low voltage NMOSs sharing a common N-type isolation region 301. That is, the substrate 600 associated with the P-well 603a, the N+ buried layer 601, the N wells 602a and 602b, the P-well 603a, the P+ board 604, the N+ board 605, And (according to some embodiments) the gate structure 606 can serve as a first isolated low voltage NMOS 300a. Similarly, the substrate 600, the N+ buried layer 601, the N-type wells 602c and 602b, the P-type well 603b, the P+ board 604, the N+ board 605, and the P-type well 603b are associated with the P-type well 603b. And (according to some embodiments) the gate structure 606 can serve as a second isolated low voltage NMOS 300b. The shared shared N-type isolation region 301 thus includes an N-type well 602b. The gate, source and drain electrodes 6 to 8 of the isolated low voltage NMOSs 300a and 300b are denoted as "G", "S" and "D", respectively.

As shown in Figures 7 and 8, respectively, during a forward ESD event, the anode side transistor 610a can (in effect) act as a forward biased diode 710a in a negative ESD event. During this period, the cathode side transistor 610b can (in effect) function as a forward biased diode 810b. Thus, during either a forward or a negative ESD event, the ESD current can be discharged with an NPN BJT at the same time by a forward biased diode.

The material of the N+ buried layer 601 may be an N- epitaxial, a deep N-type well, or a plurality of stacked N+ buried layers. The P-type wells 603a, 603b can be stacked with a P-type well and a P+ buried layer or a P-type implant. In some cases, the N-wells 602a-c can also be an N-type implant. The structure can be fabricated using any standard BCD process without the need for an additional mask. According to another exemplary embodiment, the structure may be fabricated using a non-epitaxial process such as a triple well process. The structure can also be fabricated using a single layer of poly poly or a double poly process. A local oxidation of silicone (LOCOS) process can be used in at least a portion of the fabrication of the structure, such as the fabrication of the FOX portion 609. Alternatively, a shallow trench isolation (STI) process can be used, for example, to fabricate at least a portion of the structure, such as the FOX portion 609.

FIG. 9 includes an uppermost graph 900 showing the breakdown voltage characteristics of an exemplary embodiment. As can be seen from graph 900, the breakdown voltage can have equal amplitudes in the forward (forward) and reverse (negative) directions. The bottom graphs 910 and 920 show the leakage currents 911 and 921 measured between the anode 607 and the cathode 608, and the ESD current 912 measured in an exemplary embodiment during the forward and negative ESD stress experiments, respectively. With 922. As can be seen, both measured ESD currents 912 and 922 exhibit a Snap-Back 931 indicating successful ESD protection in both forward and negative directions.

Thus, the exemplary embodiment can provide a relatively small size bidirectional bipolar transistor (BJT) for high voltage electrostatic discharge (ESD) protection. Moreover, the exemplary embodiments can be applied to a standard BCD process without requiring the use of an additional reticle. Embodiments are also applicable to different high voltage BCD processes and provide different operating voltage related ESD protection by providing an N+ buried layer or N-well process in the same process. In this connection, high voltage ESD protection can be provided in a relatively small size and through a relatively low voltage MOS structure. For devices used in high voltage settings that may encounter ESD events, high voltage ESD protection is Often needed. Some embodiments may be used for the operation of a general DC circuit. In addition, ESD protection can be provided for devices that require such protection to be bi-directionally protected, such as provided in a motor driver circuit. In this regard, for example, an embodiment can be operatively coupled between a power pad of an electric motor drive circuit and an input/output (I/O) pad to provide forward and negative high voltage ESD Protection without causing abnormal operations or introducing shackles.

Numerous modifications and other embodiments of the inventions set forth herein are apparent to those skilled in the <RTIgt; Therefore, it is understood that the invention is not limited to the specific embodiments disclosed, and modifications and other embodiments are included in the scope of the appended claims. In addition, while the above description and related drawings are described in the context of certain exemplary combinations of elements and/or functions, it should be appreciated that various combinations of elements and/or functions may be Alternative embodiments of the scope are provided. In this regard, for example, various groups of elements and/or functions other than those explicitly described above are also contemplated as being possible in the scope of the appended claims. Although specific nouns are used herein, they are used in a generic and descriptive sense only and not for the purpose of limitation.

100. . . Traditional SCR

101. . . P+ material

102. . . N-material

103. . . P type material

104. . . N+ material

150. . . Element structure equivalent diagram

160. . . Graph

161. . . Fold back

200. . . view

201. . . NPN bipolar transistor

202. . . N-type zone

201, 220. . . view

211. . . Forward biased diode

212. . . NPN BJT

230. . . Graph

231. . . Forward and reverse reentry

300a. . . Low voltage isolation NMOS

300b. . . Low voltage isolation NMOS

301. . . N-type isolation zone

310a, 310b. . . BJT transistor

311. . . Collector

410a. . . Forward biased diode

510b. . . Forward biased diode

600. . . P-type material substrate

601. . . N+ buried layer

602a-c. . . N-well

603a. . . First P-well

603b. . . Second P-well

604. . . P+ doped plate

605. . . N+ doped plate

606. . . Gate structure

607. . . anode

608. . . cathode

609. . . Field effect oxide film

610a, 610b. . . BJT transistor

900, 910, 920. . . chart

911, 921. . . Leakage current

912, 922. . . ESD current

931. . . Fold back

The present invention has been described generally, and the appended claims

Figures 1a and 1b show simplified views of prior art SCRs and their associated electronic characteristics, respectively;

Figures 2a and 2b respectively show simplified views of an embodiment of the invention and its associated electronic characteristics;

Figures 3a and 3b illustrate an electronic circuit having electrical properties substantially corresponding to an embodiment of the present invention;

Figures 4a and 4b show the circuit performance shown in Figures 2a and 2b under forward ESD stress;

Figures 5a and 5b show the circuit performance shown in Figures 2a and 2b under negative ESD stress;

Figure 6 shows a cross-sectional view of the structure of an exemplary embodiment;

Figure 7 shows a cross-sectional view of the structure of an exemplary embodiment under forward ESD stress;

Figure 8 shows a cross-sectional view of the structure of an exemplary embodiment under negative ESD stress;

Figure 9 illustrates the breakdown voltage characteristics of an exemplary embodiment and the experimental electronic gas characteristics.

600. . . P-type material substrate

601. . . N+ buried layer

602a-c. . . N-well

603a. . . First P-well

603b. . . Second P-well

604. . . P+ doped plate

605. . . N+ doped plate

606. . . Gate structure

607. . . anode

608. . . cathode

609. . . Field effect oxide film

610a, 610b. . . BJT transistor

300a, 300b. . . Low voltage isolation NMOS

301. . . N-type isolation zone

Claims (20)

A bidirectional bipolar transistor (BJT) comprising:
a p-type substrate;
An N+ doped buried layer deposited adjacent to the substrate;
a first P-type well region deposited adjacent to the N+ doped buried layer;
a second P-type well region deposited adjacent to the N+ doped buried layer; and an N-type well region adjacent to the N+ doped buried layer and surrounding the first and second P-type wells a region such that at least a portion of the N-type well region is between the first and second P-type well regions;
Wherein each of the first and second P-type wells comprises at least one N+ doped plate and at least one P+ doped plate. The bidirectional BJT of claim 1, wherein the first P-type well comprises first, second and third N+ doped plates, first and second P+ doped plates, and first and second a gate structure, the first P+ doped plate is deposited adjacent to the first N+ doped plate, the first gate structure is interposed between the first and second N-doped plates, the second gate a structure between the second and third N+ doped plates, the second P+ doped plate being deposited adjacent to the third N+ doped plate; and wherein the second P-type well comprises a fourth, And a sixth N+ doped plate, third and fourth P+ doped plates, and third and fourth gate structures, the third P+ doped plate being deposited adjacent to the fourth N+ doped plate The third gate structure is interposed between the fourth and fifth N+ doped plates, the fourth gate structure is interposed between the fifth and sixth N+ doped plates, and the fourth P+ doping A plate is deposited adjacent to the sixth N+ doped plate. The bidirectional BJT according to claim 2, further comprising first first, second and third field effect oxide (FOX) portions deposited adjacent to the N-type well region, the first The FOX portion is further deposited adjacent to the first P+ doped plate, the second FOX portion is further between the second and third P+ doped plates, and the third FOX portion is deposited adjacent And the fourth P+ doped plate. The bidirectional BJT of claim 3, wherein the first, second and third FOX parts are manufactured by a zone oxidation isolation technique (LOCOS) process. The bidirectional BJT of claim 3, wherein the first, second, and third FOX portions are fabricated by a shallow trench isolation (STI) process. The bidirectional BJT of claim 2, wherein the gate structures comprise a polysilicon layer. The bidirectional BJT of claim 6, wherein the polysilicon layer is provided as a hard mask during ion implantation. The bidirectional BJT of claim 1, wherein the N+ buried layer comprises an n-type epitaxial layer. The bidirectional BJT of claim 1, wherein the N+ buried layer comprises a deep N-type well. The bidirectional BJT of claim 1, wherein the N+ buried layer comprises a plurality of stacked N+ buried layers. The bidirectional BJT of claim 1, wherein each P-type well comprises a stacked P-well and a P+ buried layer. The bidirectional BJT of claim 1, wherein the P-type wells are fabricated by P-type implantation. The bidirectional BJT of claim 1, wherein the N-well region is fabricated by N-type implantation. The bidirectional BJT of claim 1, wherein the bidirectional BJT is fabricated by a single poly process. The bidirectional BJT of claim 1, wherein the bidirectional BJT is fabricated by a double poly process. The bidirectional BJT of claim 16, wherein the bidirectional BJT is fabricated by a non-epitaxial process. The bidirectional BJT of claim 1, wherein the non-epitaxial process comprises a triple-well process. A circuit comprising a bidirectional high voltage electrostatic discharge (ESD) protection element, the bidirectional high voltage ESD protection element comprising:
a p-type substrate;
An N+ doped buried layer deposited adjacent to the substrate;
a first P-type well region deposited adjacent to the N+ doped buried layer;
a second P-type well region deposited adjacent to the N+ doped buried layer; and an N-type well region adjacent to the N+ doped buried layer and surrounding the first and second P-type wells a region such that at least a portion of the N-type well region is between the first and second P-type well regions;
Wherein the first P-type well includes first, second and third N+ doped plates, first and second P+ doped plates, and first and second gate structures, the first P+ doped plate is deposited Adjacent to the first N+ doped plate, the first gate structure is interposed between the first and second N-doped plates, and the second gate structure is interposed between the second and third N+ doped plates And the second P+ doped plate is deposited adjacent to the third N+ doped plate; and wherein the second P-type well comprises fourth, fifth, and sixth N+ doped plates, and third a fourth P+ doped plate, and third and fourth gate structures, the third P+ doped plate being deposited adjacent to the fourth N+ doped plate, the third gate structure being between the fourth and Between the fifth N+ doped plates, the fourth gate structure is interposed between the fifth and sixth N+ doped plates, and the fourth P+ doped plate is deposited adjacent to the sixth N+ doping board. The circuit of claim 18, wherein the bidirectional high voltage ESD protection component further comprises:
An anode operatively coupled to the first, second and third N+ doped plates, the first and second P+ doped plates, and the first and second gate structures; and a cathode Operablely coupled to the fourth, fifth and sixth N+ doped plates, the third and fourth P+ doped plates, and the third and fourth gate structures;
Also wherein the circuit includes a motor driver circuit including an input/output (I/O) pad and a power pad, one of the anode or cathode of the bidirectional high voltage ESD protection component being operatively coupled to the I/ An O pad, the other of the anode or cathode of the bidirectional high voltage ESD protection element being operatively coupled to the power pad. A semiconductor device includes a first isolated low voltage n-channel metal oxide field effect transistor (LVNMOS) and a second isolated LV NMOS, wherein the first and second isolated LV NMOS share a common N-type well isolation region.