TW201416821A - Frequency testing circuit - Google Patents

Abstract

The present invention relates to a frequency testing circuit, which configured to test a first clock frequency of a first clock signal of a sever. The frequency testing circuit includes a first control unit and a first counting unit. The first control unit works at a second clock signal, the second clock signal has a second clock frequency. The first control unit outputs a first control signal and a second control signal according to the second clock signal. The first counting units starts to count the quantity of pulses of the first clock signal according to the first control signal, stops counting according to the second control signal, and obtains a counting result, the counting result represents the first clock frequency.

Description

Frequency test circuit

The present invention relates to a frequency test circuit, and more particularly to a frequency for testing a clock signal of a processor in a server.

The stability of the server work is the focus of the engineers and users. The clock signal of the processor in the server is the key to the stable operation of the entire server. Thus, the frequency of the processor clock signal needs to be very accurate. At present, engineers often use an oscilloscope to test the clock signal to obtain the frequency of the clock signal. However, the price of the oscilloscope is usually expensive and is not suitable for large-volume testing.

In view of this, it is necessary to provide a test circuit that is simple in structure, relatively inexpensive, and capable of accurately testing the frequency of the processor clock signal.

a frequency test circuit for testing a first clock signal of a server, the first clock signal having a first clock frequency, the frequency test circuit comprising a first control unit and a first counting unit, the first control unit working The second clock signal has a second clock frequency, and the first control unit outputs the corresponding first control signal and the second control signal to the first counting unit according to the second clock signal. a counting unit receives the first clock signal, and starts counting the number of pulses of the first clock signal under the control of the first control signal, stops counting under the control of the second control signal, and obtains a counting result, the counting The result is the first clock frequency.

Compared with the prior art, the frequency test circuit has a simple structure and can be applied to a product frequency test of a production line in a large amount, and the price is relatively low.

Please refer to FIG. 1 and FIG. 2. FIG. 1 is a circuit diagram of a frequency test circuit 10 according to a preferred embodiment of the present invention. 2 is a timing chart showing the operation of the frequency test circuit 10 of the present invention. The frequency test circuit 10 is configured to test a first clock frequency of the first clock signal CLK1 input to a central processing unit (CPU). The central processing unit can be used for a computer, a server, etc. In a preferred embodiment, the first clock frequency is 32768 Hz.

The frequency test circuit 10 includes a first control unit 100, a first counting unit 110, a first latch unit 120, a first comparison unit 130, and a first indication unit 140.

The first counting unit 110 includes a first clock signal input terminal CK1, an enable terminal ENABLE and a reset terminal RST. The first clock signal input terminal CK1 receives the first clock signal CLK1, and the number of pulses of the first clock signal CLK1. Counting is performed, and the obtained counting result represents the frequency value of the first clock frequency. The enable terminal ENABLE is configured to receive the first control signal C1, and the reset terminal RST is configured to receive the second control signal C2. The first counting unit 110 starts counting the number of pulses of the first clock signal CLK1 according to the first control signal C1, and stops counting according to the second control signal C2.

The first control unit 100 includes a second clock signal input terminal CK2, a first output terminal OUT1 and a second output terminal OUT2, a second clock signal input terminal CK2 receives a second clock signal CLK2, and the second clock signal CLK2 has a second clock. The frequency, that is, the first control unit 100 operates at the second clock frequency. In this embodiment, the second clock frequency is 1 Hz. The first control unit 100 generates the first control signal C1 and the second control signal C2 according to the second clock signal CLK2, and outputs the first control signal OUT1 and the second output terminal OUT2, respectively, that is, the first control signal C1. Outputted from the first output terminal OUT1, the second control signal C2 is output from the second output terminal OUT2. The first control signal C1 is output to the first counting unit 110, and the second control signal C2 is output to the first counting unit 110 and the first latch unit 120, respectively.

Specifically, the first counting unit 110 includes a first sub-counting unit 111, a second sub-counting unit 112, a third sub-counting unit 113, a fourth sub-counting unit 114, and a fifth sub-counting unit 115.

The first sub-counting unit 111 receives the first clock signal CLK1 and the first control signal C1, and starts counting the number of pulses of the first clock signal CLK1, obtains a first count value, and determines the first count value. Whether it is equal to ten, when the first count value is equal to ten, the count value of the first sub-counting unit 111 is cleared, and the first carry signal is output to the second sub-counting unit 112.

The second sub-counting unit 112 receives the first carry signal, and each time the first carry unit receives the first carry signal, the count value of the second sub-counting unit 112 is incremented by one to obtain a second count value, and the determination Whether the second count value is equal to ten, when the second count value is equal to ten, the second sub-counting unit 112 is cleared, and outputs the second carry signal to the third sub-counting unit 113.

The third sub-counting unit 113 receives the second carry signal, and the count value is incremented by one every time the second carry signal is received, the third count value is obtained, and it is determined whether the third count value is equal to ten. When the third count value is equal to ten, the third sub-counting unit 113 is cleared, and the third carry signal is output to the fourth sub-counting unit 114.

When the fourth sub-counting unit 114 receives the third carry signal, and each time the third carry signal is received, the count value is incremented by one to obtain a fourth count value, and it is determined whether the fourth count value is equal to ten. When the fourth count value is equal to ten, the fourth sub-counting unit 114 is cleared, and outputs the fourth carry signal to the fifth sub-counting unit 115.

The fifth sub-counting unit 115 receives the fourth carry signal, and each time the fourth carry signal is received, the count value is incremented by one to obtain a fifth count value.

When the first, second, third, fourth, and fifth sub-counting units 111, 112, 113, 114, and 115 receive the second control signal C2, the counting is stopped at the same time, and the first, second, third, fourth, The five count value is output to the first latch unit 120 as the count result.

It can be understood that, in this embodiment, the count value of the first counting unit 110 may include four data output ends (not shown), and each output output end is represented by binary data, such as 0001, 0010, etc., when four outputs When the data of the terminal is 1010, it indicates that the counting value of the counting unit is ten.

The first latch unit 120 includes a latch terminal LOAD for receiving the second control signal C2, and the first latch unit 120 latches the count value of the first counting unit 110 according to the second control signal C2, and The latched data is output to the first comparison unit 130.

The first latch unit 120 includes a first sub-latch unit 121, a second sub-latch unit 122, a third sub-latch unit 123, a fourth sub-latch unit 124, and a fifth sub-latch unit 125.

The first sub-latch unit 121 is configured to receive the first count value of the first sub-count unit 111, and latch and output the first count value when the second control signal C2 is received.

The second sub-latch unit 122 receives the second count value of the second sub-counting unit 112, and latches and outputs the second count value when the second control signal C2 is received.

The third sub-latch unit 123 receives the third count value of the third sub-count unit 113, and latches and outputs the third count value when the second control signal C2 is received.

The fourth sub-latch unit 124 receives the fourth count value of the fourth sub-counting unit 114, and latches and outputs the fourth count value when the second control signal C2 is received.

The fifth sub-latch unit 125 receives the fifth count value of the fifth sub-counting unit 115, and latches and outputs the fifth count value when the second control signal C2 is received.

The first comparison unit 130 is configured to receive the counting result output by the first latch unit 120, and compare the counting result with a predetermined value to determine whether the counting result is equal to a predetermined value, and output a corresponding indication signal according to the comparison result.

Specifically, the first comparison unit 130 includes a first sub-comparison unit 131, a second sub-comparison unit 132, a third sub-comparison unit 133, a fourth sub-comparison unit 134, and a fifth sub-comparison unit 135.

The first sub-comparison unit 131 receives the first count value, and compares the first count value with the first predetermined value, and outputs a corresponding first comparison signal according to the comparison result, for example, when the first count value is equal to the first When the predetermined value is used, the first sub-comparison unit 131 outputs a high-potential signal; otherwise, when the first count value is not equal to the first predetermined value, the first sub-comparison unit 131 outputs a low-potential signal. It can be understood that the high potential and low potential signals are the indication signals. In the present embodiment, the first predetermined value is 8.

The second sub-comparison unit 132 receives the second count value, and compares the second count value with the second predetermined value, and outputs a corresponding second comparison signal according to the comparison result, for example, when the second count value is equal to the second When the predetermined value is used, the second sub-comparison unit 132 outputs a high-potential signal; otherwise, when the second count value is not equal to the second predetermined value, the second sub-comparison unit 132 outputs a low-potential signal. In the present embodiment, the second predetermined value is 6.

The third sub-comparison unit 133 receives the third count value, and compares the third count value with a third predetermined value, and outputs a corresponding third comparison signal according to the comparison result, for example, when the third count value is equal to the third When the predetermined value is used, the third sub-comparison unit 133 outputs a high-potential signal; otherwise, when the third count value is not equal to the third predetermined value, the third sub-comparison unit 133 outputs a low-potential signal. In the present embodiment, the third predetermined value is 7.

The fourth sub-comparison unit 134 receives the fourth count value, and compares the fourth count value with the fourth predetermined value, and outputs a corresponding fourth comparison signal according to the comparison result, for example, when the fourth count value is equal to the fourth When the predetermined value is used, the fourth sub-comparison unit 134 outputs a high-potential signal; otherwise, when the fourth count value is not equal to the fourth predetermined value, the fourth sub-comparison unit 134 outputs a low-potential signal. In the present embodiment, the fourth predetermined value is 2.

The fifth sub-comparison unit 135 receives the fifth count value, and compares the fifth count value with a fifth predetermined value, and outputs a corresponding fifth comparison signal according to the comparison result, for example, when the fifth count value is equal to the fifth When the predetermined value is used, the fifth sub-comparison unit 135 outputs a high-potential signal; otherwise, when the fifth count value is not equal to the fifth predetermined value, the fifth sub-comparison unit 135 outputs a high-potential signal. In the present embodiment, the fifth predetermined value is 3. It can be understood that the first, second, third, fourth, and fifth predetermined values constitute the predetermined value.

The first indicating unit 140 is configured to indicate whether the counting result of the first counting unit 110 is equal to a predetermined value, and when the counting result is not equal to the predetermined value, the first indicating unit 140 performs an indication. The first indicating unit 140 includes a power terminal Vdd, a light emitting diode 141 and a current limiting resistor 142. The power terminal Vdd is configured to receive a power signal, and the power signal may be 3V. The light emitting diode 141 and the current limiting resistor are used. 142 is connected in series between the first comparison unit 130 and the power terminal Vdd.

The cathode of the LED 141 is electrically connected to the first comparison unit 130. The anode of the LED 141 is electrically connected to the power terminal Vdd through the current limiting resistor. When the indication signal is a low potential signal, the indicator signal is a low potential signal. The light emitting diode 141 is turned on and emits light.

Compared with the prior art, the frequency test circuit has a simple structure and can be applied to a product frequency test of a production line in a large amount, and the price is relatively low.

Further, by setting the first indicating unit 140, it is possible to clearly understand whether the first clock frequency is the same as the predetermined value.

The working process of the frequency test circuit 10 will be specifically described below with reference to the timing chart of FIG.

CLK1 is the clock signal to be tested, that is, the first clock signal.

CLK2 is a second clock signal, the first control unit 100 operates under the second clock signal CLK2, and the first control unit 100 outputs a first control signal C1 according to the second clock signal CLK2, wherein the first control unit 100 causes the first control signal C1 to change to a high potential at a rising edge time t1 in each cycle of the second clock signal CLK2, and to a low potential at a continuous next rising edge time, that is, at time t2, the first control signal C1 Subsequent waveform diagrams can be deduced by analogy, and will not be described here.

The first control unit 100 outputs the second control signal C2 according to the second clock signal CLK2. The second control signal C2 is opposite to the phase of the first control signal C1, that is, the first control unit 100 makes the second control signal C2 The rising edge of the second clock signal CLK2 is at a low potential at the time of T1, and is converted to a high potential at the time of the next rising edge, at time t2. Similarly, the subsequent waveform of the second control signal C2 can be deduced by analogy. Narration.

The first clock signal CLK1 is input to the first sub-counting unit 111, and the second clock signal CLK2 is input to the first control unit 100. The first control unit 100 outputs the first control signal C1 and the second control signal C2 according to the second clock signal CLK2.

The enable terminal ENABLE of the counting unit 110 receives the first control signal C1, and the reset terminal RST receives the second control signal C2. The first counting unit 110 starts the first clock signal CLK1 at the time t1 of the first control signal C1. The number of pulses is counted, and the first counting unit 110 stops counting the first clock signal CLK1 at time t2 of the second control signal C2.

Specifically, the first sub-counting unit 111, the second sub-counting unit 112, the third sub-counting unit 113, the fourth sub-counting unit 114, and the fifth sub-counting unit 115 start counting under the first control signal C1, and The counting is stopped under the control of the second control signal C2.

The latch terminal LOAD of the first latch unit 120 receives the second control signal C2, and latches and outputs the received data at time t2 of the second control signal C2.

The first comparison unit 130 receives the data output from the first latch unit 120, and performs the data with the predetermined value, and outputs a corresponding indication signal according to the comparison result.

The first indicating unit 140 receives the indication signal. When the indication signal is low, the LED 141 is turned on and emits light for prompting.

Alternatively, the first counting unit 110 may set other number of sub-counting units according to actual needs, for example, one, two, three, four or six, etc., correspondingly, the first latch unit 120, The number of the sub-latch unit and the sub-comparison unit in the comparison unit 130 may be one, two, three, four or six, etc., and is not limited thereto.

Please refer to FIG. 3 , which is a circuit diagram of a frequency test circuit according to another embodiment of the present invention. The frequency test circuit 1 in this embodiment is different in structure from the frequency test circuit 10 of the foregoing preferred embodiment. The difference is that the frequency test circuit 1 further includes a count determination circuit 20, and the count determination circuit 20 is used for the frequency test circuit 10. normal work.

The count determination circuit includes a second control unit 200, a second counting unit 210, a second latch unit 220, a second comparison unit 230, and a second indication unit 240.

The second control unit 200 and the first control unit 100 are identical in structure and signal ,, and receive a third clock signal CLK3 (not shown). The frequency and phase of the third clock signal CLK3 and the second clock signal CLK2 are both The same is 1 Hz.

The second counting unit 210 and the first counting unit 110 are the same in structure and signal, and receive the first clock signal CLK1, and the number of pulses of the first clock signal CLK1 according to the first control signal C1 and the second control signal C2. Counting is performed to obtain a count value.

The second latch unit 220 and the first latch unit 120 are configured in the same manner as the signal 埠 and the connection manner, and the count value of the second counting unit 210 is latched and output according to the second control signal C2.

The second comparison unit 230 is configured to receive the count values of the first latch unit 120 and the second latch unit 220, and compare the count values of the first and second latch units 120, 220, when the first The second latch unit 120, 220 has the same count value, indicating that the frequency test circuit 10 counts normally, and the second comparison unit 230 outputs a high potential signal to the second indication unit 240; when the first and second latch units 120 The count value of 220 is different, indicating that the frequency test circuit 10 counts abnormally, and the second comparison unit 230 outputs a low potential signal to the second indication unit 240.

The second indication unit 240 is configured in the same manner as the first indication unit 140. The second indication unit 240 is instructed to receive the high-level signal or the low-level signal output by the second comparison unit 230. Specifically, the second indication unit 240 receives the second indication unit 240. When the high-level signal is received, the indicator light does not emit light; when the second indicator unit 240 receives the low-level signal, the indicator light is illuminated.

By setting the count determination circuit 20, it is possible to accurately determine whether the second clock frequency of the second clock signal CLK2 received by the frequency test circuit 10 is accurate, and whether the frequency test circuit 10 can count normally, improving the accuracy of the frequency test circuit 10. .

Of course, the present invention is not limited to the above-disclosed embodiments, and the present invention may be variously modified in the above embodiments. Those skilled in the art will appreciate that appropriate changes and modifications of the above embodiments are within the scope of the invention as claimed.

1,10. . . Frequency test circuit

100. . . First control unit

CK1. . . First clock signal input

OUT1. . . First output

OUT2. . . Second output

110. . . First counting unit

CK2. . . Second clock signal input

ENABLE. . . Enable end

RST. . . Reset end

111. . . First sub-counting unit

112. . . Second sub-counting unit

113. . . Third sub-count unit

114. . . Fourth sub-counting unit

115. . . Fifth sub-counting unit

120. . . First latch unit

LOAD. . . Latch end

121. . . First sub-latch unit

122. . . Second sub-latch unit

123. . . Third sub-latch unit

124. . . Fourth sub-latch unit

125. . . Fifth sub-latch unit

130. . . First comparison unit

131. . . First sub-comparison unit

132. . . Second sub-comparison unit

133. . . Third sub-comparison unit

134. . . Fourth sub-comparison unit

135. . . Fifth sub-comparison unit

140. . . First indicating unit

141. . . Light-emitting diode

142. . . Current limiting resistor

Vdd. . . Power terminal

20. . . Counting decision circuit

200. . . Second control unit

210. . . Second counting unit

220. . . Second latch unit

230. . . Second comparison unit

240. . . Second indicating unit

CLK1. . . First clock signal

CLK2. . . Second clock signal

CLK3. . . Third clock signal

C1. . . First control signal

C2. . . Second control signal

1 is a block schematic diagram of a preferred embodiment of a frequency test circuit of the present invention.

2 is a timing diagram of the frequency test circuit of the present invention.

3 is a circuit diagram of a frequency test circuit according to another embodiment of the present invention.

10. . . Frequency test circuit

100. . . First control unit

CK1. . . First clock signal input

OUT1. . . First output

OUT2. . . Second output

110. . . First counting unit

CK2. . . Second clock signal input

ENABLE. . . Enable end

RST. . . Reset end

111. . . First sub-counting unit

112. . . Second sub-counting unit

113. . . Third sub-count unit

114. . . Fourth sub-counting unit

115. . . Fifth sub-counting unit

120. . . First latch unit

LOAD. . . Latch end

121. . . First sub-latch unit

122. . . Second sub-latch unit

123. . . Third sub-latch unit

124. . . Fourth sub-latch unit

125. . . Fifth sub-latch unit

130. . . First comparison unit

131. . . First sub-comparison unit

132. . . Second sub-comparison unit

133. . . Third sub-comparison unit

134. . . Fourth sub-comparison unit

135. . . Fifth sub-comparison unit

140. . . First indicating unit

141. . . Light-emitting diode

142. . . Current limiting resistor

Vdd. . . Power terminal

Claims (12)

a frequency test circuit for testing a first clock signal of a server, the first clock signal having a first clock frequency, the frequency test circuit comprising a first control unit and a first counting unit, the first control unit working The second clock signal has a second clock frequency, and the first control unit outputs the corresponding first control signal and the second control signal to the first counting unit according to the second clock signal. a counting unit receives the first clock signal, and starts counting the number of pulses of the first clock signal under the control of the first control signal, stops counting under the control of the second control signal, and obtains a counting result, the counting The result is the first clock frequency. The frequency test circuit of claim 1, wherein the frequency test circuit further includes a first latch unit, wherein the first latch unit is configured to receive a count result of the first counting unit, and After a counting unit completes counting, the counting result is latched. The frequency test circuit of claim 2, wherein the first latch unit receives the second control signal, and latches the counting result according to the second control signal. The frequency test circuit of claim 2, wherein the frequency test circuit further comprises a first comparison unit, the first comparison unit is configured to receive the count result and compare the count result with a predetermined value, and Outputting a corresponding indication signal according to the comparison result, the predetermined value characterizing a frequency value of the stable operation of the server, and when the counting result is equal to the predetermined value, indicating that the first clock signal enables the server to work stably, when the counting result is Not equal to the first predetermined value, indicating that the first clock signal cannot make the server work stably. The frequency test circuit of claim 1, wherein the first clock frequency of the first clock signal is 32768 Hz, and the second clock frequency of the second clock signal is 1 Hz. The frequency test circuit of claim 5, wherein the first counting unit comprises a first sub-counting unit, a second sub-counting unit, a third sub-counting unit, a fourth sub-counting unit, and a fifth sub-count a unit, the first sub-counting unit receives the first clock signal and counts the number of pulses of the first clock signal to obtain a first count value, and determines whether the first count value is equal to ten, when the first count value Equal to ten, the count value of the first sub-counting unit is cleared, and the first carry signal is output to the second sub-counting unit;
The second sub-counting unit receives the first carry signal, and each time the first carry unit receives the first carry signal, the count value of the second sub-count unit is incremented by one, obtaining a second count value, and determining the first Whether the second count value is equal to ten, when the second count value is equal to ten, the second sub-count unit is cleared, and the second carry signal is output to the third sub-count unit;
The third sub-counting unit receives the second carry signal, and the count value is incremented by one every time the second carry signal is received, obtaining a third count value, and determining whether the third count value is equal to ten, when The third count value is equal to ten, the third sub-counting unit is cleared, and the third carry signal is output to the fourth sub-counting unit;
When the fourth sub-counting unit receives the third carry signal, and each time the third carry signal is received, the count value is incremented by one to obtain a fourth count value, and whether the fourth count value is equal to ten, When the fourth count value is equal to ten, the fourth sub-count unit is cleared, and the fourth carry signal is output to the fifth sub-count unit;
The fifth sub-counting unit receives the fourth carry signal, and each time the fourth carry signal is received, the count value of the fifth sub-count unit is incremented by one to obtain a fifth count value;
When the first, second, third, fourth, and fifth sub-counting units receive the second control signal, the counting is stopped at the same time, and the first, second, third, fourth, and fifth count values are used as the counting result. The frequency test circuit of any one of claims 1-6, wherein the frequency test circuit is a complex programmable logic device. The frequency test circuit of any one of the preceding claims, wherein the frequency test circuit further includes a first indicating unit, the first indicating circuit is configured to indicate a counting result of the first counting unit and the Whether the predetermined values are equal or not, the first indicating circuit indicates when the counting result is not equal to the predetermined value. The frequency test circuit of claim 8, wherein the first indicating circuit comprises a power terminal and a light emitting diode, and the light emitting diode is electrically connected between the first comparing unit and the power terminal. The power terminal is used to receive a power signal. The frequency test circuit of claim 9, wherein the cathode of the light emitting diode is electrically connected to the first comparing unit, and the anode of the light emitting diode is electrically connected to the power terminal. When the counting result is not equal to the predetermined value, the first comparing unit outputs a low potential signal, and the light emitting diode is turned on and emits light. The frequency test circuit of claim 1, further comprising a count determination circuit, wherein the count determination circuit operates under a third clock signal to test the first clock frequency to obtain a test result. The frequency of the third clock signal is the same as the frequency and phase of the second clock. The counting determining unit further determines whether the test result is the same as the counting result. When the test result is different from the counting result, the counting determining circuit performs an indication. The frequency test circuit of claim 11, wherein the count determination circuit comprises a second control unit, a second counting unit, a second latch unit, a second comparing unit, and a second indicating unit, the second The control unit is configured to receive the third clock signal, control the second counting unit to test the first clock frequency according to the third clock signal, to obtain the test result, and the second latch unit is configured to count the second clock The test result of the unit is latched and output, and the comparison unit receives the test result and compares the count result to determine whether the test result is the same as the count result.