TW201415978A - Method of forming circuit layer - Google Patents

Abstract

The invention provides a method for forming a circuit layer, comprising forming a catalytic layer on a dielectric layer; removing parts of the catalytic layer and some partial thickness at the lower parts of the dielectric layer; depositing a first metallic layer on the catalytic layer; forming a second metallic layer on the dielectric layer and the first metallic layer; removing parts of the second metallic layer that are higher than the top surface of the first metallic layer to form a circuit layer thereon, wherein the bottom surface of the circuit layer is lower than the top surface of the dielectric layer; and removing the first metallic layer and the catalytic layer, thereby a fine-pitch circuit layer with fine width threads is provided while facilitating environmental protection.

Description

Circuit layer manufacturing method

The invention relates to a method for manufacturing a circuit layer, in particular to a method for manufacturing a circuit layer with a thin line width.

With the booming electronics industry, electronic products are gradually moving towards versatility and high performance. In order to meet the requirements of high integration and miniaturization of semiconductor packages for more active and passive components and lines, semiconductor package substrates have gradually evolved from two-layer boards to multilayer circuits. Multi-layer board, which uses an interlayer connection to expand the available layout area on a semiconductor package substrate in a limited space, and can be combined with a high line density integrated circuit. The use requirements, and reduce the thickness of the package substrate, can make the package to be light and thin, and improve the electrical function.

Generally, at least one circuit layer is formed in the package substrate, and those shown in FIGS. 1A to 1J are cross-sectional views of a conventional circuit layer.

As shown in Fig. 1A, a substrate body 10 is provided having a surface line 11 formed thereon.

As shown in FIG. 1B, a dielectric layer 12 is formed on the substrate body 10 and the surface line 11.

As shown in FIG. 1C, a plurality of dielectric layer blind vias 120 of the surface line 11 are formed by laser exposure.

As shown in FIG. 1D, a conductive layer 13 is formed on the dielectric layer 12 and the surface line 11.

As shown in FIG. 1E, a resist layer 14 is formed on the conductive layer 13.

As shown in FIG. 1F, the resist layer 14 is patterned to form a plurality of barrier openings 140, and a portion of the barrier openings 140 correspondingly expose the dielectric vias 120.

As shown in FIG. 1G, the circuit layer 151 and the conductive blind via 152 are respectively formed in the barrier layer opening 140 and the dielectric layer blind via 120.

As shown in FIG. 1H, the resist layer 14 and the conductive layer 13 covered therein are removed.

As shown in FIG. 1I, an insulating protective layer 16 is formed on the dielectric layer 12 and the wiring layer 151.

As shown in FIG. 1J, a plurality of exposed insulating layer opening 160 of the wiring layer 151 is formed.

However, the conventional technology must use a resist layer to form the circuit layer, so the line width and line spacing of the circuit layer are limited by the characteristics of the resist layer itself, which is not conducive to the development of the thin line width and the fine line pitch; The chemical agent that removes the barrier layer and the barrier layer that is removed by the chemical agent are both hazardous industrial wastes, which is not environmentally friendly.

Therefore, how to overcome the various problems in the above-mentioned prior art has become a problem that is currently being solved.

In view of the above various deficiencies of the prior art, the present invention discloses a method for fabricating a wiring layer, comprising: forming a catalyst layer on a dielectric layer; removing a portion of the dielectric layer and a portion of the dielectric layer below the dielectric layer Depositing a first metal layer on the catalyst layer; forming a second metal layer on the dielectric layer and the first metal layer; removing a second metal layer higher than a top surface of the first metal layer A wiring layer is formed on the dielectric layer, the bottom surface of the wiring layer is lower than a top surface of the dielectric layer; and the first metal layer and the catalyst layer are removed.

The invention further discloses a method for fabricating another circuit layer, comprising: forming a catalyst layer on a dielectric layer; removing a portion of the dielectric layer and a portion of the dielectric layer below the dielectric layer; and the catalyst layer The metal layer is chemically deposited, and the catalyst layer and the metal layer form a circuit layer, and the bottom surface of the circuit layer is higher than the top surface of the dielectric layer on the periphery of the circuit layer.

It can be seen from the above that the present invention does not need to use a resist layer to form a circuit layer, so the line width and line spacing of the circuit layer will not be restricted by the characteristics of the resist layer itself, and is advantageous for the development of thin line width and fine line pitch; There is no chemical agent used to remove the resist layer after use and a resist layer removed by the chemical agent, so that the business waste can be reduced, thereby contributing to environmental protection.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "top", "bottom", "upper", "below", "circumference" and "one" as used in this specification are for convenience only and are not intended to be limiting. The scope of the invention can be implemented, and the change or adjustment of the relative relationship is also considered to be within the scope of the invention.

First embodiment

2A to 2I are cross-sectional views showing a first embodiment of the method of manufacturing the wiring layer of the present invention.

As shown in FIG. 2A, a substrate body 20 is provided having a surface line 21 formed thereon, and the dielectric layer 22 is formed on the substrate body 20 and the surface line 21.

As shown in FIG. 2B, a catalyst layer 23 is deposited on the dielectric layer 22, and the material of the catalyst layer 23 may include palladium.

As shown in FIG. 2C, a portion of the dielectric layer 23 and a portion (small amount) of the dielectric layer 22 are removed to form a dielectric layer recess 221 and a dielectric layer of the exposed portion of the surface line 21. The blind holes 220 are removed and the catalyst layer 23 is removed by laser or sand blasting.

As shown in FIG. 2D, a first metal layer 24 is chemically deposited on the catalyst layer 23, and the material of the first metal layer 24 may be metal nickel, chromium, tin, zinc, cadmium, lead, gold, platinum, silver. , cobalt, manganese, antimony, bismuth, gallium, indium, antimony, bismuth, antimony, bismuth, antimony, bismuth, tungsten, aluminum, titanium, zirconium, molybdenum, niobium, tantalum, or alloy tin-lead, tin-lead- Antimony, tin-lead-zinc, nickel-tin, nickel-cobalt.

As shown in FIG. 2E, a conductive layer 25 is formed on the dielectric layer 22, the surface line 21, and the first metal layer 24.

As shown in FIG. 2F, a second metal layer 26 is formed on the conductive layer 25, and the material of the second metal layer 26 may be copper.

As shown in FIG. 2G, the second metal layer 26 and the conductive layer 25 are removed from the top surface of the first metal layer 24 to form a wiring layer 262 on the dielectric layer 22, and the second metal layer 26 is further formed. Filling the dielectric layer blind hole 220 to form a conductive blind hole 261 electrically connected to the surface line 21, and the bottom surface of the circuit layer 262 is lower than the top surface of the dielectric layer 22, and the removal is higher than the first The second metal layer 26 on the top surface of the metal layer 24 may be in the form of chemical mechanical polishing (CMP).

The first metal layer 24 and the catalyst layer 23 are removed as shown in FIG. 2H.

As shown in FIG. 2I, an insulating protective layer 27 is formed on the dielectric layer 22 and the wiring layer 262, and the insulating protective layer 27 has a plurality of exposed insulating insulating layer openings 270 of the wiring layer 262.

Second embodiment

3A to 3E are cross-sectional views showing a second embodiment of the method of manufacturing the wiring layer of the present invention.

As shown in FIG. 3A, a substrate body 30 is provided, on which a surface line 31 is formed, a dielectric layer 32 is formed on the substrate body 30 and the surface line 31, and the surface line 31 is formed with an embedded layer. A conductive blind via 33 in the electrical layer 32 and exposed on the surface of the dielectric layer 32.

As shown in FIG. 3B, a catalyst layer 34 is formed on the dielectric layer 32 and the conductive via hole 33. The material of the catalyst layer 34 may include palladium.

As shown in FIG. 3C, a portion of the catalyst layer 34 and a portion (small amount) of the dielectric layer 32 below the thickness of the dielectric layer 34 are removed to form the dielectric layer recess 320, and the catalyst layer 34 is removed. Laser or sandblasting can be used.

As shown in FIG. 3D, a metal layer 35 is chemically deposited on the catalyst layer 34, and the catalyst layer 34 and the metal layer 35 form a circuit layer 36. The bottom surface of the circuit layer 36 is higher than the periphery of the circuit layer 36. The top surface of the dielectric layer 32, and the conductive blind hole 33 is electrically connected to the surface line 31 and the circuit layer 36. The material of the metal layer 35 may be copper.

As shown in FIG. 3E, an insulating protective layer 37 is formed on the dielectric layer 32 and the wiring layer 36, and the insulating protective layer 37 has a plurality of exposed insulating layer opening holes 370 of the wiring layer 36.

It should be noted that the implementation of the present invention is not applicable to the presence of the substrate body, surface lines or conductive blind vias, and any circuit layer formed on the dielectric layer is applicable; further, the present invention does not In the embodiment, the circuit layer-adding step may be further performed after forming the circuit layer as shown in FIG. 2H or 3D and before forming the insulating protective layer, for example, covering the dielectric layer and forming another layer thereon. The method of the present invention can also be utilized in the manner of forming a circuit layer or the like and forming the other circuit layer.

In summary, compared with the prior art, the present invention does not need to use a resist layer to form a circuit layer, so the line width and line spacing of the circuit layer will not be limited by the characteristics of the resist layer itself, but is advantageous for the thin line width and the thin line spacing. Further, in the present invention, the chemical agent for removing the resist layer after use and the resist layer removed by the chemical agent are not used, so that the business waste can be reduced, thereby contributing to environmental protection.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10,20,30. . . Substrate body

11,21,31. . . Surface line

12,22,32. . . Dielectric layer

120. . . Dielectric hole

13,25. . . Conductive layer

14. . . Resistance layer

140. . . Resistive opening

151,262,36. . . Circuit layer

152,261,33. . . Conductive blind hole

16,27,37. . . Insulating protective layer

160,270,370. . . Insulating protective layer opening

23,34. . . Catalyst layer

220. . . Dielectric hole

221,320. . . Dielectric layer groove

twenty four. . . First metal layer

26. . . Second metal layer

35. . . Metal layer

1A to 1J are cross-sectional views showing a method of manufacturing a conventional wiring layer;

2A to 2I are cross-sectional views showing a first embodiment of the method of fabricating the circuit layer of the present invention;

3A to 3E are cross-sectional views showing a second embodiment of the method of manufacturing the wiring layer of the present invention.

20. . . Substrate body

twenty one. . . Surface line

twenty two. . . Dielectric layer

220. . . Dielectric hole

221. . . Dielectric layer groove

25. . . Conductive layer

26. . . Second metal layer

261. . . Conductive blind hole

262. . . Circuit layer

Claims (13)

A method for manufacturing a circuit layer includes:
Forming a catalyst layer on a dielectric layer;
Removing a portion of the dielectric layer and a portion of the thickness of the dielectric layer below;
Depositing a first metal layer on the catalyst layer;
Forming a second metal layer on the dielectric layer and the first metal layer;
Removing a second metal layer higher than a top surface of the first metal layer to form a circuit layer on the dielectric layer, the bottom surface of the circuit layer being lower than a top surface of the dielectric layer; and removing the first Metal layer and catalyst layer. The method for manufacturing a circuit layer according to claim 1, wherein before forming the catalyst layer, a substrate body is formed on which a surface line is formed, and the dielectric layer is formed on the substrate body and the surface line. Removing the partial thickness of the dielectric layer includes forming a dielectric layer blind via of the exposed portion of the surface line, and the second metal layer is filled into the dielectric layer blind via to form a conductive blind electrically connecting the surface line hole. The method for manufacturing a circuit layer according to claim 1, further comprising forming an insulating protective layer on the dielectric layer and the circuit layer, and the insulating protective layer has a plurality of exposed portions of the insulating protective layer opening of the circuit layer. The method for manufacturing a circuit layer according to claim 1, wherein the material of the catalyst layer comprises palladium. The method of fabricating a circuit layer according to claim 1, wherein the method of removing the second metal layer higher than the top surface of the first metal layer is chemical mechanical polishing. The method of fabricating a circuit layer according to claim 1, wherein the second metal layer is formed by electroplating. The method of fabricating a circuit layer according to claim 1, wherein the portion of the dielectric layer and a portion of the dielectric layer below the thickness of the catalyst layer is removed by laser or sand blasting. A method for manufacturing a circuit layer includes:
Forming a catalyst layer on a dielectric layer;
Removing a portion of the dielectric layer and a portion of the dielectric layer below the dielectric layer; and depositing a metal layer on the catalyst layer, and the catalyst layer and the metal layer forming a circuit layer, the underlying layer of the circuit layer A top surface of the dielectric layer above the perimeter of the circuit layer. The method for manufacturing a circuit layer according to claim 8, wherein before forming the catalyst layer, a substrate body is formed on which a surface line is formed, and the dielectric layer is formed on the substrate body and the surface line, and A conductive via hole embedded in the dielectric layer and exposed on a surface of the dielectric layer is formed on the surface line, and the conductive via hole is formed on the conductive via hole, and the conductive blind via is electrically connected to the surface line With the circuit layer. The method for manufacturing a circuit layer according to claim 8 is characterized in that the insulating layer is formed on the dielectric layer and the circuit layer, and the insulating protective layer has a plurality of exposed portions of the insulating layer of the circuit layer. The method for manufacturing a circuit layer according to claim 8, wherein the material of the catalyst layer comprises palladium. The method for manufacturing a circuit layer according to claim 8, wherein the material of the metal layer is copper. The method of fabricating a circuit layer according to claim 8, wherein the portion of the dielectric layer and a portion of the dielectric layer below the thickness of the catalyst layer is removed by laser or sand blasting.