TW201415635A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

A method for manufacturing semiconductor device is provided, including: forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film in periphery of the fin-shaped silicon layer, forming a columnar silicon layer on an upper part of the fin-shaped silicon layer; forming a gate insulating film, a gate electrode and a gate wiring, wherein the gate insulating film is formed in periphery of the columnar silicon layer, the gate electrode is formed in periphery of the gate insulating film, and the gate wiring is connected to the gate electrode; forming a first diffusion layer on an upper part of the columnar silicon layer, and forming a second diffusion layer on a lower part of the columnar silicon layer and an upper part of the fin-shaped silicon layer; forming a first silicide and a second silicide on the first diffusion layer and the second diffusion layer; accumulating an inter-layer insulating film, flattening the inter-layer insulating film, conducting etching back, forming a fifth resist for forming a first contact after exposing the upper part of the columnar silicon layer, and forming a sixth resist for forming a metal wiring.

Description

Semiconductor device manufacturing method and semiconductor device

The present invention relates to a method of fabricating a semiconductor device and a semiconductor device.

A semiconductor integrated circuit, in particular, an integrated circuit using a metal-oxide semiconductor (MOS) transistor is tending to be highly integrated. Along with this high integration, the MOS transistor micronization used therein has progressed to the nano region. When the miniaturization of such a MOS transistor is developed, there is a problem in that it is difficult to suppress a leak current, and the area occupied by the circuit cannot be made very small because the required amount of current is required. In order to solve the above problems, a Surrounding Gate Transistor (hereinafter referred to as "SGT") has been proposed, which has a structure in which a source, a gate, and a gate are arranged in a vertical direction with respect to a substrate. A structure in which a gate electrode surrounds a columnar semiconductor layer (for example, refer to Patent Document 1, Patent Document 2, and Patent Document 3).

In the existing SGT manufacturing method, due to the depth of the contact Different from each other, a contact hole in the upper portion of the mast and a contact hole in the flat layer on the lower portion of the mast are formed (for example, refer to Patent Document 4). Since they are formed separately, the number of steps is increased.

Although the contact holes on the upper part of the mast and the flat layer on the lower part of the mast are respectively formed, if the contact hole in the upper part of the mast is over-etched, there is a possibility of reaching the gate electrode, and if the etching is insufficient There is a possibility that the upper part of the mast is insulated from the contact portion.

Further, since the contact hole on the planar ruthenium layer at the lower portion of the mast is deep, it is difficult to fill the contact hole. Moreover, it is difficult to form deep contact holes.

Further, in the conventional SGT manufacturing method, a nitride film hard mask forms a column, and the column is formed in a columnar shape. After forming a diffusion layer at the lower portion of the column, the gate material is deposited, and then the gate is stacked. The pole material is planarized and etched back to form an insulating film sidewall on the sidewall of the mast and the nitride film hard mask. Then, a resist pattern for the gate wiring is formed, and after the gate material is etched, the nitride film is hard-mask removed to form a diffusion layer on the upper portion of the mast (for example, refer to the patent document 5).

In the above method, when the column spacing is narrowed, a thick gate material must be deposited between the columns, so that a hole called a void is sometimes formed between the columns. If voids are formed, holes will be formed in the gate material after etch back. Then, if an insulating film is deposited in order to form the sidewall of the insulating film, the insulating film is deposited in the void. Therefore, the gate material processing is difficult.

Therefore, it is proposed that after the formation of the column, a gate oxide film is formed, and the deposition is thin. After the polysilicon, covering the upper portion of the mast to form a resist for forming the gate wiring, etching the gate wiring, and then depositing a thick oxide film to expose the upper portion of the mast, and The thin polycrystalline silicon in the upper portion of the mast is removed, and the thick oxide film is removed by wet etching (see, for example, Non-Patent Document 1).

However, a method for using metal in a gate electrode is not shown. Moreover, it is necessary to cover the upper portion of the mast to form a resist for forming the gate wiring, and therefore, it is necessary to cover the upper portion of the mast without a self aligned process.

Further, in order to reduce the parasitic capacitance between the gate wiring and the substrate, the first insulating film is used in the conventional MOS transistor. For example, in a Fin Field-Effect Transistor (FINFET) (Non-Patent Document 2), a first insulating film is formed around one fin-shaped semiconductor layer, and the first insulating film is etched back. The fin-shaped semiconductor layer is exposed to reduce the parasitic capacitance between the gate wiring and the substrate. Therefore, in the SGT, in order to reduce the parasitic capacitance between the gate wiring and the substrate, it is necessary to use the first insulating film. The SGT has a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, and therefore a method for forming a columnar semiconductor layer is required.

Prior technical literature Patent literature

Patent Document 1: Japanese Patent Laid-Open No. 2-71556

Patent Document 2: Japanese Patent Laid-Open No. Hei 2-188966

Patent Document 3: Japanese Patent Laid-Open No. Hei 3-145761

Patent Document 4: Japanese Patent Laid-Open Publication No. 2012-004244

Patent Document 5: Japanese Patent Laid-Open Publication No. 2009-182317

Non-Patent Document 1: B.Yang, KDBuddharaju, SHGTeo, N.Singh, GDLo, and DLKwong, "Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET) ", IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp 791-794.

Non-Patent Document 2: High performance 22/20 nm fin field effect transistor CMOS device with advanced high dielectric constant/metal gate design (High performance 22/20 nm FinFET CMOS devices with advanced high-K/metal gate scheme) ), International Electron Devices Meeting (IEDM) 2010 CC. Wu et al., 27.1.1-27.1.4.

Therefore, an object of the present invention is to provide a method for manufacturing an SGT in which a contact portion between a gate wiring and a substrate is not formed, and a metal wiring is directly connected to an upper portion of a columnar layer, and The structure of the SGT obtained by this manufacturing method.

A method of manufacturing a semiconductor device according to the present invention includes the first step of forming a fin-shaped germanium layer on a germanium substrate, forming a first insulating film around the fin-shaped germanium layer, and upper portion of the finned germanium layer Forming a columnar layer; in the second step, forming a gate insulating film, a gate electrode, and a gate line, wherein the gate insulating film is formed around the columnar layer, and the gate electrode is formed on the gate insulating film In the third step, the gate wiring is connected to the gate electrode; and in the third step, a first diffusion layer is formed on the upper portion of the columnar layer, and the fin is formed on the lower portion of the columnar layer a second diffusion layer is formed on the upper portion of the ruthenium layer; and a first ruthenium compound and a second ruthenium compound are formed on the first diffusion layer and the second diffusion layer in the fourth step; and the fifth step, after the fourth step An interlayer insulating film is deposited, and the interlayer insulating film is planarized and etched back to expose the upper portion of the columnar layer, and after the upper portion of the columnar layer is exposed, a fifth electrode for forming the first contact portion is formed. The etching agent forms a contact hole by etching the interlayer insulating film, and forms a first contact portion on the second germanide by depositing a metal, and forms a sixth resist for forming a metal wiring. The above metal wiring is formed by etching.

Further, in the first step, the width of the columnar layer is the same as the width of the fin layer.

In the first step, a first resist for forming a fin-shaped germanium layer is formed on the germanium substrate, and the germanium substrate is etched to form the fin-shaped germanium layer, and the first resist is removed. A first insulating film is deposited around the fin-shaped germanium layer, and the first insulating film is etched back to expose an upper portion of the fin-shaped germanium layer, and a second resist is formed to be orthogonal to the fin-shaped germanium layer. The fin layer is etched to remove the second resist, and the columnar layer is formed such that the portion perpendicular to the fin layer and the second resist is the columnar layer.矽 layer.

In the second step, a gate insulating film is formed around the columnar layer, and a metal film and a polysilicon film are formed around the gate insulating film, and a thickness of the polysilicon film is thinner than a width of the columnar layer And forming a third resist for forming a gate wiring, forming the gate wiring by performing anisotropic etching, depositing a fourth resist, and exposing the polysilicon film on the upper sidewall of the columnar layer ,borrow The exposed polysilicon film is removed by etching, and the fourth resist is peeled off, and the metal film is removed by etching to form a gate electrode connected to the gate wiring.

Further, a semiconductor device of the present invention includes: a fin-shaped germanium layer formed on a germanium substrate; a first insulating film formed around the fin-shaped germanium layer; and a columnar germanium layer formed on the fin-shaped germanium layer And the width of the columnar layer is the same as the width of the fin layer; the gate insulating film is formed around the columnar layer; the gate electrode is formed around the gate insulating film; The pole wiring extends in a direction orthogonal to the fin-shaped layer connected to the gate electrode; the first diffusion layer is formed on an upper portion of the columnar layer; and the second diffusion layer is formed on the fin-shaped layer An upper portion of the layer and a lower portion of the columnar layer; a first telluride formed on an upper portion of the first diffusion layer; a second telluride formed on an upper portion of the second diffusion layer; and a first contact portion formed on the first portion 2. The first metal wiring is formed on the first germanide; and the second metal wiring is formed on the first contact.

Further, a semiconductor device according to the present invention includes a gate electrode, and the gate electrode includes a laminated structure of a metal film and a polysilicon film formed around the gate insulating film, and a film thickness of the polysilicon film is larger than a width of the columnar layer thin.

Further, the depth of the first contact portion is lower than the height of the columnar layer.

According to the present invention, there is provided a method of manufacturing an SGT in which a parasitic capacitance between a gate wiring and a substrate is reduced, and a contact portion of the upper portion of the columnar layer is not formed, and a metal wiring is directly connected to an upper portion of the columnar layer, and the method is provided. And get the structure of the SGT.

Since the metal wiring is directly connected to the upper portion of the columnar layer, it is not necessary to form a contact portion on the upper portion of the columnar layer.

Further, since the metal wiring is directly connected to the upper portion of the columnar layer, the depth of the contact hole for the first contact portion can be made shallow, and thus the contact hole can be easily formed, and the contact hole can be easily filled with metal.

Further, since the formation of the fin-shaped ruthenium layer, the first insulating film, and the columnar ruthenium layer is based on the conventional FINFET manufacturing method, it can be easily formed.

Further, the self-alignment process is performed by the second step of forming a gate insulating film around the columnar layer, forming a metal film and a polysilicon film around the gate insulating film, and the polysilicon film The film thickness is thinner than the width of the columnar tantalum layer, and a third resist for forming a gate wiring is formed, and the gate wiring is formed by anisotropic etching, and the fourth resist is deposited to cause the above-mentioned The polysilicon film on the upper side wall of the columnar layer is exposed, the exposed polysilicon film is removed by etching, the fourth resist is peeled off, and the metal film is removed by etching to form a gate electrode. Gate electrode. Due to the self-alignment process, high integration is possible.

101‧‧‧矽 substrate

102‧‧‧1st resist

103‧‧‧Finned layer

104‧‧‧1st insulating film

105‧‧‧2nd resist

106‧‧‧ Columnar layer

107‧‧‧gate insulating film

108‧‧‧Metal film

109‧‧‧Polysilicon film

110‧‧‧3rd resist

111a‧‧‧gate electrode

111b‧‧‧ gate wiring

112‧‧‧4th resist

113‧‧‧2nd diffusion layer

114‧‧‧1st diffusion layer

115‧‧‧ nitride film

116a, 116b‧‧‧ nitride film sidewall

117‧‧‧2nd telluride

118‧‧‧1st telluride

119, 120‧‧‧ Telluride

121‧‧‧Interlayer insulating film

122‧‧‧5th resist

123, 124‧‧‧ contact holes

127, 129‧‧1 first contact

130‧‧‧Metal

131, 132, 133‧‧‧ sixth resist

134, 135, 136‧‧‧ metal wiring

140‧‧‧Contact barrier

X-x', y-y'‧‧‧ line

Fig. 1(a) is a plan view showing a semiconductor device of the present invention. Fig. 1(b) is a cross-sectional view taken along the line x-x' of Fig. 1(a). Fig. 1(c) is a cross-sectional view taken along line y-y' of Fig. 1(a).

Fig. 2 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. figure 2 (b) is a cross-sectional view taken at the line x-x' of Fig. 2(a). Fig. 2(c) is a cross-sectional view taken along line y-y' of Fig. 2(a).

Fig. 3 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 3(b) is a cross-sectional view taken along the line x-x' of Fig. 3(a). Fig. 3(c) is a cross-sectional view taken along line y-y' of Fig. 3(a).

Fig. 4 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 4(b) is a cross-sectional view taken along the line x-x' of Fig. 4(a). Fig. 4(c) is a cross-sectional view taken along line y-y' of Fig. 4(a).

Fig. 5 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 5(b) is a cross-sectional view taken along the line x-x' of Fig. 5(a). Fig. 5(c) is a cross-sectional view taken along line y-y' of Fig. 5(a).

Fig. 6 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 6(b) is a cross-sectional view taken along the line x-x' of Fig. 6(a). Fig. 6(c) is a cross-sectional view taken along line y-y' of Fig. 6(a).

Fig. 7 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 7(b) is a cross-sectional view taken along the line x-x' of Fig. 7(a). Fig. 7(c) is a cross-sectional view taken along line y-y' of Fig. 7(a).

Fig. 8 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 8(b) is a cross-sectional view taken along the line x-x' of Fig. 8(a). Fig. 8(c) is a cross-sectional view taken along line y-y' of Fig. 8(a).

Fig. 9 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 9(b) is a cross-sectional view taken along the line x-x' of Figure 9(a). Figure 9(c) is the view of Figure 9(a) Sectional view at the y-y' line.

Fig. 10 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 10 (b) is a cross-sectional view taken along the line x-x' of Fig. 10 (a). Fig. 10 (c) is a cross-sectional view taken along line y-y' of Fig. 10 (a).

Fig. 11 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 11(b) is a cross-sectional view taken along the line x-x' of Figure 11(a). Figure 11 (c) is a cross-sectional view taken along line y-y' of Figure 11 (a).

Fig. 12 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 12(b) is a cross-sectional view taken along the line x-x' of Figure 12(a). Fig. 12 (c) is a cross-sectional view taken along line y-y' of Fig. 12 (a).

Fig. 13 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 13 (b) is a cross-sectional view taken along the line x-x' of Fig. 13 (a). Fig. 13 (c) is a cross-sectional view taken along line y-y' of Fig. 13 (a).

Fig. 14 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 14 (b) is a cross-sectional view taken along the line x-x' of Fig. 14 (a). Fig. 14 (c) is a cross-sectional view taken along line y-y' of Fig. 14 (a).

Fig. 15 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 15 (b) is a cross-sectional view taken along the line x-x' of Fig. 15 (a). Fig. 15 (c) is a cross-sectional view taken along line y-y' of Fig. 15 (a).

Fig. 16 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 16 (b) is a cross-sectional view taken along the line x-x' of Fig. 16 (a). Figure 16 (c) is a cross-sectional view taken along line y-y' of Figure 16 (a).

Fig. 17 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 17 (b) is a cross-sectional view taken along the line x-x' of Fig. 17 (a). Figure 17 (c) is a cross-sectional view taken along line y-y' of Figure 17 (a).

Fig. 18 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 18(b) is a cross-sectional view taken along the line x-x' of Figure 18(a). Figure 18(c) is a cross-sectional view taken along line y-y' of Figure 18(a).

Fig. 19 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 19 (b) is a cross-sectional view taken along the line x-x' of Fig. 19 (a). Fig. 19 (c) is a cross-sectional view taken along line y-y' of Fig. 19 (a).

Fig. 20 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 20(b) is a cross-sectional view taken along the line x-x' of Figure 20(a). Fig. 20 (c) is a cross-sectional view taken along line y-y' of Fig. 20 (a).

Fig. 21 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 21 (b) is a cross-sectional view taken along the line x-x' of Fig. 21 (a). Fig. 21 (c) is a cross-sectional view taken along line y-y' of Fig. 21 (a).

Fig. 22 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 22 (b) is a cross-sectional view taken along the line x-x' of Fig. 22 (a). Fig. 22 (c) is a cross-sectional view taken along line y-y' of Fig. 22 (a).

Fig. 23 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 23 (b) is a cross-sectional view taken along the line x-x' of Fig. 23 (a). Fig. 23 (c) is a cross-sectional view taken along line y-y' of Fig. 23 (a).

Fig. 24 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 24(b) is a cross-sectional view taken along the line x-x' of Fig. 24(a). Fig. 24 (c) is a cross-sectional view taken along line y-y' of Fig. 24 (a).

Fig. 25 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 25(b) is a cross-sectional view taken along the line x-x' of Figure 25(a). Fig. 25 (c) is a cross-sectional view taken along line y-y' of Fig. 25 (a).

Fig. 26 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 26 (b) is a cross-sectional view taken along the line x-x' of Fig. 26 (a). Fig. 26 (c) is a cross-sectional view taken along line y-y' of Fig. 26 (a).

Fig. 27 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 27 (b) is a cross-sectional view taken along the line x-x' of Fig. 27 (a). Fig. 27 (c) is a cross-sectional view taken along line y-y' of Fig. 27 (a).

Fig. 28 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 28 (b) is a cross-sectional view taken along the line x-x' of Fig. 28 (a). Figure 28(c) is a cross-sectional view taken along line y-y' of Figure 28(a).

Fig. 29 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 29 (b) is a cross-sectional view taken along the line x-x' of Fig. 29 (a). Figure 29 (c) is a cross-sectional view taken along line y-y' of Figure 29 (a).

Fig. 30 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Fig. 30 (b) is a cross-sectional view taken along the line x-x' of Fig. 30 (a). Fig. 30 (c) is a cross-sectional view taken along line y-y' of Fig. 30 (a).

Fig. 31 (a) is a plan view showing a method of manufacturing a semiconductor device of the present invention. Figure 31 (b) is a cross-sectional view taken along the line x-x' of Figure 31 (a). Figure 31 (c) is Figure 31 (a) Sectional view at the y-y' line.

Hereinafter, a manufacturing procedure of a structure for forming an SGT according to an embodiment of the present invention will be described with reference to FIGS. 2(a) to 2(c) to 31(a) to 31(c).

First, a manufacturing method is described in which a fin-shaped germanium layer 103 is formed on the germanium substrate 101, a first insulating film 104 is formed around the fin-shaped germanium layer 103, and a columnar crucible is formed on the upper portion of the fin-shaped germanium layer 103. Layer 106. As shown in FIGS. 2(a) to 2(c), a first resist 102 for forming a fin-shaped germanium layer is formed on the germanium substrate 101.

As shown in FIGS. 3(a) to 3(c), the germanium substrate 101 is etched to form a fin-shaped germanium layer 103. Here, the fin layer is formed by using the resist as a mask, but a hard mask such as an oxide film or a nitride film may be used.

As shown in FIGS. 4(a) to 4(c), the first resist 102 is removed.

As shown in FIGS. 5(a) to 5(c), the first insulating film 104 is deposited around the fin-shaped germanium layer 103. As the first insulating film, an oxide film from a high-density plasma or an oxide film from a low-pressure chemical vapor deposition may be used.

As shown in FIGS. 6(a) to 6(c), the first insulating film 104 is etched back to expose the upper portion of the fin-shaped germanium layer 103. Up to this point, the method of manufacturing the fin-shaped enamel layer of Non-Patent Document 2 is the same.

As shown in FIGS. 7( a ) to 7 ( c ), the second resist 105 is formed to be orthogonal to the fin-shaped germanium layer 103 . The portion of the fin-shaped germanium layer 103 that is orthogonal to the second resist 105 is a portion that becomes a columnar layer. Because a linear resist can be used, the pattern The possibility of resist collapse after the formation is low, and it becomes a stable process.

As shown in FIGS. 8(a) to 8(c), the fin-shaped germanium layer 103 is etched. A portion of the fin-shaped germanium layer 103 that is orthogonal to the second resist 105 is a columnar layer 106. Therefore, the width of the columnar layer 106 is the same as the width of the fin layer. The structure is such that a columnar layer 106 is formed on the upper portion of the fin layer 103, and a first insulating film 104 is formed around the fin layer 103.

As shown in FIGS. 9(a) to 9(c), the second resist 105 is removed.

Next, a gate insulating film 107 is formed around the columnar layer 106, and a metal film 108 and a polysilicon film 109 are formed around the gate insulating film 107. The film thickness of the polysilicon film 109 is thinner than the width of the columnar layer. A manufacturing method is described in which a third resist 110 for forming a gate wiring 111b is formed, a gate wiring 111b is formed by anisotropic etching, and a fourth resist 112 is deposited to form a columnar crucible The polysilicon film 109 on the upper side wall of the layer 106 is exposed, the exposed polysilicon film 109 is removed by etching, the fourth resist 112 is peeled off, and the metal film 108 is removed by etching to form a gate connected to the gate wiring 111b. Electrode 111a.

As shown in FIGS. 10(a) to 10(c), a gate insulating film 107 is formed around the columnar layer 106, and a metal film 108 and a polysilicon film 109 are formed around the gate insulating film 107. At this time, a thin polycrystalline germanium film 109 is used. Therefore, formation of voids in the polysilicon film can be prevented. The thickness of the thin polycrystalline germanium film 109 is preferably 20 nm or less. The metal film 108 may be a metal such as titanium nitride used in the semiconductor step and setting a threshold voltage of the transistor. The gate insulating film 107 is used for a semiconductor manufacturing step as long as it is an oxide film, an oxynitride film, or a high dielectric film. The film in the step can be used.

As shown in FIGS. 11(a) to 11(c), a third resist 110 for forming the gate wiring 111b is formed. In this embodiment, it is described that the resist height is higher than the columnar layer. As the width of the gate wiring becomes thinner, the polysilicon in the upper portion of the columnar layer is easily exposed. The resist height can also be lower than the columnar layer.

As shown in FIGS. 12(a) to 12(c), the polysilicon film 109 and the metal film 108 are etched. A gate electrode 111a and a gate wiring 111b are formed. At this time, if the thickness of the resist on the upper portion of the columnar layer is thin or the polysilicon in the upper portion of the columnar layer is exposed, the upper portion of the columnar layer may be etched during etching. At this time, it is desirable to make the height of the columnar tantalum layer when forming the columnar tantalum layer the same as the sum of the desired height of the columnar tantalum layer and the height of the portion to be cut in the gate wiring etching thereafter. Therefore, the manufacturing steps of the present invention become a self-aligning process.

As shown in FIGS. 13(a) to 13(c), the third resist was peeled off.

As shown in FIGS. 14(a) to 14(c), the fourth resist 112 is deposited to expose the polysilicon film 109 on the upper side wall of the columnar layer 106. It is preferred to use resist etch back. Further, a coating film such as a spin-on-glass can also be used.

As shown in FIGS. 15(a) to 15(c), the exposed polysilicon film 109 is removed by etching. Isotropic dry etching is preferred.

As shown in FIGS. 16(a) to 16(c), the fourth resist 112 is peeled off.

As shown in FIGS. 17(a) to 17(c), the metal film 108 is removed by etching, and the metal film 108 remains on the side wall of the columnar layer 106. Preferably isotropic Sexual etching. The gate electrode 111a is formed by the metal film 108 of the sidewall of the columnar layer 106 and the polysilicon film 109. Therefore, it becomes a self-alignment process.

According to the above, a manufacturing method is described in which a gate insulating film 107 is formed around the columnar layer 106, and a metal film 108 and a polysilicon film 109 are formed around the gate insulating film 107, and the film thickness ratio of the polysilicon film 109 is formed. The columnar tantalum layer has a small width and forms a third resist 110 for forming the gate wiring 111b. The gate wiring 111b is formed by anisotropic etching, and the fourth resist 112 is deposited to form a columnar shape. The polysilicon film 109 on the upper side wall of the germanium layer 106 is exposed, the exposed polysilicon film 109 is removed by etching, the fourth resist 112 is peeled off, and the metal film 108 is removed by etching to form a gate electrode 111b. Gate electrode 111a.

Next, a manufacturing method is described in which the first diffusion layer 114 is formed on the upper portion of the columnar layer 106, and the second diffusion layer 113 is formed on the lower portion of the columnar layer 106 and the upper portion of the fin layer 103.

As shown in FIGS. 18(a) to 18(c), arsenic is implanted to form the first diffusion layer 114 and the second diffusion layer 113. In the case of pMOS, boron or boron fluoride is implanted.

As shown in FIGS. 19(a) to 19(c), the nitride film 115 is deposited and heat-treated. An oxide film can also be used instead of the nitride film.

As described above, the manufacturing method is described in which the first diffusion layer 114 is formed on the upper portion of the columnar layer 106, and the second diffusion layer 113 is formed on the lower portion of the columnar layer 106 and the upper portion of the fin layer 103.

Next, a manufacturing method is shown in which the first diffusion layer 114 and the first The first germanide 118 and the second germane 117 are formed on the diffusion layer 113, respectively.

As shown in FIGS. 20(a) to 20(c), the nitride film 115 is etched to form a sidewall shape, and the gate insulating film 107 is etched, thereby forming a nitride film sidewall 116a and a nitride film sidewall. 116b.

Next, as shown in FIGS. 21(a) to 21(c), metal is deposited and heat-treated to remove unreacted metal, thereby forming the first diffusion layer 114, the second diffusion layer 113, and the gate wiring. The first telluride 118, the second telluride 117, and the telluride 119 are formed on 111b. When the upper portion of the gate electrode 111a is exposed, the germanide 120 is formed on the upper portion of the gate electrode 111a.

Since the polysilicon film 109 is thin, the gate wiring 111b is likely to have a laminated structure of the metal film 108 and the germanide 119. Since the telluride 119 is in direct contact with the metal film 108, it is possible to achieve low resistance.

As described above, the manufacturing method is described in which the first germanide 118 and the second germanide 117 are formed on the first diffusion layer 114, the second diffusion layer 113, and the gate wiring 111b.

Next, a manufacturing method is disclosed in which the interlayer insulating film 121 is deposited, and the interlayer insulating film 121 is planarized and etched back to expose the upper portion of the columnar layer 106, and the upper portion of the columnar layer 106 is exposed to be formed. The fifth resist 122 forming the first contact portion 127 is formed by etching the interlayer insulating film 121 to form the contact hole 123, and the first contact portion 127 is formed on the second germane 117 by depositing the metal 130. And forming a sixth resist 131, a sixth resist 132, and a sixth resist 133 for forming the metal wiring 134, the metal wiring 135, and the metal wiring 136, The metal wiring 134, the metal wiring 135, and the metal wiring 136 are formed by etching.

As shown in FIGS. 22(a) to 22(c), a contact stopper 140 such as a nitride film is formed to form an interlayer insulating film 121.

As shown in FIGS. 23(a) to 23(c), etch back is performed to expose the contact barrier layer 140 on the columnar layer 106.

As shown in FIGS. 24(a) to 24(c), a fifth resist 122 for forming the contact holes 123 and the contact holes 124 is formed.

As shown in FIGS. 25(a) to 25(c), the interlayer insulating film 121 is etched to form contact holes 123 and contact holes 124.

As shown in FIGS. 26(a) to 26(c), the fifth resist 122 is peeled off.

As shown in FIGS. 27(a) to 27(c), the contact barrier layer 140 is etched, and the contact hole 123, the contact barrier layer 140 under the contact hole 124, and the contact barrier layer on the columnar layer 106 are formed. Remove.

As shown in FIGS. 28( a ) to 28 ( c ), the metal 130 is deposited to form the first contact portion 127 and the first contact portion 129 . At this time, since the metal wiring is directly connected to the upper portion of the columnar layer, it is not necessary to form a contact portion on the upper portion of the columnar layer. Further, since the depth of the contact hole for the first contact portion can be made shallow, the contact hole can be easily formed, and the contact hole can be easily filled with metal.

As shown in FIGS. 29(a) to 29(c), a sixth resist 131, a sixth resist 132, and a sixth resist 133 for forming metal wirings are formed.

As shown in FIGS. 30( a ) to 30 ( c ), the metal 130 is etched to form the metal wiring 134 , the metal wiring 135 , and the metal wiring 136 .

As shown in FIGS. 31(a) to 31(c), the sixth resist 131, the sixth resist 132, and the sixth resist 133 are peeled off.

According to the above, a manufacturing method is disclosed in which the interlayer insulating film 121 is deposited, and the interlayer insulating film 121 is planarized and etched back to expose the upper portion of the columnar layer 106, and the upper portion of the columnar layer 106 is exposed to form an upper portion. The fifth resist 122 for forming the first contact portion 127 is formed by etching the interlayer insulating film 121 to form a contact hole 123, and the first contact is formed on the second germanide 117 by depositing the metal 130. The portion 127 forms the sixth resist 131, the sixth resist 132, and the sixth resist 133 for forming the metal wiring 134, the metal wiring 135, and the metal wiring 136, and the metal wiring 134 is formed by etching. Metal wiring 135 and metal wiring 136.

As described above, the SGT manufacturing method is described in which the parasitic capacitance between the gate wiring and the substrate is reduced, and the metal wiring is directly connected to the upper portion of the columnar layer without forming the contact portion on the upper portion of the columnar layer.

Fig. 1 shows the structure of a semiconductor device obtained by the above manufacturing method. As shown in FIG. 1, the semiconductor device includes a fin-shaped germanium layer 103 formed on the germanium substrate 101, a first insulating film 104 formed around the fin-shaped germanium layer 103, and a columnar shape formed on the fin-shaped germanium layer 103. The germanium layer 106, where the width of the columnar layer 106 is the same as the width of the fin layer 103; the gate insulating film 107 formed around the columnar layer 106; and the gate formed around the gate insulating film 107 Electrode electrode 111a; a gate wiring 111b extending in a direction orthogonal to the fin-shaped germanium layer 103 of the gate electrode 111a; a first diffusion layer 114 formed on an upper portion of the columnar layer 106; and an upper portion and a columnar shape formed on the fin-shaped layer 103 a second diffusion layer 113 formed on the lower portion of the germanium layer 106; a first germanide 118 formed on the upper portion of the first diffusion layer 114; a second germanide 117 formed on the upper portion of the second diffusion layer 113; and a second germanide formed on the second germanium The first contact portion 127 on the 117, the first metal interconnection 135 formed on the first germanide 118, and the second metal interconnection 134 formed on the first contact portion 127.

Further, the gate electrode 111a includes a laminated structure of the metal film 108 and the polysilicon film 109 formed around the gate insulating film 107, and the film thickness of the polysilicon film 109 is wider than the width of the columnar layer 106. thin.

Further, the depth of the first contact portion 127 is lower than the height of the columnar layer 106. Since the depth of the first contact portion 127 is shallow, the resistance of the first contact portion can be reduced.

In addition, various embodiments and modifications can be made without departing from the spirit and scope of the invention. Further, the above embodiment is intended to explain an embodiment of the present invention, and does not limit the scope of the present invention.

For example, in the above embodiment, a method of manufacturing a semiconductor device in which a p-type (including p ⁺ type) and an n type (including n ⁺ type) are respectively opposite conductivity types, and a semiconductor device obtained by the manufacturing method are of course It is also included in the technical scope of the present invention.

103‧‧‧Finned layer

106‧‧‧ Columnar layer

107‧‧‧gate insulating film

108‧‧‧Metal film

109‧‧‧Polysilicon film

111a, 111b‧‧‧ gate electrode

127, 129‧‧1 first contact

134, 135, 136‧‧‧ metal wiring

140‧‧‧Contact barrier

X-x', y-y'‧‧‧ line

Claims (7)

A method of manufacturing a semiconductor device, comprising: forming a fin-shaped germanium layer on a germanium substrate, forming a first insulating film around the fin-shaped germanium layer, and forming an upper portion of the fin-shaped germanium layer a columnar layer; a second step of forming a gate insulating film, a gate electrode, and a gate wiring; the gate insulating film being formed around the columnar layer, wherein the gate electrode is formed on the gate insulating film In the third step, the gate electrode is connected to the gate electrode, and in the third step, the first diffusion layer is formed on the upper portion of the columnar layer, and the lower portion of the columnar layer and the upper portion of the fin layer are formed. a second diffusion layer; a fourth step of forming a first germanide and a second germane on the first diffusion layer; and a fifth step, after the fourth step, depositing an interlayer insulating film The interlayer insulating film is planarized and etched back to expose the upper portion of the columnar layer, and after exposing the upper portion of the columnar layer, a fifth resist for forming the first contact portion is formed. The interlayer insulating film is etched and shaped A contact hole is formed by depositing a metal on the second silicide first contact portion, and forming a sixth resist for forming metal wiring, is formed by etching the metal wiring. The method of manufacturing a semiconductor device according to claim 1, wherein in the first step, the width of the columnar layer is the same as the width of the fin layer. The method of manufacturing a semiconductor device according to claim 2, wherein in the first step, Forming a first resist for forming a fin-shaped germanium layer on the germanium substrate, etching the germanium substrate to form the fin-shaped germanium layer, and removing the first resist, in the finned germanium layer A first insulating film is deposited around the first insulating film, and an upper portion of the fin-shaped germanium layer is exposed, and a second resist is formed so as to be orthogonal to the fin-shaped germanium layer. The layer is etched to remove the second resist, whereby the columnar layer is formed such that the portion perpendicular to the fin-shaped layer and the second resist is the columnar layer. The method of manufacturing a semiconductor device according to the first aspect of the invention, wherein in the second step, a gate insulating film is formed around the columnar layer, and a metal film is formed around the gate insulating film. And a polycrystalline germanium film, wherein the polycrystalline germanium film has a film thickness smaller than a width of the columnar germanium layer, and a third resist for forming a gate wiring is formed, and the gate wiring is formed by anisotropic etching. Depositing a fourth resist, exposing the polysilicon film on the upper side wall of the columnar layer, removing the exposed polysilicon film by etching, peeling off the fourth resist, and removing the metal by etching The film forms a gate electrode connected to the gate wiring. A semiconductor device comprising: a fin-shaped germanium layer formed on a germanium substrate; a first insulating film formed around the fin-shaped germanium layer; and a columnar germanium layer formed on the fin-shaped germanium layer The width of the columnar layer is the same as the width of the fin layer; the gate insulating film is formed around the columnar layer; the gate electrode is formed around the gate insulating film; and the gate wiring is Extending in a direction orthogonal to the fin-shaped layer connected to the gate electrode; a first diffusion layer formed on an upper portion of the columnar layer; and a second diffusion layer formed on an upper portion of the fin layer a lower portion of the columnar tantalum layer; a first telluride formed on an upper portion of the first diffusion layer; a second telluride formed on an upper portion of the second diffusion layer; and a first contact portion formed on the second telluride The first metal wiring is formed on the first germanide, and the second metal wiring is formed on the first contact. The semiconductor device according to claim 5, comprising a gate electrode, wherein the gate electrode comprises a laminated structure of a metal film and a polysilicon film formed around the gate insulating film, and a film thickness of the polysilicon film It is thinner than the width of the above columnar layer. The semiconductor device according to claim 5, wherein the depth of the first contact portion is lower than a height of the columnar layer.