TW201409779A - Wiring board, light-emitting device and method for manufacturing wiring board - Google Patents

Wiring board, light-emitting device and method for manufacturing wiring board Download PDF

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Publication number
TW201409779A
TW201409779A TW102103792A TW102103792A TW201409779A TW 201409779 A TW201409779 A TW 201409779A TW 102103792 A TW102103792 A TW 102103792A TW 102103792 A TW102103792 A TW 102103792A TW 201409779 A TW201409779 A TW 201409779A
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TW
Taiwan
Prior art keywords
metal layer
wiring
layer
light
base
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Application number
TW102103792A
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Chinese (zh)
Inventor
Akihiro Sasaki
Kazuo Shimokawa
Takuya Honma
Nobuhiko Betsuda
Kiyoshi Nishimura
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Toshiba Lighting & Technology
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Publication of TW201409779A publication Critical patent/TW201409779A/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21VFUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V23/00Arrangement of electric circuit elements in or on lighting devices
    • F21V23/001Arrangement of electric circuit elements in or on lighting devices the elements being electrical wires or cables
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides

Abstract

This invention provides a wiring board, a light-emitting device and a method for manufacturing wiring board which can inhibit decline of reflectivity of light and improve the reliability associated with bonding. A wiring board of an embodiment includes a base part being a plate shape; a wiring disposed on a surface of the base part and disposed at a position which is distant from the circumference of the base part; a first metal layer disposed at a side of the wiring opposite to a side of the base part; and a second metal layer covering the first metal layer and a sidewall of the wiring.

Description

配線基板、發光裝置及配線基板的製造方法 Wiring substrate, light emitting device, and method of manufacturing wiring substrate

後述的實施方式大致涉及配線基板、發光裝置及配線基板的製造方法。 The embodiment to be described later generally relates to a wiring board, a light-emitting device, and a method of manufacturing the wiring board.

已有將發光二極體(diode)直接安裝於基板的板載晶片(Chip On Board,COB)方式的發光裝置。在COB(Chip On Board)方式的發光裝置中,為了防止配線的腐蝕,使焊接時的接合性提高等,將積層有多個金屬層的配線或電極設置在板狀的基部上。使用電鍍法或無電鍍法來形成此種配線或電極。然而,若使用電鍍法來積層多個金屬層,則存在如下的情況,即,下層的金屬層的側壁會露出。若下層的金屬層的側壁露出,則存在如下的情況,即,下層的金屬層因氧化或硫化等而受到腐蝕,射入至側壁的光的反射率有可能因側壁受到腐蝕而下降。另一方面,若使用無電鍍法來積層多個金屬層,則會形成如下的金屬層,該金屬層具有鍍敷液中所含的還原劑成分。在此情況下,在焊料接合時會產生還原劑成分的濃縮部,因此,焊料接合的可靠性有可能會下降。 There is a chip on board (COB) type light-emitting device in which a light-emitting diode is directly mounted on a substrate. In a COB (Chip On Board) type light-emitting device, wiring or electrodes in which a plurality of metal layers are laminated are provided on a plate-like base portion in order to prevent corrosion of wiring and improve bonding at the time of soldering. Such wiring or electrodes are formed using electroplating or electroless plating. However, if a plurality of metal layers are laminated by electroplating, there is a case where the side walls of the lower metal layer are exposed. When the side wall of the lower metal layer is exposed, there is a case where the metal layer of the lower layer is corroded by oxidation, vulcanization, or the like, and the reflectance of light incident on the side wall may be lowered by corrosion of the side wall. On the other hand, when a plurality of metal layers are laminated by electroless plating, a metal layer having a reducing agent component contained in the plating solution is formed. In this case, since the concentrated portion of the reducing agent component is generated at the time of solder bonding, the reliability of solder bonding may be lowered.

本發明所要解決的問題在於提供可抑制光的反射率的下降,並且可使與接合相關的可靠性提高的配線基板、發光裝置及配線基板的製造方法。 A problem to be solved by the present invention is to provide a wiring board, a light-emitting device, and a method of manufacturing a wiring board which can suppress a decrease in reflectance of light and improve reliability in connection.

實施方式的配線基板包括:基部,呈平板狀;配線,設置在所述基部的一個面上,且設置在遠離所述基部的周緣的位置;第一金屬層,設置在所述配線的與所述基部的一側相對的一側;以及第二金屬層,將所述第一金屬層與所述配線的側壁予以覆蓋。 A wiring board according to an embodiment includes: a base portion having a flat shape; a wiring disposed on one surface of the base portion and disposed at a position away from a periphery of the base portion; and a first metal layer disposed at the wiring portion a side opposite to one side of the base; and a second metal layer covering the first metal layer and the sidewall of the wiring.

依照一實施方式,在配線基板中,在第二金屬層上包括至少包含錫的焊料部,且使第一金屬層的材料與錫相互擴散所需的活化能例如是高於使配線的材料與錫相互擴散所需的活化能。 According to an embodiment, in the wiring substrate, a solder portion containing at least tin is included on the second metal layer, and an activation energy required to mutually diffuse the material of the first metal layer and tin is, for example, higher than a material for wiring The activation energy required for the mutual diffusion of tin.

依照一實施方式,在配線基板中,第二金屬層的材料的電離能例如是高於配線的材料及第一金屬層的材料的電離能。 According to an embodiment, in the wiring substrate, the ionization energy of the material of the second metal layer is, for example, higher than the ionization energy of the material of the wiring and the material of the first metal layer.

依照一實施方式,在配線基板中,第一金屬層的厚度尺寸例如是大於第二金屬層的厚度尺寸。 According to an embodiment, in the wiring substrate, the thickness dimension of the first metal layer is, for example, greater than the thickness dimension of the second metal layer.

依照一實施方式,在配線基板中,第一金屬層實質上例如是不包含磷。 According to an embodiment, in the wiring substrate, the first metal layer substantially does not contain phosphorus, for example.

依照一實施方式,在配線基板中,第一金屬層的厚度尺寸例如是0.003 mm以上且為0.1 mm以下。 According to an embodiment, in the wiring substrate, the thickness of the first metal layer is, for example, 0.003 mm or more and 0.1 mm or less.

依照一實施方式,在配線基板中,第二金屬層的厚度尺寸例如是0.0001 mm以上且為0.0003 mm以下。 According to an embodiment, in the wiring substrate, the thickness of the second metal layer is, for example, 0.0001 mm or more and 0.0003 mm or less.

依照一實施方式,在配線基板中,第一金屬層包含鎳及鈀中的 至少任一種元素。 According to an embodiment, in the wiring substrate, the first metal layer comprises nickel and palladium At least one element.

依照一實施方式,在配線基板中,第一金屬層包括積層的多個層。 According to an embodiment, in the wiring substrate, the first metal layer includes a plurality of layers laminated.

依照一實施方式,在配線基板中,更包括:第三金屬層,設置在基部的與設置有配線的一側相對的一側;第四金屬層,設置在第三金屬層的與基部的一側相對的一側;以及第五金屬層,將第四金屬層與第三金屬層的側壁予以覆蓋。 According to an embodiment, the wiring substrate further includes: a third metal layer disposed on a side of the base opposite to a side on which the wiring is disposed; and a fourth metal layer disposed on the base of the third metal layer and the base a side opposite to the side; and a fifth metal layer covering the sidewalls of the fourth metal layer and the third metal layer.

依照一實施方式,在配線基板中,配線的材料例如是與第三金屬層的材料相同,第一金屬層的材料例如是與第四金屬層的材料相同,第二金屬層的材料例如是與第五金屬層的材料相同。 According to an embodiment, in the wiring substrate, the material of the wiring is, for example, the same as the material of the third metal layer, and the material of the first metal layer is, for example, the same as the material of the fourth metal layer, and the material of the second metal layer is, for example, The material of the fifth metal layer is the same.

依照一實施方式,在配線基板中,基部例如是由陶瓷或包含陶瓷與樹脂的複合陶瓷形成。 According to an embodiment, in the wiring substrate, the base is formed of, for example, ceramic or a composite ceramic containing ceramic and resin.

實施方式的發光裝置包括:所述配線基板;發光元件,設置在第二金屬層的與設置有第一金屬層的一側相對的一側;以及焊料部,設置在發光元件與第二金屬層之間。 A light emitting device of an embodiment includes: the wiring substrate; a light emitting element disposed on a side of the second metal layer opposite to a side on which the first metal layer is disposed; and a solder portion disposed on the light emitting element and the second metal layer between.

實施方式的配線基板的製造方法包括如下的步驟:在基部的一個面形成第一晶種層;在第一晶種層上形成第一抗蝕劑掩模;在第一抗蝕劑掩模的開口部分,且在遠離基部的周緣的位置,依次形成配線與第一金屬層;將第一抗蝕劑掩模與剩餘的第一晶種層予以除去;以及形成將第一金屬層與配線的側壁予以覆蓋的第二金屬層。 A method of manufacturing a wiring substrate of an embodiment includes the steps of: forming a first seed layer on one side of a base; forming a first resist mask on the first seed layer; and forming a first resist mask on the first resist mask An opening portion, and a wiring and a first metal layer are sequentially formed at a position away from a periphery of the base; the first resist mask and the remaining first seed layer are removed; and the first metal layer and the wiring are formed a second metal layer covered by the sidewalls.

依照一實施方式,在配線基板的製造方法中,於在基部的一個面上形成第一晶種層的步驟中,在基部的與形成有第一晶種層的一側相對 的一側的面上,可進而形成第二晶種層;於在第一晶種層上形成第一抗蝕劑掩模的步驟中,可在第二晶種層上進而形成第二抗蝕劑掩模;於在第一抗蝕劑掩模的開口部分,且在遠離基部的周緣的位置,依次形成配線與第一金屬層的步驟中,在第二抗蝕劑掩模的開口部分,且在遠離基部的周緣的位置,可進而依次形成第三金屬層與第四金屬層;在將第一抗蝕劑掩模與剩餘的第一晶種層予以除去的步驟中,可進而將第二抗蝕劑掩模與剩餘的第二晶種層予以除去;在形成將第一金屬層與配線的側壁予以覆蓋的第二金屬層的步驟中,可進而形成將第四金屬層與第三金屬層的側壁予以覆蓋的第五金屬層。 According to an embodiment, in the method of manufacturing a wiring substrate, in the step of forming the first seed layer on one side of the base, the side of the base opposite to the side on which the first seed layer is formed is opposed a second seed layer may be further formed on the surface of one side; and in the step of forming a first resist mask on the first seed layer, a second resist may be further formed on the second seed layer a mask in the opening portion of the first resist mask and at a position away from the periphery of the base, in the step of sequentially forming the wiring and the first metal layer, in the opening portion of the second resist mask, And at a position away from the periphery of the base, the third metal layer and the fourth metal layer may be sequentially formed; in the step of removing the first resist mask and the remaining first seed layer, the The second resist mask is removed from the remaining second seed layer; in the step of forming the second metal layer covering the first metal layer and the sidewall of the wiring, the fourth metal layer and the third layer may be further formed A fifth metal layer covered by the sidewalls of the metal layer.

根據本發明的實施方式,可提供可抑制光的反射率的下降,並且可使與接合相關的可靠性提高的配線基板、發光裝置及配線基板的製造方法。 According to the embodiment of the present invention, it is possible to provide a wiring board, a light-emitting device, and a method of manufacturing a wiring board which can suppress a decrease in reflectance of light and improve reliability in connection.

1‧‧‧配線基板 1‧‧‧Wiring substrate

2、302‧‧‧基部 2. Base of 302‧‧‧

3、303‧‧‧配線部 3, 303‧‧‧ wiring department

3a、303a‧‧‧配線 3a, 303a‧‧‧ wiring

3a1、4a1、303a1‧‧‧側壁 3a1, 4a1, 303a1‧‧‧ side walls

3b、303b‧‧‧第一金屬層 3b, 303b‧‧‧ first metal layer

3b1、3b2、3c1、3c2、4b1、4b2、4c1、4c2、101b‧‧‧層 3b1, 3b2, 3c1, 3c2, 4b1, 4b2, 4c1, 4c2, 101b‧ ‧ layers

3c、303c‧‧‧第二金屬層 3c, 303c‧‧‧ second metal layer

4‧‧‧接合部 4‧‧‧ joints

4a‧‧‧第三金屬層 4a‧‧‧ third metal layer

4b‧‧‧第四金屬層 4b‧‧‧fourth metal layer

4c‧‧‧第五金屬層 4c‧‧‧ fifth metal layer

5‧‧‧焊料部 5‧‧‧ solder department

11a‧‧‧第一晶種層 11a‧‧‧First seed layer

11b‧‧‧第二晶種層 11b‧‧‧Second seed layer

14a‧‧‧第一抗蝕劑掩模 14a‧‧‧First resist mask

14b‧‧‧第二抗蝕劑掩模 14b‧‧‧second resist mask

100‧‧‧發光裝置 100‧‧‧Lighting device

101‧‧‧發光元件 101‧‧‧Lighting elements

101a‧‧‧單晶基板 101a‧‧‧ single crystal substrate

101c‧‧‧凸塊 101c‧‧‧Bumps

102‧‧‧波長轉換部 102‧‧‧wavelength conversion unit

103‧‧‧密封部 103‧‧‧ Sealing Department

200‧‧‧構件 200‧‧‧ components

205‧‧‧焊料 205‧‧‧ solder

301‧‧‧晶種層 301‧‧‧ seed layer

304‧‧‧抗蝕劑掩模 304‧‧‧resist mask

A‧‧‧部分 Part A‧‧‧

圖1(a)~圖1(d)是用以對包括第一實施方式的配線基板1的發光裝置100進行例示的模式圖,圖1(a)是發光裝置100的立體圖,圖1(b)是圖1(a)的俯視圖,圖1(c)是圖1(a)的仰視圖,圖1(d)是圖1(a)的一個剖面圖。 1(a) to 1(d) are schematic views for illustrating a light-emitting device 100 including the wiring substrate 1 of the first embodiment, and FIG. 1(a) is a perspective view of the light-emitting device 100, and FIG. 1(b) 1(a) is a top view of FIG. 1(a), and FIG. 1(d) is a cross-sectional view of FIG. 1(a).

圖2(a)~圖2(c)是用以對配線基板1進行例示的模式圖,圖2(a)是圖1(d)中的A部分的放大剖面圖,圖2(b)是對積層有多個層的第一金屬層及第四金屬層進行例示的剖面圖,圖2(c)是對積層有多個層的第二金屬層及第五金屬層進行 例示的剖面圖。 2(a) to 2(c) are schematic views for illustrating the wiring board 1. Fig. 2(a) is an enlarged cross-sectional view of a portion A in Fig. 1(d), and Fig. 2(b) is An exemplary cross-sectional view is illustrated for a first metal layer and a fourth metal layer having a plurality of layers, and FIG. 2(c) is a second metal layer and a fifth metal layer having a plurality of layers laminated. An exemplary cross-sectional view.

圖3(a)~圖3(d)是用以對比較例的配線基板300的製造方法進行例示的模式步驟剖面圖。 3(a) to 3(d) are schematic cross-sectional views illustrating a method of manufacturing the wiring substrate 300 of the comparative example.

圖4(a)~圖4(e)是用以對第二實施方式的配線基板1的製造方法進行例示的模式步驟剖面圖。 4(a) to 4(e) are schematic cross-sectional views showing a method for manufacturing the wiring board 1 of the second embodiment.

第一發明是一種配線基板,其包括:基部,呈平板狀;配線,設置在所述基部的一個面上,且設置在遠離所述基部的周緣的位置;第一金屬層,設置在所述配線的與所述基部的一側相對的一側;以及第二金屬層,將所述第一金屬層與所述配線的側壁予以覆蓋。 A first invention is a wiring substrate comprising: a base having a flat shape; a wiring disposed on one surface of the base and disposed at a position away from a circumference of the base; a first metal layer disposed at the a side of the wiring opposite to a side of the base; and a second metal layer covering the first metal layer and a sidewall of the wiring.

在所述配線基板上設置有將側壁予以覆蓋的第二金屬層,所述側壁是配線的露出部分。因此,可抑制光的反射率的下降,進而可抑制光出射效率的下降。 A second metal layer covering the side walls is provided on the wiring substrate, and the side walls are exposed portions of the wiring. Therefore, it is possible to suppress a decrease in the reflectance of light, and it is possible to suppress a decrease in light emission efficiency.

另外,根據第一發明所述,第二發明是一種配線基板,其在所述第二金屬層上包括至少包含錫的焊料部,且使所述第一金屬層的材料與錫相互擴散所需的活化能(activation energy)高於使所述配線的材料與錫相互擴散所需的活化能。即,所述第一金屬層的材料與錫相互擴散時的速度慢於所述配線的材料與錫相互擴散時的速度。 Further, according to the first invention, the second invention is a wiring substrate including a solder portion containing at least tin on the second metal layer, and a material for diffusing the material of the first metal layer and tin The activation energy is higher than the activation energy required to interdif the material of the wiring with tin. That is, the speed at which the material of the first metal layer and the tin are mutually diffused is slower than the speed at which the material of the wiring and the tin diffuse.

根據所述配線基板,當對發光元件進行焊接時,在所述 第一金屬層的材料與錫之間形成合金層,但形成的合金層是強度比所述配線的材料與錫所形成的合金層的強度更高的合金層。而且,由於所述第一金屬層的材料與錫相互擴散時的速度慢,因此,可抑制合金層的厚度尺寸增大。因此,可使接合發光元件時的接合的可靠性提高。 According to the wiring substrate, when the light emitting element is soldered, An alloy layer is formed between the material of the first metal layer and the tin, but the alloy layer formed is an alloy layer having a strength higher than that of the material of the wiring and the alloy layer formed of tin. Moreover, since the speed at which the material of the first metal layer and the tin are mutually diffused is slow, it is possible to suppress an increase in the thickness dimension of the alloy layer. Therefore, the reliability of bonding at the time of joining the light-emitting elements can be improved.

另外,根據第一發明或第二發明所述,第三發明是一種配線基板,其所述第二金屬層的材料的電離能高於所述配線的材料及所述第一金屬層的材料的電離能(ionization energy)。 Further, according to the first invention or the second invention, the third invention is a wiring substrate, wherein a material of the second metal layer has a higher ionization energy than a material of the wiring and a material of the first metal layer Ionization energy.

根據所述配線基板,可抑制配線的露出部分即側壁氧化或硫化。結果,可抑制配線受到腐蝕,因此,可抑制光的反射率的下降,進而可抑制光出射效率的下降。 According to the wiring board, it is possible to suppress oxidation or vulcanization of the side wall, that is, the exposed portion of the wiring. As a result, it is possible to suppress corrosion of the wiring, and therefore, it is possible to suppress a decrease in the reflectance of light, and it is possible to suppress a decrease in light emission efficiency.

另外,根據第一發明至第三發明中的任一個發明所述,第四發明是一種配線基板,其所述第一金屬層的厚度尺寸大於所述第二金屬層的厚度尺寸。 Further, according to any one of the first to third inventions, the fourth invention is a wiring substrate, wherein a thickness dimension of the first metal layer is larger than a thickness dimension of the second metal layer.

另外,第五發明是一種發光裝置,其包括:第一發明至第四發明中的任一個發明的配線基板;發光元件,設置在所述第二金屬層的與設置有所述第一金屬層的一側相對的一側;以及焊料部,設置在所述發光元件與所述第二金屬層之間。 Further, a fifth invention is the light-emitting device, comprising: the wiring substrate according to any one of the first to fourth inventions; the light-emitting element provided on the second metal layer and provided with the first metal layer One side opposite to the other side; and a solder portion disposed between the light emitting element and the second metal layer.

在所述發光裝置中包括所述配線基板,因此,可使光出射效率提高,並且可使與發光元件等的接合相關的可靠性提高。 Since the wiring board is included in the light-emitting device, the light emission efficiency can be improved, and reliability relating to bonding of a light-emitting element or the like can be improved.

另外,第六發明是一種配線基板的製造方法,其包括如下的步驟:在基部的一個面上形成第一晶種層(seed layer);在所 述第一晶種層上形成第一抗蝕劑掩模(resist mask);在所述第一抗蝕劑掩模的開口部分,且在遠離所述基部的周緣的位置,依次形成配線與第一金屬層;將所述第一抗蝕劑掩模與剩餘的所述第一晶種層予以除去;以及形成第二金屬層,該第二金屬層將所述第一金屬層與所述配線的側壁予以覆蓋。 Further, a sixth invention is a method of manufacturing a wiring substrate, comprising the steps of: forming a first seed layer on one side of a base; Forming a first resist mask on the first seed layer; forming a wiring and a portion in the opening portion of the first resist mask at a position away from the periphery of the base a metal layer; removing the first resist mask and the remaining first seed layer; and forming a second metal layer, the second metal layer and the wiring The side walls are covered.

根據所述配線基板的製造方法,可使第一金屬層中不包含還原劑成分,因此,當對發光元件進行焊接時,可抑制產生還原劑成分(例如將第一金屬層設為鎳時的磷等)的濃縮部。結果,可使與接合相關的可靠性提高。 According to the method for manufacturing a wiring board, since the reducing agent component is not contained in the first metal layer, when the light emitting element is soldered, generation of a reducing agent component (for example, when the first metal layer is made of nickel) can be suppressed. Concentrated part of phosphorus, etc.). As a result, the reliability associated with the joint can be improved.

另外,即便配線基板的配線未形成至基部的端部為止,也可借由第二金屬層來將配線的露出部分即側壁予以覆蓋。因此,可抑制光的反射率的下降,進而可抑制光出射效率的下降。 Further, even if the wiring of the wiring board is not formed to the end portion of the base portion, the exposed portion of the wiring, that is, the side wall, can be covered by the second metal layer. Therefore, it is possible to suppress a decrease in the reflectance of light, and it is possible to suppress a decrease in light emission efficiency.

以下,一面參照附圖,一面對實施方式進行例示。再者,在各附圖中,對相同的構成要素附上相同的符號,並適當地省略詳細的說明。 Hereinafter, an embodiment will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and the detailed description is omitted as appropriate.

[第一實施方式] [First Embodiment]

圖1(a)~圖1(d)是用以對包括第一實施方式的配線基板1的發光裝置100進行例示的模式圖。 1(a) to 1(d) are schematic views for illustrating a light-emitting device 100 including the wiring substrate 1 of the first embodiment.

再者,圖1(a)是發光裝置100的立體圖,圖1(b)是圖1(a)的俯視圖,圖1(c)是圖1(a)的仰視圖,圖1(d)是圖1(a)的一個剖面圖。 1(a) is a perspective view of the light-emitting device 100, FIG. 1(b) is a plan view of FIG. 1(a), FIG. 1(c) is a bottom view of FIG. 1(a), and FIG. 1(d) is a view Figure 1 (a) is a cross-sectional view.

圖2(a)~圖2(c)是用以對配線基板1進行例示的模 式圖。 2(a) to 2(c) are diagrams for illustrating the wiring substrate 1 Figure.

再者,圖2(a)是圖1(d)中的A部分的放大剖面圖,圖2(b)是對積層有多個層的第一金屬層及第四金屬層進行例示的剖面圖,圖2(c)是對積層有多個層的第二金屬層及第五金屬層進行例示的剖面圖。 2(a) is an enlarged cross-sectional view of a portion A in FIG. 1(d), and FIG. 2(b) is a cross-sectional view showing an example of a first metal layer and a fourth metal layer in which a plurality of layers are laminated. 2(c) is a cross-sectional view showing an example of a second metal layer and a fifth metal layer in which a plurality of layers are laminated.

如圖1(a)~圖1(d)所示,在發光裝置100上設置有配線基板1、發光元件101、波長轉換部102、及密封部103。 As shown in FIGS. 1(a) to 1(d), the light-emitting device 100 is provided with a wiring board 1, a light-emitting element 101, a wavelength conversion unit 102, and a sealing portion 103.

在配線基板1上設置有基部2、配線部3、及接合部4。 The wiring board 1 is provided with a base portion 2, a wiring portion 3, and a joint portion 4.

再者,與配線基板1相關的詳情將後述。 The details related to the wiring substrate 1 will be described later.

發光元件101設置在第二金屬層3c的與設置有第一金屬層3b的一側相對的一側。 The light emitting element 101 is disposed on a side of the second metal layer 3c opposite to the side on which the first metal layer 3b is provided.

發光元件101例如可設為發光二極體、有機發光二極體、雷射二極體(laser diode)等發光元件。 The light-emitting element 101 can be, for example, a light-emitting element such as a light-emitting diode, an organic light-emitting diode, or a laser diode.

發光元件101例如可設為射出藍色光的藍色發光二極體。 The light-emitting element 101 can be, for example, a blue light-emitting diode that emits blue light.

在發光元件101為藍色發光二極體的情況下,如圖2(a)所示,可在藍寶石(sapphire)等晶格匹配性佳的單晶基板101a上,形成有包含GaN系氮化物半導體的層101b。 When the light-emitting element 101 is a blue light-emitting diode, as shown in FIG. 2(a), a GaN-based nitride can be formed on a single crystal substrate 101a having good lattice matching properties such as sapphire. Layer 101b of the semiconductor.

發光元件101經由設置在層101b側的凸塊(bump)(突起)101c而連接(倒裝晶片(flip chip)安裝)於配線部3。然而,發光元件101無需為倒裝晶片類型的發光元件,也可為如下的(打線接合(wire bonding)法)類型的發光元件,該(打線接合法)類型的發光元件在上表面形成有發光層,且利用金屬線(wire)來 將元件與配線予以電性接合。若設為倒裝晶片安裝的發光元件101,則與使用打線接合法來連接的發光元件相比較,可使安裝面積減小。另外,可使發光元件101與配線部3之間的距離縮短,因此,可使電特性提高。 The light-emitting element 101 is connected (flip chip mounted) to the wiring portion 3 via a bump (protrusion) 101c provided on the layer 101b side. However, the light-emitting element 101 need not be a flip-chip type light-emitting element, and may be a light-emitting element of the type (wire bonding method) in which light-emitting elements of the type (wire bonding method) are formed on the upper surface. Layer and use wire to The component and the wiring are electrically joined. When the light-emitting element 101 mounted on the flip chip is used, the mounting area can be reduced as compared with the light-emitting element connected by the wire bonding method. Further, since the distance between the light-emitting element 101 and the wiring portion 3 can be shortened, electrical characteristics can be improved.

另外,如圖2(a)所示,包含發光層的層101b設置在配線基板1側。包含發光層的層101b成為發熱源,因此,容易使熱散逸至配線基板1側。 Further, as shown in FIG. 2(a), the layer 101b including the light-emitting layer is provided on the wiring substrate 1 side. Since the layer 101b including the light-emitting layer serves as a heat source, it is easy to dissipate heat to the wiring board 1 side.

另外,在使用打線接合法來連接的發光元件的情況下,在光的出射側設置有配線用的電極,因此,光出射效率有可能會變差。相對於此,若設為倒裝晶片安裝的發光元件101,則在光的出射側無遮擋物,因此,可使光出射效率提高。 Further, in the case of a light-emitting element that is connected by a wire bonding method, an electrode for wiring is provided on the light-emitting side, and thus light emission efficiency may be deteriorated. On the other hand, when the light-emitting element 101 mounted on the flip-chip is provided, there is no obstruction on the light-emitting side, and therefore the light-emitting efficiency can be improved.

波長轉換部102是以將多個發光元件101予以覆蓋的方式設置。波長轉換部102包含螢光體,該螢光體由從發光元件101射出的一次光激發。 The wavelength conversion unit 102 is provided to cover a plurality of light-emitting elements 101. The wavelength conversion unit 102 includes a phosphor that is excited by primary light emitted from the light-emitting element 101.

波長轉換部102例如可設為使粒子狀的螢光體分散在具有透光性的有機物或無機物中而成的部分。作為具有透光性的有機物,例如可例示環氧(epoxy)樹脂、矽酮(silicone)系樹脂、甲基丙烯酸樹脂(聚甲基丙烯酸甲酯(Polymethyl Methacrylate,PMMA))、聚碳酸酯(Polycarbonate,PC)、環烯烴聚合物(Cycloolefin Polymer,COP)、脂環式丙烯酸(OZ)、烯丙基二乙二醇碳酸酯(Allyl Diglycol Carbonate,ADC)、丙烯酸系樹脂、氟系樹脂、矽酮系樹脂與環氧樹脂的混合樹脂(hybrid resin)、及 氨基甲酸酯樹脂等。另外,作為具有透光性的無機物,例如可例示玻璃(glass)等。 The wavelength conversion unit 102 can be, for example, a portion in which a particulate phosphor is dispersed in a translucent organic or inorganic material. Examples of the light-transmitting organic substance include an epoxy resin, a silicone resin, a methacrylic resin (Polymethyl Methacrylate (PMMA)), and a polycarbonate (Polycarbonate). , PC), Cycloolefin Polymer (COP), alicyclic acrylic acid (OZ), Allyl Diglycol Carbonate (ADC), acrylic resin, fluorine resin, anthrone a hybrid resin of a resin and an epoxy resin, and A urethane resin or the like. In addition, as the inorganic substance having light transmissivity, for example, glass or the like can be exemplified.

具有透光性的有機物優選設為如下的樹脂,該樹脂具有觸變性,且硬化之後的蕭氏硬度(Shore hardness)為D40以上。若設為此種樹脂,則容易使波長轉換部102的形狀成為所期望的形狀。另外,可抑制由外力引起的變形,因此,可使關於發光元件101與配線部3之間的連接的可靠性提高。然而,只要可確保所期望的形狀與特性,則樹脂的蕭氏硬度並不限定於所述的蕭氏硬度,也可使用蕭氏硬度為D40以下的樹脂。 The organic substance having light transmissivity is preferably a resin having thixotropic properties and having a Shore hardness of D40 or more after curing. When such a resin is used, it is easy to make the shape of the wavelength conversion part 102 into a desired shape. Further, since deformation due to an external force can be suppressed, the reliability of the connection between the light-emitting element 101 and the wiring portion 3 can be improved. However, as long as the desired shape and characteristics can be ensured, the Shore hardness of the resin is not limited to the aforementioned Shore hardness, and a resin having a Shore hardness of D40 or less may be used.

另外,在波長轉換部102的材料中,優選使用如下的樹脂材料,該樹脂材料的樹脂配位基不易因能量高的藍色光而斷裂。借由使用此種樹脂,可抑制由長時間點燈時的樹脂構造破壞所引起的著色,因此,可確保發光特性的長期可靠性。雖主要使用矽酮樹脂作為具有如上所述的特性的樹脂,但存在如下的問題:由於透氣性高,因此,外部氣體會透向波長轉換部102內部,被波長轉換部102覆蓋的要素會劣化,所以必須使所述波長轉換部102具有耐氣體腐蝕的構造。 Further, among the materials of the wavelength conversion unit 102, it is preferable to use a resin material whose resin ligand is not easily broken by blue light having high energy. By using such a resin, coloring caused by breakage of the resin structure at the time of lighting for a long period of time can be suppressed, and therefore long-term reliability of the light-emitting characteristics can be ensured. Although an fluorenone resin is mainly used as the resin having the above-described characteristics, there is a problem that since the gas permeability is high, the outside air permeates into the inside of the wavelength conversion portion 102, and the elements covered by the wavelength conversion portion 102 are deteriorated. Therefore, it is necessary to make the wavelength conversion portion 102 have a structure resistant to gas corrosion.

波長轉換部102中所含的螢光體例如可設為YAG螢光體(釔-鋁-石榴石系螢光體)。在發光元件101為藍色發光二極體,且波長轉換部102中所含的螢光體為YAG螢光體的情況下,借由從發光元件101射出的藍色光來激發YAG螢光體,從YAG螢光體放射出黃色的螢光。接著,藍色光與黃色光混合,借此,白色 光從發光裝置100射出。再者,螢光體並不限定於YAG螢光體,可根據發光裝置100的用途等,以獲得所期望的發光色的方式而適當地變更。 The phosphor contained in the wavelength conversion unit 102 can be, for example, a YAG phosphor (yttrium-aluminum-garnet phosphor). When the light-emitting element 101 is a blue light-emitting diode and the phosphor included in the wavelength conversion unit 102 is a YAG phosphor, the YAG phosphor is excited by the blue light emitted from the light-emitting element 101. Yellow fluorescent light is emitted from the YAG phosphor. Then, the blue light is mixed with the yellow light, whereby white Light is emitted from the light emitting device 100. In addition, the phosphor is not limited to the YAG phosphor, and can be appropriately changed in accordance with the use of the light-emitting device 100 or the like to obtain a desired luminescent color.

密封部103是以將波長轉換部102予以覆蓋的方式設置。 The sealing portion 103 is provided to cover the wavelength conversion portion 102.

密封部103設置在遠離基部2的周緣的位置。即,密封部103不到達基部2的端部(周緣)。 The sealing portion 103 is disposed at a position away from the circumference of the base 2 . That is, the sealing portion 103 does not reach the end portion (peripheral edge) of the base portion 2.

密封部103由具有透光性的有機物或無機物形成。 The sealing portion 103 is formed of an organic or inorganic substance having light transmissivity.

密封部103例如可由具有透光性的樹脂形成。作為具有透光性的樹脂,例如可例示環氧樹脂、矽酮系樹脂、甲基丙烯酸樹脂(PMMA)、聚碳酸酯(PC)、環烯烴聚合物(COP)、脂環式丙烯酸(OZ)、烯丙基二乙二醇碳酸酯(ADC)、丙烯酸系樹脂、氟系樹脂、矽酮系樹脂與環氧樹脂的混合樹脂、及聚氨基甲酸酯樹脂等。 The sealing portion 103 can be formed, for example, of a resin having light transmissivity. Examples of the light-transmitting resin include an epoxy resin, an anthrone-based resin, a methacrylic resin (PMMA), a polycarbonate (PC), a cycloolefin polymer (COP), and an alicyclic acrylic acid (OZ). Allyl diethylene glycol carbonate (ADC), an acrylic resin, a fluorine-based resin, a mixed resin of an anthrone-based resin and an epoxy resin, and a polyurethane resin.

在所述情況下,形成密封部103的樹脂所具有的折射率的值優選與形成波長轉換部102的樹脂所具有的折射率的值同等或低於該值。即,密封部103的折射率的值優選為波長轉換部102的折射率的值以下。 In this case, the value of the refractive index of the resin forming the sealing portion 103 is preferably equal to or lower than the value of the refractive index of the resin forming the wavelength converting portion 102. That is, the value of the refractive index of the sealing portion 103 is preferably equal to or less than the value of the refractive index of the wavelength conversion portion 102.

若設為具有如上所述的折射率的密封部103,則可抑制射入至密封部103的光返回至波長轉換部102。另外,若使形成密封部103的樹脂所具有的折射率的值、與形成波長轉換部102的樹脂所具有的折射率的值同等,則可抑制密封部103與波長轉換部102的界面中的反射。例如,可由相同的樹脂來形成密封部103 與波長轉換部102。然而,根據波長轉換部102的特性,密封部103可有可無。 When the sealing portion 103 having the refractive index as described above is used, it is possible to suppress the light incident on the sealing portion 103 from returning to the wavelength conversion portion 102. In addition, when the value of the refractive index of the resin forming the sealing portion 103 is equal to the value of the refractive index of the resin forming the wavelength conversion portion 102, it is possible to suppress the interface between the sealing portion 103 and the wavelength conversion portion 102. reflection. For example, the sealing portion 103 may be formed of the same resin. And the wavelength conversion unit 102. However, depending on the characteristics of the wavelength conversion portion 102, the sealing portion 103 may or may not be available.

接著,進而對配線基板1進行說明。 Next, the wiring board 1 will be described.

基部2的平面形狀呈矩形的平板狀。 The planar shape of the base 2 has a rectangular flat shape.

基部2優選由如下的材料形成,該材料具有絕緣性,熱膨脹小,且散熱性及耐熱性優異。基部2例如可由陶瓷(ceramics)、陶瓷與樹脂的複合陶瓷等形成。作為陶瓷,例如可例示氧化鋁(Al2O3)、氮化鋁(AlN)、氧化鈹(BeO)、滑石(steatite)(MgO.SiO2)、鋯石(ZrSiO4)、及氮化矽(Si3N4)等。 The base 2 is preferably formed of a material having insulating properties, small thermal expansion, and excellent heat dissipation and heat resistance. The base 2 may be formed of, for example, ceramics, a composite ceramic of ceramics and resin, or the like. Examples of the ceramics include alumina (Al 2 O 3 ), aluminum nitride (AlN), beryllium oxide (BeO), talatite (MgO.SiO 2 ), zircon (ZrSiO 4 ), and tantalum nitride. (Si 3 N 4 ) and the like.

基部2的厚度尺寸並無特別的限定,但若考慮剛性或散熱性等,則例如優選設為0.3 mm以上且為3 mm以下。 The thickness of the base portion 2 is not particularly limited. However, in consideration of rigidity, heat dissipation, and the like, for example, it is preferably 0.3 mm or more and 3 mm or less.

然而,並不限定於已例示的形狀、材料、及厚度尺寸,可適當地變更。 However, it is not limited to the shape, material, and thickness dimension which have been illustrated, and can be suitably changed.

如圖1(b)所示,配線部3設置在基部2的一個面上,且設置在遠離基部2的周緣的位置。即,配線部3不到達基部2的端部(周緣)。 As shown in FIG. 1(b), the wiring portion 3 is provided on one surface of the base portion 2, and is disposed at a position away from the periphery of the base portion 2. That is, the wiring portion 3 does not reach the end portion (peripheral edge) of the base portion 2.

如圖2(a)所示,在配線部3中設置有配線3a、第一金屬層3b、及第二金屬層3c。 As shown in FIG. 2(a), the wiring portion 3 is provided with a wiring 3a, a first metal layer 3b, and a second metal layer 3c.

配線3a設置在基部2的一個面上。配線3a設置在遠離基部2的周緣的位置。為了將電力供給至發光元件101而設置配線3a。因此,配線3a由具有導電性的材料形成。作為具有導電性的材料,例如可例示銅(Cu)等。再者,配線3a的形成方法將後 述。 The wiring 3a is provided on one face of the base 2. The wiring 3a is disposed at a position away from the circumference of the base 2. The wiring 3a is provided in order to supply electric power to the light emitting element 101. Therefore, the wiring 3a is formed of a material having conductivity. As the material having conductivity, for example, copper (Cu) or the like can be exemplified. Furthermore, the method of forming the wiring 3a will be Said.

第一金屬層3b設置於配線3a的與基部2的一側相對的一側的面。設置第一金屬層3b,以抑制在對發光元件101進行焊接時,由焊料中所含的錫(Sn)與配線3a形成合金。例如,在對發光元件101進行焊接時,會形成焊料中所含的錫與配線3a的銅的合金(Cu-Sn合金)。在此情況下,在一般的設備中不存在第一金屬層3b,即使僅有銅,也不會有問題,但對於特別需要長期可靠性的光源設備(發光裝置)而言,脆合金層(例如Cu-Sn合金)的成長會成問題。因此,較為理想的是以使第一金屬層3b的材料與錫相互擴散時的速度慢於銅與錫相互擴散時的速度的方式,選定第一金屬層3b的材料。 The first metal layer 3b is provided on a surface of the wiring 3a on the side opposite to one side of the base 2. The first metal layer 3b is provided to suppress formation of an alloy between the tin (Sn) contained in the solder and the wiring 3a when the light-emitting element 101 is soldered. For example, when the light-emitting element 101 is soldered, an alloy (Cu-Sn alloy) of tin contained in the solder and copper of the wiring 3a is formed. In this case, the first metal layer 3b is not present in a general device, and even if there is only copper, there is no problem, but for a light source device (light-emitting device) which particularly requires long-term reliability, a brittle alloy layer ( The growth of, for example, Cu-Sn alloys can be problematic. Therefore, it is preferable to select the material of the first metal layer 3b so that the speed at which the material of the first metal layer 3b and the tin are mutually diffused is slower than the speed at which the copper and tin are mutually diffused.

因此,對於第一金屬層3b的材料而言,使第一金屬層3b的材料與錫相互擴散所需的活化能高於使配線3a的材料與錫相互擴散所需的活化能。即,對於第一金屬層3b的材料而言,第一金屬層3b的材料與錫相互擴散時的速度慢於配線3a的材料與錫相互擴散時的速度。 Therefore, for the material of the first metal layer 3b, the activation energy required to mutually diffuse the material of the first metal layer 3b and tin is higher than the activation energy required to mutually diffuse the material of the wiring 3a and tin. That is, with respect to the material of the first metal layer 3b, the speed at which the material of the first metal layer 3b and the tin are mutually diffused is slower than the speed at which the material of the wiring 3a and the tin mutually diffuse.

作為第一金屬層3b的材料,例如可例示鎳(Ni)或鈀(Pd)等。另外,可將第一金屬層3b設為一個層,也可設為積層有多個層的層。例如,如圖2(b)所示,也可設為積層有層3b1與層3b2的第一金屬層3b。再者,積層數並不限定於已例示的數量。在設為積層有多個層的第一金屬層3b的情況下,可包含由鎳形成的層、與由鈀形成的層。即,第一金屬層3b可包含鎳及鈀中的至少 任一種元素。 As a material of the first metal layer 3b, for example, nickel (Ni), palladium (Pd), or the like can be exemplified. Further, the first metal layer 3b may be formed as one layer, or may be a layer in which a plurality of layers are laminated. For example, as shown in FIG. 2(b), the first metal layer 3b in which the layer 3b1 and the layer 3b2 are laminated may be used. Furthermore, the number of layers is not limited to the number that has been exemplified. In the case where the first metal layer 3b having a plurality of layers is laminated, a layer formed of nickel and a layer formed of palladium may be included. That is, the first metal layer 3b may include at least at least nickel and palladium. Any one element.

另外,當形成第一金屬層3b時,有時根據形成方法而在第一金屬層3b中包含異種元素。作為一例,可列舉用於無電鍍的還原劑成分。例如,存在用於無電鍍鎳的還原劑中所包含的磷(P)等。若包含磷,則當對發光元件101進行焊接時,磷的濃度會局部地升高,產生由磷的濃縮部引起的接合強度的下降等。因此,接合發光元件101時的接合的可靠性有可能會下降。因此,第一金屬層3b實質上不包含異種元素。再者,在後文中敍述使第一金屬層3b中實質上不包含異種元素的內容。 Further, when the first metal layer 3b is formed, a different element may be contained in the first metal layer 3b according to the formation method. As an example, a reducing agent component used for electroless plating is mentioned. For example, there is phosphorus (P) or the like contained in a reducing agent for electroless nickel plating. When phosphorus is contained, when the light-emitting element 101 is welded, the concentration of phosphorus locally increases, and a decrease in bonding strength due to the concentrated portion of phosphorus or the like occurs. Therefore, the reliability of the joint when the light-emitting element 101 is joined may be lowered. Therefore, the first metal layer 3b does not substantially contain a different element. Further, the content in which the first metal layer 3b does not substantially contain the heterogeneous element will be described later.

第二金屬層3c是以將第一金屬層3b與配線3a的露出部分即側壁3a1予以覆蓋的方式而設置。 The second metal layer 3c is provided to cover the first metal layer 3b and the exposed portion of the wiring 3a, that is, the side wall 3a1.

此處,若第一金屬層3b氧化,則會產生如下的問題,例如對發光元件101進行焊接時的焊料浸潤不良及伴隨該焊料浸潤不良的剩餘焊料的向上蔓延,從而有可能會產生洩漏(leak)等不良。 Here, when the first metal layer 3b is oxidized, there are problems such as solder wettability during soldering of the light-emitting element 101 and upward spread of the remaining solder accompanying the solder wettability, which may cause leakage ( Leak) and other bad.

另外,存在如下的情況:來自發光元件101的一次光、或波長轉換部102中所含的螢光體所發出的螢光的一部分在波長轉換部102與密封部103的邊界面、或密封部103與外部氣體的邊界面上被反射,接著射入至配線3a的側壁3a1。 In addition, a part of the primary light from the light-emitting element 101 or the fluorescent light emitted from the phosphor contained in the wavelength conversion unit 102 is a boundary surface of the wavelength conversion unit 102 and the sealing portion 103, or a sealing portion. The boundary surface between the 103 and the outside air is reflected, and then incident on the side wall 3a1 of the wiring 3a.

在所述情況下,若配線3a的側壁3a1受到腐蝕,則射入至側壁3a1的光的反射率會下降,從而光出射效率有可能會下降。 In this case, when the side wall 3a1 of the wiring 3a is corroded, the reflectance of light incident on the side wall 3a1 is lowered, and the light emission efficiency may be lowered.

因此,設置第二金屬層3c,以抑制第一金屬層3b與配線 3a的側壁3a1受到腐蝕。 Therefore, the second metal layer 3c is provided to suppress the first metal layer 3b and the wiring The side wall 3a1 of 3a is corroded.

為了抑制第一金屬層3b與配線3a的側壁3a1氧化,第二金屬層3c的材料的電離能高於第一金屬層3b的材料的電離能及配線3a的材料的電離能。 In order to suppress oxidation of the first metal layer 3b and the side wall 3a1 of the wiring 3a, the ionization energy of the material of the second metal layer 3c is higher than the ionization energy of the material of the first metal layer 3b and the ionization energy of the material of the wiring 3a.

作為第二金屬層3c的材料,例如可例示金(Au)或鈀等。 As a material of the second metal layer 3c, for example, gold (Au), palladium, or the like can be exemplified.

另外,可將第二金屬層3c設為一個層,也可設為積層有多個層的層。例如,如圖2(c)所示,也可設為積層有層3c1與層3c2的第二金屬層3c。再者,積層數並不限定於已例示的數量。在設為積層有多個層的第二金屬層3c的情況下,可包含由金形成的層、與由鈀形成的層。即,第二金屬層3c可包含金及鈀中的至少任一種元素。 Further, the second metal layer 3c may be formed as one layer, or may be a layer in which a plurality of layers are laminated. For example, as shown in FIG. 2(c), the second metal layer 3c in which the layer 3c1 and the layer 3c2 are laminated may be used. Furthermore, the number of layers is not limited to the number that has been exemplified. In the case where the second metal layer 3c having a plurality of layers is laminated, a layer formed of gold and a layer formed of palladium may be contained. That is, the second metal layer 3c may contain at least one of gold and palladium.

焊料部5設置在發光元件101與第二金屬層3c之間。 The solder portion 5 is provided between the light emitting element 101 and the second metal layer 3c.

可借由使用了如下的焊料的焊接來形成焊料部5,所述焊料以錫為基底(base),且至少包含金、銀、銅、鉍、鎳、銦、鋅、銻、鍺、及矽中的任一種以上的元素。 The solder portion 5 may be formed by soldering using solder as a base and containing at least gold, silver, copper, bismuth, nickel, indium, zinc, antimony, bismuth, and antimony. Any one or more of the elements.

當對發光元件101進行焊接時,存在如下的情況,即,位於焊料部5的正下方的第二金屬層3c會消失。 When the light-emitting element 101 is soldered, there is a case where the second metal layer 3c located directly under the solder portion 5 disappears.

再者,存在如下的情況,即,在焊料部5與第二金屬層3c之間形成合金層,該合金層包含焊料部5及第二金屬層3c中所含的金屬。 Further, there is a case where an alloy layer is formed between the solder portion 5 and the second metal layer 3c, and the alloy layer includes the metal contained in the solder portion 5 and the second metal layer 3c.

另外,存在如下的情況,即,當位於焊料部5的正下方的第二金屬層3c消失時,在焊料部5與第一金屬層3b之間形成 合金層,該合金層包含焊料部5及第一金屬層3b中所含的金屬。 In addition, there is a case where, when the second metal layer 3c located directly under the solder portion 5 disappears, a formation is formed between the solder portion 5 and the first metal layer 3b. An alloy layer containing the metal contained in the solder portion 5 and the first metal layer 3b.

在所述倒裝晶片類型的接合過程中,存在如下的情況,即,電極之間的空隙(clearance)狹窄,在焊接時,焊料會從電極溢出,因此,存在電極之間發生短路(short)的問題。若利用第二金屬層3c來將配線3a及第一金屬層3b予以覆蓋,則焊料容易也附著於配線3a的側壁3a1側,因此,可抑制電極之間的短路。 In the flip chip type bonding process, there is a case where the clearance between the electrodes is narrow, and the solder may overflow from the electrode during soldering, and therefore, there is a short circuit between the electrodes. The problem. When the wiring 3a and the first metal layer 3b are covered by the second metal layer 3c, the solder easily adheres to the side wall 3a1 side of the wiring 3a, so that short-circuit between the electrodes can be suppressed.

配線3a的厚度尺寸可大於第一金屬層3b的厚度尺寸。第一金屬層3b的厚度尺寸可大於第二金屬層3c的厚度尺寸。 The thickness dimension of the wiring 3a may be larger than the thickness dimension of the first metal layer 3b. The thickness dimension of the first metal layer 3b may be greater than the thickness dimension of the second metal layer 3c.

在所述情況下,若考慮導電性或使用後述的電鍍法來形成配線3a,則配線3a的厚度尺寸優選設為0.02 mm以上且為0.3 mm以下。 In this case, when the wiring 3a is formed in consideration of conductivity or by a plating method to be described later, the thickness of the wiring 3a is preferably 0.02 mm or more and 0.3 mm or less.

第一金屬層3b的厚度尺寸的下限值在產品所要求的壽命的範圍中,可設為不會因錫擴散而消失的厚度尺寸以上。另外,根據抑制成本的觀點,較為理想的是不過分厚地成膜。因此,第一金屬層3b的厚度尺寸優選設為0.003 mm以上且為0.1 mm以下。 The lower limit of the thickness dimension of the first metal layer 3b can be set to be equal to or greater than the thickness dimension which does not disappear due to the diffusion of tin in the range of the life required for the product. Further, from the viewpoint of suppressing cost, it is preferable to form a film without excessive thickness. Therefore, the thickness dimension of the first metal layer 3b is preferably set to 0.003 mm or more and 0.1 mm or less.

根據發揮所述第二金屬層3c的功能的觀點,第二金屬層3c的厚度尺寸只要設為可確實地將配線3a的表層予以覆蓋的厚度尺寸即可。因此,第二金屬層3c的厚度尺寸優選設為0.0001 mm以上且為0.0003 mm以下。 The thickness of the second metal layer 3c may be a thickness dimension that can reliably cover the surface layer of the wiring 3a from the viewpoint of exerting the function of the second metal layer 3c. Therefore, the thickness dimension of the second metal layer 3c is preferably set to 0.0001 mm or more and 0.0003 mm or less.

在接合部4中設置有第三金屬層4a、第四金屬層4b、及第五金屬層4c。 The third metal layer 4a, the fourth metal layer 4b, and the fifth metal layer 4c are provided in the joint portion 4.

設置接合部4,以將配線基板1焊接於其他構件200(例 如散熱器(heat spreader)等)。因此,接合部4不一定必需,可根據需要而適當地設置接合部4。 The joint portion 4 is provided to weld the wiring substrate 1 to other members 200 (for example) Such as a heat spreader (heat spreader, etc.). Therefore, the joint portion 4 is not necessarily required, and the joint portion 4 can be appropriately provided as needed.

第三金屬層4a設置在基部2的與設置有配線部3的一側相對的一側。第三金屬層4a設置在遠離基部2的周緣的位置。然而,第三金屬層4a是以將基部2的面予以覆蓋的方式設置。 The third metal layer 4a is provided on the side of the base 2 opposite to the side on which the wiring portion 3 is provided. The third metal layer 4a is disposed at a position away from the circumference of the base 2. However, the third metal layer 4a is provided to cover the surface of the base 2.

第四金屬層4b設置於第三金屬層4a的與基部2的一側相對的一側的面。設置第四金屬層4b,以抑制在將配線基板1焊接於其他的構件200時,由焊料205中所含的錫與第三金屬層4a形成合金。 The fourth metal layer 4b is provided on a surface of the third metal layer 4a opposite to one side of the base 2. The fourth metal layer 4b is provided to suppress formation of an alloy between the tin contained in the solder 205 and the third metal layer 4a when the wiring board 1 is soldered to the other member 200.

第四金屬層4b可設為一個層,也可設為積層有多個層的層。例如,如圖2(b)所示,也可設為積層有層4b1與層4b2的第四金屬層4b。再者,積層數並不限定於已例示的數量。 The fourth metal layer 4b may be one layer or a layer in which a plurality of layers are laminated. For example, as shown in FIG. 2(b), the fourth metal layer 4b in which the layer 4b1 and the layer 4b2 are laminated may be used. Furthermore, the number of layers is not limited to the number that has been exemplified.

第五金屬層4c是以將第四金屬層4b與第三金屬層4a的露出部分即側壁4a1予以覆蓋的方式而設置。再者,如圖2(c)所示,也可設為積層有層4c1與層4c2的第五金屬層4c。再者,積層數並不限定於已例示的數量。在設為積層有多個層的第五金屬層4c的情況下,可包含由金形成的層、與由鈀形成的層。即,第五金屬層4c可包含金及鈀中的至少任一種元素。 The fifth metal layer 4c is provided to cover the fourth metal layer 4b and the exposed portion of the third metal layer 4a, that is, the side wall 4a1. Further, as shown in FIG. 2(c), a fifth metal layer 4c in which the layer 4c1 and the layer 4c2 are laminated may be used. Furthermore, the number of layers is not limited to the number that has been exemplified. In the case where the fifth metal layer 4c having a plurality of layers is laminated, a layer formed of gold and a layer formed of palladium may be contained. That is, the fifth metal layer 4c may contain at least one of gold and palladium.

此處,第三金屬層4a、第四金屬層4b、及第五金屬層4c的材料或厚度尺寸並無特別的限定,但除了接合部4之外,還焊接其他的構件200,因此,與配線部3同樣地必須考慮接合的可靠性等。另外,只要可同時形成配線部3與接合部4,則可使生產性 提高。 Here, the material or thickness dimension of the third metal layer 4a, the fourth metal layer 4b, and the fifth metal layer 4c is not particularly limited, but other members 200 are welded in addition to the joint portion 4, and thus, Similarly, the wiring portion 3 must take into consideration the reliability of bonding or the like. In addition, productivity can be achieved as long as the wiring portion 3 and the joint portion 4 can be simultaneously formed. improve.

因此,第三金屬層4a的材料或厚度尺寸可與配線3a的材料或厚度尺寸相同。 Therefore, the material or thickness dimension of the third metal layer 4a may be the same as the material or thickness dimension of the wiring 3a.

另外,第四金屬層4b的材料或厚度尺寸可與第一金屬層3b的材料或厚度尺寸相同。 In addition, the material or thickness dimension of the fourth metal layer 4b may be the same as the material or thickness dimension of the first metal layer 3b.

另外,第五金屬層4c的材料或厚度尺寸可與第二金屬層3c的材料或厚度尺寸相同。 In addition, the material or thickness dimension of the fifth metal layer 4c may be the same as the material or thickness dimension of the second metal layer 3c.

如此,可使接合部4的接合的可靠性等提高,並且可使生產性提高。 In this way, the reliability and the like of the joint of the joint portion 4 can be improved, and the productivity can be improved.

與焊料部5的材料同樣地,可使用如下的焊料作為焊料205,所述焊料以錫為基底,且至少包含金、銀、銅、鉍、鎳、銦、鋅、銻、鍺、及矽中的任一種以上的元素,也可使用能夠在更低的溫度下接合的焊料作為焊料205。 As in the case of the material of the solder portion 5, solder may be used as the solder 205, which is based on tin and contains at least gold, silver, copper, bismuth, nickel, indium, zinc, bismuth, antimony, and bismuth. As the solder 205, solder which can be bonded at a lower temperature can also be used as the element or more.

在本實施方式的配線基板1及發光裝置100中設置有第二金屬層3c,該第二金屬層3c將配線3a的露出部分即側壁3a1予以覆蓋。因此,可抑制側壁3a1因氧化或硫化等而受到腐蝕。結果,可抑制光的反射率的下降,進而可抑制光出射效率的下降。 In the wiring board 1 and the light-emitting device 100 of the present embodiment, the second metal layer 3c is provided, and the second metal layer 3c covers the exposed portion of the wiring 3a, that is, the side wall 3a1. Therefore, it is possible to suppress the side wall 3a1 from being corroded by oxidation, vulcanization or the like. As a result, it is possible to suppress a decrease in the reflectance of light, and it is possible to suppress a decrease in the light emission efficiency.

另外,可使第一金屬層3b中實質上不包含作為還原劑成分的異種元素,因此,可抑制在對發光元件101進行焊接時,形成還原劑成分的濃縮部。結果,可使與接合相關的可靠性提高。 Further, since the dissimilar elements as the reducing agent component are not substantially contained in the first metal layer 3b, it is possible to suppress the formation of the enriched portion of the reducing agent component when the light-emitting element 101 is welded. As a result, the reliability associated with the joint can be improved.

另外,設置有第五金屬層4c,該第五金屬層4c將第三金屬層4a的露出部分即側壁4a1予以覆蓋。因此,可抑制側壁4a1 氧化。結果,可抑制第三金屬層4a受到腐蝕,因此,可使第三金屬層4a與基部2的接合的可靠性提高。 Further, a fifth metal layer 4c is provided which covers the exposed portion of the third metal layer 4a, that is, the side wall 4a1. Therefore, the side wall 4a1 can be suppressed Oxidation. As a result, corrosion of the third metal layer 4a can be suppressed, so that the reliability of bonding of the third metal layer 4a and the base 2 can be improved.

另外,由於第四金屬層4b中實質上不包含作為還原劑成分的異種元素,因此,可抑制在對其他的構件200進行焊接時,形成還原劑成分的濃縮部。結果,可使與接合相關的可靠性提高。 Further, since the fourth metal layer 4b does not substantially contain the different element as the reducing agent component, it is possible to suppress the formation of the concentrated portion of the reducing agent component when the other member 200 is welded. As a result, the reliability associated with the joint can be improved.

[第二實施方式] [Second Embodiment]

在對第二實施方式的配線基板1的製造方法進行例示之前,先對比較例的配線基板300的製造方法進行說明。 Before the method of manufacturing the wiring board 1 of the second embodiment is exemplified, a method of manufacturing the wiring board 300 of the comparative example will be described.

圖3(a)~圖3(d)是用以對比較例的配線基板300的製造方法進行例示的模式步驟剖面圖。 3(a) to 3(d) are schematic cross-sectional views illustrating a method of manufacturing the wiring substrate 300 of the comparative example.

在比較例的配線基板300的製造方法中,使用電鍍法,在遠離基部302的周端的位置形成配線部303。 In the method of manufacturing the wiring substrate 300 of the comparative example, the wiring portion 303 is formed at a position away from the peripheral end of the base portion 302 by using a plating method.

首先,如圖3(a)所示,在基部302的一個面上形成包含導電性材料的晶種層301。 First, as shown in FIG. 3(a), a seed layer 301 containing a conductive material is formed on one surface of the base portion 302.

接著,如圖3(b)所示,在晶種層301上形成抗蝕劑掩模304。 Next, as shown in FIG. 3(b), a resist mask 304 is formed on the seed layer 301.

接著,如圖3(c)所示,使用電鍍法來依次形成配線303a、第一金屬層303b、及第二金屬層303c。此時,包含導電性材料的晶種層301到達基部302的周端,因此,可從基部302的周端施加電流。因此,可在遠離基部302的周端的位置,依次形成配線303a、第一金屬層303b、及第二金屬層303c。 Next, as shown in FIG. 3(c), the wiring 303a, the first metal layer 303b, and the second metal layer 303c are sequentially formed by an electroplating method. At this time, the seed layer 301 containing the conductive material reaches the peripheral end of the base portion 302, and therefore, a current can be applied from the peripheral end of the base portion 302. Therefore, the wiring 303a, the first metal layer 303b, and the second metal layer 303c can be sequentially formed at a position away from the peripheral end of the base portion 302.

接著,如圖3(d)所示,將抗蝕劑掩模304與剩餘的晶 種層301予以除去。如此,可在遠離基部302的周端的位置形成配線部303。 Next, as shown in FIG. 3(d), the resist mask 304 and the remaining crystals are used. The seed layer 301 is removed. In this manner, the wiring portion 303 can be formed at a position away from the peripheral end of the base portion 302.

然而,若使用電鍍法,在遠離基部302的周端的位置形成配線部303,則配線303a的側壁303a1會露出。如上所述,若配線303a的側壁303a1露出,則側壁303a1會受到腐蝕,光的反射率有可能會下降,進而光出射效率有可能會下降。 However, when the wiring portion 303 is formed at a position away from the peripheral end of the base portion 302 by the plating method, the side wall 303a1 of the wiring 303a is exposed. As described above, when the side wall 303a1 of the wiring 303a is exposed, the side wall 303a1 is corroded, the reflectance of light may be lowered, and the light emission efficiency may be lowered.

在所述情況下,可使用無電鍍法,在遠離基部302的周端的位置,依次形成配線303a、第一金屬層303b、及第二金屬層303c。在此情況下,可利用第一金屬層303b與第二金屬層303c來將配線303a的側壁303a1予以覆蓋。 In this case, the wiring 303a, the first metal layer 303b, and the second metal layer 303c may be sequentially formed at a position away from the peripheral end of the base portion 302 by electroless plating. In this case, the side wall 303a1 of the wiring 303a can be covered by the first metal layer 303b and the second metal layer 303c.

此處,如上所述,使第一金屬層303b的材料與錫相互擴散所需的活化能高於使配線303a的材料與錫相互擴散所需的活化能,且不易相互擴散。例如,第一金屬層303b的材料為鎳。 Here, as described above, the activation energy required to mutually diffuse the material of the first metal layer 303b and tin is higher than the activation energy required to mutually diffuse the material of the wiring 303a and tin, and is not easily diffused. For example, the material of the first metal layer 303b is nickel.

在使用無電鍍法來形成包含鎳的第一金屬層303b的情況下,可使用次亞磷酸(H3PO2)作為還原劑。因此,第一金屬層303b中包含磷。 In the case where the first metal layer 303b containing nickel is formed using an electroless plating method, hypophosphorous acid (H 3 PO 2 ) may be used as a reducing agent. Therefore, phosphorus is contained in the first metal layer 303b.

如上所述,若第一金屬層303b中包含磷,則存在如下的情況,即,當對發光元件101進行焊接時,磷的濃度會局部地升高。由於會產生由所述磷的濃縮部引起的接合強度的下降等,因此,產生了新的問題,即,接合發光元件101時的接合的可靠性會下降。 As described above, if phosphorus is contained in the first metal layer 303b, there is a case where the concentration of phosphorus locally increases when the light-emitting element 101 is soldered. Since a decrease in bonding strength due to the concentrated portion of the phosphorus or the like occurs, a new problem arises in that the reliability of bonding when the light-emitting element 101 is bonded is lowered.

因此,在第二實施方式的配線基板1的製造方法中,根 據以下的順序來形成配線部3。 Therefore, in the method of manufacturing the wiring substrate 1 of the second embodiment, the root The wiring portion 3 is formed in the following order.

圖4(a)~圖4(e)是用以對第二實施方式的配線基板1的製造方法進行例示的模式步驟剖面圖。 4(a) to 4(e) are schematic cross-sectional views showing a method for manufacturing the wiring board 1 of the second embodiment.

再者,圖4(a)~圖4(e)中表示了同時形成配線部3與接合部4的情況。 4(a) to 4(e) show the case where the wiring portion 3 and the joint portion 4 are simultaneously formed.

在第二實施方式的配線基板1的製造方法中,使用電鍍法,在遠離基部2的周端的位置形成配線3a與第一金屬層3b、及第三金屬層4a與第四金屬層4b。接著,使用無電鍍法,以將配線3a與第一金屬層3b予以覆蓋的方式而形成第二金屬層3c,且以將第三金屬層4a與第四金屬層4b予以覆蓋的方式而形成第五金屬層4c。 In the method of manufacturing the wiring substrate 1 of the second embodiment, the wiring 3a and the first metal layer 3b, and the third metal layer 4a and the fourth metal layer 4b are formed at a position away from the peripheral end of the base 2 by a plating method. Next, the second metal layer 3c is formed by covering the wiring 3a and the first metal layer 3b by electroless plating, and the third metal layer 4a and the fourth metal layer 4b are covered. Five metal layers 4c.

首先,如圖4(a)所示,在基部2的一個面上形成第一晶種層11a。另外,在基部2的與形成有第一晶種層11a的一側相對的一側形成第二晶種層11b。 First, as shown in FIG. 4(a), a first seed layer 11a is formed on one surface of the base 2. Further, a second seed layer 11b is formed on the side of the base 2 opposite to the side on which the first seed layer 11a is formed.

形成第一晶種層11a、第二晶種層11b,以使具有絕緣性的基部2的表面產生導電性。導電性材料並無特別的限定,例如可設為與配線3a相同的材料。導電性材料例如可設為銅。 The first seed layer 11a and the second seed layer 11b are formed to impart conductivity to the surface of the insulating base 2. The conductive material is not particularly limited, and for example, it can be made of the same material as the wiring 3a. The conductive material can be, for example, copper.

例如可使用濺鍍(sputtering)法來形成第一晶種層11a、第二晶種層11b。第一晶種層11a、第二晶種層11b的厚度尺寸例如可設為0.00005 mm左右。 For example, the first seed layer 11a and the second seed layer 11b may be formed using a sputtering method. The thickness of the first seed layer 11a and the second seed layer 11b can be, for example, about 0.00005 mm.

接著,如圖4(b)所示,在第一晶種層11a上形成第一抗蝕劑掩模14a。另外,在第二晶種層11b上形成第二抗蝕劑掩模 14b。 Next, as shown in FIG. 4(b), a first resist mask 14a is formed on the first seed layer 11a. In addition, a second resist mask is formed on the second seed layer 11b. 14b.

第一抗蝕劑掩模14a用以在第一晶種層11a上的規定的位置形成配線3a與第一金屬層3b。 The first resist mask 14a is for forming the wiring 3a and the first metal layer 3b at a predetermined position on the first seed layer 11a.

第二抗蝕劑掩模14b用以在第二晶種層11b上的規定的位置形成第三金屬層4a與第四金屬層4b。 The second resist mask 14b is for forming the third metal layer 4a and the fourth metal layer 4b at predetermined positions on the second seed layer 11b.

例如使用旋塗機(spin coater),將液狀抗蝕劑均一地塗布至第一晶種層11a、第二晶種層11b上,借此,可形成第一抗蝕劑掩模14a、第二抗蝕劑掩模14b。另外,例如也可利用真空壓接機等來分別貼附幹膜抗蝕劑(Dry Film Photoresist),使用光微影(photolithography)法來分別形成第一抗蝕劑掩模14a、第二抗蝕劑掩模14b。第一抗蝕劑掩模14a的厚度尺寸例如可設為將配線3a的厚度尺寸與第一金屬層3b的厚度尺寸相加所得的值。 For example, a liquid resist is uniformly applied to the first seed layer 11a and the second seed layer 11b by using a spin coater, whereby the first resist mask 14a can be formed. Two resist masks 14b. Further, for example, a dry film resist may be attached by a vacuum crimping machine or the like, and a first resist mask 14a and a second resist may be separately formed by photolithography. Mask 14b. The thickness dimension of the first resist mask 14a can be, for example, a value obtained by adding the thickness dimension of the wiring 3a to the thickness dimension of the first metal layer 3b.

第二抗蝕劑掩模14b的厚度尺寸例如可設為將第三金屬層4a的厚度尺寸與第四金屬層4b的厚度尺寸相加所得的值。 The thickness dimension of the second resist mask 14b can be, for example, a value obtained by adding the thickness dimension of the third metal layer 4a to the thickness dimension of the fourth metal layer 4b.

接著,如圖4(c)所示,使用電鍍法,在第一抗蝕劑掩模14a的開口部分依次形成配線3a與第一金屬層3b。另外,在依次形成配線3a與第一金屬層3b的同時,在第二抗蝕劑掩模14b的開口部分依次形成第三金屬層4a與第四金屬層4b。此時,包含導電性材料的第一晶種層11a與第二晶種層11b到達基部2的周端,因此,可從基部2的周端施加電流。因此,可在遠離基部2的周端的位置,依次形成配線3a與第一金屬層3b、及第三金屬層4a與第四金屬層4b。 Next, as shown in FIG. 4(c), the wiring 3a and the first metal layer 3b are sequentially formed in the opening portion of the first resist mask 14a by electroplating. Further, while the wiring 3a and the first metal layer 3b are sequentially formed, the third metal layer 4a and the fourth metal layer 4b are sequentially formed in the opening portion of the second resist mask 14b. At this time, the first seed layer 11a and the second seed layer 11b containing the conductive material reach the peripheral end of the base 2, and therefore, a current can be applied from the peripheral end of the base 2. Therefore, the wiring 3a and the first metal layer 3b, and the third metal layer 4a and the fourth metal layer 4b can be sequentially formed at a position away from the peripheral end of the base 2.

配線3a與第三金屬層4a的材料例如可設為銅。 The material of the wiring 3a and the third metal layer 4a can be, for example, copper.

第一金屬層3b與第四金屬層4b的材料例如可設為鎳或鈀等。 The material of the first metal layer 3b and the fourth metal layer 4b can be, for example, nickel or palladium.

配線3a與第三金屬層4a的厚度尺寸可設為0.02 mm以上且為0.3 mm以下。 The thickness dimension of the wiring 3a and the third metal layer 4a can be 0.02 mm or more and 0.3 mm or less.

第一金屬層3b與第四金屬層4b的厚度尺寸可設為0.003 mm以上且為0.1 mm以下。 The thickness of the first metal layer 3b and the fourth metal layer 4b may be set to be 0.003 mm or more and 0.1 mm or less.

另外,第一金屬層3b與第四金屬層4b可分別設為一個層,也可分別設為積層有多個層的層。 Further, each of the first metal layer 3b and the fourth metal layer 4b may be one layer, or may be a layer in which a plurality of layers are laminated.

再者,由於電鍍法中的鍍敷液或製程(process)條件等可應用已知的技術,因此省略說明。 In addition, since a known technique can be applied to a plating solution or a process condition in a plating method, description is abbreviate|omitted.

接著,如圖4(d)所示,將第一抗蝕劑掩模14a、第二抗蝕劑掩模14b與剩餘的第一晶種層11a、及第二晶種層11b予以除去。 Next, as shown in FIG. 4(d), the first resist mask 14a, the second resist mask 14b, and the remaining first seed layer 11a and the second seed layer 11b are removed.

例如可使用濕式灰化(wet ashing)法,將第一抗蝕劑掩模14a、第二抗蝕劑掩模14b予以除去。 For example, the first resist mask 14a and the second resist mask 14b can be removed by a wet ashing method.

例如可使用濕式蝕刻(wet etching)法,將剩餘的第一晶種層11a、第二晶種層11b予以除去。 For example, the remaining first seed layer 11a and second seed layer 11b can be removed using a wet etching method.

接著,如圖4(e)所示,使用無電鍍法,以將第一金屬層3b與配線3a的側壁3a1予以覆蓋的方式而形成第二金屬層3c。另外,在形成第二金屬層3c的同時,以將第四金屬層4b與第三金屬層4a的側壁4a1予以覆蓋的方式而形成第五金屬層4c。 Next, as shown in FIG. 4(e), the second metal layer 3c is formed by covering the first metal layer 3b and the side wall 3a1 of the wiring 3a by an electroless plating method. Further, the fifth metal layer 4c is formed to cover the fourth metal layer 4b and the side wall 4a1 of the third metal layer 4a while forming the second metal layer 3c.

第二金屬層3c與第五金屬層4c的材料例如可設為金或鈀。 The material of the second metal layer 3c and the fifth metal layer 4c can be, for example, gold or palladium.

根據第二金屬層3c與第五金屬層4c的功能的觀點,第二金屬層3c與第五金屬層4c的厚度尺寸只要設為可確實地將配線的表層予以覆蓋的厚度即可。例如,第二金屬層3c與第五金屬層4c的厚度尺寸可設為0.0001 mm以上且為0.0003 mm以下。 The thickness of the second metal layer 3c and the fifth metal layer 4c may be a thickness that can reliably cover the surface layer of the wiring, from the viewpoint of the functions of the second metal layer 3c and the fifth metal layer 4c. For example, the thickness dimension of the second metal layer 3c and the fifth metal layer 4c can be set to 0.0001 mm or more and 0.0003 mm or less.

另外,如圖2(c)所示,第二金屬層3c與第五金屬層4c可分別設為一個層,也可分別設為積層有多個層的層。 Further, as shown in FIG. 2(c), each of the second metal layer 3c and the fifth metal layer 4c may be one layer, or may be a layer in which a plurality of layers are laminated.

再者,由於無電鍍法中的鍍敷液或製程條件等可應用已知的技術,因此省略說明。 Further, since a known technique can be applied to the plating solution or the process conditions in the electroless plating method, the description thereof will be omitted.

如上所述,可在遠離基部2的周端的位置,同時形成配線部3與接合部4。 As described above, the wiring portion 3 and the joint portion 4 can be simultaneously formed at a position away from the peripheral end of the base portion 2.

在本實施方式的配線基板1的製造方法中,使用電鍍法,在遠離基部2的周端的位置形成配線3a與第一金屬層3b、及第三金屬層4a與第四金屬層4b。 In the method of manufacturing the wiring board 1 of the present embodiment, the wiring 3a and the first metal layer 3b, and the third metal layer 4a and the fourth metal layer 4b are formed at a position away from the peripheral end of the base 2 by a plating method.

因此,可使第一金屬層3b中實質上不包含作為還原劑成分的異種元素,因此,可抑制在對發光元件101進行焊接時,形成還原劑成分的濃縮部。結果,可使與接合相關的可靠性提高。 Therefore, since the dissimilar elements which are the reducing agent components are not substantially contained in the first metal layer 3b, it is possible to suppress the formation of the enriched portion of the reducing agent component when the light-emitting element 101 is welded. As a result, the reliability associated with the joint can be improved.

另外,可使第四金屬層4b中實質上不包含作為還原劑成分的異種元素,因此,可抑制在對其他的構件200進行焊接時,形成還原劑成分的濃縮部。結果,可使與接合相關的可靠性提高。 Further, since the dissimilar element as the reducing agent component is not substantially contained in the fourth metal layer 4b, it is possible to suppress the enrichment portion in which the reducing agent component is formed when the other member 200 is welded. As a result, the reliability associated with the joint can be improved.

另外,使用無電鍍法,以將配線3a與第一金屬層3b予 以覆蓋的方式而形成第二金屬層3c,且以將第三金屬層4a與第四金屬層4b予以覆蓋的方式而形成第五金屬層4c。 In addition, an electroless plating method is used to apply the wiring 3a and the first metal layer 3b. The second metal layer 3c is formed in a covering manner, and the fifth metal layer 4c is formed to cover the third metal layer 4a and the fourth metal layer 4b.

因此,即使在遠離基部2的周端的位置,也可借由第二金屬層3c來將配線3a的露出部分即側壁3a1予以覆蓋,因此,可抑制側壁3a1因氧化或硫化等而受到腐蝕。結果,可抑制光的反射率的下降,進而可抑制光出射效率的下降。 Therefore, even at a position away from the peripheral end of the base portion 2, the exposed portion of the wiring 3a, that is, the side wall 3a1 can be covered by the second metal layer 3c, so that the side wall 3a1 can be prevented from being corroded by oxidation or vulcanization or the like. As a result, it is possible to suppress a decrease in the reflectance of light, and it is possible to suppress a decrease in the light emission efficiency.

以上,已對本發明的若干實施方式進行了例示,但這些實施方式是作為例子而被提示的實施方式,並無對發明的範圍進行限定的意圖。這些新穎的實施方式能夠以其他各種方式來實施,且在不脫離發明的宗旨的範圍內,可進行各種省略、替換、以及變更。所述實施方式或其變形例包含于發明的範圍或宗旨,並且包含於權利要求書所揭示的發明與其均等的範圍中。另外,所述各實施方式可相互組合地實施。 The embodiments of the present invention have been exemplified above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. The various embodiments of the invention can be implemented in various other forms and various modifications, substitutions and changes can be made without departing from the scope of the invention. The invention or its modifications are intended to be included within the scope and spirit of the inventions Further, the respective embodiments described above can be implemented in combination with each other.

1‧‧‧配線基板 1‧‧‧Wiring substrate

2‧‧‧基部 2‧‧‧ base

3‧‧‧配線部 3‧‧‧Wiring Department

3a‧‧‧配線 3a‧‧‧Wiring

3a1‧‧‧側壁 3a1‧‧‧ side wall

3b‧‧‧第一金屬層 3b‧‧‧First metal layer

3c‧‧‧第二金屬層 3c‧‧‧Second metal layer

4‧‧‧接合部 4‧‧‧ joints

4a‧‧‧第三金屬層 4a‧‧‧ third metal layer

4b‧‧‧第四金屬層 4b‧‧‧fourth metal layer

4c‧‧‧第五金屬層 4c‧‧‧ fifth metal layer

5‧‧‧焊料部 5‧‧‧ solder department

101‧‧‧發光元件 101‧‧‧Lighting elements

101a‧‧‧單晶基板 101a‧‧‧ single crystal substrate

101b‧‧‧層 101b‧‧ layer

101c‧‧‧凸塊 101c‧‧‧Bumps

102‧‧‧波長轉換部 102‧‧‧wavelength conversion unit

103‧‧‧密封部 103‧‧‧ Sealing Department

200‧‧‧構件 200‧‧‧ components

205‧‧‧焊料 205‧‧‧ solder

Claims (15)

一種配線基板(1),其特徵在於包括:基部(2),呈平板狀;配線(3a),設置在所述基部(2)的一個面上,且設置在遠離所述基部(2)的周緣的位置;第一金屬層(3b),設置在所述配線(3a)的與所述基部(2)的一側相對的一側;以及第二金屬層(3c),將所述第一金屬層(3b)與所述配線(3a)的側壁(3a1)予以覆蓋。 A wiring substrate (1) comprising: a base portion (2) in a flat shape; a wiring (3a) disposed on one surface of the base portion (2) and disposed away from the base portion (2) a position of the periphery; a first metal layer (3b) disposed on a side of the wiring (3a) opposite to a side of the base (2); and a second metal layer (3c) to be the first The metal layer (3b) is covered with the side wall (3a1) of the wiring (3a). 如申請專利範圍第1項所述的配線基板(1),其中在所述第二金屬層(3c)上包括至少包含錫的焊料部(5),且使所述第一金屬層(3b)的材料與所述錫相互擴散所需的活化能高於使所述配線(3a)的材料與所述錫相互擴散所需的活化能。 The wiring substrate (1) according to claim 1, wherein a solder portion (5) containing at least tin is included on the second metal layer (3c), and the first metal layer (3b) is provided The activation energy required for the material to diffuse with the tin is higher than the activation energy required to interdif the material of the wiring (3a) with the tin. 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述第二金屬層(3c)的材料的電離能高於所述配線(3a)的材料及所述第一金屬層(3b)的材料的電離能。 The wiring substrate (1) according to claim 1 or 2, wherein a material of the second metal layer (3c) has a higher ionization energy than a material of the wiring (3a) and the first The ionization energy of the material of the metal layer (3b). 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述第一金屬層(3b)的厚度尺寸大於所述第二金屬層(3c)的厚度尺寸。 The wiring substrate (1) according to claim 1 or 2, wherein the first metal layer (3b) has a thickness larger than a thickness dimension of the second metal layer (3c). 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述第一金屬層(3b)實質上不包含磷。 The wiring substrate (1) according to claim 1 or 2, wherein the first metal layer (3b) does not substantially contain phosphorus. 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述第一金屬層(3b)的厚度尺寸為0.003 mm以上且為0.1 mm以下。 The wiring board (1) according to the first or second aspect of the invention, wherein the first metal layer (3b) has a thickness of 0.003 mm or more and 0.1 mm or less. 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述第二金屬層(3c)的厚度尺寸為0.0001 mm以上且為0.0003 mm以下。 The wiring board (1) according to the first or second aspect of the invention, wherein the second metal layer (3c) has a thickness of 0.0001 mm or more and 0.0003 mm or less. 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述第一金屬層(3b)包含鎳及鈀中的至少任一種元素。 The wiring substrate (1) according to the first or second aspect of the invention, wherein the first metal layer (3b) contains at least one of nickel and palladium. 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述第一金屬層(3b)包括積層的多個層(3b1、3b2)。 The wiring substrate (1) according to claim 1 or 2, wherein the first metal layer (3b) includes a plurality of layers (3b1, 3b2) laminated. 如申請專利範圍第1項或第2項所述的配線基板(1),更包括:第三金屬層(4a),設置在所述基部(2)的與設置有所述配線(3a)的一側相對的一側;第四金屬層(4b),設置在所述第三金屬層(4a)的與所述基部(2)的一側相對的一側;以及第五金屬層(4c),將所述第四金屬層(4b)與所述第三金屬層(4a)的側壁(4a1)予以覆蓋。 The wiring substrate (1) according to claim 1 or 2, further comprising: a third metal layer (4a) disposed on the base portion (2) and provided with the wiring (3a) a side opposite to one side; a fourth metal layer (4b) disposed on a side of the third metal layer (4a) opposite to a side of the base (2); and a fifth metal layer (4c) The fourth metal layer (4b) and the sidewall (4a1) of the third metal layer (4a) are covered. 如申請專利範圍第10項所述的配線基板(1),其中所述配線(3a)的材料與所述第三金屬層(4a)的材料相同,所述第一金屬層(3b)的材料與所述第四金屬層(4b)的材料相同,所述第二金屬層(3c)的材料與所述第五金屬層(4c)的材料相同。 The wiring substrate (1) according to claim 10, wherein the material of the wiring (3a) is the same as the material of the third metal layer (4a), and the material of the first metal layer (3b) Like the material of the fourth metal layer (4b), the material of the second metal layer (3c) is the same as the material of the fifth metal layer (4c). 如申請專利範圍第1項或第2項所述的配線基板(1),其中所述基部(2)是由陶瓷或包含陶瓷與樹脂的複合陶瓷形成。 The wiring board (1) according to the first or second aspect of the invention, wherein the base (2) is formed of ceramic or a composite ceramic comprising ceramic and resin. 一種發光裝置(100),其特徵在於包括:如申請專利範圍第1項至第4項中任一項所述的配線基板(1); 發光元件(101),設置在所述第二金屬層(3c)的與設置有所述第一金屬層(3b)的一側相對的一側;以及焊料部(5),設置在所述發光元件(101)與所述第二金屬層(3c)之間。 A light-emitting device (100), comprising: the wiring substrate (1) according to any one of claims 1 to 4; a light emitting element (101) disposed on a side of the second metal layer (3c) opposite to a side on which the first metal layer (3b) is disposed; and a solder portion (5) disposed on the light emitting Between the element (101) and the second metal layer (3c). 一種配線基板的製造方法,其特徵在於包括如下的步驟:在基部(2)的一個面形成第一晶種層(11a);在所述第一晶種層(11a)上形成第一抗蝕劑掩模(14a);在所述第一抗蝕劑掩模(14a)的開口部分,且在遠離所述基部(2)的周緣的位置,依次形成配線(3a)與第一金屬層(3b);將所述第一抗蝕劑掩模(14a)與剩餘的所述第一晶種層(11a)予以除去;以及形成將所述第一金屬層(3b)與所述配線(3a)的側壁(3a1)予以覆蓋的第二金屬層(3c)。 A method of manufacturing a wiring substrate, comprising the steps of: forming a first seed layer (11a) on one side of a base (2); forming a first resist on the first seed layer (11a) a mask (14a); in the opening portion of the first resist mask (14a), and at a position away from the periphery of the base (2), wiring (3a) and a first metal layer are sequentially formed ( 3b) removing the first resist mask (14a) and the remaining first seed layer (11a); and forming the first metal layer (3b) and the wiring (3a) a second metal layer (3c) covered by the side wall (3a1). 如申請專利範圍第14項所述的配線基板的製造方法,其中於在所述基部(2)的一個面上形成所述第一晶種層(11a)的步驟中,在所述基部(2)的與形成有所述第一晶種層(11a)的一側相對的一側的面上,進而形成第二晶種層(11b),於在所述第一晶種層(11a)上形成所述第一抗蝕劑掩模(14a)的步驟中,在所述第二晶種層(11b)上進而形成第二抗蝕劑掩模(14b),於在所述第一抗蝕劑掩模(14a)的開口部分,且在遠離所述基部(2)的周緣的位置,依次形成所述配線(3a)與所述第一金屬層(3b)的步驟中,在所述第二抗蝕劑掩模(14b)的開口部分,且在遠離所述基部(2) 的周緣的位置,進而依次形成第三金屬層(4a)與第四金屬層(4b),在將所述第一抗蝕劑掩模(14a)與剩餘的所述第一晶種層(11a)予以除去的步驟中,進而將所述第二抗蝕劑掩模(14b)與剩餘的所述第二晶種層(11b)予以除去,在形成將所述第一金屬層(3b)與所述配線(3a)的側壁(3a1)予以覆蓋的所述第二金屬層(3c)的步驟中,進而形成將所述第四金屬層(4b)與所述第三金屬層(4a)的側壁(4a1)予以覆蓋的第五金屬層(4c)。 The method of manufacturing a wiring substrate according to claim 14, wherein in the step of forming the first seed layer (11a) on one surface of the base (2), at the base (2) a surface on a side opposite to a side on which the first seed layer (11a) is formed, thereby forming a second seed layer (11b) on the first seed layer (11a) In the step of forming the first resist mask (14a), a second resist mask (14b) is further formed on the second seed layer (11b) for the first resist a step of forming the wiring (3a) and the first metal layer (3b) in an opening portion of the mask (14a) at a position away from a periphery of the base (2), in the step An opening portion of the two resist masks (14b), and away from the base (2) a position of the periphery, thereby sequentially forming a third metal layer (4a) and a fourth metal layer (4b), and the first resist mask (14a) and the remaining first seed layer (11a) In the step of removing, the second resist mask (14b) and the remaining second seed layer (11b) are further removed, and the first metal layer (3b) is formed In the step of covering the second metal layer (3c) by the sidewall (3a1) of the wiring (3a), further forming the fourth metal layer (4b) and the third metal layer (4a) The fifth metal layer (4c) covered by the side wall (4a1).
TW102103792A 2012-08-28 2013-01-31 Wiring board, light-emitting device and method for manufacturing wiring board TW201409779A (en)

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