TW201409717A - TFT substrate and fabrication method thereof, display - Google Patents

Abstract

The disclosure relates to a Thin-Film Transistor (TFT) substrate, configured to a display. The TFT substrate comprises: a first substrate; a protection layer fully forming one side of the substrate; and a buffer layer forming on the protection layer. The material of the protection layer consists of characters of reflective and absorption light, for example, the metal.

Description

Thin film transistor substrate, manufacturing method thereof, and display

The present invention relates to a flat panel display technology, and more particularly to a thin film transistor substrate and a method of fabricating the same that can effectively prevent damage to a substrate when performing laser processing.

In recent years, the demand for active array flat panel displays has increased rapidly, such as active array organic light emitting devices (AMOLED) displays. The active array organic light-emitting device generally uses a thin film transistor as a switching element of a pixel and a driving circuit, and can be classified into an amorphous germanium (a-Si) and a polycrystalline germanium thin film transistor according to materials used in the active layer. Compared with amorphous germanium thin film transistors, polycrystalline germanium thin film transistors have the advantages of high carrier mobility, high drive circuit accumulation and low leakage current, and are often used for high speed operation. Therefore, low temperature polysilicon (LTPS) has become a new application of flat panel display technology. LTPS can be formed by a simple IC process and integrates the driver circuit on a pixel-based substrate, reducing manufacturing costs.

In addition, some processes of LTPS thin film transistors are generally required at high temperatures (for example, 600 ° C), for example, hydrogenation, dehydrogenation, dopant activation, or laser annealing (Laser Annealing). And so on. Generally, the low-temperature polysilicon process mostly utilizes laser annealing technology, and the laser is used as a heat source to convert the amorphous germanium structure into a polycrystalline germanium structure. And according to the current laser heat treatment process, it will exceed the critical point that the substrate can withstand, for example, 350 ° C, resulting in damage to the substrate.

In view of the fact that conventional devices are not effective in solving laser damage caused by laser processing, it is necessary to propose a novel technique to solve the above problems in an economical and effective manner.

In view of the above, one of the objects of the embodiments of the present invention is to provide a thin film transistor substrate, a method for fabricating the same, and a display for solving the problem of laser damage caused by laser processing.

One of the objects of the embodiments of the present invention is to provide a thin film transistor substrate and a method of fabricating the same, which is provided with a protective layer on one side of the substrate to prevent the laser from damaging the substrate.

In one embodiment, the present invention provides a thin film transistor substrate, which is suitable for a display, comprising: a first substrate; a protective layer formed on one side of the first substrate, the protective layer covering the first surface a substrate, wherein the protective layer is a material having characteristics of absorbing light or reflecting light; and a buffer layer formed on the protective layer.

In one embodiment, the present invention provides a method for fabricating a thin film transistor substrate, which is suitable for use in a display, comprising: providing a first substrate; forming a protective layer on one side of the first substrate, the protective layer covering the entire surface The first substrate, wherein the protective layer is a material having absorption or reflected light characteristics; and a buffer layer is formed on the protective layer.

The present invention also provides a display comprising a thin film transistor substrate as described above; a second substrate disposed opposite the thin film transistor substrate; and a display medium disposed on the thin film transistor substrate and the second substrate between.

In order to enable the reviewing committee to have a further understanding and understanding of the features, objects and functions of the present invention, the detailed structure of the device of the present invention and the concept of the design are explained below so that the reviewer can understand the disclosure. The detailed description is as follows: FIG. 1A shows a method of manufacturing a thin film transistor according to an embodiment of the present invention, and the manufacturing method is applicable to a display, and the display can be an organic light emitting display. As shown in FIG. 1A, a first substrate 101 is provided, and a protective layer 102 is disposed on one side of the first substrate 101, and then a buffer layer 103 is overlaid on the protective layer 102. A first active layer 104 and a second active layer 105 are disposed on the layer 103. In addition, the first substrate 101 may be a flexible substrate, and the material may be polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimine (PI). , Polyimide), polyether oxime (PES, Polyether Sulfone), polycarbonate (PC, Polycarbonate) or a combination thereof. The protective layer 102 is composed of a material having characteristics of absorbing light or reflecting light, and has a property of absorbing light or reflecting light, including a metal such as aluminum (Al), molybdenum (Mo), copper (Cu), or titanium ( Ti), tungsten (W), etc. or a combination thereof. In addition, the protective layer has a thickness of between 1000 Å and 2,000 Å. The aforementioned buffer layer may be composed of tantalum oxide, tantalum nitride or a combination thereof, and the first and second active layers may be composed of low temperature polycrystalline germanium. In addition, an adhesive layer may be followed on the other side of the first substrate 101 for use in the subsequent glass carrier.

As shown in FIG. 1B, through a doping activation (dopant activaton) The N+ doped regions 104a, 104f, the N-doped regions 104b, 104d and a channel 104c are formed on the first active layer 104, and the P+ doped regions 105a, 105b and the channel 105c are formed on the second active layer. . The aforementioned N+ doped region is adjacent to the N-doped region 104b, the other N+ doped region 104d is adjacent to the N-doped region 104f, and the via 104b is disposed between the N-doped regions 104b, 104d. The channel 105c of the second active layer is disposed between the P+ doping regions 105a, 105b. Next, a laser activation treatment at a temperature between 600 ° C and 1200 ° C is performed. Since the protection of the protective layer 102 is performed at this time, the physical properties of the laser penetrating the first substrate 101 and damaging the first substrate 101 can be prevented, and the adhesive layer and the glass carrier subsequent to the first substrate 101 are indirectly protected.

As shown in FIG. 1C, a gate insulating layer 106 is formed to cover the active layers 104 and 105, and a first metal layer 110a is formed, thereby causing the first active layer 104 and the second active through the doping activation process. The layer 105 forms a CMOS, PMOS or NMOS transistor with the gate insulating layer 106 and a first metal layer 110a.

As shown in FIG. 1D, an interlayer dielectric (ILD) deposition is performed on the gate insulating layer 106 and the first metal layer 110a to deposit one or more dielectric layers 107. The electrical layer 107 is etched or patterned to expose portions of the first active layer 104, the second active layer 105, and the first metal layer 110a. The foregoing etching treatment includes plasma etching or reactive ion etching, etc., and the aforementioned patterning processing includes a lithography process. The foregoing dielectric layer 107 may be composed of tantalum oxide, tantalum nitride or a combination thereof.

As shown in FIG. 1E, the dielectric layer 107 after being etched or patterned A plurality of contact holes 108 are formed, and then a second metal layer 110b is formed over the dielectric layer 107. The second metal layer 110b is doped with the N+ doping regions 104a, 104f and P+ via the contact holes 108. The areas 105a, 105b are in contact. It should be noted that the second metal layer 110 can also be in contact with the first metal layer 110a via the contact hole 108.

As shown in FIG. 1F, a passivation layer 109 is formed on the dielectric layer 107 and the second metal layer 110b. Thereafter, a subsequent conventional process (for example, forming a planarization layer, a pixel define layer, a pixel electrode, etc.) is performed, and details are not described herein. The passivation layer 109 described above comprises a material selected from the group consisting of CoWP, CoP, NiWP, NiB, CoWB, NiReP, and CoReP. After the foregoing process is completed, the glue layer and the glass carrier board subsequent to the substrate 101 can be removed.

1F shows a thin film transistor substrate of the present invention, which is suitable for use in a display, and the display can be an organic light emitting display. The thin film transistor substrate includes: a first substrate 101, and the first substrate can be a flexible substrate; a protective layer 102 is formed on one side of the first substrate 101, and the protective layer 102 covers the first surface a substrate, and the protective layer 102 is composed of a material having characteristics of absorbing light or reflecting light, and has a property of absorbing light or reflecting light, including a metal such as aluminum (Al), molybdenum (Mo), or copper (Cu). Titanium (Ti), tungsten (W), or the like, or a combination thereof, wherein the protective layer 102 has a thickness of between 1000 Å and 2000 Å; a buffer layer 103 is formed on the protective layer 102; and a first active layer 104 and a second active layer 105 are respectively formed on the buffer layer 103; a gate insulating layer 106 covering the first and second active layers 104, 105; a dielectric layer 107 formed on the gate Above the insulating layer 106; a first metal layer 110a and a plurality of extension contact holes 108 are disposed on the dielectric layer a second metal layer 110b is disposed on the dielectric layer 107, the second metal layer 110b contacts the active layer via the contact holes 108, and a passivation layer 109 covers the second metal. Layer 110b and the dielectric layer 107. In the present invention, a laser-doping activation process is applied between 600 ° C and 1200 ° C to form an N+ doped region and an N-doped region on the first active layer 104 and the second active layer 105. Forming a P+ doped region, for example, through a doping activon process to form N+ doped regions 104a, 104f, N-doped regions 104b, 104d, and a channel 104c on the first active layer 104. And forming P+ doping regions 105a, 105b and a channel 105c on the second active layer. The aforementioned N+ doped region is adjacent to the N-doped region 104b, the other N+ doped region 104d is adjacent to the N-doped region 104f, and the via 104b is disposed between the N-doped regions 104b, 104d. The channel 105c of the second active layer is disposed between the P+ doping regions 105a, 105b. The second metal layer 110b is in contact with the N+ doped regions 104a, 104f and the P+ doped regions 105a, 105b via the contact holes 108. It should be noted that the second metal layer 110 can also be in contact with the first metal layer 110a via the contact hole 108. In addition, the buffer layer 103 and the dielectric layer 107 may be composed of tantalum oxide, tantalum nitride or a combination thereof.

Furthermore, the present invention provides a display comprising: a relatively disposed thin film transistor substrate and a second substrate; and a display medium disposed between the thin film transistor substrate and the second substrate, wherein the display medium can be an organic light emitting layer.

The invention provides a protective layer on one side of the flexible substrate to prevent the laser from penetrating the flexible substrate when performing the laser technology, thereby damaging the glass substrate connected to the flexible substrate by the adhesive layer, and even destroying the softness at the same time. The physical properties of the substrate and the subsequent layer, thereby improving the yield and efficiency of the product.

The above description is only exemplary of the invention, and the scope of the invention is not limited thereto. That is to say, the equivalent changes and modifications made by the applicant in accordance with the scope of the patent application of the present invention should still fall within the scope of the patent of the present invention. I would like to ask your review committee to give a clear explanation and pray for it.

101‧‧‧First substrate

102‧‧‧Protective layer

103‧‧‧buffer layer

104‧‧‧First active layer

105‧‧‧Second active layer

106‧‧‧gate insulation

107‧‧‧Dielectric layer

108‧‧‧Contact hole

109‧‧‧ Passivation layer

110a‧‧‧First metal layer

110b‧‧‧Second metal layer

104a, 104f‧‧‧N+ doped area

104b, 104d‧‧‧N-doped zone

104c‧‧‧ channel

105a, 105b‧‧‧P+ doped area

105c‧‧‧ channel

1A to 1F show a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention.

101‧‧‧First substrate

102‧‧‧Protective layer

103‧‧‧buffer layer

106‧‧‧gate insulation

107‧‧‧Dielectric layer

109‧‧‧ Passivation layer

110a‧‧‧First metal layer

110b‧‧‧Second metal layer

Claims (21)

A thin film transistor substrate comprising: a first substrate; a protective layer formed on one side of the first substrate, the protective layer covering the first substrate over the entire surface, wherein the protective layer has absorption or reflected light characteristics a material; and a buffer layer formed on the protective layer. The thin film transistor substrate of claim 1, wherein the protective layer is a metal. The thin film transistor substrate of claim 1, wherein the protective layer is aluminum (Al), molybdenum (Mo), copper (Cu), titanium (Ti), tungsten (W), or a combination thereof. The thin film transistor substrate of claim 1, wherein the protective layer has a thickness of between 1000 Å and 2000 Å. The thin film transistor substrate of claim 1, wherein the first substrate is a flexible substrate. The thin film transistor substrate of claim 1, wherein the first substrate is polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyfluorene (PEN), polyfluorene Imine (PI, Polyimide), polyether oxime (PES, Polyether Sulfone), polycarbonate (PC, Polycarbonate) or a combination thereof. The thin film transistor substrate of claim 1, further comprising: an active layer formed on the buffer layer; a gate insulating layer covering the active layer; a first metal layer disposed on Above the gate insulating layer; a dielectric layer over the gate insulating layer; a plurality of contact holes disposed on the dielectric layer; and a second metal layer disposed over the dielectric layer via the contact holes and the active layer contact. The thin film transistor substrate of claim 7, wherein the active layer comprises an N+ doped region and an N-doped region. The thin film transistor substrate of claim 7, wherein the active layer comprises a P+ doped region. The thin film transistor substrate of claim 8, wherein the second metal layer is in contact with the N+ doping region. The thin film transistor substrate of claim 9, wherein the second metal layer is in contact with the P+ doped region. A method for manufacturing a thin film transistor substrate, comprising: providing a first substrate; forming a protective layer on one side of the first substrate, the protective layer covering the first substrate over the entire surface, wherein the protective layer has absorption light or a material that reflects light characteristics; and a buffer layer formed over the protective layer. The method for producing a thin film transistor substrate according to claim 12, wherein the protective layer is a metal. The method for manufacturing a thin film transistor substrate according to claim 12, wherein the protective layer is aluminum (Al), molybdenum (Mo), copper (Cu), titanium (Ti), tungsten (W) or a combination thereof. . The method for manufacturing a thin film transistor substrate according to claim 12, wherein the protective layer has a thickness of between 1000 Å and 2000 Å. The method for manufacturing a thin film transistor substrate according to claim 12, further comprising: forming an active layer on the buffer layer; forming a gate insulating layer to cover the active layer; and providing a first metal Laying on the gate insulating layer; forming a dielectric layer over the gate insulating layer; providing a plurality of contact holes in the dielectric layer; and disposing a second metal layer over the dielectric layer The contact holes are in contact with the active layer. The method for manufacturing a thin film transistor substrate according to claim 16, wherein a laser doping activation treatment at a temperature between 600 ° C and 1200 ° C is performed on the active layer before the gate insulating layer is formed. A complex doped region is formed. The method for fabricating a thin film transistor substrate according to claim 17, wherein the doped regions are an N+ doped region and an N-doped region. The method for fabricating a thin film transistor substrate according to claim 17, wherein the doped regions are P+ doped regions. A display comprising: a thin film transistor substrate according to claim 1; a second substrate disposed opposite to the thin film transistor substrate; and a display medium formed on the thin film transistor substrate and the first Between the two substrates. The display of claim 20, wherein the display medium is an organic light-emitting layer.