TW201409472A - Semiconductor structure with improved capacitance of bit line - Google Patents

Abstract

A semiconductor structure with improved capacitance of bit lines includes a substrate, a memory stacked structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the memory stacked structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

Description

Semiconductor structure for improving bit line capacitance

This invention relates to a semiconductor structure, and more particularly to a semiconductor structure that improves bit line capacitance.

With the development of semiconductor technology, the demand for memory devices has also tended to be smaller in size and larger in memory capacity. In response to this demand, it is required to manufacture a memory device having a high component density. Since the critical size of memory devices has been reduced to the limits of technology, designers have developed a three-dimensional stacked memory device that increases the density of memory to achieve higher memory capacity while reducing the size of individual components. However, in the three-dimensional stacked structure, the bit lines connecting the different stacked blocks make the capacitances of the respective stacked blocks parallel to each other, so that the capacitance of the bit lines is added to the capacitance of each stacked block, and the transmission of the bit signals is easy. Caused a delay.

The invention relates to a semiconductor structure for improving bit line capacitance, which is an independent control circuit added in a three-dimensional stacked memory, so that the capacitances of the respective stacked blocks are independent of each other or only a small part of the stacked blocks have parallel capacitances. To avoid signal delay caused by excessive capacitance of the bit line.

According to an aspect of the present invention, a semiconductor structure for improving bit line capacitance is provided, which includes a substrate, a memory stack structure, a plurality of bit lines, a first step contact structure, a first set of transistor structures, and a first conductive line. The bit lines straddle the memory stack formed on the substrate. A first step contact structure is formed on the substrate. The first step contact structure comprises a plurality of conductive planes and a plurality of insulating planes separated by the insulating planes for layering the plurality of bit lines to the memory stack structure. The first set of transistor structures are formed in one of the first blocks through which the bit lines pass to the conductive planes. The first set of transistor structures has a first gate around the first block. The first conductive line is connected to the first gate to control the voltage of the first gate.

According to another aspect of the present invention, a semiconductor structure for improving bit line capacitance is provided, which includes a substrate, a column of memory stack structures, a plurality of bit lines and a main bit line, a first step contact structure, and a first A set of transistor structures and a first conductive line. The bit line and the main bit line straddle the column of memory stack structures formed on the substrate. The first step contact structure is formed on the substrate, and the first step contact structure comprises a plurality of conductive planes and a plurality of insulating planes respectively. The conductive planes are separated by the insulating planes for layering the bit lines to the memories. Body stack structure. The first set of transistor structures are formed in one of the first blocks through which the main bit lines pass to the conductive planes, and the first set of transistor structures have a first gate around the first block. The first conductive line is connected to the first gate to control the voltage of the first gate.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The semiconductor structure for improving the bit line capacitance disclosed in this embodiment is to add an independently controlled circuit to the three-dimensional stacked memory, for example, a plurality of transistor structures arranged in a horizontal direction or a transistor arranged along a horizontal/vertical direction. Array structure, a set of transistor structures in the circuit can be selectively turned on such that different series of bit lines are coupled to a portion of the memory stack via transistor opening, while another set of transistor structures are selectively turned off So that the different sequence of bit lines are turned off via the transistor and the other part of the memory stack structure is kept open. Therefore, the capacitance of the bit line is the sum of the capacitances of the memory stack structure that is selected to be turned on. Therefore, the semiconductor structure of the present invention can effectively solve the problem that the capacitance of the bit line is too high and the signal is delayed.

The following is a detailed description of various embodiments, which are intended to be illustrative only and not to limit the scope of the invention.

First embodiment

Please refer to FIG. 1 , which is a top plan view of a semiconductor structure 100 for improving bit line capacitance according to an embodiment of the invention. For example, the memory cell stack structure 110 is located between the first step contact structure 121 and the second step contact structure 122, and the memory stack structure 110 is, for example, a three-dimensional anti-gate (the gate line BL1 to BL4). NAND) a flash memory having a plurality of memory planes, for example, sequentially arranged in a bottom-up order, and the first bit line BL1 is connected to the first layer memory plane via the first step contact structure 121, The two bit line BL2 is connected to the second layer memory plane via the first step contact structure 121, and so on. Likewise, the different bit lines BL1 BL BL4 are connected to different memory planes, for example via the second step contact structure 122. In one embodiment, the first step contact structure 121 and the second step contact structure 122 are respectively connected to the same memory plane but staggered first conductive stripes (odd columns) and second conductive stripes (even columns), respectively. The conductive stripe and the second conductive strip form a set of conductive strips arranged in a finger shape.

For a description of the memory stack structure 110, the step contact structures 121-122, and the detailed structure of the conductive strips, please refer to the "Semiconductor Structure and Manufacturing" of the Chinese Patent No. 100101846 filed on January 18, 2011 by the inventor of the present application. The method and the "3D array memory structure of improved bit line capacitance singleness" of Chinese Patent No. 100136822 filed on October 11, 2010.

In this embodiment, in order to control the capacitance of the bit lines BL1 BL BL4, a first group of transistor structures BLT1 and a second group of electrodes are respectively formed above the first step contact structure 121 and above the second step contact structure 122. The crystal BLT2 and the first conductive line 131 and the second conductive line 132 respectively connected to the gate of the transistor structure. The conductive line inputs a voltage for selectively turning on or off one of the first and second sets of transistor structures BLT1, BLT2 to control the capacitance of the bit lines BL1 BLBL4.

Please refer to FIG. 2 , which is a cross-sectional view along the line II of the step contact structure 121 of FIG. 1 . For example, a step contact structure 120 in which a four-layer conductive plane 120a and a four-layer insulating plane 120b are alternately arranged on a substrate 111 is used. Each of the bit lines BL1 BL BL4 is sequentially formed on the conductive plugs PG1 on the respective conductive planes 120a. The PG4 is electrically connected to the different conductive planes 120a. Therefore, the capacitances of the respective bit lines BL1 to BL4 are combined by the capacitances between the different conductive planes 120a. The material of the conductive plane 120a is, for example, polysilicon or metal. Further, the material of the insulating plane 120b is, for example, cerium oxide or cerium oxynitride. The material of the conductive plugs PG1 to PG4 is, for example, polycrystalline germanium or tungsten.

In one embodiment, the transistor structure BLT is formed over the step contact structure 120, and includes a first insulating layer 125, a gate layer 126, a second insulating layer 127, and an inner wall of the through hole PH. The gate insulating layer 123 and a semiconductor layer 124 are separated from the gate layer 126 by the gate insulating layer 123. As shown in FIG. 2, the through holes PH penetrate through the first insulating layer 125, the gate layer 126, and the second insulating layer 127, and the semiconductor layer 124 is located in the through hole PH, and the semiconductor layer 124 is adjacent to A doped region S/D is formed at one end of the second insulating layer 127 to serve as a source region or a drain region of the transistor structure BLT. The material of the first insulating layer 125 and the second insulating layer 127 is, for example, hafnium oxide or hafnium oxynitride, and the material of the gate layer 126 is, for example, doped polysilicon or metal. In addition, the material of the gate insulating layer 123 is, for example, tantalum oxide, and the doped region S/D is, for example, a heavily doped region of an n-type conductivity type, and the depth thereof may be greater than the thickness of the second insulating layer 127 to obtain a larger window.

In FIG. 2, the semiconductor layer 124 is, for example, an undoped liner layer formed in the through hole PH with a third insulating layer 128 covering the semiconductor layer 124 to reduce the resistance of the semiconductor layer 124, thereby improving The starting voltage of the transistor. The material of the third insulating layer 128 is, for example, tantalum nitride. The thickness of the third insulating layer 128 deposited in the through hole PH is preferably greater than or equal to the total thickness of the gate layer 126 and the second insulating layer 127.

In addition, please refer to the transistor structure BLT-1 of FIG. 3, which may further include a mask layer 129 and an interlayer dielectric layer 130 thereon. The mask layer 129 selectively covers the second insulating layer 127, and the interlayer dielectric layer 130 covers the mask layer 129. In addition, a conductive plug PG-1 is formed on the gate layer 126 through the mask layer 129, the interlayer dielectric layer 130, and the second insulating layer 127, so that the conductive lines 131 formed on the interlayer dielectric layer 130 or 132 may be coupled to gate layer 126 via conductive plug PG-1 to control the voltage of gate layer 126. In addition, a conductive plug PG-2 is formed on the transistor structure BLT-1 through the mask layer 129 and the interlayer dielectric layer 130, so that one of the bit lines BL1 BL BL4 can pass through the conductive plug PG-2. And connected to the transistor structure BLT-1.

In an embodiment, since the transistor structure BLT is formed in one of the horizontal blocks HB passing through the respective bit lines BL1 BLBL4 to the different conductive planes 120a, that is, in the block indicated by the broken line in FIG. 2, The current passing through the bit lines BL1 to BL4 is controlled by the gate layer 126 around the horizontal block. Therefore, the above-described metal oxide semiconductor (MOS) transistor structure BLT can be used as the bit lines BL1 to The switching elements of BL4, in turn, control the capacitance of bit lines BL1 to BL4.

Referring to FIG. 4 , two sets of SSL gate structures 112 , two sets of source lines 114 , and a plurality of conductive stripes 116 on opposite sides of the step contact structure 120 are further illustrated. Each of the step contact structures 120 can be electrically connected to the plurality of conductive stripes 116 (for example, eight) by the conductive plugs PG of the conductive plugs PG1 to PG4 which are sequentially formed on the respective conductive planes 120a in FIG. In addition, the conductive lines 118 are laterally disposed above the respective step contact structures 120, and the conductive lines 118 are connected to the gate layer 126 by the conductive plugs PG-1 as shown in FIG.

Please refer to FIGS. 5A and 5B , which are schematic diagrams showing the equivalent capacitance before and after the bit line of FIG. 1 is added to the transistor structure. In FIG. 5A, since the transistor structures BLT-1 and BLT-2 are not added, the capacitance of the bit line BL is C=C1+C2, wherein the capacitance C1 is the capacitance between the different conductive planes 120a in the first step contact structure 121. The capacitors C2 are combined to form a capacitance between different conductive planes 120a in the second step contact structure 122. In Fig. 5B, after the transistor structures BLT1 and BLT2 are added, the capacitance C of the bit line BL can be controlled by turning on or off the transistor structure. When the transistor BLT-1 is selected to be turned on, the capacitance C of the bit line BL is C1, and when the transistor BLT-2 is selected to be turned on, the capacitance C of the bit line BL is C2. Therefore, the present invention can effectively solve the problem of signal delay caused by excessive capacitance of the bit line BL by utilizing the above structure.

Please refer to FIGS. 6A-6G, which further illustrate a method of fabricating a transistor structure BLT in FIG. In FIG. 6A, a first insulating layer 125, a gate layer 126, and a second insulating layer 127 are sequentially formed over the step contact structure 120. In Figure 6B, a consistent perforation PH is formed. A liner LN and a conductor CO are formed in the through hole PH. In Fig. 6C, a gate insulating layer 123 is formed on the inner wall of the through hole PH. In FIG. 6D, a semiconductor layer 124 is formed in the through hole PH, and the semiconductor layer 124 is electrically isolated from the gate layer 126 by the gate insulating layer 123. In FIG. 6E, a doped region S/D is formed by ion implantation to the semiconductor layer 124 adjacent to one end of the second insulating layer 127. Further, in FIG. 6E, a third insulating layer 128 may be filled in the through hole PH, such that the transistor structure BLT is substantially completed. In FIG. 6F, a mask layer 129 may be selectively formed on the second insulating layer 127, and then an interlayer dielectric layer 130 is formed on the mask layer 129. In FIG. 6G, a conductive plug PG-1 is formed through the mask layer 129, the interlayer dielectric layer 130, and the second insulating layer 127. A conductive plug PG-2 is formed through the mask layer 129 and the interlayer dielectric layer 130. The final structure is shown in Figure 3 and will not be described here.

Second embodiment

Referring to FIG. 7, a schematic diagram of a semiconductor structure 101 for improving bit line capacitance in accordance with another embodiment of the present invention is shown. The first embodiment described above forms a set of transistor structures BLT above the step contact structure 120, and the present embodiment forms a set of transistor structures BLT1'(BLT2') on one side of the step contact structure 121 (122'). And a conductive line 131'(132') connected to the gate of the transistor structure BLT1'(BLT2'), the conductive line inputs a voltage for selectively turning on or off the transistor structure BLT1'(BLT2'). Descriptions of the bit lines BL1 BLBL4 (BL1' to BL4'), the first step contact structure 121 (121'), the second step contact structure 122 (122'), and the memory stack structure 110 (110'), such as The description of the first embodiment is omitted here.

Referring to FIG. 8, the first step contact structure 121 has a plurality of layers of conductive planes 120a and a plurality of layers of insulating planes 120b. In addition, the second step contact structure 122' and the third step contact structure 143 also have the same number of conductive planes 120a and insulating planes 120b as the first step contact structure 121. The third step contact structure 143 is located between the first set of transistor structures BLT1' and the second set of transistor structures BLT2'.

In FIGS. 7 and 8, the first set of transistor structures BLT1' are connected to the first memory stack structure 110 and the first region bit lines BL1 BLBL4 via the first step contact structure 121, and the second set of transistor structures The BLT 2' is connected to the second memory stack structure 110' and the second region bit lines BL1' to BL4' via the second step contact structure 122'. In addition, the four main bit lines MBL are respectively connected to the first group of transistor structures BLT1' and the second group of transistor structures BLT2 via a plurality of conductive plugs PG' and third step contact structures 143, and are connected by the first group of wires One of the first conductive lines 131' of the crystal structure BLT1' and one of the second conductive lines 132' of the second set of transistor structures BLT2' are selected to turn the transistor on or off.

Please refer to FIG. 9 , which is a cross-sectional view of the transistor structure of FIG. 7 along the VV line. For example, four stacked structures 140 formed by staggering four semiconductor layers 140a and four insulating layers 140b are formed, a gate insulating layer 141 is formed around each stacked structure 140, and a gate layer 142 is formed on the gate insulating layer 141. To form 16 transistor structures controlled by gate layer 142. In FIG. 7, when the respective bit lines BL1 to BL4 are electrically connected to the different conductive planes 120a by the conductive plugs PG1 to PG4 sequentially formed on the respective conductive planes 120a, the conductive plane 120a is further connected to FIG. The semiconductor layers 140a located in the same layer in the transistor structure BLT' are connected. The material of the insulating layer 140 b is, for example, hafnium oxide or hafnium oxynitride, and the material of the gate layer 142 is, for example, doped polysilicon or metal. In addition, the material of the gate insulating layer 141 is, for example, yttrium oxide, and the semiconductor layer 140a is, for example, an undoped polysilicon layer, which can form a doped region by ion implantation to serve as a source region of the transistor structure BLT'. Or bungee area.

In an embodiment, since the transistor structure BLT' is formed in one of the vertical blocks VB through which the respective main bit lines MBL pass to the different conductive planes 120a, that is, the blocks indicated by broken lines in FIG. The current passing through the main bit line MBL is controlled by the gate layer 142 surrounding the vertical block VB, so that the metal oxide semiconductor (MOS) transistor structure BLT' can be used as the main bit line. The switching element of MBL, in turn, controls the capacitance of the main bit line MBL.

Please refer to FIGS. 10A and 10B , which are schematic diagrams showing the equivalent capacitance before and after the bit line of FIG. 7 is added to the transistor structure. In FIG. 10A, since the transistor structures BLT-1' and BLT-2' are not added, the capacitance of the bit line BL is C=C1+C2+C3+C4, wherein the capacitors C1 and C2 are the first memory structure 110. The capacitance between the first and second step contact structures in different conductive planes 120a is combined, and the capacitors C3 and C4 are between the different conductive planes 120a of the first and second step contact structures in the second memory structure 110'. Capacitor combination. In Fig. 10B, after the transistor structures BLT-1' and BLT-2' and the main bit line MBL are added, the capacitance C' of the main bit line MBL can be controlled via the transistor on or off. When the transistor structure BLT-1' is selected to be turned on, the capacitance C' of the main bit line MBL is C1+C2, and when the transistor structure BLT-2' is selected to be turned on, the capacitance C' of the main bit line MBL is C3. +C4. Therefore, the present invention can effectively solve the problem of signal delay caused by the excessive capacitance of the conventional bit line BL by utilizing the above structure.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 100’. . . Semiconductor structure

110, 110’. . . Memory stack structure

111. . . Base

112. . . SSL gate structure

114. . . Source line

116. . . Conductive stripe

118. . . Conductive wire

120, 121, 122, 121', 122'. . . Step contact structure

120a. . . Conductive plane

120b. . . Insulation plane

131, 132, 131', 132'. . . Conductive wire

BL1~BL4, BL1'~BL4’. . . Bit line

BLT, BLT1, BLT2, BLT-1, BLT-2. . . Crystal structure

HB. . . Horizontal block

PG, PG1~PG4. . . Conductive plug

PH. . . Through hole

123. . . Brake insulation

124. . . Semiconductor layer

125. . . First insulating layer

126. . . Gate layer

127. . . Second insulating layer

128. . . Third insulating layer

129. . . Mask layer

130. . . Interlayer dielectric layer

S/D. . . Doped region

PG-1, PG-2. . . Conductive plug

140. . . Stack structure

140a. . . Semiconductor layer

140b. . . Insulation

141. . . Brake insulation

142. . . Gate layer

143. . . Third step contact structure

VB. . . Vertical block

MBL. . . Main bit line

BLT', BLT1', BLT2', BLT-1', BLT-2'. . . Crystal structure

LN. . . lining

CO. . . conductor

FIG. 1 is a top plan view showing a semiconductor structure for improving bit line capacitance according to an embodiment of the invention.

2 is a cross-sectional view of the step contact structure of FIG. 1 taken along line I-I.

Figure 3 is a schematic view showing the structure above the transistor structure.

Figure 4 further illustrates a configuration of the step contact structure.

5A and 5B are schematic diagrams showing equivalent capacitances before and after the bit line of FIG. 1 is added to the transistor structure.

6A-6G further illustrate a method of fabricating a transistor structure in FIG. 2.

FIG. 7 is a top plan view showing a semiconductor structure for improving bit line capacitance according to another embodiment of the present invention.

Figure 8 further illustrates a perspective view of the step contact structure and the transistor structure in Figure 7.

Figure 9 is a cross-sectional view showing the structure of the transistor of Figure 7 taken along line V-V.

10A and 10B are schematic diagrams showing equivalent capacitances before and after the bit line of FIG. 7 is added to the transistor structure.

100. . . Semiconductor structure

110. . . Memory stack structure

121, 122. . . Step contact structure

131, 132. . . Conductive wire

BL1~BL4. . . Bit line

BLT1, BLT2. . . Crystal structure

HB. . . Horizontal block

PG. . . Conductive plug

Claims (12)

A semiconductor structure for improving bit line capacitance, comprising:
a substrate;
a memory stack structure formed on the substrate;
a plurality of bit lines spanning the memory stack structure;
a first step contact structure is formed on the substrate, the first step contact structure comprises a plurality of electrically conductive planes and a plurality of insulating planes which are alternately stacked, and the conductive planes are separated by the insulating planes for layering and connecting a plurality of strips a bit line to the memory stack structure;
a first set of transistor structures formed in the first block through which the bit lines lead to the conductive planes, the first set of transistor structures having a first surrounding the first block a gate; and a first conductive line connected to the first gate to control a voltage of the first gate. The semiconductor structure of claim 1, wherein the plurality of transistor structures comprise a first insulating layer, a gate layer, a second insulating layer, and a first layer formed over the first step contact structure. a gate insulating layer on the inner wall of the through hole and a semiconductor layer separated from the gate layer by the gate insulating layer, the through hole penetrating the first insulating layer, the gate layer and the second insulating layer, the semiconductor The layer is located in the through hole, and the semiconductor layer has a doped region adjacent to one end of the second insulating layer to serve as a source region or a drain region of the transistor structure, wherein the plurality of transistor structures are further A mask layer is included overlying the second insulating layer. The semiconductor structure of claim 2, further comprising a third insulating layer formed in the through hole and covering the semiconductor layer. For example, the semiconductor structure described in claim 2 includes:
An interlevel dielectric layer overlying the mask layer; and a conductive plug formed on the transistor structure through the mask layer and the interlayer dielectric layer. The semiconductor structure of claim 4, further comprising another conductive plug formed on the gate through the mask layer, the interlayer dielectric layer and the second insulating layer On the floor. The semiconductor structure of claim 2, wherein the material of the gate insulating layer comprises ruthenium oxide, and the gate layer is a doped polysilicon layer. For example, the semiconductor structure described in claim 1 of the patent scope further includes:
a second step contact structure is formed on the substrate for layering the bit lines to the memory stack structure;
a second set of transistor structures formed in the second block through which the bit lines lead to the second step contact structure, the second set of transistor structures having a circumference around the second block a second gate; and a second conductive line connected to the second gate to control the voltage of the second gate. A semiconductor structure for improving bit line capacitance, comprising:
a substrate;
a first memory stack structure formed on the substrate;
a plurality of first region bit lines and a main bit line spanning the first memory stack structure;
a first step contact structure formed on the substrate, the first step contact structure comprising a plurality of electrically conductive planes and a plurality of insulating planes staggered and stacked, the conductive planes being separated by the insulating planes for layering the a bit line to the first memory stack structure;
a first set of transistor structures formed in the first block through which the main bit lines lead to the conductive planes, the first set of transistor structures having a circumference around the first block a gate; and a first conductive line connected to the first gate to control the voltage of the first gate. The semiconductor structure of claim 8, wherein the first set of transistor structures comprises a stacked structure composed of a plurality of semiconductor layers and a plurality of insulating layers staggered, a gate insulating layer and a gate layer. A gate insulating layer is formed on the stacked structure, the gate layer is formed on the gate insulating layer, and the semiconductor layers have a doped region as a source region or a drain region of the first group of transistor structures . The semiconductor structure of claim 9, wherein the material of the gate insulating layer comprises ruthenium oxide, and the gate layer is a doped polysilicon layer. For example, the semiconductor structure described in claim 8 of the patent scope further includes:
a second step contact structure is formed on the substrate for layering the second region bit lines to a second memory stack structure;
a second set of transistor structures formed in the second block through which the main bit lines lead to the second step contact structure, the second set of transistor structures having a circumference around the second block a second gate; and a second conductive line connected to the second gate to control the voltage of the second gate. For example, the semiconductor structure described in claim 11 includes:
a third step contact structure between the first set of transistor structures and the second set of transistor structures for layering the main bit lines to the first set of transistor structures and the second group Crystal structure.