TW201405564A - Operating method for memory device and memory array and operating method for the same - Google Patents
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Abstract
Description
本發明係有關於記憶裝置及其操作方法，特別係有關於記憶體陣列及其操作方法。
The present invention relates to a memory device and a method of operating the same, and more particularly to a memory array and method of operating the same.
隨著半導體技術的進步，電子元件的微縮能力不斷提高，使得電子產品能夠在維持固定大小，甚至更小的體積之下，能夠擁有更多的功能。而隨著資訊的處理量愈來愈高，對於大容量、小體積的記憶體需求也日益殷切。
With the advancement of semiconductor technology, the shrinking capability of electronic components has been increasing, enabling electronic products to have more functions while maintaining a fixed size or even a smaller volume. As the processing volume of information becomes higher and higher, the demand for large-capacity and small-volume memory is also growing.
目前的可讀寫記憶體係以電晶體結構配合記憶單元作資訊的儲存，但是此種記憶體架構隨著製造技術的進步，可微縮性已經達到一個瓶頸。因此先進的記憶體架構不斷的被提出，例如相變化隨機存取記憶體(phase change random access memory, PCRAM)、磁性隨機存取記憶體(magnetic random access memory, MRAM)、電阻式隨機存取記憶體(resistive random access memory, RRAM)、導電橋式隨機存取記憶體(conductive bridging RAM, CBRAM)等等。
The current readable and writable memory system uses a transistor structure in conjunction with a memory unit for information storage, but this memory architecture has reached a bottleneck with the advancement of manufacturing technology. Therefore, advanced memory architectures have been proposed, such as phase change random access memory (PCRAM), magnetic random access memory (MRAM), and resistive random access memory. Resistive random access memory (RRAM), conductive bridging RAM (CBRAM), etc.
然而，目前記憶裝置在操作效率上仍需改進。
However, current memory devices still need to be improved in operational efficiency.
本揭露係有關於一種記憶裝置的操作方法與記憶體陣列及其操作方法。可提升記憶裝置的操作效率。
The disclosure relates to a method of operating a memory device and a memory array and a method of operating the same. It can improve the operating efficiency of the memory device.
提供一種記憶裝置的操作方法。方法包括以下步驟。使記憶裝置處在設定狀態，方法包括提供第一偏壓至記憶裝置。讀取記憶裝置的設定狀態，方法包括提供第二偏壓至該記憶裝置。提供回復偏壓至記憶裝置。提供回復偏壓的步驟係在提供第一偏壓的步驟或提供第二偏壓的步驟之後進行。
A method of operating a memory device is provided. The method includes the following steps. The memory device is placed in a set state, the method comprising providing a first bias to the memory device. Reading the set state of the memory device includes providing a second bias to the memory device. Provide a return bias to the memory device. The step of providing a return bias is performed after the step of providing a first bias or the step of providing a second bias.
提供一種記憶體陣列的操作方法。方法包括以下步驟。使電性連接在字元線與位元線之間的雙端電極的記憶裝置處在設定狀態，方法包括藉由字元線與位元線提供第一偏壓至雙端電極的記憶裝置。讀取雙端電極的記憶裝置的設定狀態，方法包括藉由字元線與位元線提供第二偏壓至雙端電極的記憶裝置。藉由字元線與位元線提供回復偏壓至雙端電極的記憶裝置。提供回復偏壓的步驟係在提供第一偏壓的步驟或提供第二偏壓的步驟之後進行。
A method of operating a memory array is provided. The method includes the following steps. The memory device electrically connecting the double-ended electrodes between the word line and the bit line is in a set state, and the method includes a memory device that provides a first bias voltage to the double-ended electrode by the word line and the bit line. The set state of the memory device of the double-ended electrode is read, and the method includes providing a second bias to the memory of the double-ended electrode by the word line and the bit line. A memory device that provides a return bias to the double-ended electrode by a word line and a bit line. The step of providing a return bias is performed after the step of providing a first bias or the step of providing a second bias.
提供一種記憶體陣列。記憶體陣列包括數個記憶胞。記憶胞各包括第一導線、第二導線與記憶裝置。記憶裝置包括第一電極層、第二電極層與固態電解質結構。第一電極層電性連接至第一導線。第二電極層電性連接至第二導線。固態電解質結構鄰接在第一電極層與第二電極層之間。第二電極層為移動金屬離子的來源。移動金屬離子可移動至固態電解質結構中。
下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
A memory array is provided. The memory array includes several memory cells. The memory cells each include a first wire, a second wire, and a memory device. The memory device includes a first electrode layer, a second electrode layer, and a solid electrolyte structure. The first electrode layer is electrically connected to the first wire. The second electrode layer is electrically connected to the second wire. The solid electrolyte structure is adjacent between the first electrode layer and the second electrode layer. The second electrode layer is a source of mobile metal ions. Moving metal ions can move into the solid electrolyte structure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.
第1圖繪示根據一實施例之記憶裝置102的剖面圖。記憶裝置102包括第一電極層104、第二電極層106與固態電解質結構108。固態電解質結構108包括第一固態電解質層110與第二固態電解質層112。第一固態電解質層110鄰接在第一電極層104與第二固態電解質層112之間。第二固態電解質層112鄰接在第一固態電解質層110與第二電極層106之間。實施例並不限於使用具有兩個固態電解質層的固態電解質結構108。於其他實施例中，固態電解質結構(未顯示)可具有單一個固態電解質層。
1 is a cross-sectional view of a memory device 102 in accordance with an embodiment. The memory device 102 includes a first electrode layer 104, a second electrode layer 106, and a solid electrolyte structure 108. The solid electrolyte structure 108 includes a first solid electrolyte layer 110 and a second solid electrolyte layer 112. The first solid electrolyte layer 110 is adjacent between the first electrode layer 104 and the second solid electrolyte layer 112. The second solid electrolyte layer 112 is adjacent between the first solid electrolyte layer 110 and the second electrode layer 106. Embodiments are not limited to the use of a solid electrolyte structure 108 having two solid electrolyte layers. In other embodiments, the solid electrolyte structure (not shown) can have a single solid electrolyte layer.
請參照第1圖，於實施例中，第一電極層104為不易提供移動金屬離子的導體。第二電極層106為移動金屬離子的來源，其中移動金屬離子可移動至固態電解質結構108中。第一固態電解質層110與第二固態電解質層112可為介電材料。第一固態電解質層110的介電係數可大於第二固態電解質層112的介電係數。第一固態電解質層110對於移動金屬離子的可溶性可大於第二固態電解質層112對於移動金屬離子的可溶性。第二電極層106對於移動金屬離子的可溶性可大於第二固態電解質層112對於移動金屬離子的可溶性。舉例來說，第一電極層104可包括高導電性材料例如鉑(Pt)。第二電極層106可包括含有移動金屬之鍺銻碲化物(Germanium Antimony Telluride; GST)的高導電性材料，例如Cu-GST、Au-GST、Zn-GST等等，其中例如Cu、Au、Zn係用作移動金屬。第一固態電解質層110可包括氧化鉿(Hf-oxide)、氧化鋯(Zr-oxide)、或氧化鉭(Ta-oxide)。第二固態電解質層112可包括氧化矽、氮化矽、或氮氧化矽。
Referring to FIG. 1, in the embodiment, the first electrode layer 104 is a conductor that does not easily provide moving metal ions. The second electrode layer 106 is a source of mobile metal ions in which the moving metal ions can move into the solid electrolyte structure 108. The first solid electrolyte layer 110 and the second solid electrolyte layer 112 may be dielectric materials. The dielectric constant of the first solid electrolyte layer 110 may be greater than the dielectric constant of the second solid electrolyte layer 112. The solubility of the first solid electrolyte layer 110 for moving metal ions may be greater than the solubility of the second solid electrolyte layer 112 for mobile metal ions. The solubility of the second electrode layer 106 for moving metal ions may be greater than the solubility of the second solid electrolyte layer 112 for moving metal ions. For example, the first electrode layer 104 can include a highly conductive material such as platinum (Pt). The second electrode layer 106 may include a highly conductive material containing a germanium antimony Telluride (GST) such as Cu-GST, Au-GST, Zn-GST, etc., among which, for example, Cu, Au, Zn Used as a moving metal. The first solid electrolyte layer 110 may include hafnium oxide (Hf-oxide), zirconium oxide (Zr-oxide), or tantalum oxide (Ta-oxide). The second solid electrolyte layer 112 may include hafnium oxide, tantalum nitride, or hafnium oxynitride.
請參照第1圖，於一實施例中，記憶裝置102可具有第一臨界電壓Vt1、第二臨界電壓Vt2、第三臨界電壓Vt3與第四臨界電壓Vt4。於實施例中，第一臨界電壓Vt1係為使記憶裝置102處在設定狀態的臨界電壓Vt-set。第二臨界電壓Vt2係為讀取記憶裝置102之設定狀態的臨界電壓Vt-read set。第三臨界電壓Vt3係為使記憶裝置102處在重設狀態的臨界電壓Vt-reset。第四臨界電壓Vt4係為讀取記憶裝置102之重設狀態的臨界電壓Vt-read reset。於一實施例中，第一臨界電壓Vt1、第二臨界電壓Vt2與第四臨界電壓Vt4具有相同的極性，例如皆為正電壓。第三臨界電壓Vt3可具有相反的極性，例如負電壓。於實施例中，第一臨界電壓Vt1的絕對值係大於第二臨界電壓Vt2的絕對值。這裡所指的臨界電壓可以第二電極層106相對於第一電極層104作討論。
Referring to FIG. 1 , in an embodiment, the memory device 102 can have a first threshold voltage Vt1 , a second threshold voltage Vt2 , a third threshold voltage Vt3 , and a fourth threshold voltage Vt4 . In an embodiment, the first threshold voltage Vt1 is a threshold voltage Vt-set that causes the memory device 102 to be in a set state. The second threshold voltage Vt2 is a threshold voltage Vt-read set for reading the set state of the memory device 102. The third threshold voltage Vt3 is a threshold voltage Vt-reset that causes the memory device 102 to be in a reset state. The fourth threshold voltage Vt4 is a threshold voltage Vt-read reset for reading the reset state of the memory device 102. In one embodiment, the first threshold voltage Vt1, the second threshold voltage Vt2, and the fourth threshold voltage Vt4 have the same polarity, for example, both are positive voltages. The third threshold voltage Vt3 may have opposite polarities, such as a negative voltage. In an embodiment, the absolute value of the first threshold voltage Vt1 is greater than the absolute value of the second threshold voltage Vt2. The threshold voltage referred to herein may be discussed with respect to the first electrode layer 106 with respect to the first electrode layer 104.
請參照第1圖，於一實施例中，記憶裝置102係為雙端電極的記憶裝置，例如例如導電橋式隨機存取記憶體(Conductive Bridging RAM; CBRAM)。實施例之記憶裝置102可應用混合型離子電子導體(Mixed-ionic-electronic-conduction; MIEC)、雙向定限交換(Ovonic Threshold Switch,OTS)材料等等。
Referring to FIG. 1 , in one embodiment, the memory device 102 is a memory device with double-ended electrodes, such as, for example, a conductive bridged random access memory (CBRAM). The memory device 102 of the embodiment may apply a mixed-ionic-electronic-conduction (MIEC), an Ovonic Threshold Switch (OTS) material, or the like.
以下利用第1圖至第3圖說明記憶裝置102的操作方法。這裡所指的偏壓可以第二電極層106相對於第一電極層104作討論，舉例來說，當第一電極層104接地時，偏壓等於施加在第二電極層106的電壓。
Hereinafter, an operation method of the memory device 102 will be described using Figs. 1 to 3 . The bias voltage referred to herein may be discussed with respect to the first electrode layer 104 with respect to the first electrode layer 104. For example, when the first electrode layer 104 is grounded, the bias voltage is equal to the voltage applied to the second electrode layer 106.
記憶裝置102的操作方法包括使記憶裝置102處在設定狀態。
The method of operation of memory device 102 includes causing memory device 102 to be in a set state.
於實施例中，使記憶裝置102處在設定狀態的方法包括提供第一偏壓BV1至如第1圖所示之記憶裝置102。第一偏壓BV1的絕對值係實質上大於、等於用以使記憶裝置102處在設定狀態的第一臨界電壓Vt1的絕對值。如此，使得移動金屬離子從第二電極層106移動至第二固態電解質層112與第一固態電解質層110，而形成鄰接在第一電極層104與第二電極層106之間的導電橋114，如第2圖所示，因此記憶裝置102具有電性導通的特性。
In an embodiment, the method of causing the memory device 102 to be in the set state includes providing the first bias voltage BV1 to the memory device 102 as shown in FIG. The absolute value of the first bias voltage BV1 is substantially greater than or equal to the absolute value of the first threshold voltage Vt1 for causing the memory device 102 to be in the set state. As such, moving metal ions are moved from the second electrode layer 106 to the second solid electrolyte layer 112 and the first solid electrolyte layer 110 to form a conductive bridge 114 adjacent between the first electrode layer 104 and the second electrode layer 106, As shown in Fig. 2, the memory device 102 has electrical continuity characteristics.
使記憶裝置102處在設定狀態的方法可包括在記憶裝置102具有導電特性之後，停止提供第一偏壓BV1至記憶裝置102，例如使第一偏壓BV1為零，或不施加任何電壓至第一電極層104與第二電極層106，以使導電橋114中的移動金屬離子自發性地移出第二固態電解質層112而斷裂，如第3圖所示，斷裂的程度為第二固態電解質層112中實質上不存在移動金屬離子，因此記憶裝置102具有電性阻斷的特性。移動金屬離子自發性地移出第二固態電解質層112係由於移動金屬離子被第一固態電解質層110與第二電極層106吸收所致，其中第一固態電解質層110與第二電極層106對於移動金屬離子的可溶性可大於第二固態電解質層112對於移動金屬離子的可溶性。
The method of causing the memory device 102 to be in the set state may include stopping providing the first bias voltage BV1 to the memory device 102 after the memory device 102 has conductive characteristics, such as zeroing the first bias voltage BV1, or applying no voltage to the first An electrode layer 104 and a second electrode layer 106 are configured to cause the moving metal ions in the conductive bridge 114 to spontaneously move out of the second solid electrolyte layer 112 to be broken. As shown in FIG. 3, the degree of fracture is the second solid electrolyte layer. There is substantially no moving metal ions in 112, and thus the memory device 102 has an electrical blocking characteristic. The moving metal ions spontaneously move out of the second solid electrolyte layer 112 due to the absorption of the moving metal ions by the first solid electrolyte layer 110 and the second electrode layer 106, wherein the first solid electrolyte layer 110 and the second electrode layer 106 move The solubility of the metal ions may be greater than the solubility of the second solid electrolyte layer 112 for the mobile metal ions.
在使記憶裝置102處在設定狀態的步驟中，藉由移動金屬離子自發性地移出第二固態電解質層112而使導電橋114斷裂(第3圖)，斷裂的程度為第二固態電解質層112中實質上不存在移動金屬離子，且使記憶裝置102具有電性阻斷的特性並不是非常快速，而是需要花費特定的緩衝時間(relaxation time)，這緩衝時間會影響記憶裝置102的效率，也可能導致記憶體陣列中未選擇的記憶裝置102在緩衝時間內發生漏電流的問題。因此，在實施例中，在提供第一偏壓BV1以形成鄰接在第一電極層104與第二電極層106之間的導電橋114，且記憶裝置102具有電性導通的特性(如第2圖所示)之後，係提供回復偏壓Vr1至記憶裝置102，以加速導電橋114從第二固態電解質層112斷裂(如第3圖)的效率。如此能提升記憶裝置102的設定效率，也能避免漏電流的問題。於一實施例中，回復偏壓Vr1的極性係相反於第一偏壓BV1的極性。舉例來說，第一偏壓BV1為正電壓，回復偏壓Vr1為負電壓。在實施例中，提供回復偏壓Vr1的步驟可在停止提供第一偏壓BV1的瞬間立即施行，或在停止提供第一偏壓BV1後一可接受的時間(小於緩衝時間)內進行。
In the step of causing the memory device 102 to be in the set state, the conductive bridge 114 is broken by moving the metal ions spontaneously out of the second solid electrolyte layer 112 (Fig. 3), and the degree of fracture is the second solid electrolyte layer 112. There is substantially no moving metal ions in the middle, and the characteristic that the memory device 102 has electrical blocking is not very fast, but a specific relaxation time is required, which affects the efficiency of the memory device 102. It is also possible that the unselected memory device 102 in the memory array has a problem of leakage current during the buffer time. Therefore, in the embodiment, the first bias voltage BV1 is provided to form the conductive bridge 114 adjacent between the first electrode layer 104 and the second electrode layer 106, and the memory device 102 has electrical conduction characteristics (such as the second Thereafter, a recovery bias voltage Vr1 is provided to the memory device 102 to accelerate the efficiency of the conductive bridge 114 breaking from the second solid electrolyte layer 112 (as in Figure 3). This can improve the setting efficiency of the memory device 102, and can also avoid the problem of leakage current. In one embodiment, the polarity of the return bias voltage Vr1 is opposite to the polarity of the first bias voltage BV1. For example, the first bias voltage BV1 is a positive voltage and the return bias voltage Vr1 is a negative voltage. In an embodiment, the step of providing the return bias voltage Vr1 may be performed immediately at the instant when the supply of the first bias voltage BV1 is stopped, or within an acceptable time (less than the buffer time) after the supply of the first bias voltage BV1 is stopped.
於實施例中，在使在使記憶裝置102處在設定狀態之後，係讀取記憶裝置102的設定狀態。
In the embodiment, the setting state of the memory device 102 is read after the memory device 102 is placed in the set state.
讀取記憶裝置102的設定狀態的方法包括提供第二偏壓BV2至記憶裝置102，以使如第3圖所示具有電性阻斷之特性的記憶裝置102，其斷裂的導電橋114與來自第二電極層106的移動金屬離子堆積、連接成如第2圖所示之鄰接在第一電極層104與第二電極層106之間的導電橋114，而變成具有電性導通的特性。於實施例中，第二偏壓BV2的絕對值係實質上大於、等於用以讀取記憶裝置102之設定狀態的第二臨界電壓Vt2的絕對值。於一實施例中，第二偏壓BV2的極性係相同於第一偏壓BV1的極性，例如為正電壓。
The method of reading the set state of the memory device 102 includes providing the second bias voltage BV2 to the memory device 102 such that the memory device 102 having the electrical blocking characteristic as shown in FIG. 3, the broken conductive bridge 114 and the The moving metal ions of the second electrode layer 106 are deposited and connected to the conductive bridge 114 adjacent to the first electrode layer 104 and the second electrode layer 106 as shown in FIG. 2, and become electrically conductive. In an embodiment, the absolute value of the second bias voltage BV2 is substantially greater than or equal to the absolute value of the second threshold voltage Vt2 used to read the set state of the memory device 102. In one embodiment, the polarity of the second bias voltage BV2 is the same as the polarity of the first bias voltage BV1, such as a positive voltage.
讀取記憶裝置102的設定狀態的方法可包括在記憶裝置102具有導電特性之後，停止提供第二偏壓BV2至記憶裝置102，例如使第二偏壓BV2為零，或不施加任何電壓至第一電極層104與第二電極層106，以使第2圖所示之導電橋114中的移動金屬離子自發性地移出第二固態電解質層112而斷裂，如第3圖所示，斷裂的程度為第二固態電解質層112中實質上不存在移動金屬離子，因此記憶裝置102具有電性阻斷的特性。移動金屬離子自發性地移出第二固態電解質層112係由於移動金屬離子被第一固態電解質層110與第二電極層106吸收所致，其中第一固態電解質層110與第二電極層106對於移動金屬離子的可溶性可大於第二固態電解質層112對於移動金屬離子的可溶性。
The method of reading the set state of the memory device 102 may include stopping providing the second bias voltage BV2 to the memory device 102 after the memory device 102 has conductive characteristics, such as zeroing the second bias voltage BV2, or applying no voltage to the first An electrode layer 104 and a second electrode layer 106 are configured to cause the moving metal ions in the conductive bridge 114 shown in FIG. 2 to be spontaneously removed from the second solid electrolyte layer 112, as shown in FIG. There is substantially no moving metal ions in the second solid electrolyte layer 112, and thus the memory device 102 has an electrical blocking property. The moving metal ions spontaneously move out of the second solid electrolyte layer 112 due to the absorption of the moving metal ions by the first solid electrolyte layer 110 and the second electrode layer 106, wherein the first solid electrolyte layer 110 and the second electrode layer 106 move The solubility of the metal ions may be greater than the solubility of the second solid electrolyte layer 112 for the mobile metal ions.
在讀取記憶裝置102的設定狀態的步驟中，藉由移動金屬離子自發性地移出第二固態電解質層112而使導電橋114斷裂(第3圖)，斷裂的程度為第二固態電解質層112中實質上不存在移動金屬離子，且使記憶裝置102具有電性阻斷的特性並不是非常快速，而是需要花費特定的緩衝時間(relaxation time)，這緩衝時間會影響記憶裝置102的讀取效率、讀取準確度與讀取總量(read through-put)，也可能導致記憶體陣列中未選擇的記憶裝置102在緩衝時間內發生漏電流的問題。因此，在實施例中，在提供第二偏壓BV2以形成鄰接在第一電極層104與第二電極層106之間的導電橋114，且記憶裝置102具有電性導通的特性(如第2圖所示)之後，係提供回復偏壓Vr2至記憶裝置102，以加速導電橋114從第二固態電解質層112斷裂(如第3圖)的效率。如此能提升記憶裝置102的讀取效率、讀取準確度與讀取總量，也能避免漏電流的問題。於一實施例中，回復偏壓Vr2的極性係相反於第二偏壓BV2的極性。舉例來說，第二偏壓BV2為正電壓，回復偏壓Vr2為負電壓。在實施例中，提供回復偏壓Vr2的步驟可在停止提供第二偏壓BV2的瞬間立即施行，或在停止提供第二偏壓BV2後一可接受的時間(小於緩衝時間)內進行。
In the step of reading the set state of the memory device 102, the conductive bridge 114 is broken by moving the metal ions spontaneously out of the second solid electrolyte layer 112 (Fig. 3), and the degree of fracture is the second solid electrolyte layer 112. There is essentially no movement of metal ions, and the characteristic of electrically blocking the memory device 102 is not very fast, but requires a specific relaxation time, which affects the reading of the memory device 102. Efficiency, read accuracy, and read through-put may also cause leakage currents in the unselected memory device 102 in the memory array during the buffer time. Therefore, in the embodiment, the second bias voltage BV2 is provided to form the conductive bridge 114 adjacent between the first electrode layer 104 and the second electrode layer 106, and the memory device 102 has electrical conduction characteristics (such as the second After the figure is shown, a recovery bias voltage Vr2 is provided to the memory device 102 to accelerate the efficiency of the conductive bridge 114 breaking from the second solid electrolyte layer 112 (as in Figure 3). In this way, the reading efficiency, the reading accuracy, and the total reading amount of the memory device 102 can be improved, and the problem of leakage current can also be avoided. In one embodiment, the polarity of the return bias voltage Vr2 is opposite to the polarity of the second bias voltage BV2. For example, the second bias voltage BV2 is a positive voltage and the return voltage Vr2 is a negative voltage. In an embodiment, the step of providing the return bias voltage Vr2 may be performed immediately at the instant when the supply of the second bias voltage BV2 is stopped, or within an acceptable time (less than the buffer time) after the supply of the second bias voltage BV2 is stopped.
於實施例中，在讀取記憶裝置102的設定狀態之後，係使記憶裝置102處在重設狀態。
In the embodiment, after reading the set state of the memory device 102, the memory device 102 is placed in the reset state.
使記憶裝置102處在重設狀態的方法包括提供第三偏壓BV3至記憶裝置102，以使固態電解質結構108中的移動金屬離子實質上全部被吸引回第二電極層106中，而回復記憶裝置102成如第1圖所示的情況。於實施例中，第三偏壓BV3的極性係相反於第一偏壓BV1的極性與第二偏壓BV2的極性。舉例來說，第三偏壓BV3係負電壓。第三偏壓BV3的絕對值係實質上大於、等於記憶裝置102之第三臨界電壓Vt3的絕對值。於實施例中，回復偏壓Vr1、Vr2的極性相同於第三偏壓BV3的極性。回復偏壓Vr1、Vr2的絕對值小於第三偏壓BV3的絕對值。
The method of placing the memory device 102 in the reset state includes providing a third bias voltage BV3 to the memory device 102 such that the moving metal ions in the solid electrolyte structure 108 are substantially all attracted back into the second electrode layer 106, and the memory is restored. The device 102 is as shown in Fig. 1. In an embodiment, the polarity of the third bias voltage BV3 is opposite to the polarity of the first bias voltage BV1 and the polarity of the second bias voltage BV2. For example, the third bias voltage BV3 is a negative voltage. The absolute value of the third bias voltage BV3 is substantially greater than or equal to the absolute value of the third threshold voltage Vt3 of the memory device 102. In an embodiment, the polarity of the return bias voltages Vr1, Vr2 is the same as the polarity of the third bias voltage BV3. The absolute values of the recovery bias voltages Vr1, Vr2 are smaller than the absolute value of the third bias voltage BV3.
於實施例中，在使在使記憶裝置102處在重設狀態之後，係讀取記憶裝置102的重設狀態。
In the embodiment, the reset state of the memory device 102 is read after the memory device 102 is placed in the reset state.
讀取記憶裝置102的重設狀態的方法可包括提供第四偏壓BV4至記憶裝置102，以使如第1圖所示具有電性阻斷之特性的記憶裝置102，從第二電極層106中移出移動金屬離子至固態電解質結構108中，而形成如第2圖所示之鄰接在第一電極層104與第二電極層106之間的導電橋114，轉而變成具有電性導通的特性。於實施例中，第四偏壓BV4的極性係相反於第三偏壓BV3的極性。舉例來說，第四偏壓BV4為正電壓。第四偏壓BV4的絕對值係實質上大於、等於記憶裝置102之第四臨界電壓Vt4的絕對值。在一些實施例中，讀取記憶裝置102的重設狀態的方法可包括在記憶裝置102具有導電特性之後，停止提供第四偏壓BV4至記憶裝置102。
The method of reading the reset state of the memory device 102 may include providing the fourth bias voltage BV4 to the memory device 102 such that the memory device 102 having the electrical blocking characteristic as shown in FIG. 1 is from the second electrode layer 106. The moving metal ions are removed from the solid electrolyte structure 108 to form a conductive bridge 114 adjacent to the first electrode layer 104 and the second electrode layer 106 as shown in FIG. 2, and then become electrically conductive. . In an embodiment, the polarity of the fourth bias voltage BV4 is opposite to the polarity of the third bias voltage BV3. For example, the fourth bias voltage BV4 is a positive voltage. The absolute value of the fourth bias voltage BV4 is substantially greater than or equal to the absolute value of the fourth threshold voltage Vt4 of the memory device 102. In some embodiments, the method of reading the reset state of the memory device 102 can include stopping providing the fourth bias voltage BV4 to the memory device 102 after the memory device 102 has conductive characteristics.
實施例之記憶裝置102的操作方法可應用在各種雙端電極的記憶裝置，例如導電橋式隨機存取記憶體(Conductive Bridging RAM; CBRAM)、混合型離子電子導體(Mixed-ionic-electronic-conduction; MIEC)、雙向定限交換(Ovonic Threshold Switch,OTS)材料等等。
The operation method of the memory device 102 of the embodiment can be applied to various double-ended electrode memory devices, such as Conductive Bridging RAM (CBRAM), Mixed-ion-electronic-conduction (Mixed-ionic-electronic-conduction) ; MIEC), Ovonic Threshold Switch (OTS) materials, etc.
第4圖繪示根據一實施例之記憶體陣列。記憶體陣列包括數個記憶胞216。記憶胞216各包括第一導線218、第二導線220與記憶裝置202。記憶裝置202可類似第1圖所示的記憶裝置102。於一實施例中，記憶裝置202係為雙端電極的記憶裝置，例如CBRAM。記憶裝置202的第一電極層204係電性連接至第一導線218。記憶裝置202的第二電極層206電性連接至第二導線220。第一導線218可為字元線與位元線其中之一。第二導線220可為字元線與位元線其中之另一。
FIG. 4 illustrates a memory array in accordance with an embodiment. The memory array includes a plurality of memory cells 216. The memory cells 216 each include a first wire 218, a second wire 220, and a memory device 202. The memory device 202 can be similar to the memory device 102 shown in FIG. In one embodiment, memory device 202 is a dual-ended electrode memory device, such as a CBRAM. The first electrode layer 204 of the memory device 202 is electrically connected to the first wire 218. The second electrode layer 206 of the memory device 202 is electrically connected to the second wire 220. The first wire 218 can be one of a word line and a bit line. The second wire 220 can be the other of the word line and the bit line.
請參照第4圖，記憶體陣列的操作方法利用第一導線218與第二導線220施加偏壓至記憶裝置202，以進行如第1圖至第3圖說明的設定、重設、讀取、施加回復偏壓等等的步驟，並感測讀取的記憶裝置202，同時避免漏電流的問題發生在未選擇的記憶裝置202中。
Referring to FIG. 4, the operation method of the memory array uses the first wire 218 and the second wire 220 to apply a bias voltage to the memory device 202 to perform setting, resetting, reading, and the description as illustrated in FIGS. 1 to 3. The step of applying a return bias or the like and sensing the read memory device 202 while avoiding the problem of leakage current occurs in the unselected memory device 202.
請參照第4圖，在一實施例中，第一導線218與第二導線220之間只有電性連接記憶裝置202，因此能實現純的單一個電阻交叉陣列(pure 1R cross-point array)，並不需要使用額外的驅動、存取裝置。因此，記憶體陣列可具有高的元件密度與低的製造成本。
Referring to FIG. 4, in an embodiment, the first wire 218 and the second wire 220 are electrically connected to the memory device 202, so that a pure single cross-point array (pure 1R) can be realized. There is no need to use additional drivers or access devices. Therefore, the memory array can have high component density and low manufacturing cost.
第5圖為一實施例中記憶裝置的電性圖，其中在第一次正的讀取偏壓(1stread)與第二次正的讀取偏壓(2stread)之間有施加負的回復偏壓。從第5圖可發現，即使兩次讀取偏壓施加時間的間隔很短，記憶裝置在施加第二次讀取偏壓仍具有臨界切換(threshold switching)的特性。
Figure 5 is an electrical diagram of a memory device in an embodiment with an application between a first positive read bias (1 st read) and a second positive read bias (2 st read) Negative return bias. It can be seen from Fig. 5 that even if the interval between the two read bias application times is short, the memory device has the characteristic of threshold switching when the second read bias is applied.
第6圖為一比較例中記憶裝置的電性圖，其中在第一次正的讀取偏壓(1stread)與第二次正的讀取偏壓(2stread)之間並沒有施加負的回復偏壓。從第6圖可發現，即使兩次讀取偏壓施加時間的間隔很長，記憶裝置在施加第二次讀取偏壓仍不具有臨界切換(threshold switching)的特性。
Figure 6 is an electrical diagram of a memory device in a comparative example in which there is no between the first positive read bias (1 st read) and the second positive read bias (2 st read) A negative return bias is applied. It can be seen from Fig. 6 that even if the interval between the two read bias application times is long, the memory device does not have the characteristic of threshold switching when the second read bias is applied.
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
102、202．．．記憶裝置102, 202. . . Memory device
104、204．．．第一電極層104, 204. . . First electrode layer
106、206．．．第二電極層106, 206. . . Second electrode layer
108．．．固態電解質結構108. . . Solid electrolyte structure
110．．．第一固態電解質層110. . . First solid electrolyte layer
112．．．第二固態電解質層112. . . Second solid electrolyte layer
114．．．導電橋114. . . Conductive bridge
216．．．記憶胞216. . . Memory cell
218．．．第一導線218. . . First wire
220．．．第二導線220. . . Second wire
第1圖為根據一實施例之記憶裝置的示意圖。Figure 1 is a schematic illustration of a memory device in accordance with an embodiment.
第2圖為根據一實施例之記憶裝置的示意圖。2 is a schematic diagram of a memory device in accordance with an embodiment.
第3圖為根據一實施例之記憶裝置的示意圖。Figure 3 is a schematic illustration of a memory device in accordance with an embodiment.
第4圖為根據一實施例之記憶體陣列的示意圖。Figure 4 is a schematic illustration of a memory array in accordance with an embodiment.
第5圖為一實施例中記憶裝置的電性圖。Figure 5 is an electrical diagram of a memory device in an embodiment.
第6圖為一比較例中記憶裝置的電性圖。
Figure 6 is an electrical diagram of a memory device in a comparative example.
102．．．記憶裝置102. . . Memory device
104．．．第一電極層104. . . First electrode layer
106．．．第二電極層106. . . Second electrode layer
108．．．固態電解質結構108. . . Solid electrolyte structure
110．．．第一固態電解質層110. . . First solid electrolyte layer
112．．．第二固態電解質層112. . . Second solid electrolyte layer
114．．．導電橋114. . . Conductive bridge
Claims (10)
使一記憶裝置處在設定狀態，方法包括提供一第一偏壓至該記憶裝置；
讀取該記憶裝置的設定狀態，方法包括提供一第二偏壓至該記憶裝置；以及
提供一回復偏壓至該記憶裝置，其中提供該回復偏壓的步驟係在提供該第一偏壓的步驟或提供該第二偏壓的步驟之後進行。A method of operating a memory device, comprising:
Having a memory device in a set state, the method comprising providing a first bias voltage to the memory device;
Reading the set state of the memory device, the method comprising: providing a second bias to the memory device; and providing a return bias to the memory device, wherein the step of providing the return bias is performed by providing the first bias The step or step of providing the second bias is performed.
使電性連接在一字元線與一位元線之間的一雙端電極的記憶裝置處在設定狀態，方法包括藉由該字元線與該位元線提供一第一偏壓至該雙端電極的記憶裝置；
讀取該雙端電極的記憶裝置的設定狀態，方法包括藉由該字元線與該位元線提供一第二偏壓至該雙端電極的記憶裝置；以及
藉由該字元線與該位元線提供一回復偏壓至該雙端電極的記憶裝置，其中提供該回復偏壓的步驟係在提供該第一偏壓的步驟或提供該第二偏壓的步驟之後進行。A method of operating a memory array, comprising:
A memory device electrically connecting a double-ended electrode between a word line and a one-dimensional line is in a set state, the method comprising: providing a first bias voltage to the bit line and the bit line to the Memory device for double-ended electrodes;
Reading a set state of the memory device of the double-ended electrode, the method comprising: providing a second bias to the memory device of the double-ended electrode by the word line and the bit line;
Providing a return bias to the memory device of the double-ended electrode by the word line and the bit line, wherein the step of providing the return bias is performed in the step of providing the first bias or providing the second bias After the steps are taken.
一第一導線；
一第二導線；以及
一記憶裝置，包括：
一第一電極層，電性連接至該第一導線；
一第二電極層，電性連接至該第二導線；以及
一固態電解質結構，鄰接在該第一電極層與該第二電極層之間，其中該第二電極層為移動金屬離子的來源，該些移動金屬離子可移動至該固態電解質結構中。
A memory array includes a plurality of memory cells, wherein the memory cells each include:
a first wire;
a second wire; and a memory device comprising:
a first electrode layer electrically connected to the first wire;
a second electrode layer electrically connected to the second wire; and a solid electrolyte structure adjacent between the first electrode layer and the second electrode layer, wherein the second electrode layer is a source of moving metal ions, The moving metal ions can move into the solid electrolyte structure.
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