CN103579498A - Switching device and operation method thereof and storage array - Google Patents
Switching device and operation method thereof and storage array Download PDFInfo
- Publication number
- CN103579498A CN103579498A CN201210272482.7A CN201210272482A CN103579498A CN 103579498 A CN103579498 A CN 103579498A CN 201210272482 A CN201210272482 A CN 201210272482A CN 103579498 A CN103579498 A CN 103579498A
- Authority
- CN
- China
- Prior art keywords
- solid
- electrolyte layer
- state electrolyte
- switching device
- device shifter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a switching device and an operation method thereof and a storage array. The switching device comprises a first solid electrolyte layer, a second solid electrolyte layer and a switching layer, and the switching layer is arranged between the first solid electrolyte layer and the second solid electrolyte layer in an adjacent mode. The switching device can control the switching state of a storage device in the storage array, and therefore current leakage is avoided.
Description
Technical field
The invention relates to switching device shifter and method of operation thereof, particularly relevant for memory array and the method for operation thereof with switching device shifter.
Background technology
Along with the progress of semiconductor technology, the micro ability of electronic component improves constantly, and makes electronic product maintaining fixed size, under even less volume, can have more function.And along with the treating capacity of information is more and more high, also day by day ardent for the storage requirement of large capacity, small size.
Current scratch pad memory is to coordinate memory cell to do the storage of information with transistor arrangement, but this kind of memory architecture along with the progress of manufacturing technology, micro (scalability) has reached a bottleneck.Therefore advanced memory architecture is constantly suggested, phase change RAM (phase change random access memory for example, PCRAM), magnetic RAM (magnetic random access memory, MRAM), resistive random access memory (resistive random access memory, RRAM).Wherein RRAM have that read or write speed is fast, non-destructive reads, strong for the tolerance of extreme temperature, and can with existing CMOS (complementary metal oxide semiconductor, CMOS) advantage such as process integration, is regarded as having and can replaces the emerging memory technology of all Storage Media potentiality now.
Yet at present memory array is listed in the problem that still has leakage current etc. in operation.
Summary of the invention
The invention relates to a kind of switching device shifter and method of operation thereof and memory array, switching device shifter can, in order to the on off state of the storage device in control storage array, can be avoided leakage current.
The invention provides a kind of switching device shifter, switching device shifter comprises the first solid-state electrolyte layer, the second solid-state electrolyte layer and switchable layer, and switchable layer is adjacent between the first solid-state electrolyte layer and the second solid-state electrolyte layer.
The present invention also provides a kind of memory array, and memory array comprises a plurality of memory cell; Memory cell respectively comprises switching device shifter and storage device; Switching device shifter comprises the first solid-state electrolyte layer, the second solid-state electrolyte layer and switchable layer; Switchable layer is adjacent between the first solid-state electrolyte layer and the second solid-state electrolyte layer; Storage device has a plurality of contact jaws; One of them contact jaw that is electrically connected at storage device of the first solid-state electrolyte layer and the second solid-state electrolyte layer one of at least.
The present invention also provides a kind of method of operation of switching device shifter, and this switching device shifter comprises the first solid-state electrolyte layer, the second solid-state electrolyte layer and switchable layer, and switchable layer is adjacent between the first solid-state electrolyte layer and the second solid-state electrolyte layer; Method of operation comprises the following steps: apply first and be biased into switching device shifter, so that the character of switchable layer is transformed into and electrically conducts from electrical blocking-up; Apply and be different from second of the first bias voltage and be biased into switching device shifter, so that the character of switchable layer is transformed into electrical blocking-up from electrically conducting.
Preferred embodiment cited below particularly, and coordinate appended graphicly, be described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates according to the profile of the switching device shifter of an embodiment.
Fig. 2 A illustrates according to the profile of the switching device shifter of an embodiment.
Fig. 2 B illustrates according to the profile of the switching device shifter of an embodiment.
Fig. 3 A illustrates according to the profile of the switching device shifter of an embodiment.
Fig. 3 B illustrates according to the profile of the switching device shifter of an embodiment.
Fig. 4 illustrates according to the schematic diagram of the memory array of an embodiment.
Fig. 5 illustrates according to the schematic diagram of the memory array of an embodiment.
Fig. 6 illustrates according to the profile of the memory construction of an embodiment.
Fig. 7 illustrates according to the profile of the memory construction of an embodiment.
[main element symbol description]
102,202~switching device shifter; 104~the first solid-state electrolyte layer; 106~the second solid-state electrolyte layer; 108~switchable layer; 110~conducting bridge; 112~memory cell; 114,214,314~storage device; 116~the first contact jaws; The second contact jaw; 120~current switch; 222,322~the first electrodes; 224,324~the second electrodes; 226~dielectric layer; 328~electrode layer for the first time; 330~electrode layer for the second time; 332~electrode layer for the third time; The 334~four sub-electrode layer; The 336~five sub-electrode layer; 338~protuberance; BL~bit line; WL~word line.
Embodiment
Fig. 1 illustrates according to the profile of the switching device shifter 102 of an embodiment.Switching device shifter 102 comprises the first solid-state electrolyte layer 104, the second solid-state electrolyte layer 106 and switchable layer 108.Switchable layer 108 is adjacent between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106, and separates the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106.The material of the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 can comprise respectively chalcogen (chalcogenide) compound that contains metal material, for example, contain the chalcogenide of copper or silver.In an embodiment, the material of the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 can be respectively tellurium copper (Te-Cu) alloy.So the present invention is not limited to this, and in other embodiment, the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 can comprise respectively tellurium silver (Te-Ag) alloy or other suitable materials.The material of switchable layer 108 can comprise dielectric medium, for example silica, silicon nitride, silicon oxynitride or other suitable dielectric materials.
Switching device shifter 102 can utilize self-registered technology manufacture, do not need to use extra mask, so low cost of manufacture.
Please refer to Fig. 1, switching device shifter 102 is not applying under the situation of any bias voltage, and the switchable layer 108 being formed by dielectric material is the character with electrical blocking-up.In embodiment, switching device shifter 102 is used as current switch.
Fig. 2 A and Fig. 2 B illustrate according to the method for operation of the switching device shifter 102 of an embodiment.As shown in Figure 2 A, in an embodiment, to apply positive switching bias voltage (electric field) (being for example greater than in fact 0V) to switching device shifter 102, for example make the first solid-state electrolyte layer 104 ground connection of switching device shifter 102, and apply positive voltage to the second solid-state electrolyte layer 106 of switching device shifter 102, so that the metal ion of the positively charged in the second solid-state electrolyte layer 106 moves in switchable layer 108, and be accumulated between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 and form the conducting bridge 110 of adjacency, make by this switchable layer 108 there is the characteristic electrically conducting, in other words, electric current can be by conducting bridge 110 circulations in switchable layer 108 between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106.In an embodiment, use so that switchable layer 108 is transformed into the positive switching bias voltage electrically conducting.In the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106, be in the demonstration example of tellurium copper (Te-Cu) alloy, mobile metal ion is copper ion.
As shown in Figure 2 B, in an embodiment, removing the positive switching bias voltage that switchable layer 108 is transformed into electrically conduct, voltage to the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 are not for example provided, or make electric field between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 be zero (for example equaling in fact 0V) afterwards, in conducting bridge 110, the metal ion of close the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 can be attracted and move in the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106, and automatically rupture in the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106, therefore the character of switchable layer 108 is transformed into electrical blocking-up, in other words, electric current cannot circulate between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106.
Fig. 3 A and Fig. 3 B illustrate according to the method for operation of the switching device shifter 102 of an embodiment.As shown in Figure 3A, in an embodiment, to apply negative switching bias voltage (electric field) (being for example less than in fact 0V) to switching device shifter 102, for example make the first solid-state electrolyte layer 104 ground connection of switching device shifter 102, and apply negative voltage to the second solid-state electrolyte layer 106 of switching device shifter 102, so that the metal ion of the positively charged in the first solid-state electrolyte layer 104 moves in switchable layer 108, and be accumulated between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 and form the conducting bridge 110 of adjacency, make by this switchable layer 108 there is the characteristic electrically conducting, in other words, electric current can be by conducting bridge 110 circulations in switchable layer 108 between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106.In an embodiment, use so that switchable layer 108 is transformed into the negative switching bias voltage electrically conducting.In the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106, be in the demonstration example of tellurium copper (Te-Cu) alloy, mobile metal ion is copper ion.
As shown in Figure 3 B, in an embodiment, removing the negative switching bias voltage that switchable layer 108 is transformed into electrically conduct, voltage to the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 are not for example provided, or make electric field between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 be zero (for example equaling in fact 0V) afterwards, in conducting bridge 110, the metal ion of close the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106 can be attracted and move in the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106, and automatically rupture in the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106, therefore the character of switchable layer 108 is transformed into electrical blocking-up, in other words, electric current cannot circulate between the first solid-state electrolyte layer 104 and the second solid-state electrolyte layer 106.
In an embodiment, be to provide positive program bias Vp to storage device, positive program bias Vp causes positive switching bias voltage Vs in being electrically connected to the switching device shifter 102 of storage device, makes switchable layer 108 have the character electrically conducting, as shown in Figure 2 A.Then, removable positive program bias Vp, makes the switchable layer 108 of switching device shifter 102 have the character of electrical blocking-up, and as shown in Figure 2 B, meanwhile, storage device is maintained at programming state.Then, can provide positive and read bias voltage Vr with the programming state of read storage device, wherein just read bias voltage Vr and can in being electrically connected to the switching device shifter 102 of storage device, cause positive switching bias voltage Vs, make switchable layer 108 there is the character electrically conducting, as shown in Figure 2 A.In embodiment, program bias Vp, switching bias voltage Vs can represent by following formula with the relation that reads bias voltage Vr:
2*Vs>Vp>Vr>Vs
In an embodiment, be to provide and negative wipe bias voltage Ve to storage device, the negative bias voltage Ve that wipes causes negative switching bias voltage Vs in being electrically connected to the switching device shifter 102 of storage device, makes switchable layer 108 have the character electrically conducting, as shown in Figure 3A.Then, the removable negative bias voltage Ve that wipes, makes the switchable layer 108 of switching device shifter 102 have the character of electrical blocking-up, and as shown in Figure 3 B, meanwhile, storage device is maintained at erase status.Then, can provide positive and read bias voltage Vr with the erase status of read storage device, wherein just read bias voltage Vr and can in being electrically connected to the switching device shifter 102 of storage device, cause positive switching bias voltage Vs, make switchable layer 108 there is the character electrically conducting, as shown in Figure 2 A.In embodiment, wipe bias voltage Ve, switch bias voltage Vs and can represent by following formula with the relation that reads bias voltage Vr:
2*|Vs|>|Ve|>Vr>|Vs|
Fig. 4 illustrates according to the schematic diagram of the memory array of an embodiment.Memory array is classified crosspoint array (cross-point array) device as.Memory array comprises a plurality of memory cell 112.Memory cell 112 respectively comprises switching device shifter 102 and storage device 114.Switching device shifter 102 can electrically be connected with storage device 114.Switching device shifter 102 can be similar to the switching device shifter 102 shown in Fig. 1.Please refer to Fig. 4, in an embodiment, storage device 114 is to have the first relative contact jaw 116 and the second contact jaw 118.For instance, the first contact jaw 116 of storage device 114 can be electrically connected to the second solid-state electrolyte layer 106 (Fig. 1) of switching device shifter 102, the second contact jaw 118 of storage device 114 can be electrically connected to bit line BL, and the first solid-state electrolyte layer 104 (Fig. 1) of switching device shifter 102 can be electrically connected to word line WL.In embodiment, switching device shifter 102 is in order to control switch storage device 114, and current switch 120 that can be is as shown in Figure 5 represented.
Fig. 6 illustrates according to the profile of the memory construction of an embodiment.Memory construction comprises the switching device shifter 202 and storage device 214 between the first electrode 222 and the second electrode 224.Switching device shifter 202 and the storage device 214 of different layers are separated from each other by dielectric layer 226.Switching device shifter 202 can be similar to the switching device shifter 102 shown in Fig. 1.The first electrode 222 and the second electrode 224 can comprise metal for example tungsten, titanium nitride etc.For instance, the first electrode 222 is top electrode, and the second electrode 224 is bottom electrode.In an embodiment, storage device 214 comprises resistance-type memory, comprises tungsten oxide (WOx).For instance, memory construction can have side wall construction, for example the storage device 214 of single sidewall.
Fig. 7 illustrates according to the profile of the memory construction of an embodiment.The difference of the memory construction shown in the memory construction shown in Fig. 7 and Fig. 6 is, the first electrode 322 comprises for the first time electrode layer 328 and electrode layer 330 for the second time.Electrode layer 330 is for the first time between electrode layer 328 and switching device shifter 202 for the second time.The second electrode 324 comprises electrode layer 332, the 4th sub-electrode layer 334 and the 5th sub-electrode layer 336 for the third time.The 4th sub-electrode layer 334 is for the third time between electrode layer 332 and the 5th sub-electrode layer 336.Electrode layer 328 can be used different materials from electrode layer 330 for the second time for the first time.In an embodiment, for instance, electrode layer 328 comprises tungsten for the first time, and electrode layer 330 comprises titanium nitride for the second time.Electrode layer 332, the 4th sub-electrode layer 334 can be used different materials from the 5th sub-electrode layer 336 for the third time.In an embodiment, for instance, the 4th sub-electrode layer 334 comprises tungsten, and electrode layer 332 and the 5th sub-electrode layer 336 comprise titanium nitride for the third time.Storage device 314 can have protuberance 338 between for the third time between electrode layer 332, the 4th sub-electrode layer 334 and the 5th sub-electrode layer 336.
Switching device shifter in embodiment can be applied to variable resistance type memory (ReRAM), programmable metallization unit (Programmable Metallization Cell; PMC) ReRAM, phase transition storage (Phase Change Memory; PCM), magnetic RAM (Magnetoresistive Random Access Memory; MRAM) spin transfer torque magnetic RAM (Spin Transfer Torque Magnetoresistive Random Access Memory for example; STT-MRAM).Switching device shifter in embodiment can be in order to realize three-dimensional (three dimensional) ReRAM.Use switching device shifter to integrate with bipolar (bipolar) ReRAM simply.Switching device shifter installs applicable to crosspoint array (cross-point array).
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; any those who are familiar with this art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is when being as the criterion of defining depending on the claim scope of enclosing.
Claims (10)
1. a switching device shifter, comprising:
One first solid-state electrolyte layer;
One second solid-state electrolyte layer; And
One switchable layer, is adjacent between this first solid-state electrolyte layer and this second solid-state electrolyte layer.
2. switching device shifter according to claim 1, wherein the material of this first solid-state electrolyte layer and this second solid-state electrolyte layer comprises respectively chalcogen (chalcogenide) compound that contains metal material, and this switchable layer comprises silica, silicon nitride or silicon oxynitride.
3. switching device shifter according to claim 1, wherein this first solid-state electrolyte layer and this second solid-state electrolyte layer are separated from each other by this switchable layer.
4. a memory array, comprises a plurality of memory cell, and wherein the plurality of memory cell respectively comprises:
As the switching device shifter of claims 1 to 3 as described in one of them; And
One storage device, has a plurality of contact jaws, and wherein one of them the plurality of contact jaw that is electrically connected at this storage device of this first solid-state electrolyte layer and this second solid-state electrolyte layer one of at least.
5. memory array according to claim 4, wherein this storage device has one first relative contact jaw and one second contact jaw, and this of this storage device the first contact jaw is electrically connected to this second solid-state electrolyte layer of this switching device shifter.
6. memory array according to claim 4, more comprise a plurality of word lines and bit line, wherein this first solid-state electrolyte layer of this switching device shifter be electrically connected to the plurality of word line one of them, this of this storage device the second contact jaw be electrically connected to the plurality of bit line one of them.
7. memory array according to claim 4, wherein this storage device comprises variable resistance type memory (ReRAM), Programmable Metallization Cell (PMC) ReRAM, Phase Change Memory (PCM), and MRAM
8. memory array according to claim 4, wherein this storage device is electrical series connection with this switching device shifter.
9. memory array according to claim 4, wherein this switching device shifter is used as current switch.
10. a method of operation for switching device shifter, comprising:
Applying one first is biased into as the switching device shifter of claims 1 to 3 as described in one of them, so that the character of this switchable layer is transformed into and electrically conducts from electrical blocking-up; And
Apply and be different from one second of this first bias voltage and be biased into this switching device shifter, so that the character of this switchable layer is transformed into electrical blocking-up from electrically conducting.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210272482.7A CN103579498A (en) | 2012-08-02 | 2012-08-02 | Switching device and operation method thereof and storage array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210272482.7A CN103579498A (en) | 2012-08-02 | 2012-08-02 | Switching device and operation method thereof and storage array |
Publications (1)
Publication Number | Publication Date |
---|---|
CN103579498A true CN103579498A (en) | 2014-02-12 |
Family
ID=50050837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210272482.7A Pending CN103579498A (en) | 2012-08-02 | 2012-08-02 | Switching device and operation method thereof and storage array |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103579498A (en) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101635331A (en) * | 2008-07-24 | 2010-01-27 | 海力士半导体有限公司 | Resistive memory device and method of fabricating the same |
CN101728483A (en) * | 2008-10-10 | 2010-06-09 | 旺宏电子股份有限公司 | Dielectric-sandwiched pillar memory device |
CN101887903A (en) * | 2009-05-15 | 2010-11-17 | 旺宏电子股份有限公司 | Phase change memory with transistor, resistor and capacitor and operating method thereof |
CN102044293A (en) * | 2009-10-13 | 2011-05-04 | 南亚科技股份有限公司 | Cross point memory array device |
CN102544365A (en) * | 2012-01-18 | 2012-07-04 | 北京大学 | Resistance random access memory and manufacturing method thereof |
US20120168705A1 (en) * | 2010-12-30 | 2012-07-05 | Micron Technology, Inc. | Bipolar Switching Memory Cell With Built-in "On" State Rectifying Current-Voltage Characteristics |
-
2012
- 2012-08-02 CN CN201210272482.7A patent/CN103579498A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101635331A (en) * | 2008-07-24 | 2010-01-27 | 海力士半导体有限公司 | Resistive memory device and method of fabricating the same |
CN101728483A (en) * | 2008-10-10 | 2010-06-09 | 旺宏电子股份有限公司 | Dielectric-sandwiched pillar memory device |
CN101887903A (en) * | 2009-05-15 | 2010-11-17 | 旺宏电子股份有限公司 | Phase change memory with transistor, resistor and capacitor and operating method thereof |
CN102044293A (en) * | 2009-10-13 | 2011-05-04 | 南亚科技股份有限公司 | Cross point memory array device |
US20120168705A1 (en) * | 2010-12-30 | 2012-07-05 | Micron Technology, Inc. | Bipolar Switching Memory Cell With Built-in "On" State Rectifying Current-Voltage Characteristics |
CN102544365A (en) * | 2012-01-18 | 2012-07-04 | 北京大学 | Resistance random access memory and manufacturing method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Ielmini | Resistive switching memories based on metal oxides: mechanisms, reliability and scaling | |
Prakash et al. | TaO x-based resistive switching memories: prospective and challenges | |
US9208873B2 (en) | Non-volatile storage system biasing conditions for standby and first read | |
JP5469239B2 (en) | Three-dimensional array of reprogrammable non-volatile memory elements having vertical bit lines | |
JP2021122054A (en) | Effective use of memory die area | |
JP5722874B2 (en) | Three-dimensional array of reprogrammable non-volatile memory elements having vertical bit line and single sided word line architectures | |
US9196362B2 (en) | Multiple layer forming scheme for vertical cross point reram | |
CN101971264B (en) | Non-volatile memory with resistive access component | |
CN108806746A (en) | Hybrid cross point memory device and its operating method | |
TWI515935B (en) | Switching device structures and methods | |
US8824188B2 (en) | Operating method for memory device and memory array and operating method for the same | |
US20140175371A1 (en) | Vertical cross-point embedded memory architecture for metal-conductive oxide-metal (mcom) memory elements | |
WO2014138182A1 (en) | 3d non-volatile memory having low-current cells and fabrication thereof | |
US10847579B1 (en) | Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture | |
CN110800120B (en) | Memory cell with resistor and formation thereof | |
KR20160082488A (en) | Two-terminal memory electrode comprising a non-continuous contact surface | |
US9000412B2 (en) | Switching device and operating method for the same and memory array | |
US9548449B2 (en) | Conductive oxide random access memory (CORAM) cell and method of fabricating same | |
TWI485701B (en) | Switching device and operating method for the same and memory array | |
CN103579498A (en) | Switching device and operation method thereof and storage array | |
KR102210302B1 (en) | Segregation-based memory | |
Kim | High density crossbar structure for memory application | |
Rana et al. | Redox-based memristive devices | |
CN103578532A (en) | Operating method of storage device, memory array and operating method of memory array | |
Lee | Fabrication and Characterization of Nanoscale Resistance Change Memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140212 |