TW201349345A - Method for etching organic hardmasks - Google Patents

Abstract

A method of etching or removing an organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an organic hardmask to be removed, the dielectric film having a dielectric constant no greater than about 4.0, introducing over the organic hardmask an ionizable gas comprising a mixture of hydrogen and an oxidizing gas, and applying energy to the mixture to create a plasma of the mixture. The method further includes contacting the organic hardmask with the plasma, with the organic hardmask being at a temperature in excess of 200 DEG C, to remove the organic hardmask without substantially harming the underlying substrate.

Description

Method for etching an organic hard mask

The present invention relates to a cleaning process for a semiconductor lithography fabrication system, and more particularly to an organic hard mask for etching such as amorphous carbon or spin-on carbon, or removing such as amorphous carbon or spin from a low dielectric constant film. A method of applying a carbon organic hard mask.

Integrated circuits (ICs) are fabricated on a semiconductor wafer substrate by lithography. The lithography process allows the mask pattern having the desired circuit or portion thereof to be transferred to the photoresist film on the substrate by the radiant energy of the selected wavelength. These absorbed spatial image segments have energy that exceeds the critical energy of the chemical bonds in the photosensitive component of the photoresist material, producing a latent image in the photoresist. The volume of the photoresist material marked by the latent image is removed during the development process (in the case of a positive photoresist) or after development (in the case of a negative photoresist) to create a three-dimensional pattern in the photoresist film . In a subsequent process, the formed photoresist film pattern is used as an etch mask to remove the underlying substrate from the patterned opening region within the photoresist layer.

Mosaic processing techniques are commonly used in the fabrication of integrated circuits, and the recesses and vias contained in the dielectric layer form a damascene metal conductor. The openings in the hard mask layer are used to etch a desired portion of the dielectric layer to form recesses and vias. The opening of the hard mask layer is formed by etching through an opening formed in the photoresist layer overlying it. The hard mask in the damascene process can be made of an organic layer, such as a-carbon or alpha-carbon.

The development of 248 nm to 193 nm wavelength development techniques has increased the complexity of mask integration, often requiring deposition of a stack of multiple stacks on the layer to be etched. One example is a three-layer stack: a SiON anti-reflective coating (ARC) layer on which a conventional photoresist is spin-coated and treated is applied over an amorphous carbon hard mask layer. After photoresist development, fluorine dry etching transfers the pattern to the SiON layer. Photoresist removal and simultaneous oxygen-based etching Rows to remove a carbon from the hard mask layer from the opening in the SiON layer. The dielectric etch process then transfers the pattern from the a carbon hard mask to the underlying dielectric layer for the dual damascene process. After etching the dielectric layer, the a-carbon hard mask layer must be removed before Cu or other metal interconnects are formed at the back end of the wafer processing flow.

U.S. Patent No. 6,787,452 to Sudijono et al. discloses a method of controlling critical dimensions during a photoresist patterning process that can be applied to form vias and recesses in a dual damascene structure. Amorphous carbon ARC is deposited on the substrate by plasma enhanced chemical vapor deposition (PECVD). The sub-carbon layer provides a high etch selectivity versus oxygen and is disclosed as being removable by a plasma ashing step using oxygen. A method of removing a polymeric organic mask layer using a hydrogen/nitrogen based plasma is taught in U.S. Patent No. 6,458,516 to the name of U.S. Pat.

Low dielectric constant (low-k) materials, that is, those having a dielectric constant generally less than about 2.7 to 3.0, have been used in damascene processing as inter- and/or interlayer dielectrics between conductive interconnects. Quality to reduce signal transmission delay due to capacitive effects. The lower the dielectric constant of the dielectric material, the lower the capacitance of the dielectric and the lower the RC delay of the integrated circuit. Typically the low-k dielectric is a cerium oxide based material with a small amount of bound carbon, which is commonly referred to as carbon doped oxide (CDO). One example of a CDO is a CORAL brand carbon doped oxide from Novellus Systems, San Jose, California. We have found that highly oxidized conditions are generally not suitable for use with low-k materials. Oxygen removes or removes carbon from the low-k material when exposed to the O ₂ plasma. In many such materials such as CDOs, the presence of carbon helps provide a low dielectric constant. Thus, oxygen effectively increases the dielectric constant to the extent that oxygen removes carbon from these materials. With the miniaturization of the process direction for manufacturing integrated circuits and the use of dielectric materials having increasingly lower dielectric constants, it has been found that conventional stripping plasma conditions are no longer suitable.

Therefore, we need to develop an alternative treatment in the art to effectively remove the organic hard mask layer such as amorphous carbon without removing excess low-k dielectric material or greatly changing the low-k dielectric. The nature of the material.

In accordance with an embodiment of the present invention, an improved method of etching and/or removing an organic hard mask from a wafer substrate in lithography is provided.

In accordance with another embodiment of the present invention, a method of removing an organic hard mask without damaging the underlying dielectric layer is provided.

In accordance with another embodiment of the present invention, a method of removing an organic hard mask without damaging the underlying low-k dielectric layer is provided.

In accordance with another embodiment of the present invention, a method of removing an organic hard mask without affecting etching into critical dimension features of the underlying low-k dielectric layer is provided.

It will be apparent to those skilled in the art from this disclosure that the above and other embodiments can be achieved in the present invention. The present invention provides a method of etching or removing an organic hard mask (such as an amorphous carbon organic hard mask), the method comprising providing a substrate having an organic hard mask thereon to be removed; comprising hydrogen and an oxidizing gas An ionizable gas of the mixture is introduced onto the substrate and the organic hard mask; and energy is applied to the mixture to produce a plasma of the mixture. The method further comprises contacting the organic hard mask with the plasma, wherein the temperature of the substrate and the organic hard mask exceeds 200 ° C to remove at least a portion of the organic hard mask and expose without substantially destroying the underlying substrate Substrate.

Preferably, the organic hard mask is completely removed from the underlying substrate.

In another embodiment, the present invention provides a method of removing an organic hard mask on a low dielectric constant film in a lithography process, the method comprising providing an organic hard mask having a green dielectric layer to be removed thereon a dielectric film of the cap, the dielectric film having a dielectric constant of no more than about 4.0; and contacting the organic hard mask with a plasma comprising an ionized mixture of hydrogen and an oxidizing gas, wherein the dielectric film is organically hard The temperature of the mask exceeds 200 ° C to remove the organic hard mask without substantially affecting the underlying dielectric film.

In a further embodiment, the present invention provides a method of etching or removing an organic hard mask on a low dielectric constant film in a lithography process, the method comprising providing an organic to be removed thereon a hard masked dielectric film having a dielectric constant of no greater than about 4.0; an ionizable gas comprising a mixture of hydrogen and oxidizing gas introduced onto the organic hard mask; and application of energy to the mixture To produce a plasma of the mixture. The method further includes contacting the organic hard mask with the plasma, wherein the temperature of the dielectric film and the organic hard mask exceeds 200 ° C to remove the organic hard mask without substantially damaging the underlying substrate.

The organic hard mask can be a chemical vapor deposited amorphous carbon and the substrate can be a dielectric film, such as a dielectric film having a dielectric value of less than about 3.0, such as a carbon doped oxide dielectric film.

The organic hard mask may be amorphous carbon, and the dielectric film may have no more than about 2.8 Dielectric constant.

The oxidizing gas can be supplied from a source of carbon dioxide. The gas mixture is preferably substantially free of nitrogen.

In other embodiments, the present invention comprises a wafer having a dielectric layer comprising a plurality of dielectric materials, including a bulk low-k dielectric underlying a capping dielectric, the capping dielectric The mass has a higher k value than the bulk low-k dielectric. In some embodiments, both the bulk low-k dielectric and the capping dielectric are low-k dielectrics. In other embodiments, the bulk low-k dielectric is a low-k dielectric and the capping dielectric is not a low-k dielectric.

In other embodiments, the plurality of dielectric materials may comprise a dispersed bulk low-k dielectric and a capping dielectric layer, or the plurality of dielectric materials may be in the bulk low-k dielectric material and the capping dielectric material. There is a continuous gradual transition between.

20‧‧‧ wafer

22‧‧‧etch stop layer

24‧‧‧Low k dielectric layer

24a‧‧ Covering dielectric

24b‧‧‧Substantial low-k dielectric

25‧‧‧ Wafer surface

26‧‧‧Organic hard mask

28‧‧‧Dielectric ARC layer

30‧‧‧Anti-reflective coating

32‧‧‧Photoresist layer

34‧‧‧ openings

36‧‧‧ wall

36‧‧‧ Groove

36'‧‧‧Corrosion side wall

600‧‧‧ plasma equipment

601‧‧‧Exposure chamber

603‧‧‧ wafer

605‧‧‧ platform

609‧‧‧ entrance

611‧‧‧The Plasma Generation Department

613‧‧‧Induction coil

615‧‧‧Power supply

617‧‧‧Spray head assembly

730‧‧‧ Stripping unit tool

731‧‧‧Load station

733‧‧‧ stripping station

735‧‧‧ stripping station

737‧‧‧ stripping station

739‧‧‧ stripping station

741‧‧‧ stripping station

743‧‧‧ Robotic arm

The present invention can be described in detail with reference to the following detailed description in conjunction with the accompanying drawings, wherein: FIG. 1 and FIG. 1A are organic hard masks deposited on a wafer substrate on a low-k dielectric to be etched, Front view of the cross section of the photoresist and other layers.

2 and 2A are cross-sectional front views of the wafer substrate of FIGS. 1 and 1A, respectively, after the photoresist on the low-k dielectric, the organic hard mask, and other layers are etched.

3 and 3A are cross-sectional front views of the wafer substrate of FIGS. 2 and 2A, respectively, after the plurality of layers on the etched organic hard mask layer are removed.

4 and 4A are cross-sectional front views of the wafer substrate of FIGS. 3 and 3A, respectively, after etching a low-k dielectric through an organic hard mask layer.

5 and 5A are cross-sectional front views of the wafer substrate of FIGS. 3 and 3A, respectively, after the organic hard mask layer is removed by the high temperature plasma method of the present invention without destroying the low-k dielectric.

Figure 6 is a schematic illustration of a device suitable for use in practicing the present invention.

Figure 7 is a simplified block diagram showing a multi-processing station stripping tool suitable for use in practicing the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described with reference to the drawings, wherein like numerals indicate similar features of the invention.

The present invention relates to the removal of organic hard mask materials for forming ashable hard masks (AHM), such as amorphous carbon hard masks, also known as a carbon or sub-carbon, or spin coating. Hard cover. These hard masks can be formed on the substrate by chemical vapor deposition (CVD), spin coating, or other techniques. AHM materials are generally composed primarily of carbon, such as from about 50 to about 80 weight percent, with the balance being hydrogen and possibly trace amounts of nitrogen. Examples of such starting materials used to form the film comprising of CH ₄ and C ₂ H _2, or more generally C _x H _y, wherein x = 2 to 4, and y = 2 through 10.

While the method of the present invention can be used to efficiently and efficiently remove organic hard mask materials from low-k dielectric films, the method is not limited to low-k dielectric films, or even to dielectrics. The invention is also not limited to any particular class of low k dielectrics. For example, the present invention can effectively use a dielectric having a k value of less than 4.0 (also referred to as a first generation low-k dielectric) and a dielectric having a k value of less than about 2.8 (second-generation low-k dielectric) And a dielectric having a k value of less than about 2.0 (ultra-low-k dielectric). The low-k dielectric can be porous or non-porous (the latter sometimes also referred to as dense low-k dielectric). In general, the dense low-k dielectric is those having a k value of no more than 2.8, and the low-k porous dielectric system has a k value of no more than 2.2. A low-k dielectric having any suitable composition may be used, including a cerium oxide-based dielectric doped with fluorine and/or carbon. Non-oxide based ruthenium based dielectrics such as polymeric materials can also be used. Any suitable treatment can be used to deposit the low-k dielectric, including spin-on deposition and CVD deposition techniques. Any suitable method can be used in forming the porous dielectric. A typical method involves co-depositing a sulfhydryl backbone and an organic pore former, and then removing the pore former component, leaving a porous dielectric membrane. Other methods include sol-gel techniques. Specific examples of suitable low-k films are carbon-based spin-on films sold by Dow Chemicals, Inc. under the trademark SiLK, and CVD-deposited porous films sold by Novellus Systems, Inc. under the trademark CORAL.

The etching and removal of the organic hard mask is preferably performed by active plasma etching. In general, reactive plasma etching is performed in situ in a plasma reactor wherein the processing chamber promotes activation and/or dissociation of the reactive gas by applying RF energy to the capacitive coupling electrode within the processing chamber. Plasma typically produces highly reactive species that react with unwanted deposition materials in the processing chamber and etch away the material. The invention may use microwave (MW) generated plasma, inductively coupled plasma (ICP) or in a parallel plate reactive ion etch (RIE) reactor.

A plasma reactor apparatus useful in the practice of the invention includes a vacuum pump for creating a vacuum within the processing chamber. The apparatus of the present invention also includes a process gas inlet assembly, such as a pressurized gas cylinder coupled to an inlet conduit connected to a gas distribution panel or showerhead within the processing chamber. A semiconductor wafer substrate or other workpiece is placed on a carrier or platform that can apply a bias voltage to the substrate. An RF or other power supply applies electrical power between the gas distribution panel or the showerhead and the carrier to energize the process gas or gas mixture to form a plasma in the cylindrical reaction zone between the faceplate and the carrier.

The ionizable process gas system used in the present invention is preferably a mixture of hydrogen and an oxygen-containing gas or an oxidizing gas such as CO or CO ₂ . The oxidizing gas preferably comprises a mixture of about 0.5 to 10 volume percent. Preferably, the gas mixture to be ionized does not contain nitrogen to avoid damage to any of the underlying CDO dielectric layers by binding nitrogen into the film, which is known to produce interaction with the photoresist. The amine group causes a so-called photoresist poisoning effect. Sensitive photoresists, such as 193nm photoresist, react with amine groups, which neutralize acidic compounds in the photoresist and prevent them from developing properly, and are removed in the solvent removal step in the lithography sequence. Thus, residual light is retained in undesired areas of the wafer. Adding Ar or He may have some benefits, but this has not been done with a plasma suitable for H2+CO2. The use of He or Ar in the RIE etch tool can increase the etch rate or benefit the processing later by sputtering the post-etch polymer or other defects that are often left on the wafer surface 25. Therefore, there may be benefits in leaving a clean wafer surface or a surface with fewer submicron defects.

It is important to maintain the temperature of the wafer above about 200 ° C, preferably above 250 ° C, and more preferably between about 250-350 ° C during plasma etching. Heating elements can be supplied to the processing chamber for this purpose. During operation, the plasma processing gas moves from one side of the vacuum chamber to the other side due to the flow of the ionizable process gas to one side of the vacuum chamber, and the vacuum is generated on one of its opposite sides. The plasma treatment gas diffuses throughout the surface of the wafer substrate, removing the organic hard mask and carrying the volatile material to the vacuum pump assembly.

As shown in FIG. 1, wafer 20 includes an etch stop layer 22 and a low-k dielectric layer 24 deposited thereon. An organic (e.g., amorphous carbon) hard mask layer 26 is deposited on the low-k dielectric layer 24. Photoresist layer 32, selective organic (or spin-on) anti-reflective coating (ARC) layer 30, and SiOC (produced by reacting CO ₂ with Si(CH ₃ ) ₄ ), SiON or Si ₃ N ₄ ARC layer The dielectric ARC layer 28 is on the organic hard mask layer. The photoresist layer is exposed to the element pattern and developed to remove the photoresist material volume corresponding to the pattern. As shown in FIG. 2, the opening 34 in the remaining photoresist layer 32 is then used as a mask to etch the corresponding material volume from the ARC layers 28, 30 and the organic hard mask layer 26.

The photoresist layer and the ARC layer are then removed to leave an organic hard mask layer and an etched pattern opening 34 on layer 24, as shown in FIG. The photoresist layer and the residue are removed by the process disclosed in U.S. Patent Application Serial Nos. 10/890,653, the entire disclosure of which is incorporated herein by reference. Typically, the wafer is subjected to ashing to strip and remove the photoresist layer, such as by hydrogen plasma stripping to a plasma reactor and a low-k dielectric film. After stripping the photoresist and other cap layers, the organic hard mask layer is then used to etch the lower k dielectric layer underneath, for example, by reactive ion etching (RIE), as shown in FIG. 34 extends downward into the low-k dielectric layer 24 to create an opening having walls 36.

Another more common method is to expose a wafer having a plurality of layers as shown in FIG. 2 to an RIE etch without removing layers 32, 30, 28. Since the RIE etch typically takes a long time, the layers 32, 30, 28 will be completely removed before the etch stop layer 22 is exposed. The resulting structure is shown in Figure 4. This is achieved by exposing the structure shown in FIG. 2 to the RIE etch, thereby eliminating the need to separate the photoresist/ARC removal steps described above and shown in FIG. 3, and resulting in the structure of FIG.

The wafer is then subjected to the high temperature plasma cleaning process of the present invention to remove the organic hard mask layer leaving a low-k dielectric layer that is unbroken and that is susceptible to receiving conductive metal in the opening 36. The plasma treatment can be carried out in the same reactor used for the hydrogen plasma ashing process, but requires the use of heating elements to achieve the desired reaction temperature. Next, as shown in FIG. 5, the surface 25 of the dielectric layer 24 is substantially free of a-carbon or other organic hard mask residues, and the size of the etched vias or recesses 36 within the dielectric layer. It is unaffected and is not damaged by any of the corroded side walls 36'.

In the Novellus Systems Iridia 200mm etch tool, the wafer containing the organic hard mask layer on the low-k dielectric layer was heated by a heat lamp to a temperature of 280 °C. Microwave power between about 1000-3000 W (typically about 1800 W) and 2.45 GHz can be applied to a gas mixture of H ₂ /CO ₂ , which is about 500-4000 sccm (typically about 1800 sccm). The rate inflow pressure is maintained in a chamber between 750-4000 mT (typically 1000 mT). After a processing time of between 30 and 180 seconds, typically about 90 seconds, the organic hard mask layer is removed without substantially damaging the low-k dielectric layer.

In Novellus Systems' Gamma tool, a wafer containing an organic hard mask layer on a low-k dielectric layer is heated to 280 °C by a resistive heating platform. RF power between 500-3000 W (typically about 2000 W) and 3.56 MHz can be applied to a gas mixture of H ₂ /CO ₂ at a rate of about 5000-40000 sccm (typically about 20,000 sccm). The inflow pressure is maintained in a chamber between 750-4000 mT (typically 1100 mT). The tool contains from 4 to 6 platforms and the wafer is moved between all platforms during the etching process. After a total treatment or plasma exposure time of between about 20 seconds and 180 seconds, typically about 90 seconds, the organic hard mask layer is removed without substantially damaging the low-k dielectric layer.

In a Novellus Systems Iridia 300mm Sierra etch tool with dual power supplies, the wafer containing the organic hard mask layer on the low-k dielectric layer was heated to 280 °C. Microwave power between about 1000-3000 W (typically about 1800 W) and 2.45 GHz can be applied to a gas mixture of H ₂ /CO ₂ , which is about 500-4000 sccm (typically about 1800 sccm). The rate inflow pressure is maintained in a chamber between 750-4000 mT (typically 1000 mT). The platform supporting the wafer is located in the RF plasma reaction chamber and is coupled to a 3.56 MHz RF source that supplies between 500-2000 W (typically 1000 W). After a processing time of between about 30 seconds and 180 seconds, typically about 90 seconds, the organic hard mask layer is removed without substantially damaging the low-k dielectric layer.

Gas flow rate, RF power settings, exposure time, and other parameters can be adjusted to achieve the desired results for other cleaning operations.

Accordingly, the present invention provides an improved method of etching an organic hard mask and/or removing an organic hard mask layer from a wafer substrate in a lithography process, particularly removing amorphous carbon from a low-k dielectric layer. Improved method of time. The present invention achieves the removal of the organic hard mask without damaging the underlying low-k dielectric substrate.

Other embodiments

In addition to the embodiments described with reference to Figures 1 through 5 above, other embodiments of the present invention are described below with reference to Figures 1A-5A, 6 and 7.

As shown in FIG. 1A, another embodiment of the present invention includes a wafer 20 having a low-k dielectric layer 24 deposited on an etch stop layer 22. The dielectric layer 24 comprises a plurality of dielectric materials including a bulk low-k dielectric 24b under the capping dielectric 24a, covering the dielectric 24a. It has a higher k value than the bulk low-k dielectric 24b. In some embodiments, both the bulk low-k dielectric 24b and the capping dielectric 24a are low-k dielectrics. In other embodiments, the bulk low-k dielectric 24b is a low-k dielectric and the capping dielectric 24a is not a low-k dielectric.

In some embodiments, the bulk low-k dielectric can be an ultra low k (ULK) dielectric, such as having a k value of about 2.2, and the capping dielectric can be a carbon doped with a k value of about 2.9. Carbon-doped oxide (CDO).

In other embodiments, the bulk low-k dielectric layer can be CDO having a k value of about 2.9, and the cover layer can be tetraethyl orthosilicate (TEOS) having a k value of about 4.0.

In other embodiments, the plurality of dielectric materials can comprise a dispersed bulk low-k dielectric layer and a capping dielectric layer, that is, separate and adjacent dielectric layers. Alternatively, the plurality of dielectric materials can have a continuous gradual transition between the bulk low-k dielectric material and the capping dielectric material. This gradual transition can be substantially evenly from one side of the dielectric layer 24 to the other. It may also be non-uniform, changing from one dielectric to another and only crossing a portion of the total thickness of the dielectric layer 24, for example, less than 50% of the total thickness of the dielectric 24, or less than 25%, or less than 10%, or less than 5% by thickness.

An organic carbon hard mask layer 26 is deposited on the low-k dielectric layer 24. Photoresist layer 32, selective organic (or spin-on) anti-reflective coating (ARC) layer 30, and including SiOC (produced by reacting CO ₂ with Si(CH ₃ ) ₄ ), SiON or Si ₃ N ₄ ARC layer The dielectric ARC layer 28 is on the organic hard mask layer. The photoresist layer is exposed to a component pattern and developed to remove the photoresist material volume corresponding to the pattern. As shown in FIG. 2A, the opening 34 in the remaining photoresist layer 32 is then used as a mask to etch the corresponding material volume from the plurality of ARC layers 28, 30 and the organic hard mask layer 26.

The photoresist layer and the ARC layer are then removed to leave an organic hard mask layer and etched pattern openings 34 on layer 24, as shown in FIG. 3A, to expose the dielectric layer under the hard mask layer 26. twenty four. The photoresist layer and the residue are removed by the process disclosed in U.S. Patent Application Serial Nos. 10/890,653, the entire disclosure of which is incorporated herein by reference. Typically, the wafer is subjected to ashing to strip and remove the photoresist layer, such as by hydrogen plasma stripping to a plasma reactor and a low-k dielectric film. After stripping the photoresist and other cap layers, the organic hard mask layer 26 is then used to etch the underlying low-k dielectric layer 24 (24a and 24b) by, for example, reactive ion etching (RIE), as shown in the figure. 4A, wherein the opening 34 is made The lower portion extends into the low-k dielectric layer 24 to create an opening having a wall 36 that further exposes the dielectric layer 24.

Another more common method is to expose a wafer having a plurality of layers as shown in FIG. 2A to an RIE etch without removing layers 32, 30, 28. Since the RIE etch typically takes a long time, the layers 32, 30, 28 will be completely removed before the etch stop layer 22 is exposed. The resulting structure is shown in Figure 4A. This is achieved by exposing the structure shown in FIG. 2A to RIE etching, thereby eliminating the need to separate the photoresist/ARC removal steps described above and shown in FIG. 3A, and resulting in the structure of FIG. 4A.

The wafer is then subjected to the high temperature plasma cleaning process of the present invention to remove the organic hard mask leaving a low-k dielectric layer that is uncorrupted and that readily receives conductive metal in the opening 36. It is important to note that the low-k dielectrics 24a and/or 24b exposed during removal of the hard mask are not damaged by this removal process. The plasma treatment can be carried out in the same reactor used for the hydrogen plasma ashing process, but requires the use of heating elements to achieve the desired reaction temperature. Next, as shown in FIG. 5A, the surface 25 of the dielectric layer 24 is substantially free of a-carbon or other organic hard mask residues, and the size of the etched via or recess 36 in the dielectric layer is not It is also affected by any damage caused by the corroded sidewalls 36'.

device

Any suitable plasma reaction chamber apparatus can be used to practice the invention, including the Gamma and Iridia tools described above. Suitable examples in this respect it is further Novellus Gamma ^TM 2130 tool based downstream plasma configuration settings. 6 is a schematic diagram showing an embodiment of a downstream plasma apparatus 600 suitable for implementing the present invention on a wafer. Apparatus 600 has a plasma generating portion 611 and an exposure chamber 601 separated by a showerhead assembly 617. In the exposure chamber 601, the wafer 603 is placed on a platform (or stage) 605. The platform 605 is equipped with heating/cooling elements. In some embodiments, the platform 605 is also configured to apply a bias to the wafer 603. In the exposure chamber 601, the low pressure is achieved by the conduit 607 and by a vacuum pump. The source of gaseous hydrogen (with or without dilution/carrier gas) and carbon dioxide (or other weak oxidant) provides a flow of gas through inlet 609 into the plasma generating portion 611 of the apparatus. The plasma generating portion 611 is partially surrounded by an induction coil 613 connected to the power source 615. During the operation, the gas mixture is guided to the plasma generating portion 611, energy is supplied to the induction coil 613, and plasma is generated in the plasma generating portion 611. A showerhead assembly 617 having an applied voltage terminates the flow of a portion of the ions and allows neutral species to flow into the exposure chamber 601. As previously mentioned, the wafer 603 can be temperature controlled and/or can apply an RF bias.

In some embodiments, the apparatus of the present invention is a stripping unit dedicated to stripping photoresist from the wafer. Overall, this stripping unit tool will have several wafer processing stations that can process several wafers simultaneously. 7 is a simplified top block diagram showing a multi-processing station wafer stripping unit tool 730 that can be used in accordance with the present invention. The stripping unit tool 730 has five stripping stations 733, 735, 737, 739, and 741 and a load station 731. The stripping unit tool 730 is configured such that each stripping station can process one wafer, so all stripping stations can be exposed to a common vacuum. Each stripping station 733, 735, 737, 739, and 741 has its own RF power supply. The load station 731 is typically configured to have a load lock station attached thereto to place the wafer into the strip unit tool 730 without damaging the vacuum. The load station 731 is also typically configured with a heater lamp to preheat the wafer, transfer the wafer to the stripping station, and perform photoresist stripping. The stripping station 741 is typically configured with a load lock station attached thereto for outputting the wafer from the stripping unit tool 730 without damaging the vacuum. The robot arm 743 transfers wafers between stations.

In a typical production mode, wafers are processed in batch mode. Batch mode processing increases wafer throughput and is therefore often used in manufacturing operations. In batch mode, each wafer system is transferred to and processed in each station 731, 733, 735, 737, 739, and 741. For example, a typical batch mode process would proceed as follows: First the wafer is loaded to load station 731 where it is preheated by a heat lamp. Next, the robotic arm 743 transfers the wafer to the stripping station 733 where it is plasma treated for a sufficient time to strip about one-fifth of the photoresist. The robotic arm 743 then transfers the wafer to a stripping station 735 where the wafer is subjected to a plasma treatment for a sufficient time to strip another 1/5 of the remaining photoresist. This sequence is continued so that the wafers are processed at stripping stations 737, 739 and 741. When stripping station 741, most of the photoresist should be removed and wafer 741 unloaded from the stripping unit tool.

Other suitable embodiments for G400 gt ;, GxT ^TM and ^TM photoresist stripping tool comprises a tool according to the present invention Novellus Systems Company, Producer Flex ^TM etching tool Lam Research 2300, Tokyo Electron Limited of a Telius ^TM etching tool, or Applied Materials ^(TM) Etching tool.

It is generally understood that the aforementioned apparatus/processing can be used in conjunction with lithographic patterning tools or processes to fabricate or process semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Although not necessarily, but usually these tools/processes will be used together or in a common manufacturing facility. Row. The lithographic patterning of the film usually comprises some or all of the following steps, each step requires some possible tools: (1) applying a photoresist to the substrate, ie, the substrate, using a spin coating or spraying tool; Use a hot plate or hot furnace or UV curing tool to cure the photoresist; (3) use a tool such as a wafer stepper to expose the photoresist to visible or ultraviolet or X-ray; (4) develop the photoresist to use The wet bench tool selectively removes the photoresist and thereby patterns the photoresist; (5) transfers the photoresist pattern to the underlying film or substrate using a dry or plasma assisted etch tool; (6) uses, for example, RF or microwave The tool of the plasma photoresist stripper removes the photoresist.

Another embodiment of the invention is an apparatus configured to achieve the methods described herein. Suitable equipment includes hardware for performing processing operations as well as system controllers having instructions for controlling processing operations in accordance with the present invention. Suitable plasma chamber equipment, such as Gamma and Iridia tools or other tools described above, can be used in this manner. The system controller typically includes one or more processors and one or more memory devices configured to execute instructions that cause the device to perform the method in accordance with the present invention. A machine readable medium containing control processing operations in accordance with the present invention can be coupled to a system controller.

The present invention has been described in detail with reference to the preferred embodiments thereof. Therefore, it is intended that the following claims be construed as including any such alternatives, modifications, and variations

20‧‧‧ wafer

22‧‧‧etch stop layer

24‧‧‧Low k dielectric layer

24a‧‧ Covering dielectric

24b‧‧‧Substantial low-k dielectric

26‧‧‧Organic hard mask

34‧‧‧ openings

36‧‧‧ wall

Claims (18)

A method of etching or removing an organic hard mask, comprising: providing a semiconductor wafer substrate comprising an exposed low-k dielectric, wherein the substrate comprises a bulk low-k dielectric underlying the capping dielectric, The capping dielectric has a higher k value than the low-k dielectric of the body, and the substrate has an organic hard mask to be removed thereon; introducing an ionizable gas comprising a mixture of hydrogen and an oxidizing gas To the substrate and the organic hard mask; applying energy to the mixture to produce a plasma of the mixture; and contacting the organic hard mask with the plasma to remove at least a portion of the organic hard mask The underlying substrate surface or the exposed low-k dielectric is not destroyed. A method of etching or removing an organic hard mask according to claim 1, wherein the organic hard mask comprises chemical vapor deposited amorphous carbon. A method of etching or removing an organic hard mask according to claim 1, wherein the organic hard mask comprises a spin-on carbon film. The method of etching or removing an organic hard mask according to claim 1, wherein the bulk low-k dielectric and the covering dielectric are low-k dielectrics. The method of etching or removing an organic hard mask according to claim 1, wherein the bulk low-k dielectric is a low-k dielectric and the covering dielectric is not a low-k dielectric. A method of etching or removing an organic hard mask according to claim 1, wherein the low-k dielectric has a dielectric constant of no more than about 3. A method of etching or removing an organic hard mask according to claim 1 wherein the low-k dielectric has a dielectric constant of no greater than about 2.8. A method of etching or removing an organic hard mask according to claim 1 wherein the low-k dielectric has a dielectric constant of no greater than about 2.2. A method of etching or removing an organic hard mask according to claim 1, wherein the bulk low-k dielectric is an ultra-low-k dielectric having a dielectric constant of about 2.2 (ULK, ultra-low-k) And the covering dielectric is a carbon doped oxide (CDO) having a dielectric constant of about 2.9. A method of etching or removing an organic hard mask as claimed in claim 1 wherein the body is low The k dielectric is a carbon doped oxide (CDO) having a dielectric constant of about 2.9 and the covering dielectric is tetraethyl orthosilicate (TEOS) having a dielectric constant of about 4.0. . A method of etching or removing an organic hard mask according to claim 1, wherein the substrate comprises a dispersed bulk low-k dielectric and a covering dielectric layer. A method of etching or removing an organic hard mask according to claim 1, wherein the substrate comprises a gradual transition between the bulk low-k dielectric material and the covering dielectric material. A method of etching or removing an organic hard mask as claimed in claim 1, wherein the gas mixture does not contain nitrogen. A method of etching or removing an organic hard mask according to claim 1, wherein the organic hard mask is completely removed from the lower substrate. The method of etching or removing an organic hard mask according to claim 1, further comprising: applying a photoresist to the substrate; exposing the photoresist to light; patterning the photoresist and transferring the pattern to the substrate And selectively removing the photoresist from the substrate. An apparatus for etching or removing an organic hard mask on a dielectric, the apparatus comprising: (a) a plasma reaction chamber apparatus; and (b) a controller including program instructions for performing processing, The step of processing includes: providing a semiconductor wafer substrate comprising an exposed low-k dielectric, wherein the substrate comprises a bulk low-k dielectric underlying the capping dielectric, the capping dielectric having a lower k than the body a higher k value of the dielectric, and the substrate has an organic hard mask to be removed thereon; an ionizable gas comprising a mixture of hydrogen and an oxidizing gas is introduced onto the substrate and the organic hard mask Applying energy to the mixture to produce a plasma of the mixture; and contacting the organic hard mask with the plasma to remove at least a portion of the organic hard mask without damaging the substrate surface or the exposure below Low-k dielectric. A semiconductor wafer processing system comprising: the apparatus for etching or removing an organic hard mask on a dielectric as in claim 16; and a stepper. A non-transitory computer machine readable medium comprising a plurality of program instructions for controlling a plasma reaction chamber device, the program instructions comprising: a code for providing a semiconductor wafer substrate including an exposed low-k dielectric Wherein the substrate comprises a bulk low-k dielectric underlying the capping dielectric, the capping dielectric having a higher k-value than the low-k dielectric of the body, and the substrate has thereon to be removed An organic hard mask; a code for introducing an ionizable gas comprising a mixture of hydrogen and an oxidizing gas onto the substrate and the organic hard mask; a plasma for applying energy to the mixture to produce the mixture And a code for contacting the organic hard mask with the plasma to remove at least a portion of the organic hard mask without damaging the underlying substrate surface or the exposed low-k dielectric.