CN103247525A - Method for etching organic hardmasks - Google Patents

Method for etching organic hardmasks Download PDF

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Publication number
CN103247525A
CN103247525A CN2013100498563A CN201310049856A CN103247525A CN 103247525 A CN103247525 A CN 103247525A CN 2013100498563 A CN2013100498563 A CN 2013100498563A CN 201310049856 A CN201310049856 A CN 201310049856A CN 103247525 A CN103247525 A CN 103247525A
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dielectric
low
hard mask
organic hard
substrate
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CN103247525B (en
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卫斯理·P·格拉夫
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Novellus Systems Inc
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Novellus Systems Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The present invention provides a method for etching or removing an organic hardmask on a low dielectric constant film in a photolithography technology. The method comprises the steps of providing a dielectric medium film, wherein the to-be-removed organic hardmask is arranged above the dielectric medium film, and the dielectric medium film has a dielectric constant not greater than 4.0; introducing an ionogenic gas above the organic hardmask, wherein the ionogenic gas comprises a mixture of hydrogen and oxidizing gases; and applying energy to the mixture to form a plasma of the mixture. The method also comprises the step of using the plasma to contact the organic hardmask to remove the organic hardmask while not damaging a substrate therebelow substantially.

Description

The method that is used for the organic hard mask of etching
Technical field
The present invention relates to be used in the cleaning procedure in the semiconductor lithography manufacturing system, specifically relate to a kind of method for the organic hard mask such as amorphous carbon or Spun-on carbon from film having low dielectric constant etching or removal.
Background technology
Integrated circuit (IC) is made in semiconductor wafer substrate by photoetching process.The part that this photoetching process can make the mask pattern of required circuit or this pattern is transferred to photoresist film on the substrate by the radiant energy of selected wavelength.Those absorbed aerial image (aerial image) parts because its energy has surpassed the transition energy (threshold energy) of the chemical bond in the photosensitive composition of this photoresist material, thereby have formed potential image in this photoresist material.This potential image shows that this part photoresist material can be removed (under the situation of positive photoresist) or can be retained (under the situation at negative photoresist) to form three-dimensional pattern in this photoresist film after developing in developing process.In follow-up processing, formed photoresist film pattern is used as etching mask with the substrate below remove the open area of the patterning of this photoresist layer.
Mosaic technology technology (damascene processing techniques) often is used in during integrated circuit makes, and it relates in groove in dielectric layer and the hole and forms the embedded with metal conductor.Use the opening in the hard mask layer to come the required part of this dielectric layer of etching to form described groove and hole.Opening in this hard mask layer is to pass the opening that is formed in the photoresist layer that covers and self forms via etching.Hard mask in the mosaic technology can be made by organic layer, and organic layer is for example α-carbon (α-carbon) or Alpha-carbon (alpha-carbon).
The photoetching that develops into 193 nano wave lengths from the photoetching of 248 nano wave lengths has increased the complexity of mask integrated (masking integration), usually need be on layer to be etched deposit multilayer stack layer (multilayer stack).An example is the three level stack layer, and wherein SiON antireflecting coating (ARC) covers on the amorphous carbon hard mask layer, and traditional resist can be spun on this antireflecting coating also processed.After this resist is developed, by the fluorine dry etching process with design transfer to the SiON layer.This resist is removed, and removes α-carbon in the described hard mask layer together with adopting based on the etch process of oxygen with the opening from described SiON layer.Then by dielectric etch process with the dielectric layer of this pattern below described α-carbon hardmask is transferred to, this dielectric layer is used in dual-damascene method.After this dielectric layer of etching, before this wafer processes rear end forms Cu or other metal interconnected thing, need to remove α-carbon hardmask layer.
People's such as Sudijono United States Patent (USP) 6,787,452 discloses a kind of method of controlling critical size in photoresist Patternized technique process, and this method can be used to form hole and groove in dual-damascene structure (dual damascene structure).By plasma enhanced chemical vapor deposition (PECVD) method amorphous carbon ARC is deposited on the substrate.This Alpha-carbon-coating provides with respect to the high etching selectivity of oxide and has been disclosed as it and can easily have been removed by the plasma ashing step of using oxygen.People's such as Ye United States Patent (USP) 6,458,516 discloses a kind of plasma removal method polymerization, organic mask layer of using hydrogen/nitrogen base.
Low-k is (low-k) material, be that those dielectric constants are usually less than about material of 2.7 to 3.0, be used as intermetallic and/or interlayer dielectric between the conductive interconnection thing in mosaic technology, described conductive interconnection thing is used to reduce because the delay that the signal that capacity effect (capacitive effects) causes is propagated.The dielectric constant of dielectric substance is more low, and this dielectric electric capacity is just more low, and the RC of this integrated circuit postpones just more little.Usually, low-k dielectric is the silica based materials in conjunction with carbon (incorporated carbon) with some, is commonly called carbon doped oxide (CDO).The example of CDO is that trade mark is the carbon doped oxide of CORAL, and it comes from the Novellus System Co., Ltd of the San Jose (San Jose) of California (California).On the low-k material that has been found that highly oxidized environment is not suitable for usually.When being exposed to O 2In the time of in the plasma, the carbon in this low-k material can be removed or remove to oxygen.In many this materials, CDO for example, having of carbon helps provide low-k.Therefore, oxygen has been removed carbon to a certain extent from these materials, and this has improved dielectric constant effectively.Along with the technology for the manufacture of integrated circuit is used the dielectric substance with more and more lower dielectric constant towards more and more littler size development and requirement, have been found that it is inappropriate that traditional plasma is removed condition (strip plasma conditions).
Therefore, the needs that have a kind of alternative techniques of development in the art, this technological requirement can effectively be removed organic hard mask layer, amorphous carbon for example, and can not remove too much low-k dielectric substance or can substantially not change the character of low-k dielectric substance.
Summary of the invention
According to an aspect of the present invention, provide a kind of in photoetching process from the wafer substrates etching and/or remove the improved method of organic hard mask.
According to another aspect of the present invention, providing a kind of removes organic hard mask and can not damage the method for following dielectric layer.
According to another aspect of the present invention, providing a kind of removes organic hard mask layer and can not damage the method for following low-k dielectric layer.
According to another aspect of the present invention, providing a kind of removes organic hard mask layer and can not influence the method for the critical size feature that etches in the following dielectric layer.
Above-mentioned aspect and according to of the present invention open, the aspect that it will be apparent to those skilled in the art that can realize by a kind of etching disclosed by the invention or the method for removing organic hard mask (for example organic hard mask of amorphous carbon), this method comprises provides the substrate that has organic hard mask to be removed thereon, above this substrate and organic hard mask, introduce the ionogenic gas of the mixture that comprises hydrogen and oxidizing gas, and apply energy to form the plasma of this mixture to this mixture.Then, this method comprises with this plasma contact this organic hard mask, and wherein the temperature of this substrate and organic hard mask is above 200 ℃, with at least a portion of removing this organic hard mask and expose this substrate and the substrate below the material injury not.
Preferably, this organic hard mask is removed from following substrate fully.
In one aspect of the method, the present invention relates to a kind of method that covers the organic hard mask on the film having low dielectric constant of in photoetching process, removing, this method comprises provides the dielectric film that has organic hard mask to be removed thereon, this dielectric film has and is not more than about 4.0 dielectric constant, and contact this organic hard mask with the plasma of the mixture that comprises ionized hydrogen and oxidizing gas, the temperature of wherein said dielectric film and organic hard mask surpasses 200 ℃, the dielectric film to remove described organic hard mask below the non-substantial effect.
Further, the present invention relates to a kind of in photoetching process etching or removal cover the method for the organic hard mask on the film having low dielectric constant, comprise the dielectric film that has organic hard mask to be removed thereon is provided, this dielectric film has and is no more than about 4.0 dielectric constant, above this organic hard mask, introduce the ionogenic gas of the mixture that comprises hydrogen and oxidizing gas, and apply energy to form the plasma of this mixture to this mixture.This method also comprises with this plasma contact this organic hard mask, and wherein the temperature of this dielectric film and organic hard mask is above 200 ℃, the substrate below the material injury not to remove this organic hard mask.
The amorphous carbon that described organic hard mask can be chemical vapour deposition (CVD), and described substrate can be dielectric film, for example dielectric radio is less than about 3.0 dielectric film, for example, the carbon doped oxide dielectric film.
Described organic hard mask can be amorphous carbon, and described dielectric film can have and is not more than about 2.8 dielectric constant.
Described oxidizing gas can be provided by carbon dioxide source.This admixture of gas preferably is substantially devoid of nitrogen.
In other embodiments, the present invention includes the wafer with dielectric layer, this dielectric layer comprises multiple dielectric substance, this multiple dielectric substance comprise the accumulation (bulk) that is positioned at covering dielectric below low-the k dielectric, the dielectric k value of low-k that the k value of this covering dielectric is higher than this accumulation.In some embodiments, this accumulation low-k dielectric and this covering dielectric all are low-k dielectrics.In other execution mode, this accumulation is low-and the k dielectric is low-k dielectric, and this covering dielectric is not low-k dielectric.
In other embodiments, described multiple dielectric substance can comprise discontinuous accumulation low-k dielectric layer and dielectric layer, perhaps described multiple dielectric substance described accumulation low-can have transition continuous, classification between k dielectric substance and the described covering dielectric.
Description of drawings
By the reference detailed description with the accompanying drawing, can understand the present invention better, wherein:
Fig. 1 and 1A are the facade view that is deposited on organic hard mask, photoresist and other layer on the wafer substrates that is positioned at low-k dielectric top to be etched.
Fig. 2 and 2A are respectively the facade views after wafer substrates photoresist, organic hard mask and other layer above etching away low-k dielectric among Fig. 1 and the 1A.
Fig. 3 and 3A are respectively the facade views after wafer substrates among Fig. 2 and the 2A layer above removing etched organic hard mask layer.
Fig. 4 and 4A be respectively among Fig. 3 and the 3A wafer substrates pass described organic hard mask layer etching low-facade view after the k dielectric.
Fig. 5 and 5A are respectively the facade view of wafer substrates after having removed organic hard mask layer and do not damaged low-k dielectric by high-temperature plasma body method of the present invention among Fig. 3 and the 3A.
Fig. 6 shows the schematic diagram that is suitable for implementing equipment of the present invention.
Fig. 7 shows the simple block diagram that is suitable for implementing multistation removal tool of the present invention.
Embodiment
The preferred embodiments of the present invention are described with reference to the accompanying drawings, in the accompanying drawings identical numeral identical feature of the present invention.
But the present invention relates to be used to form the removal of organic hard mask material of the hard mask of ashing (AHM), described organic hard mask material is for for example being called as the amorphous carbon hardmask of α-carbon or Alpha-carbon or the hard mask of spin coating.This hard mask can be formed on the substrate by chemical vapor deposition (CVD), spin coating or other technology.This AHM material is that the nitrogen of hydrogen and possible trace is formed by the carbon of for example about 50-80 percentage by weight and surplus usually mainly.The example that is used to form the original material of this film comprises CH 4And C 2H 2, C perhaps more generally says so xH y, wherein x=2 to 4 and y=2 to 10.
Although method of the present invention can be used to efficient and remove organic hard mask material effectively from low-k dielectric film, this method is not limited to low-k dielectric film even is not confined to dielectric.The present invention also is not limited to the low-k dielectric of any concrete kind.For example, the present invention can be applicable to dielectric less than about 2.8 of the dielectric of k value less than 4.0 (be also referred to as the first generation low-k dielectric), k value (be also referred to as the second generation low-k dielectric) and the k value dielectric (being also referred to as ultralow k dielectric) less than about 2.0 effectively.(porous) that this low-k dielectric can be porous or atresia (latter be called as sometimes intensive low-the k dielectric).Usually, intensive low-the k dielectric refers to that those k values are not more than 2.8 dielectric, low-k porous dielectric is that those k values are not more than 2.2 dielectric.Can use the low-k dielectric of any suitable ingredients, comprise the dielectric with fluorine and/or carbon doped silica base.Also can use the dielectric of non-silicon-dioxide-substrate, for example polymeric material.Can use any suitable technology to deposit this low-k dielectric, comprise spin-on deposition and CVD deposition technique.Just form porous dielectric, can use any suitable method.A kind of method of example comprises the silica-based pillar of common deposition (backbone) and organic pore-foaming agent, and removes this pore-foaming agent composition subsequently, stays the dielectric film of porous.Other method comprises sol-gel technique.The trade mark that the object lesson of suitable low-k film has Dow Chemicals Co., Ltd to sell is that the carbon back spin coating type film of SiLK and trade mark that Novellus Systems Co., Ltd sells are the CVD depositing porous films of CORAL.
Preferably come etching and remove this organic hard mask by the reactive plasma etching.Usually, original position in plasma-reaction-chamber (in situ) is carried out the reactive plasma etching, wherein applies radio frequency (RF) energy by the capacitive coupling electrode that is arranged in the process chamber, and this process chamber can promote exciting of reactant gas and/or decompose.Plasma forms highly reactive material usually, and the unwanted deposition materials in this material and this process chamber reacts and it is etched away.The present invention can use plasma, the inductively coupled plasma (ICP) that produces with microwave (MW) or the plasma that produces in parallel-plate reactive ion etching (RIE) reactor.
Can be used for implementing plasma reactor apparatus of the present invention comprises for the vacuum pump that forms vacuum in process chamber.Equipment of the present invention also comprises handles the gas access assembly, for example is connected to the pressurized gas cylinder of inlet duct, and interior gas distribution face plate (faceplate) or the shower nozzle of this inlet duct and this process chamber is connected.Semiconductor wafer substrate or other workpiece are placed on base or the platform, and this base or platform can be to this undercoat biasing power (bias).RF power supply or other power supply are to applying electrical power between this gas distribution face plate or shower nozzle and this base to excite the mixture of handling gas or multiple gases to form plasma in the cylindrical conversion zone between this panel and base.
The ionogenic processing gas that uses among the present invention is hydrogen and comprise gas oxygen or oxidizability for example CO or CO preferably 2Mixture.The percent by volume that this oxidizing gas accounts for this mixture preferably about 0.5% to 10%.Preferably, this treats that the ionized gas mixture does not comprise nitrogen, to avoid being incorporated into this film and infringement that the CDO dielectric layer is arbitrarily caused by nitrogen, known this can form can with the amino of photoresist reaction, thereby cause so-called resist poisoning effect (resist poisoning effect).Responsive resist (sensitive resists), the resist of 193 nanometers for example, can react with amino, acid compound in amino this resist that can neutralize also can stop these compound normal development and stop these compounds to be removed in the solvent removal step of photoetching order (lithography sequence), thereby can stay remaining resist in undesirable zone of this wafer.Utilize the Ar or the He that increase, have some advantages, but for H 2+ CO 2Plasma does not then have this advantage.In the RIE etch tool, use He or Ar can improve etch-rate or be conducive to the polymer after this technology last removed etching by sputter or often stay other defective on the wafer surface 25.Therefore, be conducive to stay clean wafer surface or have still less sub-micron defective.
During plasma etching, it is important keeping chip temperature to surpass about 200 ℃, preferably surpasses 250 ℃, more preferably in about 250-350 ℃ scope.Can realize such purpose by heating element is provided in this process chamber.In operating process and since this process chamber flow into the vacuum that the relative side of a side of this process chamber produces with ionogenic processing gas, plasma processing gas from a lateral movement of vacuum chamber to opposite side.This plasma processing gas is diffused into the surface of this wafer substrates to remove organic hard mask and the material that volatilizees is transported towards the vacuum pump assembly.
As shown in Figure 1, wafer 20 comprises etching stopping layer 22, deposits low-k dielectric layer 24 at this etching stopping layer 22.Organic (for example amorphous carbon) hard mask layer 26 is deposited on this low-k dielectric layer 24.Resist layer 32, optional organic (or spin coating) antireflecting coating (ARC) 30 and SiOC(pass through CO 2With Si (CH 3) 4Reaction formation), SiON or Si 3N 4The dielectric ARC layer 28 of ARC layer covers on this organic hard mask layer.This resist layer is exposed to device pattern (device pattern) and is developed to remove a certain amount of anticorrosive additive material corresponding with this pattern.As shown in Figure 2, the opening 34 in the Sheng Xia resist layer 32 is used as mask then with from ARC layer 28,30 and the corresponding a certain amount of material of organic hard mask layer 26 etchings.
This resist layer and ARC layer are removed to stay organic hard mask layer and the etched pattern openings 34 of layer 24 top then, as shown in Figure 3.This resist layer and residue can be that 10/890,653,11/011,273 and 11/128,930 the disclosed method of United States Patent (USP) is removed by application number, and the disclosed content of these patents is incorporated among the application by reference at this.Usually, this wafer stands cineration technics to remove and to remove this resist layer, for example removes by the hydrogen plasma of transferring to plasma reactor and low-k dielectric film.After removing this resist layer and the layer above other, this organic hard mask layer is used to the low-k dielectric layer below for example reactive ion etching (RIE) etching then, as shown in Figure 4, its split shed 34 is continued to be etched into low-k layer 24 has wall 36 with formation opening downwards.
More general method is to be exposed to the etched wafer with layer shown in Figure 2 of RIE be used to waiting, and does not remove layer 32,30,28.Because the RIE etching requires long etching period usually, before etching stopping layer 22 was exposed, layer 32,30,28 will be removed fully.The structure that produces as shown in Figure 4.This realizes by structure shown in Figure 2 is exposed in the RIE etching, skips thus above and the described required independent resist/ARC of Fig. 3 removes step, and forms the structure among Fig. 4.
This wafer stands high-temperature plasma clean method of the present invention then to remove organic hard mask layer, makes low-k dielectric layer be without prejudice and can receive conducting metal in opening 36.Can implement this plasma at the reactor identical with being used for described hydrogen plasma cineration technics and handle, but need to use heating element to realize required temperature of reactor.Subsequently, as shown in Figure 5, the surface 25 of this dielectric layer 24 does not have α-carbon (a-carbon) or other organic hard mask residue basically, and the hole that etches in this dielectric layer or the size of groove 36 is unaffected and also do not stand any infringement, the sidewall 36 ' that for example is corroded.
In Nuo Fa system (Novellus Systems) Iridia200mm etch tool, comprise that the wafer that covers the organic hard mask layer on low-k dielectric layer is heated lamp and is heated to common 280 ℃ temperature.(being generally about 1800W's) in about 1000-3000W scope can be applied to H at the microwave power of 2.45GHz 2/ CO 2Admixture of gas, this admixture of gas is generally about 1800sccm with about 500-4000sccm() speed flow into this chamber, the pressure in this chamber maintains in the scope of 750-4000 millitorr (mT), is generally 1000 millitorrs.Processing time between about 30 to 180 seconds (being generally about 90 seconds), this organic hard mask layer was removed, and can not cause material injury by-k dielectric layer low to this afterwards.
In the Gamma of Nuo Fa system instrument, comprise that the wafer that covers the organic hard mask layer on low-k dielectric layer is heated to common 280 ℃ temperature by the resistance heating platform.(being generally about 2000W) in about 500-3000W scope can be applied to H at the RF of 3.56MHz power 2/ CO 2Admixture of gas, this admixture of gas is generally about 20000sccm with about 5000-40000sccm() speed flow into this chamber, the pressure in this chamber maintains in the scope of 750-4000 millitorr, is generally 1100 millitorrs.This instrument comprises 4 to 6 platforms, and in etching treatment procedure, wafer is moved through all platforms.Entire process between about 20 to 180 seconds or plasma exposure time (being generally about 90 seconds), this organic hard mask layer was removed, and can not cause material injury by-k dielectric layer low to this afterwards.
In having the Iridia300mm Sierra of the Nuo Fa system etch tool of duplicate supply, comprise that the wafer that covers the organic hard mask layer on low-k dielectric layer is heated to common 280 ℃ temperature.(being generally about 1800W) in about 1000-3000W scope can be applied to H at the microwave power of 2.45GHz 2/ CO 2Admixture of gas, this admixture of gas is generally about 1800sccm with about 500-4000sccm() speed flow into this chamber, the pressure in this chamber maintains in the scope of 750-4000 millitorr, is generally 1000 millitorrs.The platform that supports this wafer is positioned at the RF plasma-reaction-chamber, and is coupled to this RF source, and this RF source provides the power at 3.56MHz in the 500-2000W scope, for example power of 1000W.Processing time between about 30 to 180 seconds (being generally about 90 seconds), this organic hard mask layer was removed, and can not cause material injury by-k dielectric layer low to this afterwards.
For other clean up task, can adjust described gas flow rate, the setting of RF source, open-assembly time and other parameter to realize required result.
Therefore, the invention provides a kind of in photoetching process from the wafer substrates etching and/or remove the method for the improvement of organic hard mask layer, particularly when removing amorphous carbon from low-k dielectric layer from the wafer substrates etching and/or remove the method for the improvement of organic hard mask layer.The present invention can realize the removal of this organic hard mask and can not damage following low-k dielectric substrate.
Other embodiment
Except the embodiment that describes with reference to above Fig. 1 to Fig. 5, the present invention also has other embodiment, below with reference to Figure 1A-5A, Fig. 6 and 7 described.
Shown in Figure 1A, an alternative embodiment of the invention comprises the wafer 20 with etching stopping layer 22, deposits low-k dielectric layer 24 at this etching stopping layer 22.This dielectric layer 24 comprises multiple dielectric substance, this multiple dielectric substance comprise the accumulation (bulk) that is positioned at covering dielectric 24b below low-k dielectric 24a, the k value of the k value of this covering dielectric 24b is higher than this accumulation low-k dielectric 24a.In certain embodiments, this accumulation low-k dielectric 24a and this covering dielectric 24b are low-k dielectrics.In other embodiments, this accumulation is low-and k dielectric 24a is low-k dielectric, and this covering dielectric 24b is not low-k dielectric.
In some specific embodiments, this accumulation is low-the k dielectric can be ultralow-k(ULK) dielectric, and the k value that for example has is about 2.2 dielectric, and this covering dielectric can be that the k value that has is about 2.9 carbon doped oxide (CDO).
In other specific embodiment, this accumulation horizon can be the k value that has be carbon doped oxide (CDO) of about 2.9, this cover layer can be the k value that has be about 4.0 tetraethoxysilane (tetraethylorthosilicate) (TEOS).
In other embodiments, this multiple dielectric substance can comprise that discontinuous (discrete) piles up low-k dielectric and dielectric layer; That is to say independent, dielectric layer adjacent.Perhaps, this multiple dielectric substance this accumulation low-can have transition continuous, classification (graded transition) between k dielectric substance and the covering dielectric material.The transition of this classification can be uniform substantially from a side of this dielectric layer 24 to opposite side.Perhaps dielectric transition can be inhomogeneous above the only part of the gross thickness of this dielectric 24 from a kind of dielectric to another kind, for example the gross thickness that is less than this dielectric 24 50% or be less than 25% or be less than 10% or be less than above 5% the thickness.
At this low-organic carbon hardmask layer 26 of k dielectric layer 24 depositions.Resist layer 32, optional organic (or spin coating) antireflecting coating (ARC) 30 and SiOC(pass through CO 2With Si (CH 3) 4Reaction formation), SiON or Si 3N 4The dielectric ARC layer 28 of ARC layer covers on this organic hard mask layer.This resist layer is exposed to device pattern (device pattern) and is developed to remove a certain amount of anticorrosive additive material corresponding with this pattern.Shown in Fig. 2 A, the opening 34 in the remaining resist layer 32 is used as mask then with from ARC layer 28,30 and the corresponding a certain amount of material of organic hard mask layer 26 etchings.
This resist layer and ARC layer are removed to stay organic hard mask layer and the etched pattern openings 34 of layer 24 top then, so that the dielectric layer 24 of hard mask layer 26 belows is exposed, as shown in Figure 3A.This resist layer and residue can be that 10/890,653,11/011,273 and 11/128,930 the disclosed method of United States Patent (USP) is removed by application number, and the disclosed content of these patents is incorporated among the application by reference at this.Usually, this wafer stands cineration technics to remove and to remove this resist layer, for example removes by the hydrogen plasma of transferring to plasma reactor and low-k dielectric film.After removing this resist layer and the layer above other, this organic hard mask layer 26 is used to low-k dielectric layer 24(24a and the 24b below for example reactive ion etching (RIE) etching then), shown in Fig. 4 A, its split shed 34 is continued to be etched into low-k layer 24 downwards and is had the opening of wall 36 with formation, further exposes this dielectric layer 24.
More general method is applicable to the wafer of waiting to be exposed to the layer shown in the etched Fig. 2 of the having A of RIE, and does not remove layer 32,30,28.Because the RIE etching requires long etching period usually, before etching stopping layer 22 was exposed, layer 32,30,28 will be removed fully.The structure that produces is shown in Fig. 4 A.This realizes by the structure shown in Fig. 2 A is exposed in the RIE etching, economizes thus to omit above and the described required independent resist/ARC of Fig. 3 A removes step, and the structure among formation Fig. 4 A.
This wafer stands high-temperature plasma clean method of the present invention then to remove organic hard mask layer, makes low-k dielectric layer be without prejudice and can receive conducting metal in opening 36.Be noted that especially low-k dielectric the 24a that exposes and/or 24b can not removed the technology infringement by this in the process of removing this hard mask.Can implement this plasma at the reactor identical with being used for described hydrogen plasma cineration technics and handle, but need to use heating element to realize required temperature of reactor.Subsequently, shown in Fig. 5 A, the surface 25 of this dielectric layer 24 does not have α-carbon (α-carbon) or other organic hard mask residue basically, and the sidewall 36 ' that is corroded for example appears in the hole that etches in this dielectric layer or the size of groove 36 is unaffected and also can not stand any infringement.
Device
Any suitable plasma-reaction-chamber equipment can be used to implement the present invention, comprises Gamma mentioned above and Iridia instrument.In this respect, furthermore, suitable example is the Novellus Gamma of the plasma setting (plasma setup) of disposing the downstream TM2130 instruments.Fig. 6 is the schematic diagram that has shown the various aspects of downstream plasma equipment 600, and this plasma equipment 600 is applicable at wafer implements the present invention.The exposure chamber 601 that equipment 600 has plasma generation part 611 and separated by nozzle component 617.In this exposure chamber 601, wafer 603 is positioned on the platform (perhaps platform) 605.Platform 605 is equipped with heating/cooling element.In certain embodiments, platform 605 also is configured for wafer 603 is applied biasing force (bias).Utilize vacuum pump can make via pipeline 607 and obtain low pressure in the exposure chamber 601.Gaseous Hydrogen source of the gas (having or do not have dilution/carrier gas) and carbon dioxide source (perhaps other weak oxidant) provide plasma generation part 611 into this equipment via entrance 609 with gas stream.The sensed coil 613 of the part of plasma generation part 611 centers on, and this induction coil is connected to power supply 615.During operation, admixture of gas is introduced into plasma generation part 611, and induction coil 613 is energized, thereby produces plasma in plasma generation part 611.It has applied voltage nozzle component 617() can stop some ions to flow into exposure chamber 601, and allow neutral substance to flow into this exposure chamber 601.As mentioned above, wafer 603 can be temperature control and/or can apply the RF bias voltage.
In certain embodiments, equipment of the present invention is to be exclusively used in the removal device (strip unit) of removing photoresist from wafer.Generally speaking, such removal device instrument can have a plurality of processing of wafers station, so that a plurality of wafer can be handled simultaneously.Fig. 7 is the simple block diagram of the vertical view of demonstration multistation (multi-station) wafer removal device instrument 730, and this removal device instrument can be used according to the present invention.Removal device instrument 730 has five and removes 733,735,737,739 and the 741 and loading depots 731 in station.Removal device instrument 730 is configured to make each station can handle a wafer, so all stations can be exposed to common vacuum.Each is removed station 733,735,737,739 and 741 and has its RF power supply separately.Loading depot 731 is equipped with the loading locking station (load-lock station) that is connected with this loading depot usually and with permission wafer is input to removal device instrument 730 and can destroy vacuum.Loading depot 731 heating lamp be equipped with also can in case with wafer transfer to remove station and photoresist remove before thermal bimorph in advance.Remove station 741 and with permission wafer can not destroyed vacuum from 730 outputs of removal device instrument in the connected loading locking of configuration station usually.Mechanical arm 743 can shift wafer between station and station.
In exemplary manufacturing mode process, wafer is processed with batch mode.Batch mode can increase wafer throughput, thus in manufacture process by common use.In batch mode, each wafer is transferred to each station in 731,733,735,737,739 and 741, and processed in described station.For example, a kind of batch mode technology of example is carried out as follows: at first load the wafer into loading depot 731, in this loading depot, with heating lamp wafer is carried out preheating.Yet mechanical arm 743 to removing station 733, is removed station at this with this wafer transfer, and wafer is by the plasma treatment length, to be enough to remove about 1/5 of photoresist.Mechanical arm 743 stands 735 with this wafer transfer to removing then, removes the station at this, and wafer is by the plasma treatment length, to be enough to remove about 1/5 of remaining photoresist.Proceed this processing sequence in removing station 737,739 and 741, to handle this wafer.Removing station 741, photoresist is removed in a large number, then wafer is unloaded from this removal device instrument.
Be suitable for implementing other instrument of the present invention and comprise the GxT that can obtain from ASM Nutool Inc. TMAnd G400 TMPhotoresist removal tool, the 2300Flex that can obtain from Lam Res Corp. TMEtch tool, the Telius that can obtain from Tokyo Electron Co., Ltd TMEtch tool or the Producer that can obtain from Applied Materials company TMEtch tool.
Should be appreciated that equipment/technology as described above can be used in combination to make or produce for example semiconductor device, display unit, LED, electro-optical package etc. with photoengraving pattern instrument or technology (lithographic patterning tools or processes).Usually, though not necessarily, these instrument/technologies can be used together or implemented at common manufacturing facility.As example, some during the lithographic patterning of film comprises the steps or whole, each step can be implemented with multiple possible instrument: (1) is applied to photoresist on the substrate (being substrate) with spin coating or Spray painting tool; (2) with heating plate or heating furnace or UV tools of solidifying curing photoresist; (3) with for example instrument of wafer step-by-step exposure machine (wafer stepper) and so on this photoresist is exposed to visible light or UV or x-ray; (4) utilize the instrument such as the wet method worktop to develop this resist in order to remove resist selectively, thus this photoresist of patterning; (5) by utilize dry method or plasma assisted etch instrument with this resist design transfer in following film or substrate; And (6) use the instrument such as RF or microwave plasma resist remover to remove this resist.
Another method of the present invention is the equipment that is configured to perform the method described in this specification.A kind of suitable device comprises be used to the hardware of finishing technological operation and has for the system controller of control according to the instruction of technological operation of the present invention.A kind of suitable plasma-reaction-chamber equipment, for example Gamma and Iridia instrument or above-described other instrument are applicable to this method.This system controller generally comprises one or more memory devices and one or more processor that is configured to carry out these instructions, so that this equipment can be carried out the method according to this invention.Comprise for control and can be coupled to this system controller according to the computer-readable medium of the instruction of technological operation of the present invention.
Although specifically described the present invention in conjunction with concrete preferred embodiment, according to aforesaid description, many substituting execution modes, alter mode and modification it will be apparent to those skilled in the art that.Therefore, appended claim will comprise any these alternative, alter mode and modification that falls in true scope of the present invention and the spirit.

Claims (18)

1. an etching or remove the method for organic hard mask comprises:
Low-the k that comprises exposure is provided dielectric semiconductor wafer substrate, wherein said substrate comprise the accumulation that is positioned at covering dielectric below low-the k dielectric, the k value that this covering dielectric has is higher than this accumulation low-k dielectric, and this substrate top has organic hard mask to be removed;
Introduce ionizable gas above described substrate and organic hard mask, this ionizable gas comprises the mixture of hydrogen and oxidizing gas;
This mixture is applied energy to form the plasma of this mixture; And
Contact described organic hard mask does not damage following substrate surface or described exposure with at least a portion of removing this organic hard mask low-k dielectric with this plasma.
2. method according to claim 1, wherein said organic hard mask comprises the amorphous carbon of chemical vapour deposition (CVD).
3. method according to claim 1, wherein said organic hard mask comprises the spin coating carbon film.
4. method according to claim 1, wherein said accumulation is low-and k dielectric and described covering dielectric all are low-k dielectrics.
5. method according to claim 1, wherein said accumulation is low-and the k dielectric is that low-k dielectric and described covering dielectric are not low-k dielectrics.
6. method according to claim 1, wherein said low-the k dielectric has and is not more than about 3 dielectric constant.
7. method according to claim 1, wherein said low-the k dielectric has and is not more than about 2.8 dielectric constant.
8. method according to claim 1, wherein said low-the k dielectric has and is not more than about 2.2 dielectric constant.
9. method according to claim 1, wherein said accumulation is low-and the k dielectric is to have the k value to be about ultralow-k(ULK) dielectric, and described covering dielectric of 2.2 be to have the k value to be about 2.9 carbon doped oxide (CDO).
10. method according to claim 1, wherein said accumulation is low-and the k dielectric is to have the k value to be about 2.9 carbon doped oxide (CDO), and described covering dielectric is to have the k value to be about 4.0 tetraethoxysilane (TEOS).
11. method according to claim 1, wherein said substrate comprise discontinuous accumulation low-k dielectric layer and dielectric layer.
12. method according to claim 1, the transition of the classification that wherein said substrate is included in described accumulation between low-k dielectric substance and the described covering dielectric material.
13. method according to claim 1, wherein said admixture of gas are no nitrogen.
14. method according to claim 1, wherein said organic hard mask is removed from following substrate fully.
15. method according to claim 1 also comprises:
Photoresist is applied to described substrate;
This photoresist exposes;
Make this photoresist form pattern and with this design transfer to described substrate; And
Remove described photoresist from described substrate selectively.
16. an equipment that is used for etching or removes the organic hard mask on the dielectric, this equipment comprises:
(a) plasma-reaction-chamber device; And
(b) controller comprises the program command for implementing process, and this technology comprises the steps:
Low-the k that comprises exposure is provided dielectric semiconductor wafer substrate, wherein this substrate comprises the accumulation that is positioned at covering dielectric below low-k dielectric, the k value that this covering dielectric has is higher than this accumulation low-k dielectric, and this substrate top has organic hard mask to be removed;
Introduce ionizable gas above described substrate and organic hard mask, this ionizable gas comprises the mixture of hydrogen and oxidizing gas;
This mixture is applied energy to form the plasma of this mixture; And
Contact described organic hard mask does not damage following substrate surface or described exposure with at least a portion of removing this organic hard mask low-k dielectric with this plasma.
17. a semiconductor wafer processing system, this system comprises:
The described equipment of claim 16, and step-by-step exposure machine.
18. the computer-readable medium of a nonvolatile comprises that this program command comprises for the program command of control plasma-reaction-chamber device:
Be used for providing the code of semiconductor wafer substrate, this semiconductor wafer substrate comprises the low-k dielectric of exposure, wherein, described substrate comprise the accumulation that is positioned at covering dielectric below low-the k dielectric, the k value that this covering dielectric has is higher than this accumulation low-k dielectric, and this substrate top has organic hard mask to be removed;
Be used for introducing above described substrate and organic hard mask the code of ionizable gas, this ionizable gas comprises the mixture of hydrogen and oxidizing gas;
Be used for this mixture is applied energy with the code of the plasma that forms this mixture; And
Be used for making this plasma contact described organic hard mask does not damage following substrate surface or described exposure with at least a portion of removing this organic hard mask the dielectric code of low-k.
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