CN103247525B - Method for etching organic hard mask - Google Patents
Method for etching organic hard mask Download PDFInfo
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- CN103247525B CN103247525B CN201310049856.3A CN201310049856A CN103247525B CN 103247525 B CN103247525 B CN 103247525B CN 201310049856 A CN201310049856 A CN 201310049856A CN 103247525 B CN103247525 B CN 103247525B
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- dielectric
- low
- hard mask
- organic hard
- substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
A kind of method for etching or removing in a lithographic process organic hard mask on film having low dielectric constant.This method includes providing dielectric film, the top of the dielectric film has organic hard mask to be removed, the dielectric film has the dielectric constant no more than about 4.0, ionizable gas is introduced in the top of organic hard mask, the ionizable gas includes the mixture of hydrogen and oxidizing gas, and applies energy to the mixture to form the plasma of the mixture.When this method is additionally included in the temperature of organic hard mask more than 200 DEG C, organic hard mask is to remove organic hard mask without the substrate below material injury described in the Plasma contact.
Description
Technical field
The present invention relates to the cleaning procedure in semiconductor lithography manufacture system, is specifically related to a kind of be used for from low Jie
The method that electric constant film etched or removed organic hard mask of such as amorphous carbon or Spun-on carbon etc.
Background technology
Integrated circuit (IC) is manufactured by photoetching process in semiconductor wafer substrate.Needed for the photoetching process can make
The photoresist film that a part for the mask pattern of circuit or the pattern is transferred on substrate by selecting the radiation energy of wavelength.That
A little absorbed aerial image (aerial image) parts, in the photosensitive composition that the Other substrate materials have been exceeded due to its energy
Chemical bond transition energy (threshold energy), so as to foring potential image in the Other substrate materials.Should
Potential image show the part Other substrate materials can be removed in developing process (in the case of positive photoresist) or
(in the case of negative photoresist) can be retained after developing to form the pattern of three-dimensional in the photoresist film.Follow-up
Processing in, the photoresist film pattern that is formed is used as etching mask and gone with the open area of the patterning from the photoresist layer
Except following substrate.
Mosaic technology technology (damascene processing techniques) is frequently used in IC manufacturing
In, it, which is related in groove and hole in the dielectric layer, forms embedded with metal conductor.Etched using the opening in hard mask layer
The required part of the dielectric layer is to form the groove and hole.Opening in the hard mask layer is formed via being etched through
Opening in the photoresist layer of overlying and what itself was formed.Hard mask in mosaic technology can be made by organic layer, and organic layer is
Such as α-carbon (α-carbon) or Alpha-carbon (alpha-carbon).
The photoetching that 193 nano wave lengths are developed into from the photoetching of 248 nano wave lengths adds the integrated (masking of mask
Integration complexity), it is often necessary to multiple-level stack layer (multilayer stack) is deposited on layer to be etched.
One example is three level stack layer, and wherein SiON ARCs (ARC) are covered on amorphous carbon hard mask layer, and traditional is anti-
Erosion agent can be spun on the ARC and be processed.After the resist is developed, it will be schemed by fluorine dry etching process
Case is transferred on SiON layers.The resist is removed, together with using based on the etch process of oxygen with from the SiON layers
Opening removes α-carbon in the hard mask layer.Then the pattern is turned from the α-carbon hardmask by dielectric etch process
Following dielectric layer is moved on to, the dielectric layer is used in dual-damascene method.After the dielectric layer is etched, in the crystalline substance
Piece handling process rear end is formed before Cu or other metals interconnection thing, need to remove α-carbon hard mask layer.
Sudijono et al. United States Patent (USP) 6,787,452 discloses one kind and controlled in photoresist patterned technical process
The method of critical size, this method can be used to being formed in the dual-damascene structure (dual damascene structure) hole and
Groove.Amorphous carbon ARC is deposited on substrate by plasma enhanced chemical vapor deposition (PECVD) method.The Alpha-
Carbon-coating provides the high etching selectivity relative to oxide and is disclosed as it can be by using the plasma of oxygen
Body cineration step is easily moved away.Ye et al. United States Patent (USP) 6,458,516 discloses a kind of plasma using hydrogen/nitrogen base
The method that body removes polymerization, organic mask layer.
Low-k (low-k) material, i.e. those dielectric constants are usually less than about 2.7 to 3.0 material, inlayed
It is used as in technique between the metal between conductive interconnection thing and/or interlayer dielectric, the conductive interconnection thing is used to subtract
The delay that few signal caused by capacity effect (capacitive effects) is propagated.The dielectric constant of dielectric substance
Lower, dielectric electric capacity is lower, and the RC retardation ratio of the integrated circuit is with regard to smaller.Generally, low-k dielectric be with
The silica based materials of a number of combination carbon (incorporated carbon), commonly known as carbon doped oxide
(CDO).A CDO example is the carbon doped oxide that trade mark is CORAL, and it comes from California
(California) the Novellus System Co., Ltd of San Jose (San Jose).It has been found that highly oxidized environment leads to
Often be not suitable on low-k materials.When exposed to O2When in plasma, oxygen can be removed or removed in the low-k material
Carbon.In many this materials, such as CDO, the presence of carbon help to provide low-k.Therefore, oxygen is in certain journey
Carbon is eliminated from these materials on degree, this is effectively improved dielectric constant.With the technique court for manufacturing integrated circuit
Less and less size development and requirement use the dielectric substance with increasingly lower dielectric constant, it has been found that tradition
Plasma remove condition (strip plasma conditions) be inappropriate.
Therefore, exist in the art and develop a kind of needs of alternative techniques, this technological requirement can have been removed effectively
Machine hard mask layer, such as amorphous carbon, and excessive low-k dielectric will not be removed or will not substantially be changed
The property of low-k dielectric.
The content of the invention
According to an aspect of the invention, there is provided a kind of have from wafer substrates etching and/or removal in a lithographic process
The improved method of the hard mask of machine.
According to another aspect of the present invention, there is provided a kind of to remove organic hard mask without damaging following dielectric
The method of layer.
According to another aspect of the present invention, there is provided a kind of to remove organic hard mask layer without damaging following low-k
The method of dielectric layer.
According to another aspect of the present invention, there is provided the organic hard mask layer of one kind removal etches into following without influence
Dielectric layer in critical size feature method.
Above-mentioned aspect and according to disclosure of the invention, it will be apparent to those skilled in the art that aspect energy
By a kind of method for etching or removing organic hard mask (such as the organic hard mask of amorphous carbon) disclosed by the invention come real
Existing, this method includes providing the substrate having organic hard mask to be removed thereon, above the substrate and organic hard mask
The ionizable gas for the mixture for including hydrogen and oxidizing gas is introduced, and applies energy to the mixture to form this
The plasma of mixture.Then, this method includes with the Plasma contact organic hard mask, the wherein substrate and organic
The temperature of hard mask is more than 200 DEG C, to remove at least a portion of organic hard mask and the exposure substrate without substance damage
The following substrate of evil.
Preferably, organic hard mask is completely removed from following substrate.
In another aspect, the present invention relates to a kind of remove in a lithographic process to be covered in having on film having low dielectric constant
The method of the hard mask of machine, this method include providing the dielectric film having organic hard mask to be removed thereon, the dielectric
Film has a dielectric constant no more than about 4.0, and with the grade of the mixture for including ionized hydrogen and oxidizing gas from
Daughter contacts organic hard mask, wherein the temperature of the dielectric film and organic hard mask is more than 200 DEG C, to have described in removal
The hard mask of machine is without the dielectric film below substantial effect.
In further, it is normal to be covered in low dielectric the present invention relates to a kind of etching in a lithographic process or removal
The method of organic hard mask on number film, including provide in the dielectric film thereon with organic hard mask to be removed, the electricity
Deielectric-coating has no more than about 4.0 dielectric constant, and being introduced above organic hard mask includes hydrogen and oxidizing gas
The ionizable gas of mixture, and apply energy to the mixture to form the plasma of the mixture.This method is also
Including organic hard mask with the Plasma contact, the wherein temperature of the dielectric film and organic hard mask more than 200 DEG C, with
Organic hard mask is removed without the substrate below material injury.
Organic hard mask can be the amorphous carbon of chemical vapor deposition, and the substrate can be dielectric
Film, such as dielectric radio are less than about 3.0 dielectric film, for example, carbon doped oxide dielectric film.
Organic hard mask can be amorphous carbon, and the dielectric film can be with the dielectric no more than about 2.8
Constant.
The oxidizing gas can be provided by carbon dioxide source.The admixture of gas is preferably substantially free from there is nitrogen.
In other embodiments, the present invention includes the chip with dielectric layer, and the dielectric layer includes a variety of electricity and is situated between
Material, a variety of dielectric substances include being positioned over accumulation (bulk) below dielectric it is low-k dielectric, covering electricity
The k values of medium are low higher than the accumulation-the k values of k dielectric.In some embodiments, the accumulation it is low-k dielectric and the covering
Dielectric is all low-k dielectric.In other embodiments, the accumulation it is low-k dielectric is low-k dielectric, and the covering
Dielectric is not low-k dielectric.
In other embodiments, a variety of dielectric substances may include the low-k dielectric layer of discontinuous accumulation and cover
Lid dielectric layer, or a variety of dielectric substances are between the low-k dielectric of the accumulation and the covering dielectric
There can be the transition of continuous classification.
Brief description of the drawings
By referring to detailed description with the accompanying drawing, the present invention is better understood when, wherein：
Fig. 1 and 1A is organic hard mask, the light of deposition on the wafer substrates above low-k dielectric to be etched
Photoresist and other layers of facade view.
Fig. 2 and 2A, which is wafer substrates in Fig. 1 and 1A respectively, is etching away the photoresist above low-k dielectric, organic hard
Facade view after mask and other layers.
Fig. 3 and 3A be wafer substrates in Fig. 2 and 2A respectively remove the layer above the organic hard mask layer being etched it
Facade view afterwards.
Fig. 4 and 4A is that the wafer substrates in Fig. 3 and 3A are etching low-k dielectric through organic hard mask layer respectively
Facade view afterwards.
Fig. 5 and 5A is that the wafer substrates in Fig. 3 and 3A eliminate in the high-temperature plasma body method by the present invention respectively
Organic hard mask layer and without damage low-k dielectric after facade view.
Fig. 6 is to show the schematic diagram for being adapted for carrying out the equipment of the present invention.
Fig. 7 is to show the simple block diagram for being adapted for carrying out the multistation removal tool of the present invention.
Embodiment
The preferred embodiments of the present invention are described with reference to the accompanying drawings, identical numeral represents the identical of the present invention in the accompanying drawings
Feature.
It is described organic hard the present invention relates to the removal for forming the organic hard mask material that can be ashed hard mask (AHM)
Mask material is for example to be referred to as α-carbon either amorphous carbon hardmask of Alpha-carbon or the hard mask of spin coating.It is this to cover firmly
Film can be formed on substrate by chemical vapor deposition (CVD), spin coating or other technologies.The AHM materials are generally mainly by example
Such as from about the carbon of 50-80 percentage by weights and surplus are hydrogen and possible micro nitrogen composition.For forming the original of this film
The example of material includes CH4And C2H2, or be more generally CxHy, wherein x=2 to 4 and y=2 to 10.
Although the method for the present invention can be used for efficient from low-k dielectric film and effectively remove organic hard mask material
Material, but this method is not limited to low-k dielectric film, or even it is not limited to dielectric.Present invention is also not necessarily limited to any specific kind
Low-k dielectric of class.For example, the present invention can be effectively adapted to dielectric (the also referred to as first generation of the k values less than 4.0
Low-k dielectric), dielectric (also referred to as the second generation low-k dielectric) and k value electricity less than about 2.0 of the k values less than about 2.8
Medium (also referred to as Ultra low k dielectric).Low-the k dielectric can be porous (porous) or non-porous (the latter is sometimes
It is referred to as intensive low-k dielectric).Generally, intensive low-k dielectric refers to the dielectric that those k values are not more than 2.8, and low-k is more
Hole dielectric is the dielectric that those k values are not more than 2.2.Can be used low-k dielectric of any suitable ingredients, including with fluorine and/
Or the dielectric of the titanium dioxide silicon substrate of carbon doping.The dielectric of non-titanium dioxide silicon substrate, such as polymeric material can also be used.It can make
Low-the k dielectric, including spin-on deposition and CVD deposition technology are deposited with any suitable technique.With regard to forming porous dielectric
For, any suitable method can be used.A kind of method of example includes co-deposited silicon substrate pillar (backbone) and had
Machine pore-foaming agent, and the pore-foaming agent composition is then removed, leave porous dielectric film.Other methods include sol-gel skill
Art.The carbon-based spin coating type that the trade mark that the specific example of suitable low-k films has Dow Chemicals Co., Ltds to sell is SiLK
The trade mark that film and Novellus Systems Co., Ltds sell is CORAL CVD deposition perforated membrane.
It is preferred that etch and remove organic hard mask by reactive plasma etching.Generally, it is anti-in plasma
Indoor (in situ) in situ is answered to perform reactive plasma etching, wherein it is electric to pass through the Capacitance Coupled being arranged in process chamber
Pole applies radio frequency (RF) energy, and the process chamber can promote exciting and/or decomposing for reactant gas.Plasma is usually formed height
The material of reactivity is spent, the material reacts and etched away with the unwanted deposition materials in the process chamber.The present invention can
Using plasma, inductively coupled plasma (ICP) caused by microwave (MW) or in parallel-plate reactive ion etching
(RIE) caused plasma in reactor.
Include being used for the vacuum that vacuum is formed in process chamber available for the plasma reactor apparatus for implementing the present invention
Pump.The equipment of the present invention also includes processing gas intake assembly, such as is connected to the pressurized gas cylinder of inlet duct, the inlet duct
It is connected with the gas distribution face plate (faceplate) in the process chamber or shower nozzle.Semiconductor wafer substrate or other workpiece
It is placed on base or platform, the base or platform can be biased power (bias) to the substrate.RF power supply or its
Its power supply either applies electrical power to excite processing gas or a variety of gas to the gas distribution face plate between shower nozzle and the base
The mixture of body in the cylindrical conversion zone between the panel and base to form plasma.
The ionizable processing gas used in the present invention be preferably hydrogen and comprising oxygen or oxidisability gas
Such as CO or CO2Mixture.The oxidizing gas accounts for the percent by volume preferably from about 0.5% to 10% of the mixture.It is preferred that
Ground, this treats that ionized gas mixture does not include nitrogen, to avoid being incorporated into the film by nitrogen to the CDO dielectric layers below any
Caused by infringement, it is known that this can be formed can with photoresist react amino, so as to cause so-called resist poisoning effect
(resist poisoning effect).Sensitive resist (sensitive resists), such as 193 nanometers against corrosion
Agent, can be reacted with amino, amino can neutralize the acid compound in the resist and can prevent these compound normal developments with
And prevent these compounds from being removed in photoetching order (lithography sequence) solvent removal step, so as to meeting
Remnants resist is left in the undesirable region of the chip.Using increased Ar or He, some advantages are had, but for
H2+CO2Plasma is then without this advantage.In RIE etch instrument etch-rate or favourable can be improved using He or Ar
In the polymer removed finally by sputtering after etching in the technique or the other defects often being left behind in wafer surface 25.
Therefore, be advantageous to leave clean wafer surface or there is less sub-micron defect.
During plasma etching, keep chip temperature more than about 200 DEG C be it is important, it is preferably greater than 250 DEG C, more excellent
Selection of land is in the range of about 250-350 DEG C.Such purpose can be realized by managing indoor offer heating element heater in this place.Grasping
During work, caused by the relative side in the side for flowing into the process chamber with ionizable processing gas due to managing room in this place
Vacuum, plasma processing gas move to opposite side from the side of vacuum chamber.The plasma processing gas is diffused into the crystalline substance
The surface of piece substrate is to remove organic hard mask and transport the material of volatilization towards vavuum pump component.
As shown in figure 1, chip 20 includes etching stopping layer 22, deposition has low-k dielectric layer on the etching stopping layer 22
24.Organic (such as amorphous carbon) hard mask layer 26 is deposited on the low-k dielectric layer 24.Resist layer 32, optionally have
Machine (or spin coating) ARC (ARC) 30 and SiOC are (by by CO2With Si (CH3)4Reaction is formed), SiON or Si3N4ARC
The dielectric ARC layer 28 of layer is covered on organic hard mask layer.The resist layer is exposed to device pattern (device
Pattern) and it is developed to remove a certain amount of anticorrosive additive material corresponding with the pattern.It is as shown in Fig. 2 remaining against corrosion
It is corresponding a certain amount of to be etched from ARC layer 28,30 and organic hard mask layer 26 that opening 34 in oxidant layer 32 is then used as mask
Material.
Then the resist layer and ARC layer are removed with organic hard mask layer of the top of leaving layer 24 and the figure being etched
Case opening 34, as shown in Figure 3.The resist layer and residue can pass through Application No. 10/890,653,11/011,273 and 11/
Method disclosed in 128,930 United States Patent (USP) removes, and this Shen is incorporated herein by reference in these patent disclosure of that
Please in.Usually, the chip is subjected to cineration technics to remove and remove the resist layer, such as anti-by being transferred to plasma
The hydrogen plasma of device and low-k dielectric film is answered to remove.After the layer of the resist layer and other tops is removed, this is organic hard
Mask layer is then used to etch following low-k dielectric layer for example, by reactive ion etching (RIE), as shown in figure 4,
Its split shed 34 continues to be etched into low-k layers 24 downwards to form the opening with wall 36.
More common method is for the chip with the layer shown in Fig. 2 to be exposed to RIE etch, without removing layer
32、30、28.Because RIE etch usually requires that longer etching period, before etching stopping layer 22 is exposed, layer 32,30,
28 will be completely removed.Caused structure is as shown in Figure 4.This by by the structure shown in Fig. 2 be exposed to RIE etch in come
Realize, thus skip required single resist/ARC removal steps described by above and Fig. 3, and formed in Fig. 4
Structure.
The chip is then subjected to high-temperature plasma clean method of the invention to remove organic hard mask layer so that low-k
Dielectric layer is without prejudice and can receive conducting metal in opening 34.Can with for described hydrogen plasma ash chemical industry
Implement the corona treatment in skill identical reactor, but need to use heating element heater to realize required reactor temperature
Degree.Then, as shown in figure 5, the surface 25 of the dielectric layer 24 there is no α-carbon (a-carbon) or other organic hard
Mask residue, and the hole etched in the dielectric layer or the size of groove 38 are unaffected and be also not subjected to
Any infringement, such as the side wall 36 ' being corroded.
In system (Novellus Systems) Iridia 200mm etch tools are sent out in promise, including it is covered in low-k electricity and is situated between
The chip of organic hard mask layer on matter layer is heated the temperature that lamp is heated to usual 280 DEG C.About in the range of 1000-3000W
(typically about 1800W) microwave power in 2.45GHz can be applied to H2/CO2Admixture of gas, the admixture of gas
The room is flowed into about 500-4000sccm (typically about 1800sccm) speed, the pressure in the room maintains 750-4000 millis
In the range of holding in the palm (mT), usually 1000 millitorr.After the processing time (typically about 90 seconds) between about 30 to 180 seconds,
Organic hard mask layer is removed, without causing material injury to the low-k dielectric layer.
In system Gamma instruments are sent out in promise, include the chip quilt for the organic hard mask layer being covered on low-k dielectric layer
Resistance heating platform is heated to usual 280 DEG C of temperature.In (the typically about 2000W) about in the range of 500-3000W in 3.56MHz
RF power can be applied to H2/CO2Admixture of gas, the admixture of gas (are typically about with about 5000-40000sccm
Speed 20000sccm) flows into the room, and in the range of the pressure in the room maintains 750-4000 millitorrs, usually 1100 in the least
Support.The kit contains 4 to 6 platforms, and in etching treatment procedure, chip is moved through all platforms.About 20 to 180
After whole processing or plasma exposure time (typically about 90 seconds) between second, organic hard mask layer is removed,
Without causing material injury to the low-k dielectric layer.
In the promise hair system Iridia 300mm Sierra etch tools with dual power supply, including it is covered in low-k electricity
The chip of organic hard mask layer on dielectric layer is heated to usual 280 DEG C of temperature.(logical about in the range of 1000-3000W
Chang Weiyue 1800W) in 2.45GHz microwave power it can be applied to H2/CO2Admixture of gas, the admixture of gas is with about 500-
4000sccm (typically about 1800sccm) speed flows into the room, and the pressure in the room maintains the scope of 750-4000 millitorrs
It is interior, usually 1000 millitorr.Support the platform of the chip to be located in RF plasma-reaction-chambers, and be coupled to the RF sources,
The RF sources provide the power in 3.56MHz in the range of 500-2000W, such as 1000W power.Between about 30 to 180 seconds
Processing time (typically about 90 seconds) after, organic hard mask layer is removed, without being caused to the low-k dielectric layer
Material injury.
For other clean up tasks, the gas flow rate, the setting of RF sources, open-assembly time and other parameters are can adjust with reality
Existing required result.
Therefore, organic hard mask layer is etched and/or removed in a lithographic process from wafer substrates the invention provides a kind of
Improved method, particularly from it is low-k dielectric layer remove amorphous carbon when from wafer substrates etch and/or remove organic
The improved method of hard mask layer.The present invention can realize removing and will not damaging following low-k electricity for this organic hard mask
Dielectric substrate.
Other embodiments
In addition to the embodiment described with reference to fig. 1 above to Fig. 5, the present invention also has other embodiments, referring to
Figure 1A -5A, Fig. 6 and 7 are described.
As shown in Figure 1A, an alternative embodiment of the invention includes the chip 20 with etching stopping layer 22, in the etching
Deposition has low-k dielectric layer 24 on stop-layer 22.The dielectric layer 24 includes a variety of dielectric substances, a variety of dielectric materials
Material include being positioned over accumulation (bulk) below dielectric 24b it is low-k dielectric 24a, covering dielectric 24b k values are higher than
The accumulation is low-k dielectric 24a k values.In certain embodiments, the accumulation it is low-k dielectric 24a and covering dielectric 24b
All it is low-k dielectric.In other embodiments, the accumulation it is low-k dielectric 24a is low-k dielectric, covering dielectric 24b
It is not low-k dielectric.
In some specific embodiments, the accumulation is low-and k dielectric can be ultralow-k (ULK) dielectric, such as with
K values be about 2.2 dielectric, the covering dielectric can be the carbon doped oxide (CDO) that the k values having are about 2.9.
In other specific embodiments, the accumulation horizon can be the carbon doped oxide (CDO) that the k values having are about 2.9,
The coating can be the tetraethyl orthosilicate (tetraethylorthosilicate) (TEOS) that the k values having are about 4.0.
In other embodiments, a variety of dielectric substances may include that discontinuous (discrete) accumulates low-k dielectric
And dielectric layer；That is, single, adjacent dielectric layer.Or a variety of dielectric substances are in the accumulation
It is low-can to have transition (graded transition) that is continuous, being classified between k dielectric and covering dielectric material.
The transition of this classification can be substantially homogeneous from the side of the dielectric layer 24 to opposite side.Or from a kind of dielectric to
Another dielectric transition can be uneven only above only a part in the gross thickness of the dielectric 24, such as few
Above 50% or the thickness less than 25% or less than 10% or less than 5% of the gross thickness of the dielectric 24.
The sedimentary organic carbon hard mask layer 26 on the low-k dielectric layer 24.Resist layer 32, optional organic (or rotation
Applying) ARC (ARC) 30 and SiOC be (by by CO2With Si (CH3)4Reaction is formed), SiON or Si3N4The electricity of ARC layer
Medium A RC layers 28 are covered on organic hard mask layer.The resist layer is exposed to device pattern (device pattern)
And it is developed to remove a certain amount of anticorrosive additive material corresponding with the pattern.As shown in Figure 2 A, remaining resist layer 32
In opening 34 be then used as mask to etch corresponding a certain amount of material from ARC layer 28,30 and organic hard mask layer 26.
Then the resist layer and ARC layer are removed with organic hard mask layer of the top of leaving layer 24 and the figure being etched
Case opening 34, to cause the dielectric layer 24 of the lower section of hard mask layer 26 to be exposed, as shown in Figure 3A.The resist layer and residue
It can be removed by the method disclosed in the United States Patent (USP) of Application No. 10/890,653,11/011,273 and 11/128,930, this
A little patent disclosure of that are incorporated herein by reference in the application.Usually, the chip is subjected to cineration technics to remove
Removed with the removal resist layer, such as the hydrogen plasma by being transferred to plasma reactor and low-k dielectric film.
After the layer of the resist layer and other tops is removed, organic hard mask layer 26 be then used to for example, by reactivity from
Son etching (RIE) etches following low-k dielectric layer 24 (24a and 24b), and as shown in Figure 4 A, its split shed 34 continues downwards
Low-k layers 24 are etched into form the opening with wall 36, further expose the dielectric layer 24.
More common method is applied to the chip with the layer shown in Fig. 2A to be exposed to RIE etch, without removing layer
32、30、28.Because RIE etch usually requires that longer etching period, before etching stopping layer 22 is exposed, layer 32,30,
28 will be completely removed.Caused structure is as shown in Figure 4 A.This is by the way that the structure shown in Fig. 2A is exposed in RIE etch
To realize, the required single resist/ARC removal steps omitted described by above and Fig. 3 A are thus saved, and form figure
Structure in 4A.
The chip is then subjected to high-temperature plasma clean method of the invention to remove organic hard mask layer so that low-k
Dielectric layer is without prejudice and can receive conducting metal in opening 34.It should be noted that removing the hard mask
During exposure low-k dielectric 24a and/or 24b will not be damaged by the removal technique.Can with for described hydrogen etc. from
Implement the corona treatment in daughter cineration technics identical reactor, but it is required to realize to need to use heating element heater
Temperature of reactor.Then, as shown in Figure 5A, the surface 25 of the dielectric layer 24 there is no α-carbon (α-carbon) or its
Its organic hard mask residue, and the hole etched in the dielectric layer or the size of groove 38 it is unaffected and
Any infringement is not suffered from, such as the side wall 36 ' being corroded occurs.
Device
Any suitable plasma-reaction-chamber equipment can be used for implementing the present invention, including Gamma described above and
Iridia instruments.In this respect, furthermore, it is understood that the plasma that a suitable example is equipped with downstream is set
The Novellus Gamma of (plasma setup)TM2130 instruments.Fig. 6 is showing each of downstream plasma equipment 600
The schematic diagram of aspect, the plasma apparatus 600 are applied to implement the present invention on chip.Equipment 600 is produced with plasma
First portion 611 and the exposure chamber 601 separated by nozzle component 617.In the exposure chamber 601, chip 603 be located at platform (or
Platform) on 605.Platform 605 is equipped with heating/cooling element.In certain embodiments, platform 605 is further configured to crystalline substance
Piece 603 is biased power (bias).It can make acquisition low pressure in exposure chamber 601 via pipeline 607 using vavuum pump.Gaseous Hydrogen source of the gas
(with or without dilution/delivery gas) and carbon dioxide source (or other weak oxidants) are via entrance 609 by gas stream
Plasma-generating part 611 into the equipment is provided.A part for plasma-generating part 611 is induced coil 613 and enclosed
Around the induction coil is connected to power supply 615.During operation, admixture of gas is introduced into plasma-generating part 611,
Induction coil 613 is energized, so as to produce plasma in plasma-generating part 611.(it has outer nozzle component 617
Making alive) some ions can be prevented to flow into exposure chamber 601, and allow neutral substance to flow into the exposure chamber 601.As mentioned above
, chip 603 can be temperature control and/or can apply RF biass.
In certain embodiments, equipment of the invention is the removal device (strip for being exclusively used in removing photoresist from chip
unit).Generally speaking, such removal device instrument can have multiple wafer processing stations, so that multiple chips can be by simultaneously
Processing.Fig. 7 is the simple block diagram of the top view of display multistation (multi-station) chip removal device instrument 730, the removal
Device instrument can be used according to the present invention.Removal device instrument 730 has five and of removal station 733,735,737,739
741 and a loading depot 731.Removal device instrument 730 is configured so that each station can handle a chip, therefore institute
Some stations can be exposed to common vacuum.Each removal station 733,735,737,739 and 741 has its respective RF power supply.Dress
Carry station 731 and be commonly provided with the loading locking station (load-lock station) that is connected with the loading depot to allow to input chip
To removal device instrument 730 without destroying vacuum.Loading depot 731 can be also transferred to equipped with heating lamp by chip
Pre- thermal bimorph before being removed except station and photoresist.Removal station 741 generally configures connected loading locking station to allow crystalline substance
Piece is exported without destroying vacuum from removal device instrument 730.Mechanical arm 743 can shift chip between station and station.
During exemplary manufacturing mode, chip is processed with batch mode.Batch mode can increase crystalline substance
Piece handling capacity, thus be commonly used in the fabrication process.In batch mode, each chip is transferred to 731,733,
735th, each station in 737,739 and 741, and be processed in the station.For example, a kind of batch mode technique of example with
Following manner is carried out：Loading depot 731 is loaded the wafer into first, and in the loading depot, chip is preheated with heating lamp.So
And the chip is transferred to removal station 733 by mechanical arm 743, in the removal station, during chip is plasma treated one section, with
It is enough remove photoresist about 1/5.Then the chip is transferred to removal station 735 by mechanical arm 743, in the removal station, chip quilt
During one section of corona treatment, to be enough remove remaining photoresist about 1/5.Continue this processing sequence to go
Except station 737,739 and 741 in handle the chip.In removal station 741, photoresist is largely removed, then by chip from the removal
Device instrument unloads.
Be adapted for carrying out the present invention other instruments include can be from the GxT that ASM Nutool Inc. obtainsTMAnd G400TMLight
Photoresist removal tool, can be from the 2300Flex that Lam Res Corp. obtainsTMEtch tool, can be from the limited public affairs of Tokyo Electron
Take charge of obtained TeliusTMEtch tool can be from the Producer that Applied Materials companies obtainTMEtch tool.
It should be appreciated that apparatus described above/technique can be with photoengraving pattern instrument or technique (lithographic
Patterning tools or processes) be used in combination with manufacture or produce for example semiconductor devices, display device,
LED, electro-optical package etc..Usually, although not necessary, these instrument/techniques can be in common manufacturing facility quilt
It is used together or implements.As an example, the lithographic patterning of film comprise the following steps in it is some or all, each step can
Implemented with a variety of possible instruments：(1) photoresist is applied on substrate (i.e. substrate) with spin coating or Spray painting tool；(2)
With heating plate or heating furnace or UV tools of solidifying solidification photoresist；(3) such as chip step-by-step exposure machine (wafer is used
The photoresist is exposed to visible ray or UV or x- rays by instrument stepper) etc；(4) using such as Wet bench it
The instrument of class develops the resist selectively to remove resist, so as to pattern the photoresist；(5) by using dry method
Or the Resist patterns is transferred in following film or substrate by plasmaassisted etch tool；And (6) use such as RF
Or the instrument of microwave plasma resist removal machine etc removes the resist.
Another method of the present invention is arranged to the equipment for completing the method described in this specification.It is a kind of suitable
Equipment include being used for the hardware for completing technological operation and be with the instruction for being used to control process according to the invention to operate
System controller.A kind of suitable plasma-reaction-chamber equipment, such as Gamma and Iridia instruments or above-described other
Instrument is applicable to this method.The system controller generally comprises one or more storage devices and one or more and is configured to
The processor of these instructions is performed, so that the equipment is able to carry out the method according to the invention.Comprising for controlling according to this hair
The computer-readable medium of the instruction of bright technological operation can be coupled to the system controller.
Although the present invention has been described in detail in combined particular preferred embodiment, according to foregoing description, many is replaced
For property embodiment, modification mode and modification it will be apparent to those skilled in the art that.Therefore, appended right
It is required that by including any these alternatives fallen within the true scope and spirit of the present invention, modification mode and modification.
Claims (18)
1. a kind of method for etching or removing organic hard mask, including：
The semiconductor wafer substrate for the low-k dielectric for including exposure is provided, wherein the substrate includes being positioned under dielectric
Side accumulation it is low-k dielectric, the k values that the covering dielectric has higher than the accumulation it is low-k dielectric, and the substrate above tool
There is organic hard mask to be removed, wherein the low-k dielectric of the accumulation is thicker than the covering dielectric；
Ionizable gas is introduced in the top of the substrate and organic hard mask, the ionizable gas includes hydrogen and oxidisability gas
The mixture of body；
Energy is applied to the mixture to form the plasma of the mixture；And
Organic hard mask described in the Plasma contact, wherein the temperature of the substrate and organic hard mask is more than 200
DEG C, it is situated between with removing at least a portion of organic hard mask without damaging the low-k electricity of following substrate surface or the exposure
Matter.
2. according to the method for claim 1, wherein organic hard mask includes the amorphous carbon of chemical vapor deposition.
3. according to the method for claim 1, wherein organic hard mask includes spin coating carbon film.
4. according to the method for claim 1, wherein the low-k dielectric of the accumulation and the covering dielectric are all low-k
Dielectric.
5. according to the method for claim 1, wherein the low-k dielectric of the accumulation is low-k dielectric and the covering
Dielectric is not low-k dielectric.
6. according to the method for claim 1, wherein the low-k dielectric has the dielectric constant no more than 3.
7. according to the method for claim 1, wherein the low-k dielectric has the dielectric constant no more than 2.8.
8. according to the method for claim 1, wherein the low-k dielectric has the dielectric constant no more than 2.2.
9. according to the method for claim 1, wherein the low-k dielectric of the accumulation is the ultralow-k that there is k values to be 2.2
(ULK) dielectric, and the covering dielectric is the carbon doped oxide (CDO) that there is k values to be 2.9.
10. according to the method for claim 1, wherein the low-k dielectric of the accumulation is the carbon doping oxygen that there is k values to be 2.9
Compound (CDO), and the covering dielectric is the tetraethyl orthosilicate (TEOS) that there is k values to be 4.0.
11. according to the method for claim 1, wherein the substrate includes the low-k dielectric layer of discontinuous accumulation and covering
Dielectric layer.
12. according to the method for claim 1, wherein the substrate is included in the low-k dielectric of the accumulation and the covering
The transition of classification between dielectric.
13. according to the method for claim 1, wherein the admixture of gas is nitrogen-free.
14. according to the method for claim 1, wherein organic hard mask is removed completely from following substrate.
15. the method according to claim 11, in addition to：
Photoresist is applied to the substrate；
Expose the photoresist；
The photoresist is formed pattern and the pattern is transferred on the substrate；And
Selectively the photoresist is removed from the substrate.
16. a kind of equipment for the organic hard mask being used to etch or remove on dielectric, the equipment include：
(a) plasma-reaction-chamber device；And
(b) controller, including the programmed instruction for implementing process, the technique comprise the following steps：
The semiconductor wafer substrate for the low-k dielectric for including exposure is provided, the wherein substrate includes being positioned over below dielectric
Accumulation it is low-k dielectric, the k values that the covering dielectric has higher than the accumulation it is low-k dielectric, and the substrate above have
Organic hard mask to be removed the, wherein low-k dielectric of the accumulation is thicker than the covering dielectric；
Ionizable gas is introduced in the top of the substrate and organic hard mask, the ionizable gas includes hydrogen and oxidisability gas
The mixture of body；
Energy is applied to the mixture to form the plasma of the mixture；And
Organic hard mask described in the Plasma contact, wherein the temperature of the substrate and organic hard mask is more than 200
DEG C, it is situated between with removing at least a portion of organic hard mask without damaging the low-k electricity of following substrate surface or the exposure
Matter.
17. a kind of semiconductor wafer processing system, the system include：
Equipment described in claim 16, and step-by-step exposure machine.
18. a kind of etching removes the organic hard system of mask system and included：
Device, for providing semiconductor wafer substrate, the semiconductor wafer substrate includes low-k dielectric of exposure, wherein, institute
State substrate include being positioned over accumulation below dielectric it is low-k dielectric, the k values that the covering dielectric has are higher than the accumulation
Low-k dielectric, and there is organic hard mask to be removed above the substrate, wherein described in the low-k dielectric ratio of the accumulation
Covering dielectric is thick；
Device, for introducing ionizable gas in the top of the substrate and organic hard mask, the ionizable gas includes hydrogen
With the mixture of oxidizing gas；
Device, for applying energy to the mixture to form the plasma of the mixture；And
Device, for making organic hard mask described in the Plasma contact, wherein the temperature of the substrate and organic hard mask
Degree is more than 200 DEG C, to remove at least a portion of organic hard mask without damaging following substrate surface or the exposure
Low-k dielectric.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/372,363 | 2012-02-13 | ||
| US13/372,363 US8664124B2 (en) | 2005-10-31 | 2012-02-13 | Method for etching organic hardmasks |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103247525A CN103247525A (en) | 2013-08-14 |
| CN103247525B true CN103247525B (en) | 2017-11-17 |
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|---|---|---|---|
| CN201310049856.3A Expired - Fee Related CN103247525B (en) | 2012-02-13 | 2013-02-07 | Method for etching organic hard mask |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR102083680B1 (en) |
| CN (1) | CN103247525B (en) |
| SG (1) | SG193093A1 (en) |
| TW (1) | TWI587390B (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9040430B2 (en) * | 2013-06-27 | 2015-05-26 | Lam Research Corporation | Method of stripping organic mask with reduced damage to low-K film |
| CN104445049B (en) * | 2013-09-24 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | MEMS forming method |
| KR102306612B1 (en) * | 2014-01-31 | 2021-09-29 | 램 리써치 코포레이션 | Vacuum-integrated hardmask processes and apparatus |
| KR102204116B1 (en) | 2016-09-14 | 2021-01-19 | 베이징 이타운 세미컨덕터 테크놀로지 컴퍼니 리미티드 | Strip process with high aspect ratio structures |
| US10796912B2 (en) | 2017-05-16 | 2020-10-06 | Lam Research Corporation | Eliminating yield impact of stochastics in lithography |
| CN107968094A (en) * | 2017-11-21 | 2018-04-27 | 长江存储科技有限责任公司 | A kind of ledge structure forming technology for 3D nand flash memories |
| CN108550577A (en) * | 2018-05-17 | 2018-09-18 | 长江存储科技有限责任公司 | The manufacturing method of three-dimensional storage and three-dimensional storage |
| US11183398B2 (en) * | 2018-08-10 | 2021-11-23 | Tokyo Electron Limited | Ruthenium hard mask process |
| CN113039486A (en) | 2018-11-14 | 2021-06-25 | 朗姆研究公司 | Hard mask manufacturing method capable of being used in next generation photoetching |
| CN114200776A (en) | 2020-01-15 | 2022-03-18 | 朗姆研究公司 | Underlayer for photoresist adhesion and dose reduction |
| CN112133626B (en) * | 2020-10-12 | 2023-06-06 | 成都海威华芯科技有限公司 | Manufacturing method of metal hard mask and wafer |
| CN115394636B (en) * | 2022-10-26 | 2023-01-03 | 广州粤芯半导体技术有限公司 | Semiconductor lithography method, system, apparatus, and computer-readable storage medium |
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|---|---|---|---|---|
| US6541397B1 (en) * | 2002-03-29 | 2003-04-01 | Applied Materials, Inc. | Removable amorphous carbon CMP stop |
| CN1914715A (en) * | 2004-01-30 | 2007-02-14 | 应用材料公司 | Techniques for the use of amorphous carbon(apf) for various etch and litho integration scheme |
| CN1953146A (en) * | 2005-10-05 | 2007-04-25 | 应用材料公司 | Process to open carbon based hardmask |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4879159B2 (en) * | 2004-03-05 | 2012-02-22 | アプライド マテリアルズ インコーポレイテッド | CVD process for amorphous carbon film deposition |
| US20070134917A1 (en) * | 2005-12-13 | 2007-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Partial-via-first dual-damascene process with tri-layer resist approach |
| US7637269B1 (en) * | 2009-07-29 | 2009-12-29 | Tokyo Electron Limited | Low damage method for ashing a substrate using CO2/CO-based process |
-
2013
- 2013-02-05 SG SG2013009741A patent/SG193093A1/en unknown
- 2013-02-06 TW TW102104640A patent/TWI587390B/en not_active IP Right Cessation
- 2013-02-07 CN CN201310049856.3A patent/CN103247525B/en not_active Expired - Fee Related
- 2013-02-12 KR KR1020130015077A patent/KR102083680B1/en active IP Right Grant
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6541397B1 (en) * | 2002-03-29 | 2003-04-01 | Applied Materials, Inc. | Removable amorphous carbon CMP stop |
| CN1914715A (en) * | 2004-01-30 | 2007-02-14 | 应用材料公司 | Techniques for the use of amorphous carbon(apf) for various etch and litho integration scheme |
| CN1953146A (en) * | 2005-10-05 | 2007-04-25 | 应用材料公司 | Process to open carbon based hardmask |
Also Published As
| Publication number | Publication date |
|---|---|
| SG193093A1 (en) | 2013-09-30 |
| CN103247525A (en) | 2013-08-14 |
| TW201349345A (en) | 2013-12-01 |
| TWI587390B (en) | 2017-06-11 |
| KR20130093038A (en) | 2013-08-21 |
| KR102083680B1 (en) | 2020-03-02 |
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