TW201347148A - Non-volatile memory and manufacturing method thereof - Google Patents

Abstract

A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a first doping region, a second doping region, a select gate, a source line, a control gate, a charge storage structure and a bit line. The first doping region and the second doping region are separated and disposed in the substrate. The select gate is disposed on the substrate between the first doping region and the second doping region. The source line is disposed on the substrate at a first side of the select gate and is connected to the first doping region. The control gate is disposed on the substrate at a second side of the select gate, wherein the first side is opposite to the second side. The charge storage structure is disposed between the control gate and the substrate, between the control gate and the select gate and between the select gate and the source line. The bit line is disposed on the substrate at the second side of the select gate and is connected to the second doping region.

Description

Non-volatile memory and manufacturing method thereof

The present invention relates to a memory and a method of fabricating the same, and more particularly to a non-volatile memory and a method of fabricating the same.

Flash memory components have become widely used in personal computers and electronic devices because they have the advantages of allowing data to be stored, read, erased, etc., and the stored data does not disappear after power-off. A non-volatile memory component used.

1 is a schematic cross-sectional view of a conventional charge trapping type non-volatile memory. Referring to FIG. 1 , the non-volatile memory 10 includes a substrate 100 , a storage transistor 110 , a select transistor 120 , a doped region 130 , a source line 140 , and a bit line 150 . The storage transistor 110 and the selection transistor 120 are disposed on the substrate 100. The storage transistor 110 includes a charge storage structure 112 (consisting of a first dielectric layer 112a, a charge storage layer 112b and a second dielectric layer 112c stacked in sequence), a control gate 114, and a spacer 116. The select transistor 120 includes a gate dielectric layer 122, a select gate 124, and a spacer 126.

However, in the memory 10 described above, there is a certain interval between the storage transistor 110 and the selection transistor 120, between the selection transistor 120 and the source line 140, and between the storage transistor 110 and the bit line 150. The distance, therefore, has limitations on the size reduction of components, which is not conducive to the development of component miniaturization, and also requires a higher voltage to be applied due to the longer gate length during the stylization operation.

The present invention provides a non-volatile memory that has a smaller size.

The present invention further provides a method of fabricating a non-volatile memory that can form a non-volatile memory having a smaller size.

The present invention provides a non-volatile memory comprising a substrate, a first doped region, a second doped region, a select gate, a gate dielectric layer, a source line, a control gate, a charge storage structure, and a bit line. The first doped region and the second doped region are disposed separately in the substrate. The selection gate is disposed on the substrate between the first doped region and the second doped region. The gate dielectric layer is disposed between the selection gate and the substrate. The source line is disposed on the substrate on the first side of the selection gate and is connected to the first doping region. The control gate is disposed on the substrate on the second side of the selection gate, wherein the first side and the second side are opposite each other. The charge storage structure is disposed between the control gate and the substrate, between the control gate and the selection gate, and between the selection gate and the source line. The bit line is disposed on the substrate on the second side of the selection gate and is connected to the second doping region.

According to the non-volatile memory of the embodiment of the invention, the thickness of the charge storage structure is, for example, between 10 nm and 20 nm.

According to the non-volatile memory of the embodiment of the invention, the charge storage structure is composed of, for example, a first dielectric layer/charge storage layer/second dielectric layer.

The non-volatile memory according to the embodiment of the invention further includes a cap layer disposed on the top of the selection gate.

The non-volatile memory according to an embodiment of the invention further includes a metal telluride layer disposed on top of the source line, on the top of the control gate, and on the surface of the second doped region.

The non-volatile memory according to the embodiment of the invention further includes a metal telluride layer disposed on top of the source line, on top of the selected gate, on top of the control gate, and in the second doped region on the surface.

According to the non-volatile memory of the embodiment of the invention, the source line is, for example, a polysilicon plug.

The invention further provides a method for fabricating a non-volatile memory, which is to form a selective gate structure on the substrate and a first dielectric layer on the selective gate structure. A first doped region is then formed in the substrate on the first side of the select gate structure. Next, a charge storage structure is formed on the substrate to cover the selected gate structure and the first dielectric layer, and the charge storage structure exposes the first doped region. Then, a control gate is formed on the charge storage structure on the second side of the selection gate structure, and a source line connected to the first doping region is formed, wherein the control gate is located on the sidewall of the selection gate structure. A portion of the charge storage structure is then removed to expose the first dielectric layer and a portion of the substrate. Subsequently, a second doped region is formed in the exposed substrate. Thereafter, a bit line connected to the second doping region is formed.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the thickness of the charge storage structure is, for example, between 10 nm and 20 nm.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the charge storage structure is composed of, for example, a first dielectric layer/charge storage layer/second dielectric layer.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the charge storage structure is, for example, conformally forming a layer of charge storage structural material prior to the substrate. Thereafter, a portion of the charge storage structural material layer is removed to expose the first doped region.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the control gate and the source line is, for example, forming a conductor layer on a substrate. A portion of the conductor layer is then removed to form a source line on a first side of the select gate structure and a control gate on a second side of the select gate structure.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the above is further included on the top of the source line and on the top of the control gate after forming the second doping region and before forming the bit line. And forming a metal telluride layer on the surface of the second doped region.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, after removing a portion of the charge storage structure and before forming the second doped region, the method further includes removing the first dielectric layer.

The method for fabricating a non-volatile memory according to an embodiment of the invention is further included on the top of the source line and on the top of the selected gate after forming the second doped region and before forming the bit line A metal telluride layer is formed on the top of the control gate and on the surface of the second doped region.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the method for forming the bit line includes, for example, forming a second dielectric layer on the substrate. An opening is then formed in the dielectric layer to expose a portion of the second doped region. Thereafter, a conductor layer is formed in the opening.

According to the method for fabricating a non-volatile memory according to an embodiment of the invention, the source line is, for example, a polysilicon plug.

Based on the above, in the non-volatile memory of the present invention, since the source line and the selection gate structure and the selection gate structure and the control gate are separated only by the charge storage structure, it is known from the conventional Non-volatile memory can be compared to having a smaller size.

The above described features and advantages of the present invention will be more apparent from the following description.

2A to 2E are schematic cross-sectional views showing a method of fabricating a non-volatile memory according to a first embodiment of the present invention. First, referring to FIG. 2A, a substrate 200 is provided. The substrate 200 has a memory region 200a and a logic region 200b. Then, a dielectric material layer 202, a conductor layer 204, and a dielectric material layer 206 are sequentially formed on the substrate 200. In the present embodiment, the conductor layer 204 is, for example, a polysilicon layer. Next, a patterning process is performed to remove portions of the dielectric material layer 202, the conductor layer 204, and the dielectric material layer 206 in the memory region 200a to form the select gate structure 208 and the dielectric on the select gate structure 208. Layer 210, wherein select gate structure 208 includes select gate 208a (consisting of patterned conductor layer 204) and gate dielectric layer 208b between selected gate 208a and substrate 200 (by patterned dielectric) Material layer 202 constitutes). In this embodiment, the dielectric layer 210 can serve as a cap layer on top of the select gate 208a.

Then, referring to FIG. 2B, a doping region 212 is formed in the substrate 200 on one side of the selection gate structure 208. The method of forming the doping region 212 is, for example, performing an ion implantation process. In the present embodiment, the doping region 212 is used, for example, as a source region of the memory. Next, a charge storage structural material layer 214 is formed on the substrate 200. In detail, in the present embodiment, the charge storage structure material layer 214 is composed of a first dielectric layer, a charge storage layer, and a second dielectric layer which are sequentially conformally formed on the substrate 200 (in order to make the pattern clear These layers are not shown). The first dielectric layer is, for example, an oxide layer, the charge storage layer is, for example, a nitride layer, and the second dielectric layer is, for example, an oxide layer. That is, the charge storage structural material layer 214 is a well-known ONO composite layer. The thickness of the charge storage structural material layer 214 is, for example, between 10 nm and 20 nm.

Next, referring to FIG. 2C, a portion of the charge storage structure material layer 214 is removed to expose the doped region 212 and the dielectric material layer 206 of the logic region 200b, and form the charge storage structure 214a. The method of removing the portion of the charge storage structural material layer 214 is, for example, an anisotropic etching process in conjunction with exposing the location of the doped region 212 and the mask of the logic region 200b. Control gate 216 is then formed on charge storage structure 214a on the other side of the select gate structure 208 (the side opposite the doped region 212). Further, a source line 218 connected to the doping region 212 is formed. The source line 218 is, for example, a polysilicon plug. The method of forming the control gate 216 and the source line 218 is, for example, forming a conductor layer on the substrate 200. Then, an anisotropic etching process is performed to remove a portion of the conductor layer to form a control gate 216 and a source line 218 on the two sides of the selection gate structure 208, wherein the control gate 216 is located in the selection gate structure 208. The sidewalls are isolated from the select gate structure 208 by the charge storage structure 214a, and the source line 218 is also isolated from the select gate structure 208 by the charge storage structure 214a.

Then, referring to FIG. 2D, a portion of the charge storage structure 214a is removed to expose the dielectric layer 210 and a portion of the substrate 200 such that the charge storage structure 214a is only between the control gate 216 and the substrate 200, and the gate 216 is controlled and selected. Between the gate structure 208 and the dielectric layer 210 and between the source line 218 and the select gate structure 208 and the dielectric layer 210. Next, the dielectric material layer 202, the conductor layer 204, and the dielectric material layer 206 in the logic region 200b are patterned to form a gate structure 220 and a dielectric layer 222 on the gate structure 220. Gate structure 220 includes a gate 220a (consisting of patterned conductor layer 204) and a gate dielectric layer 220b (consisting of patterned dielectric material layer 202) between gate 220a and substrate 200. In this embodiment, the dielectric layer 222 can serve as a cap layer on top of the gate 220a. Doped regions 224 are then formed in exposed substrate 200. The doped regions 224 on the two sides of the gate structure 220 are used as the source region and the drain region, respectively. In addition, the doped region 224 in the memory region 200a serves as the drain region of the memory. A spacer 226 is then formed on the sidewall of the gate structure 220. The spacer 226 is formed by, for example, forming a layer of spacer material on the substrate 200, and then performing an anisotropic etching process to remove a portion of the spacer material layer. In particular, in the step of forming the spacer 226 on the sidewall of the gate structure 220, the spacer 226 is also formed on the sidewall of the control gate 216.

Thereafter, referring to FIG. 2E, a metal telluride layer 228 is selectively formed on top of the source line 218, on top of the control gate 216, and on the surface of the doped region 224. The method of forming the metal telluride layer 228 is, for example, a self-aligned silicide (salicide) process. Next, a dielectric layer 230 is formed on the substrate 200. Thereafter, a bit line 232 is formed in the dielectric layer 230 to be connected to the metal germanide layer 228 (if the metal germanide layer 228 is not formed, the doped region 224 is connected). The bit line 232 is formed by, for example, forming an opening in the dielectric layer 230 exposing a portion of the metal telluride layer 228 (if the metal germanide layer 228 is not formed, exposing the doped region 224), and then opening the opening A conductor layer is formed in the middle. In this way, the fabrication of the non-volatile memory 20 of the present embodiment can be completed.

In the non-volatile memory 20, since the source line 218 and the selection gate structure 208 and between the selection gate structure 208 and the control gate 216 are separated only by the charge storage structure 214a, it is conventionally known. The non-volatile memory 20 can be of a smaller size than the non-volatile memory. In addition, since the non-volatile memory 20 has a small size and the charge storage structure 214a is between the selection gate 208a and the control gate 216, source-side injection can be used for stylized operations. The mode applies a lower write voltage.

In particular, in the present embodiment, the fabrication of the non-volatile memory 20 can be integrated with the fabrication of components in the logic region 200b, and since the charge storage structure 214a is formed in the logic region 200b. The source region and the drain region (doped region 224) are formed before, so the impurity concentration distribution of the source region and the drain region in the logic region 200b is not affected by the process of forming the charge storage structure 214a. The effect of the thermal budget changes the characteristics of the transistor (eg short channel effect).

3A-3C are schematic cross-sectional views showing a method of fabricating a non-volatile memory according to a second embodiment of the present invention. In the present embodiment, FIG. 3A is continued after FIG. 2C, and therefore the same elements will be denoted by the same reference numerals and will not be described.

First, referring to FIG. 3A, after performing the steps described in FIG. 2C, a portion of the charge storage structure 214a is removed to expose the dielectric layer 210 and a portion of the substrate 200 such that the charge storage structure 214a is only located at the control gate 216 and the substrate. Between 200, between control gate 216 and select gate structure 208 and dielectric layer 210, and between source line 218 and select gate structure 208 and dielectric layer 210. Next, the dielectric layer 210 and the dielectric material layer 206 in the logic region 200b are removed to expose the top of the select gate 208a and the conductor layer 204. Thereafter, the conductor layer 204 in the logic region 200b is patterned with the dielectric material layer 202 to form the gate structure 220. Gate structure 220 includes a gate 220a (consisting of patterned conductor layer 204) and a gate dielectric layer 220b (consisting of patterned dielectric material layer 202) between gate 220a and substrate 200.

Then, referring to FIG. 3B, a doped region 224 is formed in the exposed substrate 200. The doped regions 224 on the two sides of the gate structure 220 are used as the source region and the drain region, respectively. In addition, the doped region 224 in the memory region 200a serves as the drain region of the memory. A spacer 226 is then formed on the sidewall of the gate structure 220. The spacer 226 is formed by, for example, forming a layer of spacer material on the substrate 200, and then performing an anisotropic etching process to remove a portion of the spacer material layer. In particular, in the step of forming the spacer 226 on the sidewall of the gate structure 220, the spacer 226 is formed on the sidewalls of the control gate 216 and the source line 218 at the same time.

Thereafter, referring to FIG. 3C, a metal telluride layer 228 is selectively formed on top of the source line 218, on top of the select gate 208a, on top of the control gate 216, and on the surface of the doped region 224. The method of forming the metal telluride layer 228 is, for example, a self-aligned metal telluride process. Next, a dielectric layer 230 is formed on the substrate 200. Thereafter, a bit line 232 is formed in the dielectric layer 230 to be connected to the metal germanide layer 228 (if the metal germanide layer 228 is not formed, the doped region 224 is connected). The bit line 232 is formed by, for example, forming an opening in the dielectric layer 230 exposing a portion of the metal telluride layer 228 (if the metal germanide layer 228 is not formed, exposing the doped region 224), and then opening the opening A conductor layer is formed in the middle. In this way, the fabrication of the non-volatile memory 30 of the present embodiment can be completed.

In particular, in the non-volatile memory 30, since the top height of the selection gate 208a is lower than the top height of the control gate 216, the metal germanide layer 228 on the top of the gate 208a can be avoided and controlled. The metal telluride layer 228 on top of the gate 216 contacts to create a short circuit.

In addition, as in the non-volatile memory 20, in the non-volatile memory 30, only the charge is between the source line 218 and the select gate structure 208 and between the select gate structure 208 and the control gate 216. The storage structure 214a is isolated so that the non-volatile memory 30 can be of a smaller size than conventional non-volatile memory.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 20, 30. . . Non-volatile memory

100, 200. . . Base

110. . . Storage transistor

112, 214a. . . Charge storage structure

112a. . . First dielectric layer

112b. . . Charge storage layer

112c. . . Second dielectric layer

114,216. . . Control gate

116, 126, 226. . . Clearance wall

120. . . Select transistor

122, 208b, 220b. . . Gate dielectric layer

124, 208a. . . Select gate

130, 212, 224. . . Doped region

140, 218. . . Source line

150, 232. . . Bit line

200a. . . Memory area

200b. . . Logical line area

202, 206. . . Dielectric material layer

204. . . Conductor layer

208. . . Gate structure

210, 222, 230. . . Dielectric layer

214. . . Charge storage structural material layer

220. . . Gate structure

220a. . . Gate

228. . . Metal telluride layer

1 is a schematic cross-sectional view of a conventional non-volatile memory.

2A to 2E are schematic cross-sectional views showing a method of fabricating a non-volatile memory according to a first embodiment of the present invention.

3A-3C are schematic cross-sectional views showing a method of fabricating a non-volatile memory according to a second embodiment of the present invention.

20. . . Non-volatile memory

200. . . Base

200a. . . Memory area

200b. . . Logical line area

208. . . Gate structure

208a. . . Select gate

208b, 220b. . . Gate dielectric layer

210, 222, 230. . . Dielectric layer

212, 224. . . Doped region

214a. . . Charge storage structure

216. . . Control gate

218. . . Source line

220. . . Gate structure

220a. . . Gate

226. . . Clearance wall

228. . . Metal telluride layer

232. . . Bit line

Claims (17)

A non-volatile memory comprising: a substrate; a first doped region and a second doped region are disposed separately in the substrate; a select gate disposed in the first doped region and the second On the substrate between the doped regions; a gate dielectric layer disposed between the select gate and the substrate; a source line disposed on the substrate on a first side of the select gate, and Connected to the first doped region; a control gate disposed on the substrate on a second side of the select gate, wherein the first side and the second side are opposite to each other; a charge storage structure disposed on Between the control gate and the substrate, between the control gate and the select gate, and between the select gate and the source line; and a bit line disposed at the second of the select gate On the substrate on the side, and connected to the second doped region. The non-volatile memory of claim 1, wherein the charge storage structure has a thickness between 10 nm and 20 nm. The non-volatile memory of claim 1, wherein the charge storage structure is composed of a first dielectric layer/charge storage layer/second dielectric layer. The non-volatile memory of claim 1, further comprising a cap layer disposed on top of the select gate. The non-volatile memory of claim 4, further comprising a metal telluride layer disposed on top of the source line, on top of the control gate, and on a surface of the second doped region on. The non-volatile memory of claim 1, further comprising a metal telluride layer disposed on top of the source line, on top of the select gate, on top of the control gate, and On the surface of the second doped region. The non-volatile memory of claim 1, wherein the source line comprises a polysilicon plug. A method of fabricating a non-volatile memory, comprising: forming a selective gate structure on a substrate; and a first dielectric layer on the selected gate structure, wherein the gate structure comprises a select gate and a gate dielectric layer between the select gate and the substrate; a first doped region formed in the substrate on a first side of the select gate structure; and a charge storage structure formed on the substrate Covering the selected gate structure and the first dielectric layer, and the charge storage structure exposes the first doped region; forming a control gate on the charge storage structure on a second side of the select gate structure And forming a source line connected to the first doping region, wherein the control gate is located on a sidewall of the selective gate structure; removing a portion of the charge storage structure to expose the first dielectric layer And a portion of the substrate; forming a second doped region in the exposed substrate; and forming a bit line connected to the second doped region. The method for fabricating a non-volatile memory according to claim 8, wherein the charge storage structure has a thickness of between 10 nm and 20 nm. The method of fabricating the non-volatile memory of claim 8, wherein the charge storage structure is composed of a first dielectric layer/charge storage layer/second dielectric layer. The method for fabricating a non-volatile memory according to claim 8, wherein the method for forming the charge storage structure comprises: conformally forming a layer of charge storage structural material on the substrate; and removing a portion of the charge A layer of structural material is stored to expose the first doped region. The method for fabricating a non-volatile memory according to claim 8 , wherein the method of forming the control gate and the source line comprises: forming a conductor layer on the substrate; removing a portion of the conductor layer, The source line is formed on the first side of the select gate structure, and the control gate is formed on the second side of the select gate structure. The method of fabricating the non-volatile memory of claim 8, wherein the forming of the second doped region and before forming the bit line are further included on top of the source line, A metal telluride layer is formed on the top of the control gate and on the surface of the second doped region. The method of fabricating the non-volatile memory of claim 8, wherein the removing the portion of the charge storage structure and before forming the second doped region further comprises removing the first dielectric layer . The method of fabricating the non-volatile memory of claim 14, wherein the forming of the second doped region and before forming the bit line are further included on top of the source line, A metal telluride layer is formed on the top of the selection gate, on the top of the control gate, and on the surface of the second doped region. The method for fabricating a non-volatile memory according to claim 8 , wherein the method for forming the bit line comprises: forming a second dielectric layer on the substrate; forming an opening in the dielectric layer And exposing a portion of the second doped region; and forming a conductor layer in the opening. The method of fabricating the non-volatile memory of claim 8, wherein the source line comprises a polysilicon plug.