TW201347043A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A disclosed semiconductor device includes a semiconductor deposition layer formed over an insulation structure and above a substrate. The device includes a gate formed over a contact region between first and second implant regions in the semiconductor deposition layer. The first and second implant regions both have a first conductivity type, and the gate has a second conductivity type. The device may further include a second gate formed beneath the semiconductor deposition layer.

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor technology, and more particularly to a Junction Field Effect Transistor (JEFT) device and a method of fabricating the same.

The conventional junction field effect transistor element has a structure as shown in Fig. 1. The junction field effect transistor element 100 illustrated in FIG. 1 is formed over a semiconductor substrate 102 such as a germanium wafer. The substrate 102 can be modified by a fabric process such as diffusion doping, ion implantation, or in-situ doping to introduce a P-type dopant. An N-well 104 is formed in the substrate 102 to provide a path for the charge to flow between the source and drain terminals. The N-well 104 can introduce N-type dopant formation by a conventional fabric process. The junction field effect transistor component 100 further includes a plurality of first routing regions 106 and a plurality of second routing regions 108. Each of the first value regions includes a high concentration of N-type dopants, and each of the first value regions can serve as a source or a drain. The second value regions 108 each include a P-type dopant, and each of the second value regions can serve as a gate.

During operation, a positive drain-source voltage (V _DS ) drives the charge in the N-well 104 to flow from the source to the drain. The conductivity of the N-well 104 may be a negative value by the gate-to-source voltage _{(gate-source voltage, V GS} ) control, this negative value of V _GS that each PN junction depletion region induced formed (depletion region). The value of the gate-to-source voltage V _GS can be adjusted to the channel where the depletion region pinch off the charge flow to close the junction field effect transistor element 100. The voltage at which this is clamped is referred to as a pinch off voltage (V _P ). When the junction field effect transistor component is integrated in an integrated circuit, the influence of the semiconductor substrate noise can change V _P , resulting in inconsistencies and defects of the plurality of junction field effect transistor components. Therefore, in order to allow for a more accurate V _P , it is necessary to insulate the junction field effect transistor element.

A first exemplary embodiment discloses a semiconductor device including a substrate, an insulating structure formed on the substrate, and a semiconductor deposited layer formed over the insulating structure and the substrate, the semiconductor deposited layer having a first conductivity type. The disclosed semiconductor device further includes a first layout region formed in the semiconductor deposition layer, the first layout region having a first conductivity type and a higher doping concentration than the semiconductor deposition layer; and a second layout region, Formed in the semiconductor deposited layer, the second value region has a higher doping concentration than the first conductive type and the semiconductor deposited layer. The disclosed semiconductor device further includes a metal contact layer formed on a contact region of the first layout region of the semiconductor deposition layer and the second layout region of the semiconductor deposition layer, thereby contacting the metal contact layer with the semiconductor deposition layer The interval forms a junction, wherein the junction is a Schottky barrier.

A second exemplary embodiment discloses a semiconductor device including a substrate, a first insulating structure formed on the substrate, and a first semiconductor deposited layer formed on the first insulating structure. The disclosed semiconductor device further includes a second insulating structure formed on the first semiconductor deposited layer, a second semiconductor deposited layer formed on the second insulating structure, and the second semiconductor deposited layer having a conductive type. The disclosed semiconductor device can include a first routing region formed in the second semiconductor deposition layer, the first routing region having a conductivity type and a higher doping concentration than the second semiconductor deposition layer; and a second routing region Formed in the second semiconductor deposition layer, the second value region has a conductivity type and a higher doping concentration than the second semiconductor deposition layer. a metal contact layer is formed on a contact region of the first routing region of the second semiconductor deposition layer and the second routing region of the second semiconductor deposition layer, thereby forming a contact region between the metal layer and the second semiconductor deposition layer The junction, wherein the junction is a Schottky barrier.

Related manufacturing methods of the semiconductor device disclosed in the present invention are also disclosed.

2 is a cross-sectional view of a junction field effect transistor element 200 that reduces noise and increases the sharpness of the pinch. The junction field effect transistor device 200 includes a substrate 202 and an insulating structure 204 formed on the substrate 202. The insulating structure 204 can be used to substantially protect the structure thereon from the effects of noise and interference from the underlying substrate. The insulating structure 204 may include a field oxide layer (FOX) formed on the substrate 202. In some embodiments, a high temperature oxide layer 208 (HTO) may be formed on the field oxide layer 206. on. Field oxide layer 206 and high temperature oxide layer 208 can be formed by standard photomasking and thermal oxidation techniques. For example, the field oxide layer 206 can be formed by a local oxidation of silicon (LOCOS) process. The same process can be repeated to form the high temperature oxide layer 208. Exemplary techniques for LOCOS include shallow trench isolation (STI) or silicon on insulator (SOI). Although the values may vary, the field oxide layer may have a thickness ranging from 1000 angstroms to 10,000 angstroms, preferably about 5000 angstroms, and the high temperature oxide layer 208 may have a thickness between 120 angstroms and 400 angstroms, preferably about 300 angstroms.

Below the insulating structure 204, a first well region 210 can be formed within the substrate 210 below the insulating structure 204. In the embodiment depicted in FIG. 2, substrate 202 includes a P-type dopant, but in another embodiment, substrate 202 can include an N-type dopant. In either embodiment, the first well region 210 can be a P well or an N well.

A semiconductor deposition layer 212 is formed over the insulating structure 204 by a deposition process over the insulating structure 204. The semiconductor deposition layer 212 can have a first conductivity type that causes charge to flow from the source 214 to the drain 216. The conductivity of the semiconductor deposition layer 212 can be controlled by the gate 218. The structure of the junction field effect transistor element 200 will be described in more detail below with reference to FIG.

Figure 3 is a partial view of the junction field effect transistor element 200. The semiconductor deposition layer 212 may be a polysilicon layer manufactured by a standard process, and as discussed above, the semiconductor deposition layer 212 may be modified by a fabric process to have a first conductivity type, and the first conductivity type may be N type or P. type. In one embodiment, the semiconductor deposition layer 212 may be formed by depositing polycrystalline germanium, for example, phosphorous chloride (N-type dopant of POCl may be introduced by in-situ doping during polycrystalline germanium deposition). In one embodiment, the concentration of POCl ₃ is about 1*10 ¹¹ /cm ² . Other N-type dopants such as phosphorus (P) may also be used. In another embodiment, The N-type dopant is introduced by diffusion doping or in-situ doping of the ion implantation. In still another embodiment, the same process as the introduction of the N-type dopant may be applied to the semiconductor sink. A P-type dopant is introduced into the buildup 212. An example of a P-type dopant is boron (Bordon, B).

A first value region 214 may be formed in the semiconductor deposition layer 212, the first value region having a first conductivity type and having a higher doping concentration than the semiconductor deposition layer 212. The first value area 214 can be labeled as source 214. A second routing region 216 can be formed in the semiconductor deposition layer 212, the second routing region having a first conductivity type and having a higher doping concentration than the semiconductor deposition layer 212. The second value area 216 can be labeled as a drain 216.

In the exemplary embodiment illustrated in FIG. 3, the first conductivity type is N-type, and the semiconductor deposition layer 212 is operable to provide an N-channel for charge in the first N+-valued region 214 and the second N+-valued region 216. Flow between. In another embodiment, the first conductivity type can be P-type, and the semiconductor deposition layer 212 can operate to provide a P-channel to cause charge to flow between the first P+ doped region 214 and the second P+ doped region 216.

In addition to the semiconductor deposition layer 212, the junction field effect transistor device 200 further includes a metal contact layer 218 formed on one of the contact regions 220 of the semiconductor deposition layer 212. The contact region 220 is located in the first value region 214 and The second cloth value area is 216. The metal contact layer 218 can include a suitable metal such that the junction between the metal contact layer 218 and the contact region 220 of the semiconductor deposition layer 212 acts as a Schottky barrier. Depending on whether the semiconductor deposition layer 212 includes N-type or P-type dopants, the Schottky barrier can be used as a P-type gate or an N-type gate, respectively. Metal contact layer 218 as described above may be labeled as gate 218. To form a P-type gate, the metal contact layer 218 can comprise a suitable metal such as titanium, tungsten, nickel, platinum, aluminum, gold or cobalt. To form an N-type gate, the metal contact layer 218 can comprise a suitable metal such as platinum (Pt).

The gate 218 can be operated to control the conductivity of the channel of the semiconductor deposition layer 212. In operation, a positive drain-source voltage (V _DS ) causes charge to flow from the source 214 of the semiconductor deposition layer 212 into the drain 216. The conductivity of the semiconductor deposition layer 212 can be controlled by a negative gate-source voltage (V _GS ), and the negative V _GS induces a depletion region in or around the contact region 220 (depletion) Region). The value of V _GS can be adjusted to the channel where the depletion region pinch off the charge flow to close the junction field effect transistor element 200. The pinch off voltage (V _P ) may vary depending on the thickness of the semiconductor deposited layer. In an exemplary embodiment, the range of thickness of the semiconductor layer can be deposited between 0.7-30 volts V _P. In another embodiment, the thickness of the semiconductor deposited layer can range from 500 angstroms to 6,000 angstroms.

By forming the metal contact layer 218 and the semiconductor deposition layer 212 on the insulating structure 204, the noise and interference originating from the substrate 202 are substantially reduced, and the semiconductor sink can be enhanced by the gate 218 and the more accurate V _P . Control of the conductivity of the buildup 212. Another advantage of the disclosed structure is that the first well region 210 below the insulating structure 204 can be used to accommodate other components that may have no space to form a PN junction in the junction field effect transistor.

Figure 4 is a front elevational view of a junction field effect transistor element 300 having a three dimensional gate structure. The junction field effect transistor element 300 includes a substrate 302 and a first insulating structure 304 formed on the substrate. Similar to the insulating structure 204 discussed in Figures 2 and 3, the first insulating structure 304 can be used to substantially protect the structure thereon from the effects of noise and interference from the underlying substrate 302. The first insulating structure 304 can include a field oxide layer 306 formed on the substrate 302. In some embodiments, the first insulating structure 304 further includes a gate oxide layer 308 disposed on the field oxide layer 306. Field oxide layer 306 and gate oxide layer 308 can be formed using conventional photomasks and thermal oxidation techniques.

The junction field effect transistor element 300 further includes a first semiconductor deposition layer 310 formed on the first insulation structure 304, a second insulation structure 312 formed on the first semiconductor deposition layer 310, and a second insulation formed thereon. A second semiconductor deposition layer 314 on structure 312. FIG. 5 is a partial view of the structure formed on the first insulating structure 304 in the junction field effect transistor element 300. In one embodiment, the first semiconductor deposition layer 310 and the second semiconductor deposition layer 314 may extend toward the first long axis 320 and the second long axis 322, respectively, as shown in FIG. In an exemplary embodiment, the first major axis 320 is substantially orthogonal to the second major axis 322, but in another embodiment, the first major axis 320 is adjustable at an angle to the second major axis. The first semiconductor deposition layer 310 can include any of N-type or P-type dopants to provide the conductivity required to form a three-dimensional gate structure, as will be described in more detail below. In one embodiment, the first semiconductor deposited layer may be deposited with tungsten telluride WSi and cobalt telluride CoSi to form a germanide that reduces the resistance of the first semiconductor deposited layer 310. The insulating structure 312 can be a high temperature oxide layer 208 as described in the embodiments of FIGS. 2 and 3.

Additionally, the second semiconductor deposition layer 314 can be substantially similar to the semiconductor deposition layer 212 described in the embodiments of FIGS. 2 and 3. The second semiconductor deposition layer 314 can be a polysilicon layer manufactured by a standard process, and can be modified by a fabric process to have a first conductivity type, and the first conductivity type can be N-type or P-type. In an exemplary embodiment illustrated in FIG. 6, the second semiconductor deposition layer 314 may be formed by depositing polysilicon on the first insulating structure 304 and the second insulating structure 312, and the N-type dopant may be deposited. In the case of polysilicon, the in-situ doping value is in the second semiconductor deposition layer 314. In another embodiment, the N-type dopant can be introduced by diffusion doping or in-situ doping of ion cloth values. In yet another embodiment, the N-type dopant can be replaced with a P-type dopant and introduced into the second semiconductor deposition layer 314 in the same process.

Referring to FIGS. 4-6, a first layout region 316 may be formed in the second semiconductor deposition layer 314. The first layout region 316 has the same conductivity type and second as the second semiconductor deposition layer 314. The semiconductor deposition layer 314 has a high doping concentration. The first value area 316 can be labeled as source S. A second layout region 318 may be formed in the second semiconductor deposition layer 314, the second layout region 318 having the same conductivity type as the second semiconductor deposition layer 314 and a higher doping concentration than the second semiconductor deposition layer 314. . The second value area 318 can be labeled as the drain D.

The junction field effect transistor element 300 includes a metal contact layer formed on a contact region 326 of the second semiconductor deposition layer 314, the contact region 326 being located between the first value region 316 and the second value region 318. Similar to the metal contact layer 218, the metal contact layer 324 can include a suitable metal such that the junction between the metal contact layer 324 and the contact region 326 of the second semiconductor deposition layer 314 acts as a Schottky barrier. Metal contact layer 324 may surround second semiconductor deposition layer 314 and be out of contact with the first semiconductor deposition layer. According to the second semiconductor deposition layer 314 including N-type or P-type dopants, the Schottky barrier can be used as a P-type gate or an N-type gate, respectively. Metal contact layer 324 as described above may be labeled as gate 324.

After the value of the N-type or P-type dopant, the conductivity of the second semiconductor deposition layer 314 allows charge to flow from the source 316 to the drain 318. The conductivity of the second semiconductor deposition layer 314 can be controlled by both the gate 324 and the first semiconductor deposition layer 310. When executed independently, the first shutter gate 324 can be of a negative-to-source voltage V _GS1 control of the second conductive semiconductor layer 314 is deposited, this V _GS1 in the contact region 326, or a first depletion region induced around . The value of V _GS1 can be adjusted to the channel of the pinch region pinch off charge flow to close the junction field effect transistor element 300. However, the first semiconductor deposition layer 300 and the second insulating structure 312 can function as a second gate in the second semiconductor deposition layer 314 to form a second depletion region. The second depletion region can be formed by additionally applying a negative second gate to source voltage V _{GS2 on} an electrode (not shown) connected to the first semiconductor deposition layer 310. In addition to the improvement caused by the first insulating structure 304, the first depletion region and the second depletion region can interact with each other, which not only better controls the V _P but also improves the precision of the pinch.

By improving the controllability and precision of the pinch-off voltage, the junction field effect transistor elements disclosed herein can achieve more different improvements in integrated circuits (ICs). For example, in recent years, in view of the high conversion efficiency and low standby power consumption of the junction field effect transistor element disclosed in the present invention, it is particularly suitable for the development of green technology. A switched power IC includes an integrated startup circuit and a Pulse Width Moldulation (PWM) circuit. Figure 7 illustrates a conventional high voltage startup circuit 400 that continues to generate power dissipation after startup. The resistor 410 can be selected from the group that can provide a charging curremt ( _IC ) to the capacitor 420 and enable the pulse width modulation circuit to operate. The pulse width modulation circuit 430 continues to operate until its voltage V _{CC is} below the minimum operating voltage, and then an auxiliary current I _{aux is} applied to the pulse width modulation circuit. Pulse width modulation circuit 430 typically operates between 10V and 30V. To reduce power consumption, the resistor 410 of the startup circuit can be replaced by an HV depletion (MOS) or HV JEFT component. However, an HV depletion NMOS has a large leakage current (>100μA) at the threshold voltage (<-4V). A HV JEFT requires a large drift region to form a reduced surface field (RESURF), so the pinch feature of the HV JEFT lacks accuracy.

FIG. 8 illustrates an exemplary circuit 500 including a junction field effect transistor element 510 of the present disclosure. Junction field effect transistor element 510 can be any junction field effect transistor configuration in accordance with the disclosed principles. In addition to the junction field effect transistor element 510, the circuit 500 further includes a pulse width modulation circuit 520, an HV depletion MOS 530, and a diode 540. In operation, the source during startup of the extreme gate voltage V _S is less than the junction field effect transistor device of the pinch voltage V _P, and the junction field effect transistor device exhibits a low resistance. An exemplary pinch voltage V _P is approximately 15 volts. When the junction field effect transistor element exhibits low resistance, an HV depletion MOS 530 having an exemplary threshold voltage (V _th ) -3 V can provide the operation of the pulse width modulation circuit 520 and the charging of the capacitor 450. The current is until the V _S of the junction field effect transistor element 510 reaches the pinch voltage V _p . When V _{S is} higher than the pinch-off voltage V _P , the resistance of the junction field effect transistor element 510 is greatly increased, while the drain-to-source voltage remains the same as the pinch-off voltage V _P . When V _{S is} higher than the pinch voltage V _{P by} a threshold voltage V _th , the MOS 530 will be turned off. For example, in an exemplary embodiment, the pinch-off voltage V _P is about 15V and the threshold voltage V _th is -3V. The graph of Fig. 9 shows that in this embodiment, when V _{S is} higher than the clamping voltage V _{P by} about 15 V, the current from the MOS 530 (I _D ) increases due to the resistance of the junction field effect transistor element 510. Start to lower. When V _S reaches 18V, that is, above the pinch voltage V _{P -} a threshold voltage V _th , the current I _D from the MOS 530 will stop. Referring to FIG. 8, after the pulse width modulation is started, I _aux can be used to charge the capacitor 550. Therefore, the junction field effect transistor element 510 capable of accurately controlling the pinch-off voltage V _P can reduce the leakage current of the HV depletion MOS 530 and increase the efficiency.

Although the present invention has been disclosed above by way of example, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the invention is not limited to the specific embodiments disclosed, and the modifications and modifications are intended to be included within the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. .

100, 200, 300. . . Junction field effect transistor component

102, 202, 302. . . Substrate

104. . . N well

106. . . First value area

108. . . Second value area

204. . . Insulation structure

206, 306. . . Field oxide layer

208. . . High temperature oxide layer

210. . . First well area

212. . . Semiconductor deposit

214, S. . . Source

216, D. . . Bungee

218, 324. . . Metal contact layer

220, 326. . . Contact area

304. . . First insulation structure

308. . . Gate oxide layer

310. . . First semiconductor deposition layer

312. . . Second insulation structure

314. . . Second semiconductor deposition layer

316. . . First value area, source

318. . . Second value area, bungee

320. . . First long axis

322. . . Second long axis

400, 500. . . Circuit

410. . . resistance

420, 550. . . capacitance

430, 520. . . Pulse width modulation circuit

530. . . HV depletion MOS

540. . . Dipole

I _D . . . Current from MOS

I _IC . . . recharging current

I _AUX . . . Auxiliary current

V _Z . . . Crash voltage

V _CC . . . Supply voltage

V _S . . . Source to gate voltage

V _ss . . . Source voltage

V _gg . . . Gate voltage

Figure 1 is a cross-sectional view showing a conventional junction field effect transistor element.

2 is a cross-sectional view of a junction field effect transistor element in accordance with the present invention.

Fig. 3 is a partial view showing a specific structure of the junction field effect transistor element of Fig. 2.

Figure 4 is a front elevational view of a junction field effect transistor element 300 having a three dimensional gate structure.

Figure 5 is a partial elevational view of one embodiment of the junction field effect transistor element of Figure 4.

Figure 6 is a partial elevational view of another embodiment of the junction field effect transistor component of Figure 4.

Figure 7 illustrates a conventional circuit including a resistor.

FIG. 8 illustrates an embodiment of a circuit including a junction field effect transistor component disclosed herein.

Figure 9 is a diagram showing the relationship between the source-to-gate voltage of the junction field effect transistor element and the drain voltage of the MOS device in one embodiment of Fig. 8.

300. . . Junction field effect transistor component

302. . . Substrate

304. . . First insulation structure

308. . . Gate oxide layer

310. . . First semiconductor deposition layer

312. . . Second insulation structure

314. . . Second semiconductor deposition layer

Claims (10)

A semiconductor component comprising:
a substrate;
An insulating structure formed on the substrate;
a semiconductor deposition layer formed on the insulating structure and over the substrate, the semiconductor deposition layer having a first conductivity type;
a first value region formed in the semiconductor deposition layer, the first value region having the first conductivity type and a higher doping concentration than the semiconductor deposition layer;
a second layout region formed in the semiconductor deposition layer, the second layout region having the first conductivity type and a higher doping concentration than the semiconductor deposition layer; and a metal contact layer formed on the semiconductor sink a contact region located between the first value region and the second value region, and a junction formed between the metal contact layer and the contact region of the semiconductor deposition layer, wherein The junction is a Schottky barrier. The semiconductor component of claim 1, wherein the insulating structure comprises a field oxide layer. The semiconductor device of claim 2, wherein the insulating structure further comprises a high temperature oxide layer disposed over the oxide layer. The semiconductor device of claim 1, further comprising a first well region formed in the substrate, wherein the first well region is located below the insulating structure, and the first well region has the first Conductive or a second conductivity type. The semiconductor device of claim 1, wherein the semiconductor deposited layer comprises a polysilicon layer. The semiconductor device of claim 1, wherein the first conductivity type is N-type, and the Schottky barrier can function as a P-type gate. The semiconductor device according to claim 1, wherein the first conductivity type is a P type, and the Schottky barrier can function as an N-type gate. A semiconductor component comprising:
a substrate;
a first insulating structure is formed on the substrate;
a first semiconductor deposition layer is formed on the first insulation structure;
a second insulating structure formed on the first semiconductor deposited layer;
a second semiconductor deposition layer formed on the second insulation structure, the second semiconductor deposition layer having a conductivity type;
a first routing region formed in the second semiconductor deposition layer, the first routing region having the conductivity type and a higher doping concentration than the second semiconductor deposition layer;
a second routing region formed in the second semiconductor deposition layer, the second routing region having the conductivity type and a higher doping concentration than the second semiconductor deposition layer;
a metal contact layer formed on a contact region of the second semiconductor deposition layer, the contact region being located between the first layout region and the second layout region, a junction formed on the metal contact layer and the Between the contact regions of the second semiconductor deposition layer, wherein the junction is a Schottky barrier. The semiconductor device of claim 8, wherein the first insulating structure comprises a field oxide layer and a gate oxide layer, the gate oxide layer being disposed on the field oxide layer. A method of manufacturing a semiconductor device, comprising:
Forming an insulating structure on a substrate;
Forming a semiconductor deposition layer on the substrate and on the insulating structure, the semiconductor deposition layer having a first conductivity type;
Forming a first value region in the semiconductor deposition layer, the first value region having the first conductivity type and a higher doping concentration than the semiconductor deposition layer;
Forming a second value region in the semiconductor deposition layer, the second value region having the first conductivity type and a higher doping concentration than the semiconductor deposition layer;
Forming a metal contact layer on a contact region of the second semiconductor deposition layer, the contact region being located between the first routing region and the second routing region, and further the metal contact layer and the second semiconductor sink A junction is formed between the contact regions of the laminate, wherein the junction is a Schottky barrier.