TW201345154A - Input/output circuit - Google Patents

Abstract

Input/output circuit including a gating circuit, a transmission circuit and a first switch. The gating circuit has a first gating terminal, a second gating terminal and a gating control terminal, and selectively conducts between the first gating terminal and the second gating terminal according to signal at the gating control terminal; signal at the first gating terminal is in associated with an input signal and an enable signal. The transmission circuit has a first signal terminal and an output terminal respectively coupled to the second gating terminal and a pad. The first switch has a first coupling terminal and a second coupling terminal respectively coupled to an internal terminal and the gating control terminal, and selectively conducts between the first coupling terminal and the second coupling terminal according to the enable signal. The internal terminal is coupled to the pad.

Description

Output circuit

The present invention relates to an input-output circuit, and more particularly to an input-output circuit that can improve response speed after transmission and reception switching.

Various electronic devices based on integrated circuits/wafers are the most important hardware foundation of the modern information society. The electronic device is composed of different wafers; in order to integrate the functions of different wafers, an input and output circuit is arranged in each wafer to exchange data and signals with other wafers.

In a communication application, the input and output circuits of different chips use the same line to exchange data. Please refer to FIG. 1 , which is a schematic diagram of data input between two input and output circuits 100 and 102 in such an application. The input and output circuit 100 is provided with a transmission module TX1 and a receiving module RX1, and is coupled to a trace 12 (for example, a wiring on a circuit board) via a pad PAD1; and a transmission module is provided in the input/output circuit 102. The TX2 and the receiving module RX2 are coupled to the trace 12 via the pad PAD2. The transmission module TX1 is controlled by the uniform energy signal OEN1; when the enable signal OEN1 is logic 0, the transmission module TX1 is enabled to drive the signal of the pad PAD1 according to the signal I1. When the enable signal OEN1 is logic 1, the transmission module TX1 is disabled, and the signal of the pad PAD1 is no longer controlled to maintain the pad PAD1 in a driveable state; and the receiving module RX1 can be used as a pad. The signal of PAD1 is received as signal C1. Similarly, the transmission module TX2 is controlled by the enable signal OEN2.

The input and output circuits 100 and 102 can be respectively disposed on two different wafers. When the input-output circuit 100 is to transmit data to the input-output circuit 102, the enable signals OEN1 and OEN2 are logic 0 and logic 1, respectively; in the input-output circuit 100, the transmission module TX1 is enabled, and the driver pad PAD1 is driven according to the signal I1. The signal is driven by the trace 12 to drive the signal of the pad PAD2. In the input-output circuit 102, the transmission module TX2 is disabled, so that the signal of the pad PAD2 can be driven by the transmission module TX1; and the receiving module RX2 receives the signal of the pad PAD2 as the signal C2. In other words, the input and output circuits 100 and 102 can be respectively used as the transmitting end and the receiving end; the data in the signal I1 can be sent through the transmission module TX1 and the pad PAD1, and received to the signal C2 via the pad PAD2 and the receiving module RX2.

In contrast, the functions of the input and output circuits 100 and 102 can be exchanged as the receiving end and the transmitting end, respectively. When the input-output circuit 102 is to transmit data to the input-output circuit 100, the enable signals OEN1 and OEN2 are respectively logic 1 and logic 0; in the input-output circuit 102, the transmission module TX2 is enabled, and the driver pad PAD2 is driven according to the signal I2. The signal is driven by the trace 12 to drive the signal of the pad PAD1. At the same time, the transmission module TX1 in the input/output circuit 100 is disabled, so that the signal of the pad PAD1 can be driven by the transmission module TX2, and the receiving module RX1 receives the signal of the pad PAD1 as the signal C1.

Please refer to FIG. 2, which shows a conventional input-output circuit 10. For example, the input-output circuit 10 can implement the input-output circuit 100 in FIG. 1, and is driven according to the signal I1 when the signal OEN1 is logic 0. The pad PAD1 is connected, and the signal of the pad PAD1 is received as the signal C1 when the signal OEN1 is logic 1. The input-output circuit 10 operates between the operating voltages VD33 and Vss, and is provided with transistors Tp0 to Tp9 (for example, p-channel MOS field-effect transistors), Tn0 to Tn7 (for example, n-channel MOS field-effect transistors), and Dp1 to Dp3 (for example, p-channel MOS field-effect transistor), Dn1 to Dn3 (for example, n-channel MOSFET), resistor R0, NAND gate ND0, inverse gate NR0, and inverters Iva and Ivb. The transistors Tp0 to Tp9 and Tn0 to Tn7 are coupled between the nodes a0 to a9.

In the input-output circuit 10, when the signal OEN1 is logic 0, the signals of the node a8 and the node a6 are the inverted signals of the signal I1; the signals of the node a6 and the node a8 are respectively transmitted to the gates of the transistors Tp1 and Tn1. The transistors Tp1 and Tn1 can drive signals on the node a0 and the pad PAD1 accordingly. For example, when the signal I1 is logic 0, the transistor Tp1 is not turned on, but the transistor Tn1 is turned on, and the voltage of the node a0 is pulled down to the operating voltage Vss, so that the signal of the logic 0 can be driven on the pad PAD1. In contrast, when the signal I1 is logic 1, the transistor Tn1 is not turned on, and the transistor Tp1 is turned on, and the signal of the node a0 is pulled up to the operating voltage VD33, so that the signal of the logic 1 can be driven on the pad PAD1.

When the signal OEN1 is logic 1, the signal of the node a8 is logic 0, and the signal of the node a6 is logic 1, respectively, so that the transistors Tp1 and Tn1 are turned off and do not conduct, and the signal of the node a0 is no longer dominant; thus, the signal of the pad PAD1 It can be driven by other circuits such as the input and output circuit 102. The signal of the pad PAD1 is transmitted to the node a2 via the nodes a0, a1 to form via the four pairs of complementary transistors of the transistors Tp0 and Tn0, the transistors Dp1 and Dn1, the transistors Dp2 and Dn2, and the transistors Dp3 and Dn3. Four inverters are received as signal C.

In some applications, when the signal OEN1 is logic 1 and the pad PAD1 is driven, the signal voltage of the pad PAD1 may exceed the operating voltage VD33 of the input-output circuit 10. For example, the operating voltage VD33 can be equal to 3.3 volts, but the voltage of the pad PAD1 can reach 5 volts. When the voltage of the pad PAD1 is higher than the operating voltage VD33, the high pad voltage may cause harmful electrical stress on the transistors input into the circuit 10 (such as the transistors Tp0 to Tp9), and also in the transistor. The drain of the Tp1 is electrically connected to the source, and the leakage from the pad PAD1 to the operating voltage VD33 is formed. In order to reduce the negative effects caused by the high pad voltage, the body poles of the transistors Tp0 to Tp9 (ie, the well poles of the n-type well) are coupled to the same node w.

When the signal OEN1 is logic 1, if the signal voltage received by the pad PAD1 is not higher than the working voltage VD33, the transistors Tp8 and Tn5 are not turned on, and the transistor Tp7 is turned on to couple the node w to the working voltage VD33, so that the node w The voltage is equal to the operating voltage VD33. Since the voltage of the pad PAD1 is not higher than the operating voltage VD33, maintaining the voltage of the node w at the operating voltage VD33 ensures that the transistor Tp1 is completely turned off, and the voltage difference between the gate, the body, the source and the drain It can be maintained within the tolerance range of the transistor.

In contrast, when the signal OEN1 is logic 1 but the signal voltage received by the pad PAD1 is higher than the operating voltage VD33, the transistor Tp8 is turned on to turn off the transistor Tp7, so the voltage of the node w is no longer controlled by the operating voltage VD33. The voltage of the node w will float, and the voltage of the pad PAD1 will rise beyond the operating voltage VD33; the transistor Tp2 will also cause the voltage of the node a7 to follow the voltage of the pad PAD1 and exceed the operating voltage VD33. In this way, the transistor Tp1 can be completely turned off without leakage, and the mutual voltage difference between the gate, the body, the source and the drain can be maintained within the tolerance range of the transistor. The high pad voltage is also transmitted from the node a0, a1 to the node a4, so that the transistor Tp3 is completely turned off, and the gate ND0 is protected. At the same time, the transistor Tp5 can be completely turned off.

In other words, the transistors Tn6, Tp6, Tp4, and Tp5 in the conventional input/output circuit 10 can function as a protection at a high pad voltage. However, when the signal OEN1 is changed from logic 0 to logic 1, the conventional input/output circuit 10 cannot be quickly switched from signal transmission to signal reception. Please refer to FIG. 3, which is a waveform sequence of the relevant signals when the conventional input/output circuit 10 switches between transmission and reception. The input/output circuit 10 can be used as the input/output circuit 100 in FIG. 1 to exchange data with the input/output circuit 102. Between time t0 and t1, signal OEN1 is logic 0, and input/output circuit 10 drives pad PAD1 to logic 1 (eg, operating voltage VD33) to transfer logic 1 to pad PAD2.

After the time point t1, the signal OEN1 is logic 1, the signal OEN2 is logic 0, and the input and output circuit 102 drives the pad PAD2 to logic 0 (for example, the operating voltage Vss), and the pad PAD1 of the input/output circuit 10 should be able to After the time point t1, it is quickly driven to a logic 0 to smoothly receive the signal transmitted from the input/output circuit 102. However, as shown in FIG. 3, the voltage of the pad PAD1 cannot be quickly changed from logic 1 to logic 0 after time t1, and is delayed until time t2 to transition to logic 0. Obviously, this delay has affected the response speed and efficiency of the data exchange; this delay is due to the circuit structure of the conventional input and output circuit 10.

Before time t1, when the conventional output-in circuit 10 transmits logic 1, the signal OEN1 is logic 0, the transistor Tn5 is turned on, the voltage of the node a5 is the operating voltage Vss, and the node a6 also makes the transistor Tp1 with the operating voltage Vss. Turn on. After the time point t1, when the signal OEN1 transitions to logic 1, the voltage of the node a6 should rise to the operating voltage VD33 to completely turn off the transistor Tp1, so that the transistor Tp1 no longer controls the voltage of the node a0. However, after the time point t1, the voltage of the node a5 affects the voltage of the node a6 via the transistors Tp4 and Tp5; if the voltage of the node a5 also rises to the operating voltage VD33, the voltage of the node a6 can completely turn off the transistor Tp1. Before the transistor Tp1 is turned off, since the turned-on transistor Tp1 tends to pull the voltage of the node a0 to the operating voltage VD33, the voltage of the node a0 is difficult to fall to the logic 0 of the operating voltage Vss due to the competition of the transistor Tp1. However, since the voltage of the node a5 is to be slowly increased from the operating voltage Vss to the operating voltage VD33 via the source and drain sharing of the transistor Tp7, the conventional input-output circuit 10 is delayed until the time point t2. In order to enable the pad PAD1 to be driven to logic 0, the logic 0 cannot be received quickly and smoothly by the pad PAD1 after the time point t1.

In order to overcome the shortcomings of the prior art, the present invention provides an input-output circuit having a preferred circuit architecture to quickly respond to the reception of data after transmission and reception alternation.

It is an object of the present invention to provide an input-output circuit comprising a gate circuit, a transmission circuit, a first switch, a second switch, a bias circuit and a receiving circuit. The gate pass circuit has a first gate end, a second gate end and a gate control end, and is selectively conductive between the first gate end and the second gate end according to the signal of the gate control terminal; The signal at the gate is associated with an input signal and a consistent signal. The transmission circuit has a first signal end, a second signal end and an output end, the first signal end and the output end are respectively coupled to the second gate end and a pad; the transmission circuit causes the signal of the output end to be associated with the first signal The signal of the terminal and the signal of the second signal end. The first switch has a first coupling end and a second coupling end, respectively coupled to an internal end and a gate control end, and selectively at the first coupling end and the second coupling end according to the enabling signal The inner end is coupled to the pad. The second switch is coupled between the second coupling end and a second operating voltage, and selectively turns the second coupling end to the second operating voltage according to the enabling signal. The bias circuit is coupled between the second coupling end, the inner end and a well terminal, and the signal of the well end is associated with the signal of the inner end and the second coupling end. The receiving circuit is coupled to the first coupling end, and provides a receiving signal according to the signal of the first coupling end.

In one embodiment, the first switch includes a first transistor and a second transistor. The first transistor has a first gate and two first channel ends, respectively coupled to the enable signal, the first coupling end and the second coupling end. The second transistor has a second gate and two second terminals, respectively coupled to the inversion signal of the enable signal, the first coupling end and the second coupling end. The first transistor and the second transistor system are a pair of complementary transistors.

In one embodiment, the second switch includes a third transistor and a fourth transistor. The third transistor has a third gate and two third channel ends; the third gate is coupled to the first operating voltage. The fourth transistor has a fourth gate and two fourth channel ends; the fourth gate is coupled to the inversion signal of the enable signal. One of the third channel ends is coupled to the second coupling end, the other of the two third channel ends is coupled to one of the two fourth channel ends, and the other of the two fourth channel ends is coupled to the second Operating Voltage.

In one embodiment, the transmission circuit includes a first driving transistor having a first gate, two first channel ends, and a first bulk, respectively coupled to the first signal terminal, the first operating voltage, The output is at the end of the well.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Referring to Figure 4, illustrated is an output-in circuit 20 in accordance with an embodiment of the present invention. For example, the input-output circuit 20 can be used to implement the input-output circuit 100 in FIG. 1; the pads PAD and the signals OEN, I, and C in the input-output circuit 20 can be used as the pads PAD1 in the input-output circuit 100, respectively. Signals OEN1, I1 and C1. When the signal OEN (enable signal) is logic 0, the input/output circuit 20 drives the signal of the pad PAD according to the signal I (which can be regarded as an input signal); when the signal OEN is logic 1, the input and output circuit enables the pad PAD to be It is driven by other circuits (such as the input and output circuits of another chip) and receives the signal of the pad PAD as the signal C (ie, a received signal).

As shown in FIG. 4, the input/output circuit 20 operates between an operating voltage VD33 (e.g., 3.3 volts) and Vss (e.g., 0 volts), and is coupled with a transmission front side circuit 22 and a reception front side circuit 36, and is provided with a gate circuit. 24. A transmission circuit 26, switches 30 and 32 (first and second switches, respectively), a bias circuit 28 and a receiving circuit 34, and includes transistors P2, N7 and a resistor R.

The transmission front side circuit 22 is provided with inverters Iv1, Iv2, a reverse gate ND and an inverse gate NR. The signal OEN is coupled to the node e9, and the inverter Iv1 is coupled between the node e9 and the anti-gate ND to invert the signal OEN. The inverse gate ND reverses the inverse signal of the signal I and the signal OEN, and provides the operation result to the node e6. Inverter Iv2 inverts signal OEN to signal OENb and provides signal OENb to node e8. The inverse gate NR reverses the signal I and the signal OEN, and outputs the operation result to the node e5. Under the operation of the transmission front side circuit 22, the signals of the nodes e6 and e5 are related to the signal I and the signal OEN; when the signal OEN is logic 0, the signals of the nodes e5 and e6 are equal to the inverted signal of the signal I. When the signal OEN is logic 1, the node e5 is maintained at the operating voltage Vss, and the node e6 is the operating voltage VD33.

The gate circuit 24 can be regarded as a first gate terminal and a second gate terminal respectively at the two ends of the nodes e6 and e7; the node e4 is a gate control terminal. The gate pass circuit 24 includes a transistor N3 (such as an n-channel MOS field-effect transistor) and an electro-optic crystal P3 (such as a p-channel gold-oxygen half-field effect transistor); the gate, source and drain of the transistor N3. The operating voltage VD33, the nodes e6 and e7 are respectively coupled, and the gate, the source, the drain and the body of the transistor P3 are respectively coupled to the nodes e4, e7, e6 and w. The transistor P3 can be selectively turned on between the nodes e6 and e7 according to the signal of the node e4. For example, when the voltage of the node e7 is higher than the voltage of the node e4 by a predetermined value (ie, the absolute value of the threshold voltage of the transistor P3), the transistor P3 is turned on.

The two ends of the nodes e7 and e5 can be regarded as a first signal end and a second signal end, respectively, and the node e0 is an output end. The transmission circuit 26 includes one (or more) transistors P1 and a set (or sets) of transistors N1 and N2 connected in series. The gate, the source, the drain and the body of the transistor P1 (for example, a p-channel gold-oxygen half-effect transistor) are respectively coupled to the node e7, the operating voltage VD33, the nodes e0 and w; the pad PAD is coupled At node e0. The gates of the transistors N1 and N2 (for example, n-channel MOS field-effect transistors) are respectively coupled to the node e5 and the operating voltage VD33, the gate of the transistor N2 is coupled to the node e0, and the source is coupled to the transistor N1. The drain of the transistor N1 is coupled to the operating voltage Vss. The transistor N2 can be used as a protection and step-down circuit to properly clamp the gate voltage of the transistor N1 so that the gate and the source of the transistor N1 do not withstand excessive electrical stress between the gate and the source. . The transistors P1 and N1 are driving transistors, which operate according to the signals of the nodes e7 and e5, respectively, so that the signal of the node e0 is associated with the signals of the nodes e5 and e7.

The resistor R is coupled between the nodes e0 and e1 and can be used as a protection circuit, such as an electrostatic discharge protection circuit; the node e1 can be regarded as an internal terminal. The gate, the drain, the source and the body of the transistor P2 (for example, a p-channel MOS field-effect transistor) are respectively coupled to the operating voltage VD33, the nodes e1, e7 and W. The gate, the drain and the source of the transistor N7 (for example, an n-channel gold-oxygen half-effect transistor) are respectively coupled to the operating voltage VD33, the node e1 and the node e2, and can be used as a step-down circuit; when the voltage of the node e1 When the operating voltage VD33 is equivalent, the transistor N7 can cause the voltage of the node e2 to be lower than the operating voltage VD33.

The switch 30 is a first coupling end and a second coupling end respectively at the two ends of the nodes e2 and e4. The node e2 is coupled to the node e1 via the transistor N7; the nodes e8 and e9 are the two switch control terminals. The switch 30 includes two transistors P6 (e.g., a p-channel MOS field effect transistor) and a transistor N6 (e.g., an n-channel MOS field effect transistor). The gate, the drain and the source of the transistor N6 (ie, the two channel ends) are respectively coupled to the enable signal OEN of the node e9, the nodes e2 and e4. The gate, the drain and the source (the two-channel end) of the transistor P6 are respectively coupled to the inverted signal OENb of the signal OEN, the nodes e4 and e2, and the body of the transistor P6 is coupled to the node w. The transistor P6 and the transistor N6 may be a pair of complementary transistors. Switch 30 is selectively conductive between nodes e2 and e4 in accordance with signal OEN. When the signal OEN is logic 1, the switch 30 turns on the node e2 to the node e4; when the signal OEN is logic 0, the node e2 does not conduct to the node e4.

The switch 32 is coupled between the node e4 and the operating voltage Vss, and includes transistors N4 and N5 (for example, two n-channel MOS field-effect transistors). The gate, the drain and the source (the two channel ends) of the transistor N4 are respectively coupled to the operating voltage VD33, the node e4 and the drain of the transistor N5. The gate and the source of the transistor N5 are respectively coupled to the signal OENb and the operating voltage Vss. Similar to transistor N2, transistor N4 can limit the gate voltage of transistor N5; transistor N5 allows switch 32 to selectively conduct node e4 to operating voltage Vss in accordance with signal OEN. When the signal OEN is logic 0, the transistor N5 is turned on, so that the voltage of the node e4 is equivalent to the operating voltage Vss. When the signal OEN is logic 1, the transistor N5 is not turned on, and the voltage of the node e4 does not depend on the operating voltage Vss.

The bias circuit 28 is coupled between the nodes e4, e1 and w, and includes transistors P7 and P8 (for example, two p-channel MOS field-effect transistors), and the node w is a well terminal. The gate, the source, the drain and the body of the transistor P8 are respectively coupled to the operating voltage VD33, the nodes e1, e4 and w; the gate and the source of the transistor P7 are respectively coupled to the node e4 and the operating voltage VD33, the body pole Coupling with the bungee is at node w. Bias circuit 28 can correlate the signal (voltage magnitude) of node w to the signals of nodes e1 and e4.

The receiving circuit 34 is coupled between the nodes e2 and e3, and includes two transistors P9, P0 (for example, a pair of p-channel MOS field-effect transistors) and a transistor N0 (such as an n-channel MOS field-effect transistor). The gate of the transistor P9 is coupled to the node e1, the body and the source are coupled to the operating voltage VD33, and the drain is coupled to the source of the transistor P0. The gate, the drain and the body of the transistor P0 are coupled to the nodes e2 and e3 and the operating voltage VD33, respectively. The gate, the drain and the source of the transistor N0 are coupled to the nodes e2 and e3 and the operating voltage Vss, respectively.

The receiving front side circuit 36 may include three transistors U1p, U2p and U3p (for example, three p-channel gold oxide half field effect transistors), and three other transistors U1n, U2n and U3n (for example, three n-channel gold oxide half-field effects). The transistor) forms three inverters connected in series. The source and the body of the transistors U1p to U3p are both coupled to the operating voltage VD33; the sources of the transistors U1n to U3n are all coupled to the operating voltage Vss. The receiving circuit 34 can receive the signal of the node e2 as the signal of the node e3, and the receiving front side circuit 36 further receives the signal of the node e3 as the signal C.

In FIG. 4, the body poles (not shown) of the transistors N0 to N7, U1n to U3n are all coupled to the operating voltage Vss.

The operation of the input/output circuit 20 of the present invention can be described as follows. When the signal OEN is logic 0, the signal OENb is logic 1, the signals of the nodes e5 and e6 are the inverted signals of the signal I, and the transistors N6 and P6 of the switch 30 are turned off and non-conducting. The transistors N4 and N5 in the switch 32 are both turned on, so the voltage of the node e4 is controlled by the voltage of the node 32 by the switch 32, which is equivalent to the operating voltage Vss. The low voltage of the node e4 turns on the transistor P7, maintaining the voltage of the node w at the operating voltage VD33; the transistor P8 is not conducting. The low voltage of node e4 also turns on transistor P3, so that the signal of node e6 can be transmitted to node e7. Thus, the transistors P1 and N1 in the transmission circuit 26 can transmit the signal I according to the signal of the driver pad PAD according to the signal I. For example, if the signal I is logic 0, the transistor P1 is turned off, the transistor N1 is turned on, and the signal of the node e0 is pulled down to the operating voltage Vss to transfer the logic 0. In contrast, if the signal I is logic 1, the transistor N1 is turned off, and the transistor P1 is turned on, and the signal of the node e0 is pulled up to the operating voltage VD33 to transfer the logic 1. Furthermore, the transistor P2 is also not turned on.

When the signal OEN is logic 1, the input-output circuit 20 causes the signal of the pad PAD to be driven by other circuits (such as another output of another chip into the circuit, not shown). Since the signal OEN is logic 1, the transistor N5 of the switch 32 is not turned on, the switch 32 no longer controls the voltage of the node e4; the transistors P6 and N6 of the switch 30 are both turned on, the node e2 is turned on to the node e4, and the transistor N7 is turned on. The node e1 is turned on to the node e2. If the signal of the pad PAD is not higher than the working voltage VD33, the transistor N7 causes the voltage of the node e2 to be lower than the operating voltage VD33, and the transistor P7 is maintained to be turned on via the node e4 to maintain the voltage of the node W at the operating voltage VD33; Crystal P8 is turned off. The receiving circuit 34 controls the voltage of the node e3 according to the voltage of the node e2, so that the signal of the pad PAD can be received as the signal C of the front side receiving circuit 36 via the nodes e0, e1, e2 and e3. For example, if the pad PAD is driven to logic 0, the transistor N0 in the receiving circuit 34 is turned off, and the transistors P9 and P0 are both turned on, and the voltage of the node e3 is pulled up to the operating voltage VD33 in reverse. If the voltage of the pad PAD is driven to the operating voltage VD33, the transistor N0 is turned on, and the voltage of the node e3 is inverted to the operating voltage Vss.

If the voltage of the pad PAD is driven beyond the operating voltage VD33, the transistor P8 will be turned on between the nodes e1 and e4, and the transistor P7 will be turned off, so that the voltage of the node w is no longer controlled by the operating voltage VD33; the voltage of the node w The voltage of the pad PAD can be floated to exceed the operating voltage VD33. The transistor P2 turns on the node e1 to the node e7, so the transistor P1 can be completely turned off; the gate and drain voltages of the transistor P1 both exceed the operating voltage VD33, but the voltage of the node w also exceeds the operating voltage. VD33, so the voltage difference between the gate, source, drain and body of transistor P1 can be maintained within the tolerance range of the transistor. The transistor P3 is also completely turned off by the voltage of the node e4 to protect the anti-gate ND from the high pad voltage. In other words, when the voltage of the pad PAD exceeds the operating voltage VD33, the input/output circuit 20 of the present invention can reduce the influence of the high pad voltage, so that the transistors are protected from excessively high electrical stress.

In the conventional input-output circuit 10 of FIG. 2, the node a6 of the control transistor Tp1 is coupled to the node a5 via the transistors Tp4 and Tp5, and the node a5 is insulated from the pad PAD1 by the closing of the transistor Tp8. . Therefore, when the conventional input/output circuit 10 switches the receiving logic 0 after transmitting the logic 1, the voltage of the node a5 can only slowly change depending on the charge sharing, and affects the voltage transition speed of the node a6, so that the conventional output is input into the circuit 10. It is not possible to receive logic 0 quickly, as shown in Figure 3.

In contrast, when the input/output circuit 20 of the present invention switches the reception logic 0 after transmitting the logic 1, since the node e6 of the control transistor P1 is insulated from the node e4 of the bias circuit 28, Therefore, the voltage of the node e6 can independently respond to the change of the signal OEN. Moreover, when the logic 0 is received by the pad PAD, the voltage of the pad PAD can be transmitted to the node e4 via the nodes e0, e1, e2 and the switch 30, and the transistor P3 can be quickly turned on, and the voltage of the node e6 can be It is quickly transferred to node e7 to turn off transistor P1, allowing pad PAD to be driven quickly to a low level logic zero.

Please refer to FIG. 5, which is a waveform sequence of the relevant signals when the input/output circuit 20 of the present invention switches between transmission and reception. The input/output circuit 20 is used to implement the input/output circuit 100 in FIG. 1 to exchange data with the input/output circuit 102. The signals OEN, I, C and the pad PAD of the input/output circuit 20 are signals input to the circuit 100, respectively. OEN1, I1, C1 and pad PAD1.

As shown in FIG. 5, between time t0 and t1, signal OEN is logic 0, and input/output circuit 20 drives pad PAD to logic 1 to transfer logic 1 to input and output circuit 102 of pad PAD2. After the time t1, the signal OEN is logic 1, the signal OEN2 is logic 0, and the input and output circuit 102 drives the pad PAD2 to logic 0, and the pad PAD of the output circuit 20 of the present invention can be quickly responded and driven. To logic 0, a logic 0 is quickly received by the output-in circuit 102.

In summary, compared with the prior art, the present invention not only protects the transistors in the input and output circuits from high-pad voltage, but also improves the response speed of the pad signals during transmission and reception switching, thereby improving the data. The effectiveness of the exchange.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10, 20, 100-102. . . Output circuit

12. . . Traces

twenty two. . . Transmission front side circuit

twenty four. . . Gate circuit

26. . . Transmission circuit

28. . . Bias circuit

30, 32. . . switch

34. . . Receiving circuit

36. . . Receiving front side circuit

Tx1-Tx2. . . Transmission module

Rx1-Rx2. . . Receiving module

Tp0-Tp9, Tn0-Tn7, P0-P3, P6-P9, N0-N7, Dp1-Dp3, Dn1-Dn3, U1p-U3p, U1n-U3n. . . Transistor

R0, R. . . resistance

A0-a9, e0-e9, w. . . node

VD33, Vss. . . Operating Voltage

I, OEN, C, I1-I2, OEN1-OEN2, C1-C2, OENb. . . Signal

PAD1-PAD2, PAD. . . Pad

ND0, ND. . . Reverse gate

NR0, NR. . . Reverse or gate

Iva-Ivb, Iv1-Iv2. . . inverter

T0-t2. . . Time

Figure 1 is a schematic diagram of data exchange between different input and output circuits.

Figure 2 illustrates a conventional output-in circuit.

Fig. 3 is a diagram showing the response of the input/output circuit at the time of transmission and reception switching in the waveform timing of the correlation signal.

Figure 4 illustrates an input-output circuit in accordance with an embodiment of the present invention.

Fig. 5 is a diagram showing the response of the output/output circuit at the time of transmission and reception switching with the waveform timing of the relevant signal.

20. . . Output circuit

twenty two. . . Transmission front side circuit

twenty four. . . Gate circuit

26. . . Transmission circuit

28. . . Bias circuit

30, 32. . . switch

34. . . Receiving circuit

36. . . Receiving front side circuit

P0-P3, P6-P9, N0-N7, U1p-U3p, U1n-U3n. . . Transistor

R. . . resistance

E0-e9, w. . . node

VD33, Vss. . . Operating Voltage

I, OEN, C, OENb. . . Signal

PAD. . . Pad

ND. . . Reverse gate

NR. . . Reverse or gate

Iv1-Iv2. . . inverter

Claims (8)

An input-in circuit includes: a gate-connecting circuit having a first gate-passing terminal, a second gate-passing terminal and a gate-passing control terminal, and selectively selecting the signal according to the gate-passing control terminal at the first gate-passing end The signal is connected to the second gate; the signal of the first gate is associated with an input signal and a uniform signal; a transmission circuit has a first signal end and an output end coupled to the second gate respectively And a first switch having a first coupling end and a second coupling end respectively coupled to an inner end and a first switch; and a first switch having a signal coupled to the signal at the first signal end; The gate is controlled to be electrically connected between the first coupling end and the second coupling end according to the enabling signal; wherein the internal end is coupled to the pad. The input/output circuit of claim 1, wherein the first switch comprises: a first transistor having a first gate and two first channel ends, respectively coupled to the enable signal, a first coupling end and the second coupling end; and a second transistor having a second gate and two second channel ends respectively coupled to the inversion signal of the enable signal, the first coupling The second transistor and the second coupling end; wherein the first transistor and the second transistor system are complementary to each other. The input/output circuit of claim 1, further comprising: a second switch coupled between the second coupling end and a second operating voltage, selectively selecting the second switching voltage according to the enabling signal The second coupling end is electrically connected to the second working voltage. The input/output circuit of claim 3, wherein the second switch comprises: a first transistor having a first gate and two first channel ends; the first gate coupled to the first An operating voltage; and a second transistor having a second gate and two second channel ends; the second gate is coupled to the inversion signal of the enable signal; wherein the two first channel ends are One of the two first channel ends is coupled to one of the two second channel ends, and the other of the two second channel ends is coupled to the second operation. Voltage. The input/output circuit of claim 1, further comprising a bias circuit coupled between the second coupling end, the inner end and a well terminal, so that the signal of the well extreme is associated with a signal of the first end and the second coupling end; and the transmission circuit includes: a first driving transistor having a first gate, two first channel ends and a first body, respectively coupled to the first The signal terminal, a first operating voltage, the output terminal and the well terminal. The input/output circuit of claim 1, wherein the transmission circuit further has a second signal end, and the signal of the output end is associated with the signal of the first signal end and the second signal end. The input/output circuit of claim 1, further comprising: a receiving circuit coupled to the first coupling end, and providing a receiving signal according to the signal of the first coupling end. The input/output circuit of claim 1, wherein the first switch comprises a switch control end coupled to the enable signal or the inversion signal of the enable signal.