JP2007071702A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which separates and connects output buffer and pads for output in arbitrary operation timing while maintaining a normal mode. <P>SOLUTION: The pad itself for output to be cut is simultaneously used as control terminal of separation or connection. By giving negative pulse potential lower than the negative potential of a power line to the pad for output, the output pad is controlled for separation or connection. The control circuit used in the control makes control for not varying separation or connection state when the potential of the pad for output is the potential between the positive power line and the negative power line. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a setting function for setting the semiconductor integrated circuit to a desired mode when testing the semiconductor integrated circuit.

  In recent years, with the increase in operating frequency of semiconductor integrated circuits, reduction in current consumption has become a common requirement as a design requirement for semiconductor integrated circuits. Under such circumstances, the configuration and method for accurately grasping the current consumption of the semiconductor integrated circuit are attracting particular attention.

  When conducting an accurate operation current consumption test of a semiconductor integrated circuit, a test device inputs a signal from the outside to a specific input terminal of the semiconductor integrated circuit, and simulates the same state as when the semiconductor integrated circuit is operating In addition, a method is known in which the current flowing between the power supplies of the semiconductor integrated circuit is measured for a certain period while the operation of the semiconductor integrated circuit is continued in a pseudo manner.

  However, when a test is performed with the test device connected to the output terminal of the semiconductor integrated circuit, the semiconductor integrated circuit is apparently loaded with a capacity due to the load capacity of the test device itself. There is a problem that the correct operating current consumption of the semiconductor integrated circuit itself cannot be measured.

  In order to solve such a problem, many proposals are seen. A technique for separating the output terminal of the semiconductor integrated circuit from the test apparatus at the time of the test by the test apparatus is known (for example, Patent Document 1). reference.).

The prior art disclosed in Patent Document 1 separates the output buffer circuit mounted on the semiconductor integrated circuit and the pad serving as the output terminal, thereby eliminating the influence of the load capacity of the connected test apparatus. is there.
In other words, a switching means is provided between the output buffer circuit and the pad serving as the output terminal, and the output buffer circuit and the pad are separated when the semiconductor integrated circuit is tested by controlling the switching means.

  This will be described in detail with reference to the drawings. FIG. 3 is a diagram for explaining the prior art semiconductor integrated circuit disclosed in Patent Document 1, which has been rewritten to the extent that it does not depart from its gist. 3, 100 is an output buffer, 20 is a test pad, 30 is a P-channel MIS transistor, 5 is an output pad, 60 is an N-channel MIS transistor, 70 is a control signal line, 80 is a latch circuit, 90 is Test signal line.

Between the output buffer 100 and the output pad 5, there is a P-channel MIS transistor 30 that functions as a switch for connecting and separating between them. Between the output pad 5 and the latch circuit 80, there is an N-channel MIS transistor 60 that functions as a switch for connecting and separating between the output pad 5 and the latch circuit 80.
The gate of the N-channel MIS transistor 60 is connected to the test signal line 90. The latch circuit 80 is a latch for storing control information for ON / OFF control of the P-channel MIS transistor 30, and the latch circuit 80 and the P-channel MIS transistor 30 are connected by a control signal line 70. .

Next, the operation of the prior art disclosed in Patent Document 1 will be described. First, a case where a predetermined signal is input from a test apparatus to test a semiconductor integrated circuit will be described. This state is called a test mode.
First, a high level signal is input to the test pad 20, and the N-channel MIS transistor 60 is turned on by transmitting a high level signal via the test signal line 90. As a result, the output pad 5 and the input of the latch circuit 80 are connected.
Next, a high level signal is input to the output pad 5. At this time, in order to prevent a collision between a signal input from the output pad 5 and an output signal of the output buffer 100, the output buffer 100 is set to a normal state for outputting a high impedance state or a high level signal. As a result, a high level is stored in the latch circuit 80, and the P-channel MIS transistor 30 is turned off. At this time, the P-channel MIS transistor 30 is a low active circuit.

  Next, the test pad 20 is shifted to the low level. The N-channel MIS transistor 60 is turned off when a low-level signal is transmitted through the test signal line 90. As a result, the latch circuit 80 is separated from the output pad 5 while maintaining the high level, and the P-channel MIS transistor 30 is maintained off and the output buffer 100 and the output pad 5 are separated. .

  Thus, in order to test the semiconductor integrated circuit after separating the output buffer 100 and the output pad 5, a desired signal is input from a test device to an input pad (not shown) and the output buffer 100 is operated. The current consumption is measured. By doing so, an unnecessary capacity or the like is not connected to the output pad 5, so that an accurate current consumption can be achieved.

Next, a case where the semiconductor integrated circuit disclosed in Patent Document 1 is normally operated will be described. This state is referred to as a normal mode for convenience.
First, the output buffer 100 and the output pad 5 are connected. A high level signal is input to the test pad 20. The N-channel MIS transistor 60 is turned on when a high level signal is transmitted through the test signal line 90. As a result, the output pad 5 and the input of the latch circuit 80 are connected.
Next, a low level signal is input to the output pad 5. At this time, in order to prevent a collision between the low level signal input from the output pad 5 and the output signal of the output buffer 100, the output buffer 100 is set to a high impedance state or a state of outputting a low level signal. As a result, the low level is stored in the latch circuit 80, and the P-channel MIS transistor 30 is turned on.

  Next, by causing the test pad 20 to transition to the low level, the test signal line 90 is set to the low level, the N-channel MIS transistor 60 is turned off, and the latch circuit 80 maintains the low level in the output pad. 5, the P-channel MIS transistor 30 is maintained in an ON state, and the output buffer 100 and the output pad 5 are connected.

  In this way, after connecting the output buffer 100 and the output pad 5, a normal output signal in the normal mode is transmitted to the output pad 5.

Japanese Patent Laid-Open No. 10-73639 (page 3, FIG. 1)

However, the prior art disclosed in Patent Document 1 has an output buffer 100 and an output pad 5.
It is necessary to always fix the output state of the output buffer 100 to a specific state at the time of disconnection and connection transition, that is, it is necessary to interrupt or stop the operation of the semiconductor integrated circuit in the normal mode and enter the test mode. was there.
In conducting a current consumption test during operation of a semiconductor integrated circuit, after interrupting or stopping the operation of the semiconductor integrated circuit, wait until the target operation timing to be tested, and then start a current consumption test during operation. Was a factor that hindered shortening of measurement time.

  The prior art disclosed in Patent Document 1 always fixes the output state of the output buffer 100 to a high level, low level, or high impedance state when the output buffer 100 and the output pad 5 are separated or the connection is shifted. Therefore, a control circuit for fixing the output state of the output buffer 100 is necessary. Providing a control circuit necessary only for testing the semiconductor integrated circuit on the semiconductor integrated circuit has been a factor that hinders miniaturization.

  Therefore, an object of the present invention is to input a signal from a test device only to an output pad connected to an output buffer to be separated or connected, so that the output buffer and the output pad can be connected at any operation timing while maintaining the normal mode. A semiconductor integrated circuit that can be separated or connected is provided.

  In order to solve the above-described problems, the semiconductor integrated circuit of the present invention employs the following configuration.

  A separation means between the internal circuit and the pad; and a control means for controlling the separation means. The control means changes the separation means according to the presence or absence of a negative pulse signal larger than the negative power supply voltage input from the outside to the pad. It is characterized by controlling.

The control means includes a diode, a MIS transistor, a resistor, and a latch circuit.
Connect the cathode terminal of the diode to the pad, connect the anode terminal of the diode to the power supply line that supplies the negative power supply potential,
In the MIS transistor, a source terminal and a bulk terminal are connected to a pad, a gate terminal is connected to a power supply line that supplies a negative power supply potential, a drain terminal is connected to one terminal of a resistor and an input of a latch circuit. The other terminal of the resistor is connected to a power supply line for supplying a positive power supply potential, and the output of the latch circuit is connected to a disconnecting means.

  The control means switches between a positive power supply potential and a negative power supply potential according to the presence or absence of a negative pulse signal, and outputs the switching power.

By applying the configuration of the semiconductor integrated circuit of the present invention, the connection and separation between the output buffer and the output pad can be performed continuously from the normal mode without going through the test mode. It is possible to measure an accurate operating current consumption in a short time directly from the timing.
Further, the semiconductor integrated circuit of the present invention does not require a particularly complicated control circuit for its control. For this reason, miniaturization of the semiconductor integrated circuit itself is not hindered.

[Description of overall configuration: Fig. 1]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of a semiconductor integrated circuit according to the present invention. In FIG. 1, 1 is an output buffer, 3 is a transmission gate (hereinafter referred to as TG), 5 is an output pad, 6 is an N-channel MIS transistor, 7 is a control signal line, 8 is a latch circuit, and 9 is a clock signal. Lines 10, 10 are diodes, 12 are resistors, 13 is a positive power supply line (hereinafter referred to as VDD), and 14 is a negative power supply line (hereinafter referred to as VSS).
The potential of VDD13 is at the GND level. The potential of the VSS 14 is a negative potential level such as −1.5V or −3.0V, for example. The semiconductor integrated circuit of the present invention operates with a potential difference between the potential of VDD13 and the potential of VSS14.

  The semiconductor integrated circuit of the present invention applies the negative potential VIN lower than the potential level of VSS 14 from the test device to the output pad 5, so that the output buffer 1, the output pad 5, Can be separated or connected. Test devices generally have a function called a driver that generates pulses having an arbitrary width and arbitrary amplitude at arbitrary timings as set by the measurer. By utilizing this driver function, VIN is used. Is generated.

The TG 3 is a disconnecting unit that connects or separates the output pad 5 and the output buffer 1 that is an internal circuit.
The N channel MIS transistor 6, the latch circuit 8, the diode 10, and the resistor 12 constitute a control means.

  Between the output buffer 1 and the output pad 5, there is a TG 3 that functions as a switch for connecting and separating between them. Between the output pad 5 and the VSS 14, a diode 10 is provided as a TG3 disconnection control means. The diode 10 has a cathode terminal connected to the output terminal 5 and an anode terminal connected to the VSS 14. Similarly, an N-channel MIS transistor 6 and a resistor 12 are connected in series between the output pad 5 and the VDD 13 as a TG3 disconnection control means.

  The source terminal and bulk terminal of the N-channel MIS transistor 6 are connected to the output pad 5, the drain terminal is connected to one terminal of the resistor 12, and the gate terminal is connected to the VSS 14. The other terminal of the resistor 12 is connected to the VDD 13.

  Similarly, a latch circuit 8 is provided as a TG3 disconnection control means. The input of the latch circuit 8 is connected to the intersection of the N-channel MIS transistor 6 and the resistor 12 by the clock signal line 9, and the output is connected to the control signal input of the TG 3 by the control signal line 7.

  TG3 is a high active circuit that is turned on when the control signal of the control signal 7 is at a high level (VDD13 potential) and turned off when the control signal 7 is at a low level (VSS14 potential). The latch circuit 8 uses a toggle flip-flop. At this time, it is assumed that the latch circuit 8 inverts the output state by the falling control signal.

The diode 10 includes a plurality of conductive regions selectively provided on a semiconductor substrate, and is configured by joining conductive regions having different conductivity types.
When the potential difference between the anode terminal, which is the other terminal, and the anode terminal, which is the other terminal, is greater than a predetermined potential difference (hereinafter referred to as VF), the diode 10 is electrically connected between the cathode terminal and the anode terminal. This is generally called forward connection.
Contrary to the forward connection, when the anode terminal has a potential lower than VF with respect to the cathode terminal, the cathode terminal and the anode terminal are insulated. This is called reverse connection. Such electrical characteristics are general.

The resistor 12 is composed of a resistance element formed on a semiconductor substrate. Although not particularly limited, for example, a diffused resistor formed by selectively forming a conductive region on a semiconductor substrate, a polysilicon resistor provided on the semiconductor substrate, or the like.

  Next, the operation in each potential state of the output pad 5 of the semiconductor integrated circuit of the present invention will be described.

First, the operation when the potential of the output pad 5 is VDD 13 will be described.
When the potential of the output pad 5 is VDD13, the cathode terminal of the diode 10 is connected to the output pad 5, so that the potential of the diode 13 is VDD13. Since the anode terminal of the diode 10 is connected to the VSS 14, the anode terminal has a potential lower than VF with respect to the cathode terminal. That is, the diode 10 is connected in the reverse direction and both ends of the diode 10 are insulated.
Further, since the gate terminal of the N-channel MIS transistor 6 is connected to the anode terminal of the diode 10 and the VSS 14, the potential of the VSS 14 is applied to the gate terminal due to the insulation of the diode 10. On the other hand, since the source terminal and the bulk terminal are connected to the output pad 5, the potential of VDD13 is applied. For this reason, the potential of the gate terminal with respect to the source terminal and the bulk terminal is reverse biased and turned off.

The clock signal line 9 of the latch circuit 8 is connected to the intersection of the N-channel MIS transistor 6 and the resistor 12 connected in series between the output pad 5 and the VDD 13, and the N-channel MIS transistor 6 is connected to the latch circuit 8. Since it is turned off, the potential of VDD 13 is transmitted through the resistor 12.
As a result, since the input of the latch circuit 8 becomes the potential of VDD13, the control signal line 7 of TG3 which is also the output signal of the latch circuit 8 maintains the immediately preceding state.
Since the state of the control signal line 7 does not change, the on / off state of the TG 3 does not change, and the state of separation or connection between the output buffer 1 and the output pad 5 does not change.
That is, the state of TG3 does not change at the potential (high level) of VDD13 which is one of the two potentials that are formed inside the semiconductor integrated circuit and output from the output buffer 1.

Next, the operation when the potential of the output pad 5 is VSS 14 will be described.
When the potential of the output pad 5 is VSS 14, the cathode terminal of the diode 10 is connected to the output pad 5, and thus becomes the potential of VSS 14. Since the anode terminal of the diode 10 is connected to the VSS 14, the diode 10 is reversely connected and both ends of the diode 10 are insulated.
Further, since the gate terminal of the N-channel MIS transistor 6 is connected to the anode terminal of the diode 10 and the VSS 14, only the potential of the VSS 14 is applied to the gate terminal due to the insulation of the diode 10, and the source terminal and Since the bulk terminal is connected to the output pad 5, the potential of VSS14 is applied. For this reason, there is no potential of the gate terminal with respect to the source terminal and the bulk terminal, and it is turned off.

  As described above, the N-channel MIS transistor 6 is in the same state as when the potential of the output pad 5 is VDD 13, so that the two potentials output from the output buffer 1 by the semiconductor integrated circuit are internally formed. At one VSS 14 potential (low level), the state of TG3 does not change.

  As is apparent from the above description, the state of TG 3 does not change at any potential that is internally formed by the semiconductor integrated circuit and output from the output buffer 1, that is, the connection between the output buffer 1 and the output pad 5. The state does not change.

Next, the operation when the potential of the output pad 5 transits from VDD13 or VSS14 to the negative potential VIN lower than the potential of VSS14 will be described.
When a negative potential VIN from the potential of VSS14 is applied to the output pad 5 by a test device (not shown) and the potential difference between the potential of VSS14 and VIN is larger than VF, the cathode terminal of the diode 10 is connected to the output pad 5 Therefore, the potential becomes VIN. At this time, since the anode terminal is connected to VSS 14, a potential difference of VF is generated with respect to the cathode terminal.

  Since the gate terminal of the N-channel MIS transistor 6 is connected to the anode terminal of the diode 10 and the VSS 14, VSS is applied to the gate terminal, and the source terminal and the bulk terminal are connected to the output pad 5. Therefore, the potential is more negative than the potential of VSS. As a result, the N-channel MIS transistor 6 is turned on by generating a potential VF between the source terminal, the bulk terminal, and the gate terminal.

  When the N-channel MIS transistor 6 is turned on, the output pad 5 and the VDD 13 are conducted through the resistor 12, and is a connection point between the source terminal of the N-channel MIS transistor 6 and one terminal of the resistor 12. The potential of the clock signal line 9 is the same as the potential of VDD 13 and the potential of VIN applied to the output pad 5 when the N-channel MIS transistor 6 is turned on (hereinafter referred to as a conduction resistance between the source terminal and the drain terminal). This is a value divided by the resistance of the resistor 12 and the resistance of the resistor 12.

When the on-resistance of the N-channel MIS transistor 6 is sufficiently smaller than the resistance of the resistor 12, the potential of the clock signal line 9 is sufficiently lower than the potential of VDD13.
When the input of the latch circuit 8 is sufficiently lower than the potential of VDD13, the falling signal is input to the latch circuit 8, and the control signal line 7 for transmitting the control signal of TG3 which is also the output of the latch circuit 8 Invert from state.
When the control signal of TG3 is inverted, the state of TG3 is also inverted, so that the state of separation or connection between the output buffer 1 and the output pad 5 is switched.

[Description of Operation: FIG. 2]
Next, the operation of the semiconductor integrated circuit of the present invention will be described with reference to FIG. FIG. 2 is a time chart for explaining the operation of the semiconductor integrated circuit of the present invention.
In FIG. 2, a signal a is an output signal of the output buffer 1 formed inside the semiconductor integrated circuit. The signal b is a pulse signal input to the output pad 5 from a test device (not shown). The signal c is a signal of the clock signal line 9 that is an input signal of the latch circuit 8. The signal d is a signal from the output pad 5. The signal e is a signal on the control signal line 7 which is a control signal for the TG 3 and an output signal for the latch circuit 8.

  The three broken lines drawn in the horizontal direction of each signal shown in FIG. 2 indicate the potential level. The uppermost part of the broken line is the potential level of VDD13 and is expressed as VDD. The middle level is the potential level of VSS14 and is expressed as VSS. The lower level is the potential level of VIN of a negative pulse lower than the potential level of VSS 14 input to the output pad 5 from a test device (not shown), and is expressed as VIN.

The solid line of each signal shown in FIG. 2 is a fixed voltage level. The solid line between the potential level of VDD 13 and the potential level of VSS 14 shown in the signals b and d indicates a floating level without a specific voltage level.
Further, the solid line between the potential level of VSS 14 of signal c and VIN which is a negative potential level from VSS 14 indicates the potential level of output pad 5 and the potential level of VDD 13 with N-channel MIS transistor 6 and resistor 12. Is the potential level divided by.

The lowest part of the time chart shown in FIG. 2 shows a section between the on-control state and off-control state of TG3. As shown by the signal b, every time a negative pulse signal lower than the potential of the VSS 14 is input to the output pad 5, the control signal line 7 which is a control signal of TG3 is inverted, and TG3 is turned off or on.

Next, transition of separation or connection between the output buffer 1 and the output pad 5 will be described with reference to FIG. It is assumed that the signal e of the control signal line 7, which is a control signal of TG3, is initially at a high level (VDD13 potential).
At this time, the state of TG3 is ON, and the output buffer 1 and the output pad 5 are connected.
The signal b input to the output pad 5 from a test device (not shown) is floating. At this time, the signal c of the clock signal line 9 which is a control signal of the latch circuit 8 is the potential of VDD13.
Since the signal c is at the potential of VDD13, the signal e, which is the control signal of TG3, maintains the initial high level.
Since the output buffer 1 and the output pad 5 are connected and the signal b is floating, the signal a which is the output signal of the output buffer 1 formed inside the semiconductor integrated circuit is transmitted to the signal d of the output pad 5. .

  Next, a case where a signal b, which is a pulse signal of the potential VIN, is applied to the output pad 5 from a test device (not shown) at timing 1 in the drawing will be described.

The input from the test device (not shown) to the output pad 5 is assumed to be in a floating state after applying the signal b which is a pulse signal of the potential VIN.
At timing 1, the signal d of the output pad 5 is pulled to the potential VIN which is an input signal from a test device (not shown).
The signal c of the clock signal line 9 that is a control signal of the latch circuit 8 becomes a negative potential from the potential of the VSS 14.
Since the signal c is more negative than the potential of the VSS 14, the signal e, which is the control signal of the TG3, is inverted from the initial high level and becomes the low level (the potential of the VSS 14). As a result, the state of TG3 is also reversed from on to off.

  At this time, the output pad 5 is disconnected from the output buffer 1, and the signal b of the output pad 5 has no potential to be transmitted and becomes floating. Similarly, the signal c of the clock signal line 9 which is a control signal of the latch circuit 8 is pulled to a high level by the resistor 12 and fixed because the signal b becomes floating. As a result, the signal e, which is the control signal for TG3, also maintains the low level, and the state of TG3 also remains off.

  Further, a case where a signal b that is a pulse signal having a negative potential VIN from the potential of VSS 14 is applied to the output pad 5 from a test device (not shown) at timing 2 in the drawing will be described.

The input from the test device (not shown) to the output pad 5 is assumed to be in a floating state after applying the signal b which is a pulse signal of the potential VIN.
At timing 1, the signal d of the output pad 5 is pulled to the potential VIN which is an input signal from a test device (not shown).
The signal c of the clock signal line 9 that is a control signal of the latch circuit 8 becomes a negative potential from the potential of the VSS 14.
Since the signal c is more negative than the potential of the VSS 14, the signal e which is a control signal of the TG3 is inverted from the low level and becomes the high level. As a result, the state of TG3 is also reversed from off to on. At this time, the output pad 5 is connected to the output buffer 1.

  The signal c of the clock signal line 9 that is a control signal of the latch circuit 8 is pulled to a high level by the resistor 12 and fixed because the signal b becomes floating after timing 2. As a result, the signal e, which is the control signal for TG3, also maintains a high level, and the state of TG3 also remains on. Therefore, since the output buffer 1 and the output pad 5 are connected and the signal b is floating, the signal a which is the output signal of the output buffer 1 formed inside the semiconductor integrated circuit is the signal d of the output pad. To communicate.

As is apparent from the above description, the semiconductor integrated circuit according to the present invention only applies a negative potential lower than the negative power supply potential to the output pad without setting the semiconductor integrated circuit to a special mode such as a test mode. The output buffer and the output pad can be separated or connected at any timing in the normal mode.
With such a configuration, the current consumption can be accurately measured by eliminating the influence of the load capacity of the measuring device connected to the output pad by using the test device. Moreover, since the measurement can be continuously performed without changing the mode from the normal mode, the time required for the measurement of the current consumption can be greatly shortened. As a result, the lead time at the time of testing the semiconductor integrated circuit using the test apparatus can be shortened, which has the effect of reducing the cost of the semiconductor integrated circuit.

  Since the semiconductor integrated circuit of the present invention does not require a large additional circuit for current consumption measurement, the chip size is not unnecessarily increased. Therefore, it can be used for highly integrated semiconductor integrated circuits.

It is a circuit diagram which shows the structure of the semiconductor integrated circuit of this invention. 3 is a time chart for explaining the operation of the semiconductor integrated circuit of the present invention. It is a circuit diagram which shows the structure of the semiconductor integrated circuit in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Output buffer 3 Transmission gate 5 Output pad 6 N channel MIS type transistor 7 Control signal 8 Latch circuit 9 Clock signal line 10 Diode 12 Resistor 13 VDD
14 VSS

Claims (3)

  A separation means between the internal circuit and the pad; and a control means for controlling the separation means, the control means depending on the presence or absence of a negative pulse signal greater than the negative power supply voltage input from the outside to the pad A semiconductor integrated circuit characterized by controlling said separating means. The control means includes a diode, a MIS transistor, a resistor, and a latch circuit,
The cathode terminal of the diode is connected to the pad, the anode terminal of the diode is connected to a power supply line that supplies a negative power supply potential,
The MIS transistor has a source terminal and a bulk terminal connected to the pad, a gate terminal connected to a power supply line for supplying the negative power supply potential, and a drain terminal connected to one terminal of the resistor. Connected to the input of the latch circuit, the other terminal of the resistor is connected to a power supply line for supplying a positive power supply potential;
2. The semiconductor integrated circuit according to claim 1, wherein the output of the latch circuit is connected to the disconnecting means.   3. The semiconductor integrated circuit according to claim 1, wherein the control means switches between a positive power supply potential and a negative power supply potential according to the presence or absence of the negative pulse signal.

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