TW201344868A - Area efficient through-hole connections - Google Patents

Abstract

Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.

Description

High area efficiency electronic component and manufacturing method thereof

The present invention relates to a method and structure for reducing the area of a semiconductor element, and more particularly to a method and structure for using a via connection to improve the area efficiency of a semiconductor element.

Semiconductor electronic diodes are commonly used in rectifier circuits or electrostatic discharge (ESD) protection circuits. According to the definition used in this patent application, an "electronic diode" is a two-terminal rectifying semiconductor component for a rectifying circuit or an electrostatic discharge (ESD) protection circuit. Examples of electron diodes include PN junction diodes, Schottky diodes, or breakdown diodes such as transient voltage suppression (TVS) electron diodes, sag diodes, Zener diodes . Optoelectronic semiconductor components, such as solar cells, optical or infrared sensors, optical semiconductor components such as light-emitting diodes (LEDs), are not part of the electronic diodes defined in this patent application because their primary function is optical performance, not electronics. Figure 1 (a) shows a schematic symbol of a PN junction diode or a Schottky diode. Figure 1(b) shows a schematic symbol of a collapsed diode. One of the methods of making a breakdown diode is to increase the doping concentration of the interface diode. Another common method is to connect an electronic triode (BJ) as shown in Figure 1 (f). Sometimes a resistor (Rbe) is connected to the diode of the triode (BJ) as shown in Figure 1(g). Due to the feedback mechanism of the triode, the components in Figure 1 (f, g) can be equivalent functional circuits of the crash diode. This patent application will use the symbols of Figure 1(b) to represent various types of crash collapse diodes, such as TVS diodes, sag diodes, Zener diodes, diodes connected to two poles, or other types. The collapse of the diode. The "crash diode" defined in this patent application is a diode that is designed to be safely collapsed within a pre-selected voltage range. Figure 1 (c) shows a rectifier circuit using four electronic diodes.

Electrostatic discharge (ESD) is a sudden transient current caused by direct contact or electrostatic field induction between two objects of different potentials. Electrostatic discharge (ESD) is a serious problem for solid-state electronic components, such as integrated circuits (ICs). The most advanced integrated circuits (ICs) include high performance components in nanometer (nm) size. Such highly sensitive circuit components cannot survive ESD attacks, and they are often separated from external circuitry to avoid ESD damage. Input and/or output (I/O) circuits exposed by the IC to the external environment typically have thick gates and long channels: IC (I/O) circuits are typically low-performance with different high-performance core circuits. Components. Even so, IC (I/O) circuits often require protection from embedded ESD protection circuits such as snap-back transistors and electronic diodes. The requirements for surviving ESD attacks and the high performance requirements create conflicting requirements in circuit design. Ultra-precision advanced IC technology makes ESD protection more difficult. For example, nano-advanced contact points and perforations are often the weak points of ESD attacks. To make ESD-resistant components, additional manufacturing steps (ESD implants, germanium blocks, thick gate transistors, ...) are required. Embedded ESD protection circuits typically occupy significant areas, require additional manufacturing steps, and cause performance issues. Therefore, it is highly desirable to provide an external ESD protection chip to replace or simplify the embedded ESD protection circuit of an integrated circuit die.

According to the definition used in this patent application, a "wafer" is a packaged semiconductor component that can be assembled on a circuit board. Thus, a "wafer" contains semiconductor components, conductor pins, and packaged protective materials. According to this definition, an unpackaged semiconductor die is not a complete "wafer". According to the definition used in this patent application, an "External Electrostatic Discharge (ESD) Protection Circuit" is an ESD protection circuit for protecting circuits outside the ESD protection circuit chip.

Conventional ESD protection components typically include a snap-back triode or an electronic diode. This patent application uses an electronic diode of an ESD protection element as an example. Electronic diodes have been used as the main components of "external ESD protection circuits." For example, Texas Instruments' TPD4E001 product is an external ESD protection chip that protects four I/O signals. Figure 1 (d) shows a schematic diagram of Texas Instruments TPD4E001. This device has four I/O pins (IO1-IO4), a power pin (VDD) and a ground pin (VSS). The first I/O pin (IO1) is connected to two electronic diodes (DD1, DS1); the other electrode of the electronic diode DD1 is connected to the power pin (VDD), and the electronic diode DS1 The other electrode is connected to the ground pin (VSS) as shown in Figure 1(d). Similarly, the other three I/O pins (IO2-IO4) are also connected to an electronic diode (DS2-DD4) connected to the power pin (VDD) and an electronic diode connected to the ground pin (VSS). (DD2-DD4). In addition, a crash diode (ZD1) is connected between VDD and VSS, as shown in Figure 1(d). Under normal operating conditions, all electronic diodes (DD1-DD4, DS1-DS4, ZD1) are in high impedance reverse bias. If IO1 experiences a negative charge electrostatic attack, DS1 is forward biased, providing a safe path to discharge negative charge to ground. If IO1 experiences a positive charge electrostatic attack, DD1 is a forward bias and ZD1 crash, providing a safe path to discharge to VDD and/or ground. Other I/O pins (IO2-IO4) have similar protection mechanisms.

ESD-protected electronic diodes can also be integrated with other types of circuits. For example, the Texas Instruments SLLS876 includes a 6-channel ESD protection circuit integrated with an electromagnetic interference (EMI) filter on a single wafer. Figure 1 (e) shows a schematic of one channel of TI's SLLS876 EMI/ESD protection wafer. The input channel (Ch_In) is connected to a crash diode (ZD41), capacitor (C41), and resistor (R41), while the output channel (Ch_Out) is connected to another crash diode (ZD42) and the other capacitor (C42) ), and the other terminal of the resistor R41. The other terminals of ZD41, C41, C42, and ZD42 are connected to the ground, as shown in Figure 1(e). The resistor (R41) and the two capacitors (C41, C42) form an EMI filter. The "PI" filter is used in this example, and the "T" filter is also commonly used here. Sometimes, the parasitic capacitance of the diode (ZD41, ZD42) is treated as a capacitor (C41, C42) of the EMI filter. The ESD protection circuit provided by the crash diode (ZD41, ZD42) connects Ch_In and Ch_Out. If Ch_In encounters a negative charge electrostatic attack, ZD41 is forward biased, which provides a safe path to discharge negative charges to ground. If Ch_In encounters a positive charge electrostatic attack, the ZD41 uses a crashing mechanism of the crash diode to provide a safe path to discharge positive charges to the ground. If Ch_Out encounters a negative charge electrostatic attack, ZD42 is forward biased, which provides a safe path to discharge negative charge to ground. If Ch_Out encounters a positive charge electrostatic attack, the ZD42 uses a crashing mechanism of the crash diode to provide a safe path to discharge positive charges to the ground.

These and other external ESD protection components are typically fabricated by IC integrated circuit technology. Figure 2 (a-e) is a simplified symbolic diagram illustrating prior art ESD protection wafer fabrication steps. 2(a) is a simplified view of a single crystal semiconductor wafer (209) including a plurality of dies (200). The die (200) is a repeating unit on a semiconductor wafer that can be individually cut into IC integrated circuits in a wafer. A common example of a single crystal semiconductor wafer is a single crystal germanium wafer. Figure 2(b) is an enlarged view of the area marked in the wafer of Figure 2(a). In this example, the die (200) and other die in the semiconductor wafer (209) are separated by a scribe line (208); the bond pads (212) on the surface of the die (200) provide an externally connected opening. After the electronic diodes and other electronic components have been fabricated on the semiconductor wafer (209), the semiconductor dies (200) on the wafer (209) are sliced along the scribe line (208) to become one by one. Separate components. Figure 2(c) is a simplified symbolic representation of one of the cut grains (200). In this example, a die (200) includes a 4-channel (210) ESD/EMI circuit that includes the components shown in Figure 1(e). As shown in Figure 2(c), each channel (210) on the die (200) includes two bond pads (212), two collapsed diodes (201), two capacitors (202), and one Resistance (203). Sometimes parasitic capacitance can be used as the capacitor (202) without the use of separately fabricated capacitor elements. The bond pads (212) provide openings for the semiconductor elements (222) on the semiconductor die to be connected to the outside. Two ground and power line bond pads (216) provide openings for ground and power connections. For the sake of clarity, the simplified simplifications of Figure 2(c) and other figures represent structures that are actually very complex, and the detailed structure inside the semiconductor component (222) is often not depicted in detail to avoid over-complicating graphics.

The external ESD protection circuit is typically fabricated on a single crystal semiconductor substrate using an integrated circuit process. The process used to fabricate external ESD circuits is specialized. Therefore, external ESD protection wafers are typically more efficient than typical embedded ESD protection. Embedded ESD protection can typically be tested with a 2000 volt mannequin ESD, while external ESD protection wafers can typically pass tests above 16,000 volts. The ESD protection circuit on the semiconductor die (200) in Figure 2(c) requires packaging to perform its function, requiring conductor pins to connect the embedded embedded electrical components to the board level electronic components. Prior art ESD protection circuits typically provide conductor pins for external connections in an integrated circuit package. For example, Texas Instruments' product SLLS876 uses a TDFN package. 2(d) is a plan view showing that the die (200) in FIG. 2(c) is placed in an integrated circuit package (219) to form a wafer, and FIG. 2(e) is a cross-sectional view showing FIG. The package wafer in (d) extends the cross-sectional structure of the mark line in Fig. 2(d). Bond pads (212) on the die (200) provide openings for connecting the single crystal semiconductor component (222) to external electronic components. The bond pads (212) are connected to metal lines (215) within the package (219) via bond wires (218). This packaging grade metal wire (215) is often referred to as a "lead frame." The lead frame (215) is attached to an outer metal pin (214) at the edge of the package as shown in Figure 2(d, e). In this example, the ground wire (216) is a metal plate (216) that is connected to the bottom of the TDFN package by another bond wire (211). Some chips may use metal pins to support ground connections.

While prior art ESD protection wafers have proven to be very effective ESD protection devices, their use is limited. The most important reason is that the prior art ESD wafer area is too large. Prior art external ESD protection wafers use semiconductor single crystal dies placed in an IC package, and thus are similar in size to IC chips of the same I/O number. For example, Texas Instruments' TPD6F002 product uses a package area of 3 mm by 1.35 mm. There is usually not enough room to place this external ESD wafer to protect a large number of signals. For these reasons, prior art external ESD protection wafers are only used for some special signals, such as RF signals, or for special applications. In order to save board area, prior art ESD circuits are typically integrated into the wafer. The ability to move components, such as cell phones, often depends on the ability to package the wafer in a small space. Therefore, the ability to reduce the area of the wafer is often the most important factor in determining the value of the external ESD protection wafer or diode wafer. The electronics industry has invested a great deal of effort to reduce the area of ESD wafers using various IC packaging technologies. The present invention demonstrates an efficient method and structure for printing techniques to reduce the area of ESD protected wafer or electronic diode wafers.

Prior art external ESD protection wafers use a single crystal diode circuit placed in an IC package, so the cost is similar to an IC wafer of the same number of I/Os. Using embedded ESD protection is generally more cost effective than using an external ESD protection chip. Leadframes for bond leads and integrated circuit packages typically introduce about 2 nh and parasitic capacitance and a parasitic inductance of about 2 pf - a value large enough to cause high performance signals. Therefore, there is a great need to reduce the cost of external ESD protection wafers and their parasitic impedance.

One prior art approach to reducing the size and parasitic impedance of external ESD protection wafers is to use a ball grid array (BGA) package. For example, TI placed two crash diodes in a BGA package measuring 1.2 mm by 1.2 mm. The example in Fig. 2(f) shows a cross-sectional structural view of the die (200) in Fig. 2(c) when it is placed in a BGA package. In this example, the semiconductor die (200) is inverted on the BGA substrate (242). To reduce parasitic impedance, metal balls (245), rather than bond leads, are used to form the connection between the bond pads (212) on the semiconductor die (200) and the metal lines (246) on the BGA substrate (242). The substrate metal line (246) is then connected to the solder balls (249) outside the BGA substrate (242) via vias (247) and pads (248). BGA packages are typically smaller than TDFN packages, but BGA packages typically cost more than the same I/O number of TDFN packages. Bonding leads are sometimes used to form the connection between bond pads (212) and substrate metal lines (246) to reduce cost, but result in higher parasitic impedance.

The above examples show that the formation of conductor pins is a major source of problems in the area, cost, and performance of prior art external ESD protection wafers or electronic diode wafers. A "conductor pin" of a wafer, as defined in this patent application, is an electrical conductor in a packaged wafer for providing an electrical connection from an internal circuit to an external board level circuit of the wafer. In the example of Figure 2 (d, e), the conductor pins include bond wires (218), lead frames (215), and package pins (214). In the example of Fig. 2(f), the "conductor pin" includes a metal ball (245), a substrate metal wire (246), a through hole (247), a spacer (248), and a solder ball (249). These prior art integrated circuit packages use complex conductor pins, resulting in large size, high cost, and high parasitic impedance. Therefore, it is preferable to use other methods to provide packaging for ESD protection wafers or electronic diode wafers.

Printing techniques used in similar publications have been applied to the production of passive circuit components such as resistors, capacitors, or resistor-capacitor (RC) filters. The simplified diagram in Figure 8 (a-e) illustrates circuit components fabricated by various printing techniques. The printing technique shown in Fig. 8(a) uses a roller (893) to print the pattern (894) on the substrate (891). The material of the substrate (891) may be ceramic, metal, plastic, paper, semiconductor, or many other types of materials. As shown in Figure (b), the selectively adhered ink on the roller (893) is printed on the substrate in a predetermined pattern (895). Objects other than cylinders, blocks, plates, sheets, or other shapes can also be used for printing. In addition to scrolling, the printed body can have different ways of moving. For example, "stamping" printing generally refers to the printing of blocks, sheets, or films that use linear motion. The basic principles of electronic printing technology and publishing printing technology are similar, except that the ink used in electronic printing technology includes electronic materials. The dry ink is used as an electronic material such as a conductor, an insulator, a resistor, a dielectric, or a semiconductor. The use of electronic printing techniques allows multiple layers of electronic materials to be stacked in a predetermined pattern to produce low cost electronic components.

There are other variations in electronic printing technology, such as screen printing and inkjet printing. Screen printing is a printing technique that uses a woven mesh to support ink clogging of the mold. The screen attached to the screen allows the ink to be selectively transferred to the substrate. Different electronic materials, such as conductors, insulators, resistors, or semiconductors, are first mixed with a solvent such as an ink, and then screen printed onto a substrate to fabricate circuit components. Figure 8 (c, d) is a symbolic simplified diagram of screen printing technology. Figure 8(c) shows a mold (802) engraved with the desired printed pattern (804) placed on a substrate (801). Typical materials for the mold include silk or steel woven mesh. The substrate can be ceramic, metal, plastic, paper, semiconductor, or many other types of materials. A roller (803) or other mechanism presses the ink through the mold (802) and prints the desired material (805) onto the substrate (801) in the desired pattern (804) as shown in Figure 8(d). Heating and drying processes are often required to consolidate the printed material. The final material for screen printing or other types of printing processes is typically "dry ink", which is a liquid or paste at the time of printing, and becomes a solid form of material after printing by heat treatment or other type of drying process. Using a similar process, multiple layers of dry ink material can be printed on the same substrate to form electronic components.

Figure 8(e) is a simplified diagram of an ink jet printing method. In this example, the print head (812) injects ink (813) containing electrical material onto the substrate (811) in a predetermined pattern (815). The method of inkjet printing the position and shape of the control pattern is similar to that of a computer inkjet printer.

Fig. 8(f-h) illustrates a printing method called "inking". Dipping ink is a change in printing technology. Most printing techniques involve different methods of printing ink onto a flat substrate, while dipping ink is immersing the substrate in the ink. Fig. 8(f) illustrates a common case of ink immersion in which a liquid or paste ink line (831) is first printed on a flat surface, and a substrate (830) is moved toward the ink line (831) until the substrate (830) is wetted to the ink line ( Stop after 831), as shown in Figure 8(g). After the substrate (830) is removed from the ink line (831), the ink is applied to the edge of the substrate (830) in the desired mode (833) as shown in Figure 8(h). After the heat treatment, the dry ink material is fixed to the edge of the substrate (830) in a solid form. The shape of the printed structure depends on the ink and the shape of the substrate. Sometimes the ink can spread over the entire surface without special shapes. The pattern of ink can sometimes be very complicated. Fig. 8(f-h) is a symbolic diagram which simplifies the case where a single substrate is stained with ink. In practical applications, a large number of substrates are often immersed in different patterns of ink at the same time. Dip is a printing technique commonly used to build wafer edge conductor pins. The invention is also applicable to ink-impregnated insulators. In addition to ink, it is also suitable for other types of materials such as photoresist materials.

For the sake of clarity, simplified symbolic graphics are used to describe complex techniques, and many details, such as material handling, temperature control, and precision control details, are not necessarily included in our discussion. Printing, according to the definition of application for this special case, consists of three basic steps: (1) preparing the ink, mixing the desired electronic material in a liquid or paste solution; (2) pressing the liquid or paste ink The desired pattern is placed on the surface of the desired object; (3) the solution in the ink is removed to form the desired solid electronic material. Examples of electronic printing techniques include screen printing, ink jet printing, stamping, flexography, gravure, ink, or offset printing.

Surface mounted resistive wafers have been fabricated by printing techniques. The diagram of Figure 3 (a-f) illustrates the steps of fabricating a surface mount resistive wafer using printing techniques. The first step is usually to pattern the printed conductor (301) on the substrate (300) as shown in Figure 3(a). A common example of a substrate material is alumina. A common example of a conductor ink is a silver paste. Conductor inks typically require an electrical conductor that is converted to dry ink after heat treatment by a temperature and timing configuration specified by the manufacturer. The next step is to print a thin film resistor (302) between the conductors (301) as shown in Figure 3(b). Silver and palladium alloys are an example of a printed film resistive material. The resistance of the thin film resistor (302) is determined by its geometry and its sheet resistance. After the heat treatment, a protective insulating layer (303) is usually printed on the surface of the resistive layer (302) as shown in Fig. 3(c). Epoxy resin is a typical material used to protect the insulating layer. The next step is to print an electrode layer (304) to cover the exposed conductor plate (301) as shown in Figure 3(d). Nickel is a common material used as the electrode layer (304). After the electronic components have been printed, the substrate (300) is cut into individual dies (310) as shown in Figure 3(e). In this example, the die (310) of Figure 3(e) includes circuitry in the range indicated by the dark lines on the substrate (300) of Figure 3(d). Sometimes, after the die is cut, the side conductors (305) can be printed on the die by stamping or dipping. Fig. 3(f) is a simplified cross-sectional structural view along the mark line in Fig. 3(e). Figure 3 (g) shows the three-dimensional external structure of the resistive wafer of Figure 3 (e). In this example, each of the resistive wafers (310) includes eight edge conductor pins (365) for supplying four resistors. "Edge conductor pins", as defined in this patent application, are conductor pins that are attached to the edges of a surface mount package. Fig. 3 (q-k) and Fig. 4 (g, h) show examples of "edge conductor pins". The examples shown in Figures 2(f) and 5(c) are not "edge conductor pins" because they are placed in the wafer and do not extend to the edge of the wafer. The use of edge conductor pins typically results in smaller wafer sizes and excellent mechanical properties after soldering of printed circuit boards (PCBs). The edge conductor pins (365) provide the board level I/O pins of the resistor die (310), directly connecting the embedded electronic components via wires (304, 305, 301); no other bond wires, lead frames, or pins are needed. The parasitic inductance of the edge conductor pins is typically much lower than the parasitic inductance of the integrated circuit package. A resistive wafer typically has 1 to 8 resistors. The example of Figure 3(h) shows a three-dimensional view of a two I/O pin wafer, such as a single resistor resistor chip. The size of the 8 I/O wafer is approximately four times the size of the two I/O chips. Printed circuit wafers have a variety of other designs. Sometimes, side conductors (375) printed by stamping or dipping may be used to extend the edge conductor pins as shown in the wafer (370, 378) of Figure 3 (I, j). Sometimes, a groove (385) may be added between the edge conductor pins as shown by the wafer (380) in Figure 3(k). Sometimes the side wires are laid in the grooves instead of between the grooves. Wafers with similar structures can also be used for other electronic components such as resistor-capacitor (RC) filters.

The electronics industry uses a widely accepted, naming scheme for naming resistive wafers or other printed circuit wafers. This naming uses two numbers associated with the length of the wafer (RL1, RL) and two or three numbers associated with the width or I/O spacing (RW1, RW) of the wafer. For example, if the wafer (368) in Figure 3(h) is a standard "0402" resistive wafer, the length (RL1) of the wafer should be about 0.04 inches and the width (RW1) of the wafer should be about 0.02 inches. The thickness of the wafer (RH1) is relatively unimportant and is therefore generally not specified in the nomenclature. When a wafer has more than two I/O edge conductor pins, as shown in Figure 3(g), the wafer is usually named according to the length (RL) between the opposite ends of the edge conductor pins, and Adjacent edge conductor pin spacing (RW). For example, if the wafer (310) in Figure 3(g) is a standard "0402" resistive wafer, the length (RL) between the opposite edge conductor pins should be approximately 0.04 inches. The distance between the adjacent edge conductor pins (RW) should be approximately 0.02 inches. The thickness (RH) of the wafer is relatively unimportant and is therefore generally not specified in the nomenclature. Table 1 lists the commonly used resistor chips and their dimensions. For example, if the wafer (368) in Figure 3(h) is a standard 0402 resistive wafer, the length (RL1) of the wafer should be about 0.04 inches and the width (RW1) of the wafer should be about 0.02 inches. If the wafer (310) in Figure 3(g) is a standard 0402 resistive wafer, the length (RL) between the opposite edge conductor pins should be about 0.04 inches, while its adjacent edge conductors The distance between the pins (RW) should be approximately 0.02 inches. As another example, if the wafer (368) in Figure 3(h) is a standard "0201" resistive wafer, the length of the wafer (RL1) should be about 0.024 inches and the width of the wafer (RW1) should be about 0.012 inches. If the wafer (310) in Figure 3(g) is a standard 0201 resistive wafer, the length (RL) between the opposite edge conductor pins should be about 0.024 inches, while its adjacent edge conductors The distance between the pins (RW) should be approximately 0.016 inches. As another example, if the wafer (368) in Figure 3(h) is a standard "01005" wafer, the length (RL1) of the wafer should be about 0.016 inches and the width (RW1) of the wafer should be about 0.008 inches. This nomenclature has been widely used to describe the dimensions of resistive wafers and other types of printed circuit wafers, such as RC component wafers. This patent application will describe the size of an ESD wafer or an electronic diode wafer using printed edge conductor pins in accordance with this nomenclature.

In the electronics industry, the package shown in the above example is often referred to as a "surface mount rectangular passive component" (SMRPC). Because they are commonly used for surface mounted passive components such as resistive wafers, capacitor wafers, and resistive capacitor (RC) wafers. SMRPC packages are typically significantly smaller and cheaper than comparable I/O counts of integrated circuit packages or electronic diode packages. The main reason is that SMRPC packages typically use edge conductor pins. Electronic printing techniques, such as screen printing, infusion printing, stamping, flexo, gravure, ink, or offset printing, have been applied to the manufacture of passive components to reduce costs. The cost of electronic printing is typically significantly lower than the cost of using integrated circuit packages. The area of the printed wafer is typically also smaller than the area of the integrated circuit package wafer. Electronic printing technology can not only achieve smaller size and lower cost, but also reduce parasitic inductance. The edge conductor pins of a printed circuit wafer are typically printed directly onto the substrate, and it is not necessary to use leadframes and bond leads. Therefore, the parasitic inductance of an electronic printed package is typically significantly lower than the parasitic inductance of an integrated circuit package.

In the electronics industry, electronic printing technology is often referred to as "thick film technology" to compare the "thin film technology" commonly used in integrated circuits. This is because the thickness of the printed film typically exceeds 10 microns, while the thickness of the film used in the integrated circuit is typically less than 2 microns. The precision of electronic printing technology is usually measured in tens of microns. Such precision is of course insufficient to support the fabrication of advanced integrated circuits, but it is a package pin sufficient to fabricate external ESD protection wafers or rectifying diode chips.

This patent application is part of the extension of the previous patent application (CIP application). This patent application focuses on the application of printed conductor pins, side conductor pins, and side insulators in wafer level packaging. During the development of the side insulator manufacturing process, it was found that the derivative process of the invention can be applied to the construction of via connections, thus extending the scope of the patent application.

A photoresist, as defined in this patent application, is a radiation-inducing material that is used in a lithography process to form a pattern structure on a substrate. Different types of photoresist materials may induce different sources of radiation, such as visible light, ultraviolet light, X-rays, electron beams, and ion beam radiation. Photoresist materials can be divided into two categories: positive photoresist and anti-light resistor. The photoresist exposed to the positive photoresist becomes soluble in the developing solution, while the unexposed portion is still insoluble in the developing solution. The portion of the photoresist exposed to the photoresist in the radiation becomes insoluble, and the unexposed portion is soluble in the developing solution. The term "developing photoresist material", as used in accordance with the definition of this patent application, refers to a photoresist material that is insoluble in the developing solution and remains on the substrate after the photoresist cleaning process. A "developing photoresist material" is a photoresist that is not exposed to radiation for a positive photoresist. A "developing photoresist material" is a photoresist that has been exposed to radiation for a negative photoresist.

The via, as defined in this patent application, is an opening on the semiconductor substrate that extends from the front side of the semiconductor substrate to the back side of the semiconductor substrate. After the through hole is opened, it may be filled with other materials. The front side of the semiconductor substrate refers to the surface on the semiconductor substrate where electronic components such as integrated circuits, transistors, resistors, and/or capacitors are present. The back surface of the semiconductor substrate refers to the other surface opposite to the front surface of the semiconductor substrate. If a semiconductor substrate has electronic components on both sides, the surface of the more complicated electronic component is defined as the front side.

The simplified illustration of Figure 14 (a-l) illustrates a conventional manufacturing process for through-hole connections. Fig. 14 (a) shows a cross-sectional view of the ruthenium substrate. For the sake of clarity, the electronic components built on the germanium substrate are not drawn in a simplified illustration. The cross-sectional view shown in Fig. 14 (b), and the top view of Fig. 14 (c) show the structure after the through hole (121) has been opened in the crucible substrate (120). The symbolic cross-sectional view of Figure 14(d) shows that the insulating material (122) has been deposited on both surfaces of the substrate (120) and filled with vias (121). Figure 14 (e-j) illustrates a conventional method of opening a via (127) in an insulating material (122) using a lithography process. The photoresist material (123) is first placed on the surface, as shown in Figure 14(e), and selectively exposed to radiation (125) in a pattern defined by the mask (124), as shown in Figure 14(f). Show. The photoresist in the example of Fig. 14(f) is a positive photoresist, so that the photoresist exposed to the radiation region (126) becomes soluble in the developing solution. These exposed photoresist materials (126) are removed after the cleaning process as shown in Figure 14(g). The remaining photoresist material (123) acts as an etch mask so that the vias (127) can be accurately etched into the insulating material (122) as shown in Figure 14(h). The conventional method removes the developed photoresist material (123) as an etch mask after the via hole (127) has been turned on, as shown in the cross-sectional view of Fig. 14(i) and the top view of Fig. 14(j). Using a similar method, a conductor film (128) can be used to form the via conductor pins, as shown in the cross-sectional view of Figure 14(k) and the top view of Figure 14(l).

With conventional methods, the electrical connection of the vias is difficult. Prior art methods typically require a large distance between the vias, and the number of vias per wafer is thus limited. Conventional via connections are often difficult to control parasitic impedance and limit the application of high speed electronics. A method disclosed by Trezza in U.S. Patent 7,157,372, which fills a semiconductor via with an insulator and then etches the via in the insulator as a means of controlling the impedance and reducing the via connection. One of the preferred embodiments of the present invention forms a through-hole side using a developed photoresist material. The preferred embodiment of the present invention requires fewer manufacturing steps to provide better parasitic impedance control than Trezza. U.S. Patent No. 6,667,551 discloses a through hole in which a small hole is formed in the surface of a semiconductor substrate and a large hole is opened inside the semiconductor substrate. Regardless of the smaller and larger holes, the method in Hanaoka et al. is opened by the front side of the semiconductor substrate. One of the preferred embodiments of the present invention opens an aperture from the front side and then opens a larger aperture from the back side to form a through hole. The preferred embodiment of the present invention requires fewer processing steps and provides better control than Hanaoka et al.

Accordingly, a primary object of a preferred embodiment of the present invention is to reduce the area of a surface mount package comprising active electronic components built on a germanium substrate.

Another object of preferred embodiments of the present invention is to provide a cost effective surface mount package.

A further object of the preferred embodiment of the invention is also to reduce the I/O parasitic inductance of the surface mount package.

Other major objects of the preferred embodiment of the present invention are to reduce the area occupied by the via connections.

Another object of a preferred embodiment of the present invention is to provide better control of the parasitic parameters of the via connections. These and other goals are achieved by using side conductors in place of bumps and/or through holes formed using developed photoresist materials.

Although the features of the invention have been described in the appended claims. The preferred embodiment of the present invention, including its organization, content, objects, and features, can be better understood from the following detailed description in conjunction with the drawings.

Prior art external ESD protection wafers are typically placed on prior art external ESD protection wafers, typically a single crystal semiconductor substrate whose area is cost within the integrated circuit package. As discussed in the previous examples, and the main source of performance issues. The area is usually the most important factor in determining the value of the ESD protection chip. Figure 4 (a-i) illustrates a process for reducing the area of ESD protected wafers. In this example, the single crystal semiconductor wafer (209) has been fabricated using a method similar to that shown in the example of Fig. 2(a). Electronic components such as electronic diodes, resistors, capacitors, and bond pads have also been fabricated using methods similar to those shown in Figure 2 (a-c). After the single crystal semiconductor wafer is thinned, it is molded into a rectangular substrate (499) as shown in Fig. 4(a). The material of the molded substrate (499) may be epoxy, plastic, glass, metal, ceramic, photoresist or other types of materials. This substrate (499) is shaped to suit the shape of the printing process and to provide the required mechanical strength. 4(b) shows another view of the substrate (499) of FIG. 4(a) and shows a symbolic structural diagram of one of the crystal grains (200) in the substrate (499). In this example, the die (200) has the same structure as the die in Figure 2(c). In the following steps, a resistive printing technique similar to that shown in Figure 3 (a-i) is used to make the electrical connections on the die (200). For convenience, the following figures show printed structures on a single die to represent printed structures on all of the dies on substrate (209). For convenience, a roller (498) is used to represent various printing processes according to the symbol of the printed substrate (499); in fact, various electronic printing technologies, such as screen printing, inkjet printing, stamping, and softness. Plates, intaglio, ink, offset, or other printing techniques are suitable for this application, so the invention is not necessarily limited to a particular printing technique. Starting from the structure in Figure 4(b), the conductor (401) is designed to form bond pads (212, 216) electrically connected to the die on the surface of the substrate, as shown in Figure 4(c). These surface conductors (401) can be formed using IC technology or printing techniques. Photolithographic aluminum films are commonly used conductors if IC technology is used. If printing techniques are used, as shown in this example, solid silver dry ink formed after the heat treatment of the silver paste is a commonly used material in this application. It is often desirable to increase the roughness of the semiconductor surface prior to printing the conductor. A solid material of dry ink is formed after heat treatment by the temperature and time period specified by the manufacturer. Of course, the above two types of techniques can also be used in combination to form the surface conductor (401). After the surface conductor (401) is formed, an insulating layer (404) is printed thereon to provide mechanical protection as shown in Figure 4(d). Epoxy resin is a typical material used to protect the insulating layer (404). After the protective insulating layer (404) is formed, an electrode layer (405) is printed thereon to cover the exposed conductor layer (401) as shown in Fig. 4(e). A dry nickel alloy is a common material for the electrode layer (405). The substrate (499) is then cut into individual wafers. Figure 4 (f) is a simplified symbolic cross-sectional view of the structure of Figure 4 (e). Figure 4(g) shows a three-dimensional external view of an ESD/EMI wafer (400) using the die of Figure 4(e). In this example, a dry ink side conductor forms part of the edge conductor pins (475) of the wafer. Such side conductors are typically formed by stamping or dipping ink. The surface conductor (401), as part of the edge conductor pin (475), provides an electrical connection from the edge conductor pin (475) to the internal circuitry (222) of the wafer. The edge conductor pins (477, 476) on the left and right hand sides of the wafer (400) in Figure 4(g) provide ground and/or power line pins. Electroplating is often used to plate additional conductor layers on the edge conductor pins to provide better electrical and mechanical properties. The wafer (400) in this example contains a 4-channel ESD/EMI protection circuit. The outer structure (499) of this wafer (400) is similar to the wafer (370) of Figure 3(i) except for the left and right edge conductor pins (477, 476). Therefore, the area of this wafer is likely to be approximately equal to or smaller than the area of the resistive wafer of the same number of I/Os. Figure 4(h) shows an example of a wafer (489) containing an ESD/EMI protection circuit for one channel. The single channel wafer (489) includes I/O edge conductor pins (485) and ground/power line edge conductor pins (486, 487) and circuitry similar to that of Figure 1 (e). The outer structure of this wafer (489) is similar to the wafer of Figure 3(j) except for the left and right edge conductor pins (486, 487). In addition to single or 4-channel wafers, 2, 6, 8, or other channel count wafers can be fabricated using similar methods.

The ESD/EMI protection wafer shown in Figure 4(e, f, g) can support the same function as the ESD/EMI protection wafer shown in Figure 2(d, e). The difference is that the package-printed package using printed dry ink conductors to form edge conductor pins replaces the integrated circuit package. In this example, the shape of the wafer (489, 499) is designed to resemble 0402, 0201, 01005, or other standard SMRPC wafers. The only difference in the outer structure of the wafer (499) compared to the outer structure of the resistive wafer (370) in Figure 3(i) is the excess edge conductor pins (476, 477) on either side. Other types of electronic diode circuits can also be fabricated in a similar process. For example, the ESD protection circuit of Figure 1(d) can also be fabricated in a similar process. For the ESD protection circuit of Figure 1(d), one conductor pin is required for each I/O signal. Thus, a wafer (499) like Figure 4(g) can protect 8 ESD I/O signals and two power/ground pins. A wafer (489) like Figure 4(i) can protect 2 ESD I/O signals. A similar printed conductor pin can also be used as shown in Figure 1 (a, b) for a universal electronic diode or collapsed diode. For example, a wafer (368, 378) similar to that of Figure 3 (h, i) can carry an electronic diode, while a wafer (310, 370, 380) similar to that of Figure 3 (g, i.k) can carry four electronic diodes. A similar edge conductor pin structure can also be used in the rectifier circuit of Figure 1 (c). The shape of the rectifying wafer can be similar to that of the wafer in Figure 3 (g-k) or Figure 4 (g-h). For example, two rectifiers can be placed in a wafer (310, 370, 380) similar to that shown in Figure 3 (g, I, k), and a rectifier can be placed on a wafer (489) similar to that shown in Figure 4 (h).

The cost of a printed package is typically significantly lower than the cost of an IC package. However, the spacing between the edge conductor pins is typically greater than the spacing between the bond pads of the IC. To support the edge conductor pins, the IC bond pad pitch may be larger than the typical bond pad pitch, which may result in a larger area. New structures may be needed to accommodate the needs of printing technology. The total cost is determined by the competing packaging costs and mold costs. For ESD protection wafers or electronic diode wafers, the use of printed packaging technology typically reduces overall cost.

As shown in the above example, the use of printed dry ink to form the edge conductor pins allows the area of the electronic diode wafer (489, 499) to be substantially the same or less than a standard number of 0402, 0201, or 01005 resistive wafers of comparable I/O. A resistive wafer having an area smaller than the smallest can also be realized because the size of the diode can be smaller than the size of the resistor. As in the example of Fig. 4(g, h), it is very advantageous to make the size of the electronic diode wafer (489, 499) similar to that of 0402, 0201, 01005, or other types of surface mount resistor wafers. It is also advantageous to have the pin locations of the electronic diode wafers (489, 499) compatible with standard 0402, 0201, 01005, or other standard surface mount resistor wafer pin locations. Having the size of the wafer similar to the size of a standard resistive wafer allows the electronic diode wafer of the present invention to use existing resistive wafer machines, resulting in significant operational cost savings. According to the definition used in this patent application, for a standard "0402" wafer, the distance between the ends of the edge conductor pins of the opposite I/O signals is 0.04 inches, while its adjacent I/O The spacing between the edge conductor pins of the signal is 0.02 inches. Thus, when the invention refers to "a wafer having an area that is substantially the same or smaller than the area of a standard 0402 surface mount resistor wafer having a comparable number of I/Os", the wafer area is approximately equal to or less than [(0.04 inches by 0.02 inches). Multiply ((the number of I/O edge conductor pins in the crystal embedded) divided by 2)], that is, approximately [(0.0004 inch square) multiplied by (in the embedded I/O edge conductor connection) The number of feet)]. According to the definition used in this patent application, for a standard "0201" wafer, the distance between the ends of the edge conductor pins of the opposite I/O signals is 0.024 inches, while its adjacent I/O The spacing between the edge conductor pins of the signal is 0.016 inches. Thus, when the invention refers to "a wafer having an area that is substantially the same or smaller than the area of a standard 0201 surface mount resistor wafer having a comparable number of I/Os", the wafer area is approximately equal to or less than [(0.024 inches by 0.016 inches). Multiply ((the number of I/O edge conductor pins in the crystal embedded) divided by 2)], that is, approximately [(0.0002 inch square) multiplied by (in the embedded I/O edge conductor connection) The number of feet)]. According to the definition used in this patent application, for a standard "01005" wafer, the distance between the ends of the edge conductor pins of the opposite I/O signals is 0.016 inches, while its adjacent I/O The spacing between the edge conductor pins of the signal is 0.012 inches. Thus, when the invention refers to "a wafer having an area that is substantially the same or smaller than the area of a standard 01005 surface mount resistor wafer having a comparable number of I/Os", the wafer area is approximately equal to or less than [(0.016 inches by 0.012 inches). Multiply ((the number of I/O edge conductor pins in the crystal embedded) divided by 2)], that is, approximately [(0.0001 inch square) multiplied by (in the embedded I/O edge conductor connection) The number of feet)]. The "area" referred to in the above definition refers to the area of the soldered surface of the surface mount package. The ground/power line conductor pins are not counted as the number of I/O conductor pins. Since the bond pads are connected to the edge conductor pins (475) through the wide conductors (403, 405, 401), the parasitic inductance of such packages is typically much lower than the parasitic inductance of the integrated circuit package.

While the above is a description of specific examples of the invention, other modifications and variations will be apparent to those skilled in the art. For example, after the die is sliced, the side conductors may or may not be used as part of the edge conductor pins. The shape of the mold substrate in Fig. 4(a) is not necessarily rectangular. It can also be printed directly on a semiconductor wafer without the use of a molded substrate. In addition to the conductors, the invention can also print resistors, capacitors, or other electrical components on the substrate. Electronic components can be placed on both sides of the substrate instead of one side of the substrate. For the example of Figure 4(a), the semiconductor wafer is first formed into a molded substrate and then sliced. Figure 4(i) shows an example in which a semiconductor wafer (209) is first sliced and then the die (200) thereon is placed over a mold substrate (469) to print conductor leads. The substrate (469) can be treated in a manner similar to that described above. These and other variations will be apparent from the disclosure of this patent application, and it is understood that there are many other modifications and variations. Therefore, the specific examples described above should not be construed as limiting the scope of the invention.

Figure 5 (a-c) shows an example of using a conductor ball instead of a printed conductor to provide a low impedance conductor pin. Figure 5(a) shows a top view of a die (200) which is identical to the die of Figure 2(c). After the protective layer (503, 505) is placed over the die (200), the "under bump metallurgy" (UBM) (507) is placed on the bond pads (212, 216) and then the conductor balls (501) are placed in the UBM ( 507), as shown in the top view of Fig. 5(b), and the cross-sectional view of Fig. 5(c). Techniques for placing conductor balls have been developed for use in ball grid array (BGA) integrated circuit packages. The components shown in Figure 5(b, c) can support the same functions as those previously shown in Figure 2(d, e), but the cost of bumping techniques is typically significantly higher than printing techniques. The size of the bump wafer is limited by the desired ball-to-ball spacing (Dbb) and ball-to-edge spacing (Dbe). Today's bumping techniques typically require Dbb greater than 0.4 mm and Dbe greater than 0.08 mm. These regulations limit the ability to reduce the size of the wafer by bumping techniques. Use edge conductors instead of bumps to remove those constraints. Thus, wafers using the edge conductor pins of the present invention can generally be smaller than wafers using bump balls or bump structures.

The cost of the electronic diode circuit discussed in the above examples is generally controlled by the cost of the single crystal semiconductor component. Therefore, it is worthwhile to use an electronic diode fabricated from a non-single crystal semiconductor to further reduce the cost. Non-single crystal semiconductor materials, as defined in this patent application, refer to polycrystalline or amorphous semiconductor materials.

Fig. 6 (a-i) is a cross-sectional view illustrating a manufacturing step of a non-single crystal semiconductor electronic diode. Fig. 6(a) shows a cross-sectional view of the substrate (601). The substrate can be ceramic, plastic, metal, semiconductor, or other type of material. Fig. 6(b) is a cross-sectional view showing a conductor layer (602) laid on the substrate (601). Fig. 6(c) is a cross-sectional view showing the formation of an electron diode when two layers of non-single crystal semiconductor (603, 604) are deposited on a substrate. The two electron diode layers (603, 604) may be a PN junction diode formed of a p-type non-single crystal semiconductor and an n-type non-single crystal semiconductor. Another option is to lay a layer of non-single crystal semiconductor and then surface doping to produce a second semiconductor layer of the opposite type. Another option is to form a Schottky diode using a layer of non-single crystal semiconductor (603) and a layer of metal (604). A common example of a non-single crystal material (603, 604) is polycrystalline germanium or amorphous germanium. The cross section shown in Fig. 6(d) is when a shield layer (605) is laid on the electron diode layer (602, 603). The shape of this shield layer (605) can be determined by printing, lithography, or other types of methods. The next step is to etch away the electron diode layer (603, 604) that is not covered by the shield layer (605), as shown in Figure 6(e). After the shielding layer (605) is removed, the electronic diode (610) is formed between the two electronic diode layers (603, 604) according to the shape defined by the shielding layer, as shown in FIG. 6(f). The next step is to print the insulating layer (611) in the desired shape, as shown in Figure 6(g). A typical material used as an insulator for printed circuit boards is doped glass. The next step is to print a conductor layer (612) to connect the electronic diodes (610) and form conductor pins as shown in Figure 6(h). The next step is to print an insulating layer (615) overlying the protective electronic diode (610) as shown in Figure 6(i). Epoxy resin is a typical material used to protect the insulating layer. The next step is to print an electrode layer over the exposed conductor layer, as shown in the previous example. In the above example, only the structure of the electronic diode is shown for the sake of simplicity. The formation of other components such as resistors and capacitors is not shown in the above example. After the electronic component has been printed on the substrate (601), the substrate can be cut into individual wafers having a shape similar to the previous example.

Fig. 6(a-i) is a symbolic simplified diagram illustrating the manufacturing steps of a non-single crystal semiconductor diode. The component properties of a non-single crystal semiconductor electronic diode, such as the breakdown voltage or reverse bias leakage current of a collapsed diode, are generally not as well controlled as the component properties of a single crystal semiconductor electronic diode. However, many applications, such as ESD protection, do not require precise control of many electronic diode properties. Electron diodes formed on non-single crystal semiconductors are often sufficient to support ESD protection circuits. ESD protection wafers fabricated by methods similar to those of Figure 6 (a-i) can also support the functionality of existing ESD protection wafers.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. For example, in the above example, the shape of the electronic diode is determined by the process of mask control, but the printing technique is also applicable to the control of the shape of the electronic diode. The electron diode layer may be two layers laid separately, or a layer may be laid and then a second layer may be fabricated by a surface doping process. As can be appreciated, there are many other possible modifications. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention.

Figure 7 (a-e) is a cross-sectional view illustrating another step of fabricating a non-single crystal semiconductor electronic diode using a printing technique. Fig. 7(a) shows a cross section of the substrate (701). The cross-sectional view of Fig. 7(b) shows that a layer of non-single crystal semiconductor (702) is printed on the substrate (701). The cross-sectional view of Figure 7(c) shows that another layer of non-single-crystal semiconductor (703) of different doping type is printed on the substrate (701). The second layer (703) partially overlaps the first layer (702) and forms an electronic diode (710) at the junction of the overlapping regions. The two layers (702, 703) may be a PN electrical diode formed of a p-type non-single crystal semiconductor and an n-type non-single crystal semiconductor, or a Schottky diode formed of a non-single crystal semiconductor and a layer of metal. A common example of a non-single crystal semiconductor material is polycrystalline germanium or amorphous germanium. The two layers (702, 703) can also be two different semiconductors. The cross-sectional view of Figure 7(d) shows that a layer of insulator protection layer (711) is printed overlying the electronic diode (710). The cross-sectional view of Figure 7(e) shows a layer of conductor (712) printed to form a conductor pin or a wire connecting an electronic diode (710). Using a similar fabrication process, the present invention can also integrate resistors, capacitors, or other circuit components with the electronic diode (710) of a non-single crystal semiconductor. For the sake of brevity, the structure of the other components is not described in the above examples. After the electronic components have been printed, the substrate (701) can be cut into individual wafers. ESD protection wafers or electronic diode wafers fabricated using processes similar to those of Figure 7 (a-e) can support the same functions of existing ESD protection wafers or electronic diode wafers. The difference is that the printed wire directly connected to the electronic diode replaces the integrated circuit package, while the non-single semiconductor diode replaces the single crystal diode. The ESD protection wafer or electronic diode wafer of the printed conductor pins can typically be smaller than the 0402 or 0201 or 01005 resistance wafers having the same number of I/Os. It is highly advantageous to have an ESD protected wafer or an electronic diode wafer that is similar in size to 0402 or 0201 or 01005 or other types of resistive wafers. It is also highly advantageous to have the pin locations of the ESD protection wafer or electronic diode wafer compatible with the pin locations of 0402 or 0201 or 01005 or other types of resistive wafers.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention.

In the above example, the semiconductor electronic diode chip is packaged before being placed on the circuit board. It is very advantageous if the semiconductor electronic diode is printed directly on the circuit board. Figure 9(a) is a simplified cross-sectional view showing a circuit board (901) with embedded surface conductor lines (902). Under normal circumstances, the electronic diode circuit is first packaged into a wafer before it can be soldered to the board. The printed non-single crystal semiconductor electrical diode can be printed directly on the circuit board without packaging. The cross-sectional view of Fig. 9(b) shows that a layer of non-single crystal semiconductor (903) is printed on the circuit board (901). The cross-sectional view of Figure 9(c) shows that another layer of non-single-crystal semiconductor layer (904) of different doping type is printed on the circuit board (901). The second layer (904) partially overlaps the first layer (903) and forms an electronic diode (909) at the junction of the overlapping regions. The two layers (903, 904) may be a PN diode formed of a p-type non-single crystal semiconductor and an n-type non-single crystal semiconductor, or a Schottky diode formed of a non-single crystal semiconductor and a layer of metal. A common example of a non-single crystal semiconductor material is polycrystalline germanium or amorphous germanium. The two layers (903, 904) can also be two different semiconductors. The cross-sectional view of Figure 9(d) shows a layer of insulator protection layer (905) printed onto the electronic diode (909). The circuit board (901) can be a common printed circuit board (PCB), a flexible printed circuit board commonly used for moving components, a glass circuit board commonly used for photoelectric display elements, a BGA package substrate, or other types of board-level substrates.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. The above preferred embodiments focus on the electronic diode circuit, however the same principles apply to other types of active or integrated circuits, particularly die level surface mount packages. A grain level surface mount package, according to the definition used in this patent application, is a wafer comprising at least one single crystal semiconductor die having an area that is no more than 20% larger than the largest semiconductor die area within the wafer. .

Figure 10 (a-n) is a simplified symbolic diagram illustrating the process of an integrated circuit die level surface mount package. The simplified diagram of Fig. 10(a) shows a single crystal germanium substrate (99) comprising a plurality of crystal grains. Fig. 10(b) is an enlarged view showing four crystal grains (7-10) on the single crystal germanium substrate (99) of Fig. 10(a). Adjacent grains are separated by a cutting line (98). Each die contains an integrated circuit that supports the function of a single IC die after the die is sliced and connected to the conductor pins. The structure of the actual integrated circuit is usually very complicated, so the following example will use a symbolic schematic or block diagram to represent the integrated circuit. In this example, as shown in the schematic of Figure 10(b), each die contains a differential amplifier with a pair of differential inputs (I+, I-), a pair of differential outputs (O+, O-), one Power down control signal (PD), power supply (VDD, AVDD) and ground (GND). All input and / or output (I / O) signals, power (AVDD and VDD), and ground (GND) are connected to bond pads (11) to provide external connections to the IC semiconductor substrate. After the IC fabrication process is completed, an insulator protective film (14) is printed to cover the active components as shown in Figure 10(c). Typical materials for insulator protective films are plastic or epoxy. A simplified cross-sectional view of Figure 10 (d-g) illustrates wafer thinning and cutting processes. Figure 10 (d) shows a cross-sectional view of a grain (10) in Figure 10 (a-c). The crucible substrate in Fig. 10 (d-g) is placed face down on the tape or on a flat surface (31). The structures in the examples of the present invention are not necessarily drawn to actual scale. The thickness of the germanium substrate (99) is usually reduced before the grain slicing, as shown in Fig. 10(e). In this example, an insulating layer (12) is laid on the back side of the germanium substrate as shown in Fig. 10(f). Typical materials used for this insulating layer can be epoxy, plastic, dielectric, or photoresist. This insulating layer preferably has surface particles as shown in Fig. 13(e). After the back insulating layer (12) is laid, a precision diamond blade is usually used, and the ruthenium substrate (99) is cut along the scribe line (98) into individual dies (7, 10) as shown in Fig. 10(g). The example of Fig. 10(h) shows the three-dimensional structure of one crystal grain (10) cut by the above process. The cut crystal grains (10) were immersed in the insulating ink layer (27) using an ink immersion process similar to that shown in Fig. 8 (f-h). After the heat treatment, a dry ink side insulating layer (21) is laid on the side of the bottom of the die (10) as shown in Fig. 10(i). A similar process can be repeated to spread another dry ink side insulating layer (22) on the side of the top of the die (10) as shown in Figure 10(j). Preferably, the side insulating layer is mixed with surface particles as shown in Fig. 13(e). The side insulating layer can also be formed using other methods such as stamping, printing, sputtering, spinning, or brushing. Another good option, especially for low temperature applications, is to use a photoresist side insulator instead of a dry ink material. Preferably, the side insulator has a thickness of less than 100 microns. Using the ink immersion process similar to that shown in Fig. 8 (f-h), the die (10) of Fig. 10(j) is immersed in the printed ink conductor wire (29) as shown in Fig. 10(k). After the heat treatment, the dry ink side conductor pin (23) is formed on the side of the bottom of the die (10) as shown in Fig. 10(l). A similar process can be repeated to spread another dry ink side conductor pin (24) on the side of the top of the die (10) as shown in Figure 10(m). Other methods such as stamping, printing, or sputtering can also be applied to form the side conductor pins. Plating is often used to plate more conductor material on the side conductor pins (23, 24). The die (10) in Figure 10(m) is now a finished packaged wafer (28) because it already has conductor pins (23, 24) to support board level assembly. Figure 10 (n) shows a cross section of the wafer (28) of Figure 10 (m). The area of the wafer (28) in Fig. 10(m) is about the same as the area of the die (10); therefore, the wafer (28) in Fig. 10(m) is a grain size package wafer.

While the above is a description of specific examples of the invention, other modifications and variations will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. For example, the side conductor pins (23, 24) in the above example are dry ink conductors formed by dip ink. Other manufacturing methods, such as stamping, plating, sputtering, chemical laying, or other methods, can also be used to form the side conductor pins. The material used for the side conductor pins does not have to be a dry ink material. In the example of Fig. 10 (h-j), the dry ink insulating material is applied to the side surface by the dipping method before the side conductor pins are formed. Stamping, plating, spinning, spreading photoresist, or other methods can of course be used to form the side insulators. The material used for the side insulators does not have to be a dry ink material. For example, photoresist materials are also suitable for side insulators. The cross-sectional view of Figure 10 (o-s) illustrates other processes that can be used to form a side insulator. First, the ruthenium substrate (99) having the back surface thinned as shown in Fig. 10(e) is cut along the scribe line (98) as shown in Fig. 10(o). After the first dicing as shown in Fig. 10(o), an insulating layer (62) is placed to fill the space after cutting, as shown in Fig. 10(p). Epoxy resin is a typical material that can be used in this application; the side insulating layer is preferably mixed with surface particles as shown in Fig. 13(e). Using a thin cutting blade, the structure in Figure 10(p) is cut a second time along the cutting path (98). This second cut removes a portion of the insulating material filled in the dicing street (98) leaving the insulating material (62) on the side of the die (7, 10) as shown in Figure 10(q). The die of Fig. 10(q) can be bump-packed or joined to the side conductor as shown in Fig. 10(k-m) to become a grain-level package wafer.

While the above is a description of specific examples of the invention, other modifications and variations will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. For example, in the above example, the die (7, 10) is still on the tape (31) after the first cut shown in Figure 10(o), so that the space between the die is limited by the first The interval of one cut. Another method is to rearrange the grains after cutting so that the space between the grains is no longer limited by the interval of the first cut. Figure 10 (r) illustrates another process for laying a side insulator. After slicing, starting from the structure of FIG. 10(g) or FIG. 10(o), the insulating layer (32) may be spread between the back surface and the crystal grains (7, 10) by sputtering or other thin film processing to produce The side insulator is shown in Figure 10(r). If this insulating layer (32) can be separated along the cutting path (98), it is not necessary to use a second cut to separate the grains (7, 10). Figure 10(s) illustrates another example. Starting from the structure of Fig. 10(g), a thin film of yttrium oxide and/or tantalum nitride (65) is grown on the exposed side of the crucible by an insulator film growth process to form a side insulator. This method allows a selective long insulator film to be on the bare crucible. The die of Fig. 10(r) or Fig. 10(s) has been prepared, and the side conductor can be added using the process shown in Fig. 10(k-m) to become a grain-level package wafer. In the above example, the substrate is facing down, and a similar method is of course applicable to the process in which the substrate is facing upward.

Figure 10 (a-s) illustrates a process for forming a side insulator and a side conductor pin to fabricate a grain level surface mount package. The "side" of a surface mount package is defined as (a) a surface having at least one common edge with the soldered surface of the surface mount package, and (b) the surface having a different angle than the soldered surface. The sides are typically nearly perpendicular to the soldered surface of the surface mount package, but there may be exceptions. The soldered surface is designed to face one surface of the board after board level assembly. For a grain-level surface mount package, the soldered surface is typically the same or opposite surface as the surface of the germanium substrate within it, with one exception. A "side insulator" is an insulator laid on the side of a surface mount package for providing an electronically insulating material between the tantalum substrate and the side conductor. Examples of materials for the side insulator include: a dry ink insulator, a photoresist material, or an insulator having surface particles. For mold grain grade packaging, the side insulators are preferably thinner than 100 microns. A "side conductor pin" is a conductor that includes a conductor laid on a surface of a surface mount package and extends from a soldered surface of the surface mount package to a side conductor pin. Typically the side conductor pins extend from the weld face through one or more sides to a surface opposite the weld face. Sometimes a side conductor pin may not extend all the way to the surface opposite the weld face, but the side conductor pins defined in this patent application extend at least to 60% of the depth of one side. For example, the conductor pins in Figure 3 (ik), Figure 4 (g, h), Figure 10 (m), Figure 11 (f), Figure 12 (ak), and Figure 15 (h) are " The side conductor pins", while the conductor pins of Figures 2 (e, f), Figure 3 (g, h), and Figure 5 (c) are not "side conductor pins". The conductor pins shown in Figure 3 (g.h) are "edge conductor pins" but not "side conductor pins" because they do not extend to the sides of the wafer. If the conductor pin extends to 60% of the surface thickness (RH, RH1) of at least one surface mount package, it is the "side conductor pin". In order to achieve the advantages of smaller size and better mechanical properties, the side conductor pins always include conductors laid on the surface of the surface mount package. Metal pins, bumps, balls, or other structures attached to the sides but not on the side surfaces are not "side conductor pins." For example, Figure 2(e) shows a metal pin attached to the side of a packaged wafer. Such a structure is not a "side conductor pin" and they do not have the advantage of a side conductor pin. The conductor pins are wafer level electronic connections, so the circuit connections added during board level assembly are not conductor pins.

Current grain-level package wafers are typically placed with bump balls (501) or bumps on the surface of the germanium substrate as shown in the example of Figure 5 (a-c). Figure 5 (d) is a simplified cross-sectional view showing the structure of the wafer of Figure 5 (c) mounted on a printed circuit board (530). Typically the wafer is turned upside down and the conductor balls (501) are aligned with the solder plates (531) on the printed circuit board (530) as shown in Figure 5(d). The bonding between the conductor balls (501) and the welded plates (531) is usually formed by a solder paste (532). The mechanical stress generated during the installation usually deforms the conductor ball (501) as shown in Figure 5(d). The ball-to-ball spacing (Dbb) is typically limited to printed circuit board technology. Today's technology typically requires Dbb to reach or exceed 0.4 mm. This ball-to-ball spacing (Dbb) tends to increase the area for many ICs. Therefore, the cost reduction of the wafer is often limited to the ball-to-ball spacing (Dbb). The wafer (540) shown in the cross-sectional structural view of Fig. 5(e) has the same function as the wafer shown in Fig. 5(d), except that the wafer uses edge conductor pins (542) instead of bumps. ball. In this example, the wafer (540) using the side conductors is also mounted on the same solder plate (531) on the same printed circuit board (530) as shown in Figure 5(d). The side conductor pins (542) typically include solder paste so no additional solder paste is required. The solder paste (543) on the side conductor pins (542), after assembly of the board, typically flows onto the solder pads (531) on the printed circuit board (530) as shown in Figure 5(e). Comparing Figure 5(d) with Figure 5(c), the advantages of the side conductor pins can be seen. Due to the limitation of the distance between the ball and the ball, the area of the germanium die (541) in the wafer (540) using the side conductor pins (542) can generally be smaller than the germanium die in the wafer using the bump package ( 200) area; for the same reason, the wafer area is also small. The mechanical structure shown in Figure 5(d) is complex, while the mechanical structure shown in Figure 5(e) is compact - resulting in better mechanical strength, better thermal performance, and better reliability. The parasitic impedance of the side conductor pins is also generally lower than that of the bump wafer. Therefore, a grain-level surface mount package using side conductor pins can generally outperform a functionally equivalent bump wafer in terms of cost, size, mechanical strength, reliability, electrical properties, and thermal performance.

While the above is a description of specific examples of the invention, other modifications and variations will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. For example, the soldered surface of the wafer in Fig. 5(e) is also the front side of the germanium grain, and the reverse side may also be the soldered surface. Figure 10 (an) illustrates a fabrication process for fabricating a surface mount package containing a single germanium die, and a similar fabrication process is also applicable to a wafer containing multiple die and using side conductor pins, as shown in Figure 11. The simplified symbol diagram of (af) is shown.

Figure 11 (a) is a simplified view of a single crystal germanium substrate (49) comprising a plurality of crystal grains. Fig. 11(b) is an enlarged view of four crystal grains (50-53) on the ruthenium substrate (49) in Fig. 11(a). Adjacent grains are separated by a scribe line (48). In this example, each wafer includes an integrated circuit memory component. The structure of the memory elements is very complicated, so the symbolic block diagram is used to represent the memory elements. Typical examples of memory components are flash memory, read only memory (ROM), dynamic random access memory (DRAM), and static random access memory (SRAM). As shown in the symbol block diagram of Figure 11(b), a typical memory component has one or more memory arrays, control circuitry, and data input and/or output (I/O) circuitry. In this example, each memory element also has a die select signal (Sd) that allows an external circuit to selectively control the memory elements within the die. All I/O controls, die select signals, and power supplies for the memory components are connected to bond pads (41) to provide openings for external connections to the ICs on the semiconductor substrate. After the IC fabrication process has been completed, the side conductor pins (42) are printed or laid on the surface to form a bond pad (41) to the edge of the die (50-51). The die select signal (Sd) is connected to the different edge of the die by side conductor pins (Sdm0-Sdm3) as shown in Fig. 11(c). After the side conductor pins (42, Sdm0-Sdm3) are formed, an insulator protective film (44) is printed to cover the active elements as shown in Fig. 11(c). Typical materials for insulator protective films are plastic or epoxy. Using the flow shown in Fig. 10 (dg, s), in addition to the position where the side conductor pins (42, Sdm0) are exposed, the present invention can wrap the die (50) with an insulator (44, 45) as shown in the figure. The symbolic three-dimensional picture of 11(d) is shown. Other grains (51-53) can be prepared in a similar manner. Fig. 11(e) shows an example in which four crystal grains (50-53) are stacked. The side conductor pins (42, 54) of the same signal on different dies (50, 51) are aligned on the same line, but the selection signals (Sdm0-Adm3) on different dies are not aligned on the same line. Above, as shown in Figure 11 (e). Using a process similar to the example in Figure 10 (k-m), the side conductor pins (59, Ps0-Ps3) can be used to form a wafer in which a plurality of memory dies are stacked, as shown in Figure 11(f). Additional conductor material is typically plated onto the side conductor pins by electroplating. The side conductor pins (Ps0-Ps3) on the left side are used to selectively control the memory elements in different dies (50-53). The memory chip area of Figure 11(f) is approximately equal to the area of one memory die, however its storage capacity is equal to the sum of the memory capacities of the plurality of memory cells. Moreover, it is also possible to stack a plurality of wafers of Fig. 11(f) up and down into a high-capacity memory wafer stack, occupying a small board area. Therefore, the side conductor pins can be very efficient in producing high-capacity memory chips or memory systems.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. In addition to differential amplifiers or memory components, the side conductor pins are suitable for a wide variety of integrated circuit wafers, as shown in the example in Figure 12(a-k). For the sake of clarity, a symbolic schematic or block diagram is used to represent the integrated circuit or electronic component in Figure 12 (a-k).

Figure 12 (a) shows a surface mount package (60) comprising a germanium die (61) of a diode. The side conductor pins (62) at the top and bottom provide an external electrical connection to the diode. Figure 12(b) shows another surface mount package (87) comprising a germanium die (63) of a bidirectional transient voltage suppression diode (PNNP TVS). The side conductor pins (86) in this example cover the three sides of the wafer (87) instead of one side, as shown in Figure 12(b). The example of Figure 12(c) shows an external structure similar to the wafer of Figure 12(b) containing a back-to-back collapsed diode die (64) to support the function of the TVS diode similar to Figure 12(b). . Figure 12(d) shows a surface mount package (65) comprising a germanium die (66) having a double junction transistor (NPN) therein. The side conductor pins (67, 68) provide an external electrical connection to the double junction transistor. Figure 12(e) shows a surface mount package (70) of a germanium die (71) having a field effect transistor (FET); the side conductor pin (67-69) provides the field effect transistor (FET) The external connection of the three terminal and bottom electrodes. The example of Fig. 12(f) shows a wafer similar to the outer structure of the wafer of Fig. 12(e), comprising a buffer or amplifier die (80) having an integrated circuit therein; the side conductor pins provide the The external connection of the buffer, amplifier input, output, power supply, and ground. Figure 12 (g) shows a surface mount package (72) of a germanium die (73) with an ESD/EMI circuit; the side conductor pins (74) provide an external electrical connection to the ESD/EMI circuit. Figure 12(h) shows a surface mount package similar in Figure 12(g) with a germanium die (75) with an operational amplifier inside; a side conductor pin (74) providing the outside of the op amp Electronic connection. Figure 12 (i) shows a surface mount package (76) of a germanium die (77) having a radio frequency (RF) integrated circuit; the side conductor pins (78-79) provide the exterior of the RF integrated circuit Electronic connection. Figure 12(j) shows a surface mount package having an external structure similar to that of Figure 12(i), which includes a germanium die (85) having a clock circuit therein. Figure 12(k) shows a surface mount package (76) of a germanium die (81) with a 74 series integrated circuit; in this example, it is a 7400 4-NAND logic die; side conductors The foot (82) provides an external electrical connection to the circuit. All of the wafers in Figure 12 (a-k) have an area that is very close to the germanium grain area. Therefore, the side conductor pins enable them to be grain level surface mount packages.

The above shows that the side conductor pins are actually applied to an example of providing an external electronic connection of a germanium substrate containing active electronic components. The active electronic component, according to the definition used in this patent application, is an electronic diode or a triode. A surface mount package of a germanium substrate having active electronic components, the side conductor pins can be used to have an area of approximately equal to or less than the area of the resistor 0402 or 0201 or 01005 of the equivalent I/O number. A resistive wafer with an area smaller than the smallest is also achievable. For the wafer of the germanium substrate with active electronic components, adjust the position of the side conductor pins so that the pin positions of these surface mount packages are compatible with the standard 0402, 0201, 01005, or other standard resistor chip pin positions. Very beneficial. Having the wafer size similar to that of a standard resistive wafer allows the wafer of the present invention to be flexible to use existing resistive wafer machines with significant operational cost savings.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. For example, printing techniques are often used in the above examples, however other techniques are also applicable to the surface mount package of the present invention.

The example of Fig. 13 (a-c) illustrates how a photoresist material is used for an electronic component. Figure 13 (a) shows a wafer (100) having a horizontal scribe line (101) and a vertical scribe line (102). Usually the photoresist material (105) is first laid on the back side of the wafer (100) as shown in Figure 13(b). The wafer is rotated to distribute the photoresist (105) over the entire wafer (100) as shown in Figure 13(c). The photoresist (105) thickness is typically controlled by the rotational speed. The symbolic cross-sectional view of Fig. 13(d) shows that the photoresist layer (105) is laid on the surface of the ruthenium substrate (100). The surface particles (110) are sometimes intentionally placed on the surface of the photoresist (105) which has not been hardened, as shown in Fig. 13(e). The surface particles can provide the surface roughness of the photoresist layer to improve the adhesion of the conductor layer or other surface layers. Surface particles can also improve mechanical and thermal properties. In this example, the base layer of surface particles (110) is a photoresist (105) layer. An example of a photoresist material is the SU-8 photoresist developed by IBM. It can be irradiated with ultraviolet light to harden the SU-8 photoresist. Other materials such as ink, plastic, epoxy, plastic, dielectric, or ceramic materials can also be used as the base layer for surface particles. Surface particles, as defined in this patent application, are (a) particles having an average diameter of less than 50 microns, (b) particles intentionally disposed on the surface of the base layer to provide surface roughness, and (c) components different from the base. Particles of layer composition. Typical materials for surface particles are ceramic materials such as alumina particles.

In addition to rotation, the photoresist can also be applied to the substrate by brushing, printing, dipping, or other methods. Figure 13 (f) shows a method in which the side of the sample (113) is immersed in a photoresist layer (115) disposed on a plane (111). The side insulator can be fabricated using this method of photoresisting. The surface particles are sometimes intentionally placed on the side insulator to form a structure as shown in Fig. 13(e).

In carrying out the above invention, it has been found that the related method can be used for via connection, thus developing the following derivative invention. The simplified diagram of Figure 15 (a-1) illustrates the procedure for forming a via connection. Fig. 15 (a) shows a cross-sectional view after opening the via hole (121) on a tantalum substrate (120) using a conventional method similar to that shown in Fig. 14 (a-c). The symbolic cross-sectional view of Fig. 15(b) shows that the photoresist material (150) covers both surfaces of the substrate (120) and fills the via holes (121). Depending on the pattern of the reticle (151), the photoresist material (150) is selectively exposed to radiation (152) as shown in Figure 15(c). The photoresist in this example is a photoresist, and the photoresist (159) exposed to radiation becomes a resistive photoresist; a positive photoresist can also be used, but the pattern of the mask (151) is black and white. After the cleaning process, the developed photoresist material (159) remaining on the germanium substrate (120) becomes an electrical insulator. Further, the via holes (156, 158) are opened in the developing photoresist material (159) as shown in the cross-sectional view of Fig. 15(d) and the top view of Fig. 15(e). Comparing the flow shown in Fig. 14 (ej), the conventional method uses the developed photoresist material (123) as a mask to define the shape of the via hole (127) according to the lithography process, and removes the developed photoresist material after the etching process is completed. (123), as shown in Fig. 14(i). For the example of the invention shown in Figure 15 (b-e), the developed photoresist material (159) remains as part of the component and they are used directly to form vias (156, 158). The developed photoresist material can be made into a highly precise and complex shape. Direct use of developed photoresist materials for optimum precision and cost effectiveness. The above example shows that one via (121) in the substrate (120) can open more than one hole (158) due to the accuracy of the developed photoresist material. Using conductive, sputtering, chemical deposition, electroplating, and/or other methods, the conductive material (155, 157) may be laid over the vias (156, 158) defined by the developed photoresist material (159) to form via connections, as shown in cross-section 15 (f) and top view 15 (g). Side conductor pins can also be made in a similar manner. For example, the present invention can cut the conductor material (155) in the through hole (156) on the right side of FIG. 15(f) along the dicing street (154) marked with a broken line in FIG. 15(f), and on the substrate (120) The side faces form side conductor pins (155) as shown in Figure 15(h). For the sake of clarity, the present invention is often used to represent a very complex structure, and the structures in the drawings are not necessarily drawn to scale.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. For example, the through hole on the substrate or in the developed photoresist material may be in the shape of a round hole, a groove, a long slit, or the like. The sides of the through holes may have rounded edges, non-orthogonal, stepped, or many other shapes. The developed photoresist material is the primary electronic insulating material used between the via conductor and the substrate, but other materials may also be used in conjunction with the developed photoresist material to support the same purpose. For example, all of the sidewalls around the via do not necessarily require a developed photoresist material; the developed photoresist material does not necessarily have to cover the full depth of the via. However, in the through-hole structure of the present invention, the developed photoresist material should cover a depth of more than half of a through hole. The conductor material does not always fill the entire through hole. Sometimes, the conductor material may be a film attached to the side of the through hole. As shown in the example procedure of Figure 16 (a-p), the vias do not necessarily open in a single process.

Figure 16 (a) is a cross-sectional view of a substrate (120). In the examples in Figures 15 (ah) and 16 (ap), electrical components such as integrated circuits, transistors, diodes, capacitors, resistors, and/or other components may have been built on the germanium substrate (120); These components are not drawn in those figures. In this example, shallow holes (141-143) of various shapes are opened on the front side of the substrate as shown in cross-sectional view 16(b) and top view 16(c). The term "shallow hole" as used in the present invention is a hole that does not completely penetrate the substrate, as opposed to the through hole. Can be used to open shallow holes in processes such as etching, cutting, laser cutting, and/or ion beam milling. Opening a shallow hole can usually be more precise than opening a through hole. To form an insulating material covering those shallow holes (141-143), a photoresist material (160) is laid on the surface of the substrate as shown in Fig. 16(d). The photoresist material (160) is selectively exposed to radiation (144) according to the mode defined by the reticle (140), as shown in Figure 16(e). The photoresist in this example is a photoresist, and the photoresist (162) exposed to radiation becomes a wash-resistant photoresist; positive photoresist can also be used, but the pattern of the mask (151) is black and white. After the cleaning process, the developed photoresist material (162) remains on the germanium substrate (120) while the remaining photoresist material is washed away as shown in Figure 16(f). During this process, various shaped holes (147-149) are opened within the developed photoresist material (162). Other types of methods, such as oxidation, can also be used to make this insulating layer (162). After the insulating layer is formed, the conductor films (131, 132) are laid on the front side as shown in cross-sectional view 16 (g) and top view 16 (h). In this example, the two conductor films (131, 132) are defined as rectangles with long turns pointing in different directions. No conductor film is laid in the slit-shaped hole (149) as shown in Fig. 16 (g, h).

After the above-described process on the front surface of the substrate is completed, the shallow holes (133, 134) are opened on the back surface of the substrate as shown in the cross-sectional view of Fig. 16(i) and the bottom view of Fig. 16(j). Cutting, etching, laser cutting, ion beam milling, and/or other methods can be used to open shallow holes. These holes (133, 134) are opened to a sufficient depth to reach the shallow holes (141-143) on the front side, the insulator (162), and the conductor film (131, 132) as shown in Fig. 16(i). The photoresist material (161) is laid on the back side, as shown in Fig. 16(k), and then the photoresist (161) on the back surface is irradiated with the radiation (146) defined by the photomask (145), as shown in Fig. 16(l). Show. The photoresist in this example is a photoresist, and the photoresist (162) exposed to radiation becomes a wash-resistant photoresist; positive photoresist can also be used, but the pattern of the mask (151) is black and white. After the cleaning process, the developed photoresist material (166) remains on the back side of the germanium substrate (120) while the remaining photoresist material is washed away as shown in Figure 16(m). During this process, various shaped apertures (167-169) are opened within the developed photoresist material (166). The shallow holes (147-149) opened from the front side are combined with the shallow holes (167-169) opened from the back side to form through holes in the insulating material. This structure allows more front area to be used to build electronic components and achieve better accuracy. Cost-effectiveness is another advantage. The conductor film (137, 138) can be laid on the back side, from the back hole (167-168), combined with the front conductor film (131, 132) to form a through hole connection, as shown in Figure 16 (n) and Figure 16 (o) The bottom view is shown in the top view of Figure 16(p). Such conductor films can be laid by sputtering, printing, electroplating, chemical metal processing, and/or other methods. In this example, the back conductor film (137, 138) is defined as a rectangle with a long 邉 perpendicular to the rectangular length of the front conductor film (131, 132) to provide better alignment tolerance, as shown in Figure 17 (h, i). Shown. In this example, no conductor film is laid in the slit-shaped hole (169), so that the slit-shaped hole (169) formed from the back surface and the slit-shaped hole (149) formed from the front surface are combined into a slit-shaped passage. The hole, as shown in Figure 16 (np), supports the function of the scribe line. The opening (149) of the scribe line opened using this method can be narrow - for example, narrower than 10 microns - so that the scribe line can be significantly narrower than conventional scribe lines. It is even possible to create a wafer without a front scribe line using this method.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. For example, the front insulator can be fabricated without using a developed photoresist material. These front structures can be fabricated using a typical integrated circuit fabrication process. Therefore, the insulator via holes are not necessarily formed entirely inside the developed photoresist material. The advantages of the present invention are generally seen when more than half of the vias are defined by a developed photoresist material. It is often advantageous to open smaller front holes and larger back holes, which allows more front area to be used to build electronic components. The structure shown in the above example is simplified and simplified. The front and back structures can have a wide variety of shapes. The conductor material does not always completely fill the via. The back hole may reach a plurality of front holes or a portion of the front holes to form through holes. The front face may also reach a plurality of back or back holes to form a through hole. A through hole of the present invention can also be established in more than two steps.

Figure 17 (a) is a simplified view of a single crystal germanium substrate (49) comprising a plurality of crystal grains. Fig. 17 (b) shows an enlarged view of four crystal grains (170-173) on the ruthenium substrate in Fig. 17 (a). Adjacent grains are separated by dicing streets (174, 175). In this example, the integrated circuit in each wafer includes an integrated circuit memory device (Mem), a logic circuit (Lg), a power bond pad (Pr), and a ground bond pad (Gn). The structure of integrated circuits is very complex, and a simplified symbol block diagram is used to represent them. Typical examples of memory components are non-electrical memory, dynamic random access memory (DRAM), and static random access memory (SRAM).

After the IC fabrication process is completed, edge conductor pins (177) and via connections (179) are fabricated on the die (170-173) as shown in Figure 7(c). The horizontal cutting path (175) shown in this example is narrower than the example shown in Fig. 11(b) because the present invention can use the cutting path shown in Fig. 16(n). A large number of via connections (179) can be fabricated in a small area using the structures (131, 132, 137, 138) disclosed in the above examples. In this example, the edge conductor pin (177) is fabricated using a structure (155) similar to the example shown in Figure 15(h). After wafer level processing, the die (170) on the wafer (49) is divided into individual dies having a structure as shown in Figure 17(d). Fig. 17(e) shows an example in which four crystal grains (170-173) are stacked. The power and ground lines of the die stack are connected to the edge conductor pins (177). The signal connections between the dies are mostly achieved by the via connections (179) without the use of bond pads, so the area efficiency of these integrated circuit components (170-173) is better than conventional methods. Sometimes another die (IOC) can be placed over the die stack of Figure 17(e), as shown in Figure 17(f). The die (IOC) has via connections (179) connected to other die (170-173), bond pads (IOP) to support external connections, and input/output (IO) control circuitry to control input/output. activity. This separates the core circuitry from the input/output circuitry, enabling significant cost savings.

A simplified view of Fig. 17(g) shows a cross-sectional view of the via connection (179) used in the die stack of Fig. 17(f). The structure of the via connections on each of the dies (10c, 170-173) is similar to the structure in Fig. 16(n). The front conductor film (131-132) on each of the dies is connected to the back conductor film (137, 138) of the die stacked thereon to form an electronic connection through the die stack (10c, 170-173). The impedance of such via connections (179) is typically much lower than that of conventional cross-die connections, allowing for high speed communication that is not possible with conventional methods. The above via connections are designed to tolerate errors in alignment. The top view of Fig. 17(h) shows the case where the front surface conductor film (131-132) is perfectly connected to the back surface conductor film (137, 138). The shape of each pair of conductor films (131, 137) (132, 138) points in different directions, so when the alignment is not perfect, as shown in Fig. 17 (i), the electronic connection is still effective.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the specific embodiments discussed herein are not to be construed as limiting the scope of the invention. For example, the front and back conductor films shown in the above example are aligned on the same vertical line, and they can be stacked at different locations; the shape of these conductor films need not be rectangular. The via connections in the above example are only used for communication between the die within the die, and the via connections can also support external communication.

While the invention has been described with respect to the specific embodiments of the present invention, other modifications and changes will be apparent to those skilled in the art. Therefore, the following claims are intended to cover the modifications and variations of the invention

100. . . Wafer

101. . . Horizontal cutting

102. . . Vertical cutting

105. . . Photoresist

110. . . Surface particle

111. . . flat

113. . . sample

115. . . Photoresist layer

120. . .矽 substrate

121. . . Through hole

122. . . Insulation Materials

123. . . Photoresist material

124. . . Mask

125. . . radiation

126. . . Radiation area photoresist

127. . . Through hole

128. . . Conductor film

131. . . Conductor film

132. . . Conductor film

133. . . Shallow hole

134. . . Shallow hole

137. . . Conductor film

138. . . Conductor film

140. . . Mask

141~143. . . Shallow hole

144. . . radiation

145. . . Mask

146. . . radiation

147~149. . . hole

150. . . Photoresist material

151. . . Mask

152. . . radiation

154. . . cutting line

155. . . Conductor material (side conductor pin)

156. . . Through hole

157. . . Conductor material

158. . . Through hole

159. . . Photoresist material

160. . . Photoresist material

161. . . Photoresist material

162. . . Photoresist material

167~169. . . Shallow hole

170~173. . . Grain

174. . . cutting line

175. . . cutting line

177. . . Edge conductor pin

179. . . Through hole connection

200. . . Grain

201. . . Crashing diode

202. . . capacitance

203. . . resistance

208. . . cutting line

209. . . Single crystal semiconductor wafer

210. . . aisle

211. . . Bonding lead

212. . . Mat

214. . . External metal pin (package pin)

215. . . Metal wire (lead frame)

216. . . Ground wire bond pad

218. . . Bonding lead

219. . . Integrated circuit package

222. . . Semiconductor component

242. . . BGA substrate

245. . . Metal ball

246. . . metal wires

247. . . Through hole

248. . . Gasket

249. . . Welding ball

300. . . Substrate

301. . . conductor

302. . . Thin film resistor

303. . . Protective insulation

304. . . Electrode layer

305. . . Side conductor

310. . . Wafer

365. . . Edge conductor pin

368. . . Wafer

370. . . Wafer

378. . . Wafer

380. . . Wafer

385. . . Groove

400. . . Wafer

401. . . conductor

404. . . Insulation

405. . . Electrode layer

469. . . Molded substrate

475. . . Edge conductor pin

476. . . Edge conductor pin

477. . . Edge conductor pin

485. . . I/O edge conductor pin

486. . . Ground wire edge conductor pin

487. . . Power cord edge conductor pin

489. . . Wafer

498. . . roller

499. . . Wafer

501. . . Conductor ball

503. . . The protective layer

505. . . The protective layer

507. . . Under bump metal layer (UBM)

530. . . A printed circuit board

531. . . Welded plate

532. . . Solder paste

540. . . Wafer

541. . . Grain

542. . . Side conductor pin

543. . . Solder paste

601. . . Substrate

602. . . Conductor layer

603. . . Non-crystal semiconductor

604. . . Non-crystal semiconductor

605. . . Shield

610. . . Electronic diode

611. . . Printed insulation

612. . . Conductor layer

615. . . Insulation

701. . . Substrate

702. . . (first layer) non-single crystal semiconductor

703. . . (second layer) non-single crystal semiconductor

710. . . Electronic diode

711. . . Insulator protection layer

712. . . conductor

801. . . Substrate

802. . . Mold

803. . . roller

804. . . Printed pattern

805. . . material

811. . . Substrate

812. . . Print head

813. . . ink

815. . . pattern

830. . . Substrate

831. . . Ink line

833. . . mode

891. . . Substrate

893. . . roller

894. . . mode

895. . . mode

901. . . Circuit board

902. . . Surface conductor line

903. . . (first layer) non-single crystal semiconductor

904. . . (second layer) non-single crystal semiconductor

905. . . Insulator protection layer

909. . . Electronic diode

7~10. . . Grain

12. . . Dry ink side insulation

14. . . Insulator protective film

twenty one. . . Dry ink side insulation

twenty three. . . Dry ink side conductor pin

twenty four. . . Dry ink side conductor pin

27. . . Ink

28. . . Wafer

29. . . Ink conductor line

31. . . tape

32. . . Insulation

41. . . Mat

42. . . Side conductor pin

44. . . Insulator protective film

45. . . Insulator

48. . . cutting line

49. . .矽 substrate

50~53. . . Grain

54. . . Side conductor pin

59. . . Side conductor pin

60. . . Surface mount package (wafer)

61. . .矽 grain

62. . . Insulation

63. . .矽 grain

64. . .矽 grain

65. . . Cerium oxide and/or tantalum nitride film

66. . .矽 grain

67. . . Side conductor pin

68. . . Side conductor pin

69. . . Side conductor pin

70. . . Surface mount package (wafer)

71. . .矽 grain

72. . . Surface mount package (wafer)

73. . .矽 grain

74. . . Side conductor pin

75. . .矽 grain

76. . . Surface mount package (wafer)

77. . .矽 grain

78. . . Side conductor pin

79. . . Side conductor pin

80. . .矽 grain

82. . . Side conductor pin

85. . .矽 grain

86. . . Side conductor pin

87. . . Surface mount package (wafer)

98. . . Cutting line (cutting line)

99. . . Single crystal germanium substrate

Figure 1 (ag) is a schematic diagram of an electronic diode and an ESD protection circuit; Figure 2 (af) illustrates the structure of a prior art ESD protection wafer; Figure 3 (ak) simplifies the symbolicity of the prior art resistive wafer printing process Figure 4 (ai) is a simplified symbolic diagram illustrating how to use a resistive wafer printing process to package an ESD-protected wafer; Figure 5 (ac) is a simplified symbolic diagram illustrating how to use the tin of the conductor pins The ball encapsulates another ESD protection wafer; Figure 6 (ai) is a symbolic simplified diagram of a non-single-crystal electronic semiconductor diode manufacturing process; Figure 7 (ae) is a simplified symbolic diagram illustrating another type of non- Single crystal semiconductor electronic diode manufacturing process; Figure 8 (ah) is a simplified symbolic figure, illustrating the electronic printing technology; Figure 9 (ad) is a cross section of the non-single crystal semiconductor electronic diode printed on the circuit board Figure 10 (as) is a simplified symbolic diagram illustrating how the side conductor pins are fabricated to mount the package on the grain level surface; Figure 11 (af) is a simplified symbolic diagram illustrating how to use the side conductor pins Stacking multiple grains into a grain-level surface Figure 12 (ak) illustrates how the side body pins are applied to different types of active components and integrated circuits; Figure 13 (af) shows an example of using photoresist as an insulating material; Figure 14 (al) shows the previous Technical through-hole manufacturing procedure; Figure 15 (ah) is a simplified symbolic diagram illustrating the procedure by which the developed photoresist material of the present invention is used to form vias; Figure 16 (ap) is a simplified symbolic diagram, an example A manufacturing procedure illustrating how to open holes from both sides of the semiconductor substrate to form via holes; and FIG. 17(ai) shows an example of using the via connection of the present invention to stack integrated circuit dies.

120. . .矽 substrate

121. . . Through hole

154. . . cutting line

155. . . Side conductor pin

156. . . Through hole

157. . . Conductor material

158. . . Through hole

159. . . Photoresist material

Claims (20)

An electronic component comprising: a substrate; at least one via hole disposed on the germanium substrate; a developed photoresist material disposed inside the via hole on the germanium substrate; a hole in the developed photoresist material, and The hole extends to a depth that exceeds a depth of one half of the through hole on the germanium substrate; and a via hole conductor material that provides a front surface of the germanium substrate to the germanium substrate via the hole in the developed photoresist material Electronic connection on the back. The electronic component of claim 1, wherein the developed photoresist material inside the via hole on the germanium substrate defines two or more of the holes, and the holes extend deeper than the germanium substrate The depth of one half of the through hole. The electronic component according to claim 1, wherein the through hole on the cymbal substrate is a through hole formed by combining a hole opened from a front surface of the cymbal substrate and a hole opened from a back surface of the cymbal substrate. The electronic component of claim 1, wherein the via conductor material forms a conductor pin on a side of the germanium substrate. The electronic component of claim 1 further comprising at least one integrated circuit on the germanium substrate. The electronic component of claim 5, further comprising at least one memory component on the germanium substrate. The electronic component of claim 6, wherein the memory component is a dynamic random memory component. The electronic component of claim 6, wherein the memory component is a non-electrical memory component. The electronic component of claim 6, wherein the memory component is a static random memory component. A method of manufacturing an electronic component on a germanium substrate, comprising the steps of: opening at least one via on a germanium substrate; laying a developed photoresist material in the via; defining at least one hole in the developed photoresist material, and half the depth of the hole depth of the through hole extending beyond the silicon based plate; and overlaid with a through-hole conductor material, the conductor material through the hole in the developed photoresist material is _provided on the front surface of the silicon substrate to the silicon Electronic connection on the back of the substrate. The method of claim 10, further comprising: defining two or more of the holes in the developed photoresist material inside the through hole on the substrate, and the holes extend to a depth exceeding the 矽The depth of one half of the through hole on the substrate. The method of claim 10, wherein the step of opening the through hole on the crucible substrate further comprises: a step of opening a hole from a front surface of the crucible substrate, and a step of opening a hole from a back surface of the crucible substrate, And the depth of the two holes is not deeper than the depth of the germanium substrate, but the hole opened from the front surface of the germanium substrate and the hole opened from the back surface of the germanium substrate are combined to form the through hole on the germanium substrate. The method of claim 10, further comprising the step of forming a side conductor pin of the germanium substrate using a via conductor material. The method of claim 10, further comprising the step of fabricating at least one integrated circuit component on the germanium substrate. The method of claim 14, further comprising the step of fabricating a memory component on the germanium substrate. The method of claim 15, wherein the memory component is a dynamic random memory component. The method of claim 15, wherein the memory component is a non-electrical memory component. The method of claim 15, wherein the memory component is a static random memory component. A method of opening a through hole on a ruthenium substrate, comprising the steps of: opening a first hole from a front surface of a ruthenium substrate, and the depth of the first hole is shallower than a depth of the ruthenium substrate; opening a back from the back surface of the ruthenium substrate a second hole, wherein the depth of the second hole is shallower than a depth of the germanium substrate; and the first hole opened from the front surface of the germanium substrate and the second hole opened from the back surface of the germanium substrate are combined on the germanium substrate Through hole. The method of claim 19, wherein the first opening opened from the front side of the crucible substrate is narrower than 10 microns.