CN101026140A - Substrate for forming semiconductor element and manufacturing method of the semiconductor element - Google Patents
Substrate for forming semiconductor element and manufacturing method of the semiconductor element Download PDFInfo
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- CN101026140A CN101026140A CNA2007100789972A CN200710078997A CN101026140A CN 101026140 A CN101026140 A CN 101026140A CN A2007100789972 A CNA2007100789972 A CN A2007100789972A CN 200710078997 A CN200710078997 A CN 200710078997A CN 101026140 A CN101026140 A CN 101026140A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Dicing (AREA)
- Electroplating Methods And Accessories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a semiconductor board and a method for manufacturing semiconductor element. When the post electrodes are formed to the silicon board 2 under the wafer state with the semiconductor-element forming region 1A and the alignment-mark forming region 21A in the same plane size as the semiconductor-element forming region 1A by the electroplating, a plurality of the post electrodes 10 are formed to the semiconductor-element forming region 1A. The post electrodes 22 and 23 for the alignment and a plurality of dummy post electrodes 24 are formed in the alignment-mark forming region 21A in this case. The partial concentration and increase of the plating current can be prevented by forming the dummy post electrodes 24 in this case.
Description
Technical field
The present invention relates to the manufacture method of semiconductor element formation with substrate and semiconductor element.
Background technology
In the manufacture method of semiconductor element formation, following method is arranged: form column (post) electrode on whole on the Semiconductor substrate in wafer state with substrate, on whole on the Semiconductor substrate of wafer state, cover the diaphragm seal of formation peripherally of columnar electrode, separate with each semiconductor element by scribing (dicing) then, obtain so-called wafer-class encapsulation body (WLP).At this moment, cover on whole on the Semiconductor substrate of wafer state columnar electrode formed diaphragm seal peripherally after, after promptly having formed columnar electrode, form solder ball at the upper surface of columnar electrode, when forming mark (marking) or carrying out scribing, need calibrate at the back side of the Semiconductor substrate of wafer state.
So, following method is arranged: in order after forming columnar electrode, positively to discern collimating marks in the manufacture method of existing semiconductor element, a plurality of semiconductor elements form the zone and planar dimension forms the Semiconductor substrate that the identical collimating marks in zone forms the zone with this semiconductor element and to possessing, when forming columnar electrode by metallide, form the zone at each semiconductor element and form a plurality of columnar electrodes respectively, form the zone in collimating marks and form calibration columnar electrode (for example with reference to patent documentation 1).
Patent documentation 1:(Japan) spy opens the 2005-93461 communique
But, in the manufacture method of the semiconductor element of in above-mentioned patent documentation 1, putting down in writing, form at each semiconductor element on almost whole of zone and be and form a plurality of columnar electrodes rectangularly, forming middle body that the identical collimating marks in zone forms the zone at planar dimension and semiconductor element and form calibration and use columnar electrode, is the white space that does not form columnar electrode so collimating marks forms the peripheral part in zone.
Its result, when using columnar electrode by metallide formation columnar electrode and calibration, because electroplating current density is certain, so form the zone forming the adjacent semiconductor element of the white space of peripheral part in zone with collimating marks, electroplating current is concentrated and is increased, be formed on this semiconductor element form the zone columnar electrode the plating growth failure accelerate, this columnar electrode forms the shape of distortion.And calibration also accelerates singularly with the plating growth of columnar electrode, and calibration forms the shape of distortion with columnar electrode.This situation, the size of the Semiconductor substrate of wafer state is big more just remarkable more, and electroplating velocity is remarkable.
Summary of the invention
So, the object of the present invention is to provide the manufacture method of a kind of semiconductor element with substrate and semiconductor element, columnar electrode and calibration are not the shape of distortion with columnar electrode.
In order to reach above-mentioned purpose, the semiconductor element substrate that the present invention relates to is characterized in that possessing: Semiconductor substrate (2); Having a plurality of semiconductor elements that comprise a plurality of connection pads (3) respectively forms zone (1A) and has with collimating marks that above-mentioned semiconductor element forms the identical planar dimension in zone (1A) and form zone (21A); A plurality of columnar electrodes (10) are formed on above-mentioned each semiconductor element and form in the zone (1A), at least with some electrical connection of above-mentioned connection pads (3); And illusory columnar electrode (24), be formed on above-mentioned collimating marks and form zone (21A), be not electrically connected with columnar electrode (22,23) and above-mentioned connection pads (3) than being formed on the calibration that above-mentioned columnar electrode (10) that above-mentioned each semiconductor element forms zone (1A) lacks with number.
And, the manufacture method of the semiconductor element that the present invention relates to, it is characterized in that: prepare Semiconductor substrate (2), this Semiconductor substrate (2) has a plurality of semiconductor elements that comprise a plurality of connection pads (3) respectively and forms zone (1A) and have with collimating marks that above-mentioned semiconductor element forms the identical planar dimension in zone (1A) and form zone (21A); Form zone (1A) at above-mentioned each semiconductor element, form some a plurality of columnar electrodes (10) that are electrically connected respectively with above-mentioned connection pads (3), and, form zone (21A) in above-mentioned collimating marks, form any calibration that is not electrically connected columnar electrode (22,23) and a plurality of illusory columnar electrode (24) with above-mentioned connection pads (3).
Effect of the present invention is as follows:
According to the present invention, because forming the zone in collimating marks forms calibration and also forms a plurality of illusory columnar electrodes outside with columnar electrode, increase so electroplating current can not concentrated partly, columnar electrode, calibration can not be the shape of distortion with columnar electrode and illusory columnar electrode then.
Description of drawings
Fig. 1 (A) is the vertical view that utilizes an example of the semiconductor element that manufacture method of the present invention makes, and Fig. 1 (B) is the profile along the IB-IB line of Fig. 1 (A).
Fig. 2 (A) is the vertical view of an example of the element of the band collimating marks that obtains simultaneously when making semiconductor element shown in Figure 1, and Fig. 2 (B) is the profile along the IIB-IIB line of Fig. 2 (A).
Fig. 3 is when making semiconductor element shown in Figure 1, the vertical view of the silicon substrate of the initial wafer state of preparing.
Fig. 4 is the profile along the IV-IV line of Fig. 3.
Fig. 5 is the profile of the operation of map interlinking 4.
Fig. 6 is the profile of the operation of map interlinking 5.
Fig. 7 is the profile of the operation of map interlinking 6.
Fig. 8 is the profile of the operation of map interlinking 7.
Fig. 9 is the profile of the operation of map interlinking 8.
Figure 10 is the profile of the operation of map interlinking 9.
Figure 11 is the profile of the operation of map interlinking 10.
Figure 12 is the profile of the operation of map interlinking 11.
Embodiment
Fig. 1 (A) is the vertical view that utilizes an example of the semiconductor element that manufacture method of the present invention makes, and Fig. 1 (B) is the profile along the IB-IB line of Fig. 1 (A).This semiconductor element 1 is known as CSP (chip size package: the die size packaging body), possess the silicon substrate 2 of plane square shape.At the upper surface of silicon substrate 2 integrated circuit (not shown) of predetermined function is set, at the upper surface periphery, a plurality of connection pads 3 that are made of aluminium metalloid etc. are connected setting with integrated circuit.
At the upper surface of the silicon substrate except that the central portion of connection pads 32, the dielectric film 4 that is made of silica or silicon nitride etc. is set, the central portion of connection pads 3 exposes via being arranged on the peristome 5 on the dielectric film 4.At the upper surface of dielectric film 4, the diaphragm 6 that epoxylite or polyimide based resin etc. constitute is set.With the dielectric film 6 of the peristome 5 corresponding parts of dielectric film 4 on peristome 7 is set.
At the upper surface of diaphragm 6, the substrate metal layer 8 that is made of copper etc. is set.In the entire upper surface of substrate metal layer 8, the wiring 9 that is made of copper etc. is set.An end that comprises the wiring 9 of substrate metal layer 8 is connected with connection pads 3 via the peristome 5,7 of dielectric film 4 and diaphragm 6.At wiring 9 connection pads portion upper surface, the columnar electrode 10 that is made of copper etc. is set.
At the upper surface that comprises wiring 9 diaphragm 6, the upper surface that the diaphragm seal 11 that is made of epoxylite or polyimide based resin etc. is configured to its upper surface and columnar electrode 10 is same plane.Therefore, the upper surface of columnar electrode 10 exposes.At this moment, the flat shape of columnar electrode 10 is circular.Then, the upper surface that exposes at the quilt of columnar electrode 10 is provided with solder ball 12.
Then, Fig. 2 (A) is the vertical view of an example of the element of the band collimating marks that obtains simultaneously when making semiconductor element 1 shown in Figure 1, and Fig. 2 (B) is the profile along the IIB-IIB line of Fig. 2 (A).The part-structure of the element 21 of this band collimating marks is identical with the part-structure of semiconductor element 1.
That is to say, in the part of the element 21 of being with collimating marks, upper surface at silicon substrate 2 with planar dimension identical with the planar dimension of the silicon substrate 2 of semiconductor element 1, the integrated circuit (not shown) of predetermined function is set, at the upper surface periphery a plurality of connection pads 3 are set with integrated circuit with being connected, upper surface at the silicon substrate except that the central portion of connection pads 32 is provided with dielectric film 4, and the central portion of connection pads 3 exposes via the peristome 5 that is arranged on the dielectric film 4.
Then, in other parts of element 21 of band collimating marks, diaphragm 6 is set at the upper surface of the dielectric film 4 of the upper surface that comprises the connection pads of exposing via peristome 53.At this moment, with the dielectric film 6 of the peristome 5 corresponding parts of dielectric film 4 on peristome is not set.
In the upper face center portion of diaphragm 6 and a predetermined position of upper surface substrate metal layer 8a, 8b are set, a plurality of substrate metal layer 8c are set at the upper surface periphery.The entire upper surface of substrate metal layer 8a, 8b, 8c is provided with illusory wiring 9a, 9b, 9c.At this moment, comprise that illusory wiring 9a, 9b, the 9c of substrate metal layer 8a, 8b, 8c only is made of connection pads portion, on electricity, everywhere do not connect.
Upper surface at illusory wiring 9a, 9b, 9c is provided with temporary transient calibration columnar electrode 22, formal calibration columnar electrode 23 and illusory columnar electrode 24.At the upper surface of diaphragm 6, it is same plane with columnar electrode 22, formal calibration with the upper surface of columnar electrode 23 and illusory columnar electrode 24 with temporary transient calibration that diaphragm seal 11 is configured to its upper surface.
At this moment, temporary transient calibration is circular with the flat shape of columnar electrode 22.Flat shape circular different of columnar electrode 22 are used in formal calibration with the flat shape of columnar electrode 23 and temporary transient calibration, be roughly cross shape.The flat shape of illusory columnar electrode 24 is circular.
At this, an example of size is described.The flat shape of illusory columnar electrode 24 and configuration section are apart from identical with columnar electrode 10.That is to say that the diameter of illusory columnar electrode 24 and columnar electrode 10 is 0.2mm, the configuration section distance is 0.4mm.And, in Fig. 1 and Fig. 2,, illustrate 19 illusory columnar electrodes 24 and reach and 25 columnar electrodes 10, but actual bar number is total to hundreds of for the ease of diagram.
Temporary transient calibration is the members that are used to carry out the temporary transient location of the silicon substrate that is used for wafer state as described later with columnar electrode 22, forms greatlyyer, and for example diameter is 0.75mm.Formal calibration is the members that are used to carry out the formal location of the silicon substrate that is used for wafer state as described later with columnar electrode 23, forms lessly, and for example, the length on one side is in the square area of 0.45mm, roughly forms cross shape with live width 0.15mm.
Then, an example to the manufacture method of the semiconductor element 1 of above-mentioned formation describes.At first, as shown in Figure 3, prepare the silicon substrate (Semiconductor substrate) 2 of wafer state.At this, in Fig. 3, in the square that is surrounded by ordinate and horizontal line, unimpressed zone is that semiconductor element forms regional 1A, and the zone of * marking is that collimating marks forms regional 21A.At this moment, collimating marks forms regional 21A to be had with semiconductor element and forms the identical planar dimension of regional 1A, is arranged on upper left, upper right, lower-left and these 4 positions, bottom right of the silicon substrate substrate 2 of wafer state.
Then, Fig. 4 is the profile along the IV-IV line of Fig. 3.Under this state, semiconductor element forms regional 1A and collimating marks, and to form regional 21A be same structure.That is to say, form integrated circuit (scheming not shown), form the connection pads 3 that constitutes by aluminium metalloid layer etc. at upper surface periphery and integrated circuit with being connected at the upper surface that respectively forms regional 1A, 21A of the silicon substrate 2 of wafer state.
At the upper surface of the silicon substrate except that the central portion of connection pads 32, the dielectric film 4 that is made of silica etc. is set, the central portion of connection pads 3 exposes via being arranged on the peristome 5 on the dielectric film 4.And, form regional 21A and semiconductor element in collimating marks and form scribe line 31 is set between the regional 1A.
Then, as shown in Figure 5,, form the diaphragm 6 that constitutes by epoxylite etc. by plasma CVD method in the entire upper surface of the dielectric film 4 of the upper surface that comprises the connection pads of exposing via peristome 53.Then, utilize photoetching process, form at semiconductor element on the diaphragm 6 of regional 1A and peristome 5 corresponding parts dielectric film 4 and form peristome 7.At this moment, form among the regional 21A in collimating marks, with the diaphragm 6 of the peristome 5 corresponding parts of dielectric film 4 on do not form peristome.
Then, as shown in Figure 6, the entire upper surface of diaphragm 6 that forms the upper surface that comprises the connection pads 3 that the peristome 5,7 via dielectric film 4 and diaphragm 6 exposes of regional 1A at semiconductor element forms substrate metal layer 8.At this moment, substrate metal layer 8 can only be the copper layer that forms by plated by electroless plating (chemical plating), also can be the copper layer that only forms by sputter, can also be to form the copper layer by sputter on the thin layers such as titanium that form by sputter.
Then, the upper surface composition at substrate metal layer 8 forms anti-plated film 32.At this moment, forming the anti-plated film 32 in the regional corresponding part, form peristome 33,33a, 33b, 33c with wiring 9,9a, 9b, 9c.Then, by carrying out with the metallide of substrate metal layer 8 the upper surface formation wiring 9 of the substrate metal layer 8 in the peristome 33 of preventing plated film 32,33a, 33b, 33c, 9a, 9b, 9c as the copper of electroplating current path.Then, peel off anti-plated film 32.
Then, as shown in Figure 7, form anti-plated film 34 at the upper surface composition of the substrate metal layer 8 that comprises wiring 9,9a, 9b, 9c.At this moment; form zone, temporary transient calibration at columnar electrode 10 and form zone, formal calibration with columnar electrode 32 and form zone and illusory columnar electrode 24 with columnar electrode 32 and form on the diaphragm 34 in the area relative part, form peristome 35,36,37,38.
Then, by carrying out with the metallide of substrate metal layer 8 as the copper of electroplating current path, form among the regional 1A at semiconductor element, the connection pads portion upper surface of the wiring 9 in the peristome 35 of anti-plated film 34 forms columnar electrode 10, form among the regional 21A in collimating marks, illusory wiring 9a, 9b in the peristome 36,37,38 of anti-plated film 34, the upper surface of 9c form and temporarily calibrate with columnar electrode 22, formal calibration columnar electrode 23 and illusory columnar electrode 24.
So, also form a plurality of illusory columnar electrodes 24 owing to form regional 21A formation calibration in addition with columnar electrode 22,23 in collimating marks, increase so electroplating current can not concentrated partly, columnar electrode 10, calibration can not be the shape of distortion with columnar electrode 22,23 and illusory columnar electrode 24 then.
Then, peel off anti-plated film 34.Then, if forming among the regional 1A to connect up at semiconductor element 9 is mask, forming among the regional 21A with each columnar electrode 22,23,24 in collimating marks is mask, the unwanted part of substrate metal layer 8 is removed in etching, then as shown in Figure 8, only residual substrate metal layer 8,8a, 8b, 8c under wiring 9,9a, 9b, 9c.
Then; as shown in Figure 9; by silk screen print method, spin coating method; entire upper surface at the diaphragm 6 that comprises wiring 9 and each columnar electrode 10,22,23,24 forms the diaphragm seal 11 that is made of epoxylite etc., and its thickness is thicker slightly than the height of each columnar electrode 10,22,23,24.Therefore, under this state, the upper surface of each columnar electrode 10,22,23,24 is covered by diaphragm seal 11.
Then, by suitably grinding the upper surface side of removing diaphragm seal 11 and each columnar electrode 10,22,23,24, as shown in figure 10, the upper surface of each columnar electrode 10,22,23,24 is exposed, and make the upper surface of diaphragm seal 11 of upper surface of each columnar electrode 10,22,23,24 that comprises that this exposes smooth.
Then, as shown in figure 11, the upper surface that forms the columnar electrode 10 among the regional 1A at semiconductor element forms solder ball 12.Then, at the lower surface of the silicon substrate 2 of wafer state, form predetermined mark (marking) at the predetermined position that forms the corresponding zone of regional 1A with each semiconductor element.So, constituting semiconductor element forms with substrate 100.Then, as shown in figure 12, form with substrate 100, then obtain the semiconductor element 1 shown in a plurality of Fig. 1 (A), (B), and obtain the element 21 of the band collimating marks shown in 4 Fig. 2 (A), (B) if cut off semiconductor element with scribe line 31.
But the solder ball 12 after columnar electrode 10 forms operation forms operation, mark (marking) forms in operation and the scribing operation, need carry out the position alignment of the silicon substrate 2 of wafer state.And, before the upper surface of each columnar electrode 10 forms solder ball 12, at the upper surface printing solder layer of each columnar electrode 10, also need position alignment in this case sometimes.Moreover, form the contact of carrying out electricity after the operation before the scribing operation at mark (marking) and check under the situation of operation, also need the position alignment of the silicon substrate 2 of wafer state.
In this case, will form calibration that regional 21A forms in collimating marks uses as collimating marks with columnar electrode 22,23.At this moment, temporary transient calibration is circular with the flat shape of columnar electrode 22, identical with the flat shape of columnar electrode 10, temporary transient calibration is 0.75mm with the diameter of columnar electrode 22, diameter 0.2mm than columnar electrode 10 is a lot of greatly, and be formed on collimating marks and form regional 21A, so columnar electrode 10 can be identified as by mistake.
But temporary transient calibration is the members of temporary transient location that are used to carry out the silicon substrate 2 of wafer state with columnar electrode 23, and formally calibrating with columnar electrode 23 is the members of formal location that are used to carry out the silicon substrate 2 of wafer state.At this, for example in dicing device, possess temporary transient location and use video camera with video camera and formal the location.At this moment, temporary transient location is the video camera that field range is big, the lens multiplying power is lower with video camera, and formally locating with video camera is the video camera that field range is narrower, the lens multiplying power is higher.
In addition, temporary transient location is accommodated in formal location with carrying out in the field range of video camera for the formal calibration on the silicon substrate 2 that makes wafer state with columnar electrode 23.Formal location is the location behind the temporary transient location, so can carry out high-precision location for the scribe line 31 that makes the scribing saw cut off the silicon substrate 2 of wafer state exactly under the situation of dicing device carries out.
And, at this moment, make circular different with the flat shape of the flat shape of columnar electrode 23 and formal calibration usefulness columnar electrode 22 of formal calibration, be roughly cross shape, so two calibrations can not confused with columnar electrode 22,23, can positively prevent the generation of collimating marks mistake identification.
And temporary transient calibration is not limited to circle with the flat shape of columnar electrode 22, for example also can be square.And formal calibration is not limited to be roughly cross shape with the flat shape of columnar electrode 23, for example also can be roughly the L word shape.
Claims (17)
1. a semiconductor element forms and uses substrate, it is characterized in that possessing:
Semiconductor substrate (2) has a plurality of semiconductor elements that comprise a plurality of connection pads (3) respectively and forms zone (1A) and have with collimating marks that above-mentioned semiconductor element forms the identical planar dimension in zone (1A) and form zone (21A);
A plurality of columnar electrodes (10) are formed on above-mentioned each semiconductor element and form in the zone (1A), at least with some electrical connection of above-mentioned connection pads (3); And
Illusory columnar electrode (24), be formed on above-mentioned collimating marks and form zone (21A), be not electrically connected with columnar electrode (22,23) and above-mentioned connection pads (3) than being formed on the calibration that above-mentioned columnar electrode (10) that above-mentioned each semiconductor element forms zone (1A) lacks with number.
2. semiconductor element as claimed in claim 1 forms and uses substrate, it is characterized in that,
Above-mentioned illusory columnar electrode (24) is configured in the periphery that above-mentioned each collimating marks forms zone (21A) at least.
3. semiconductor element as claimed in claim 2 forms and uses substrate, it is characterized in that,
The flat shape of above-mentioned illusory columnar electrode (24) is identical with above-mentioned columnar electrode (10).
4. semiconductor element as claimed in claim 3 forms and uses substrate, it is characterized in that,
The configuration section of above-mentioned illusory columnar electrode (24) is apart from identical with above-mentioned columnar electrode (10).
5. semiconductor element as claimed in claim 1 forms and uses substrate, it is characterized in that,
Above-mentioned calibration is mutual different shape with columnar electrode (22,23), by the temporary transient calibration that is used to temporarily locate with columnar electrode (22) and the formal calibration that is used to formally locate with columnar electrode (23) formation.
6. semiconductor element as claimed in claim 5 forms and uses substrate, it is characterized in that,
Above-mentioned temporary transient calibration is circular or square with the flat shape of columnar electrode (22), and above-mentioned formal calibration is roughly cross shape or roughly L word shape with the flat shape of columnar electrode (23).
7. semiconductor element as claimed in claim 1 forms and uses substrate, it is characterized in that,
Above-mentioned calibration comprise with columnar electrode (22,23) the temporary transient calibration that is used to temporarily locate with columnar electrode (22) and the formal calibration that is used to formally locate with columnar electrode (23), temporary transient calibration with the size of the upper surface of columnar electrode (22) greater than the size of above-mentioned formal calibration with the upper surface of columnar electrode (23).
8. semiconductor element as claimed in claim 1 forms and uses substrate, it is characterized in that,
On above-mentioned Semiconductor substrate (2), has diaphragm (6); this diaphragm (6) has the peristome (7) that exposes above-mentioned connection pads (3), and above-mentioned columnar electrode (10), above-mentioned calibration are formed on (6) on the said protection film with columnar electrode (22,23) and illusory columnar electrode (24).
9. semiconductor element as claimed in claim 8 forms and uses substrate, it is characterized in that,
Above-mentioned connection pads (3) also is formed on above-mentioned each semiconductor element and forms in the zone (1A).
10. the manufacture method of a semiconductor element is characterized in that:
Prepare Semiconductor substrate (2), this Semiconductor substrate (2) has a plurality of semiconductor elements that comprise a plurality of connection pads (3) respectively and forms zone (1A) and have with collimating marks that above-mentioned semiconductor element forms the identical planar dimension in zone (1A) and form zone (21A);
Form zone (1A) at above-mentioned each semiconductor element, form some a plurality of columnar electrodes (10) that are electrically connected respectively with above-mentioned connection pads (3), and, form zone (21A) in above-mentioned collimating marks, form any calibration that is not electrically connected columnar electrode (22,23) and a plurality of illusory columnar electrode (24) with above-mentioned connection pads (3).
11. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that,
Each semiconductor element forms the above-mentioned calibration that the above-mentioned columnar electrode (10) in zone (1A), above-mentioned collimating marks form zone (21A) and forms simultaneously with columnar electrode (22,23) and a plurality of illusory columnar electrode (24).
12. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that,
Above-mentioned illusory columnar electrode (24) is configured in the periphery that above-mentioned each collimating marks forms zone (21A) at least.
13. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that,
Above-mentioned calibration is mutual different shape with columnar electrode (22,23), by the temporary transient calibration that is used to temporarily locate with columnar electrode (22) and the formal calibration that is used to formally locate with columnar electrode (23) formation.
14. the manufacture method of semiconductor element as claimed in claim 13 is characterized in that,
Above-mentioned temporary transient calibration is circular or square with the flat shape of columnar electrode (22), and above-mentioned formal calibration is roughly cross shape or roughly L word shape with the flat shape of columnar electrode (23).
15. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that,
Above-mentioned calibration comprise with columnar electrode (22,23) the temporary transient calibration that is used to temporarily locate with columnar electrode (22) and the formal calibration that is used to formally locate with columnar electrode (23), temporary transient calibration with the size of the upper surface of columnar electrode (22) greater than the size of above-mentioned formal calibration with the upper surface of columnar electrode (23).
16. the manufacture method of semiconductor element as claimed in claim 15 is characterized in that,
Use columnar electrode (23) afterwards in formation above-mentioned columnar electrode (10), temporary transient calibration with columnar electrode (22) and above-mentioned formal calibration, re-use above-mentioned temporary transient calibration with the temporary transient collimating marks of columnar electrode (22) conduct, then use above-mentioned formal calibration to carry out the position alignment of above-mentioned Semiconductor substrate (2) as formal collimating marks with columnar electrode (23).
17. the manufacture method of semiconductor element as claimed in claim 16 is characterized in that,
The operation of carrying out the position alignment of above-mentioned Semiconductor substrate comprises that solder ball forms, mark forms, arbitrary operation of scribing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006039135A JP2007220870A (en) | 2006-02-16 | 2006-02-16 | Semiconductor board and method for manufacturing semiconductor element |
| JP039135/2006 | 2006-02-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101026140A true CN101026140A (en) | 2007-08-29 |
| CN100468714C CN100468714C (en) | 2009-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2007100789972A Expired - Fee Related CN100468714C (en) | 2006-02-16 | 2007-02-16 | Substrate for forming semiconductor element and manufacturing method of the semiconductor element |
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| Country | Link |
|---|---|
| JP (1) | JP2007220870A (en) |
| KR (1) | KR100858386B1 (en) |
| CN (1) | CN100468714C (en) |
| TW (1) | TWI353028B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097414A (en) * | 2010-11-24 | 2011-06-15 | 日月光半导体制造股份有限公司 | Semiconductor device with marked conduction columns |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5007250B2 (en) * | 2008-02-14 | 2012-08-22 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP5363034B2 (en) | 2008-06-09 | 2013-12-11 | ラピスセミコンダクタ株式会社 | Semiconductor substrate and manufacturing method thereof |
| US8251601B2 (en) * | 2010-12-21 | 2012-08-28 | Visera Technologies Company Limited | Camera module and method for fabricating the same |
| JP5503790B2 (en) * | 2013-09-05 | 2014-05-28 | ラピスセミコンダクタ株式会社 | Semiconductor substrate |
| US9589900B2 (en) | 2014-02-27 | 2017-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal pad for laser marking |
| US9666522B2 (en) | 2014-05-29 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment mark design for packages |
| TWI611486B (en) * | 2014-12-31 | 2018-01-11 | 矽品精密工業股份有限公司 | Semiconductor structure and fabrication method thereof |
| JP6527269B2 (en) * | 2018-04-18 | 2019-06-05 | ラピスセミコンダクタ株式会社 | Semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2674528B2 (en) * | 1994-09-21 | 1997-11-12 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH09306914A (en) * | 1996-05-16 | 1997-11-28 | Oki Electric Ind Co Ltd | Wiring forming method of semiconductor element |
| JP3424164B2 (en) * | 1998-12-24 | 2003-07-07 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| JP3843919B2 (en) * | 2002-09-09 | 2006-11-08 | 株式会社デンソー | Semiconductor wafer plating method |
| JP4292041B2 (en) * | 2003-09-12 | 2009-07-08 | カシオ計算機株式会社 | Semiconductor substrate, semiconductor substrate manufacturing method, and semiconductor device manufacturing method |
| JP4074862B2 (en) * | 2004-03-24 | 2008-04-16 | ローム株式会社 | Semiconductor device manufacturing method, semiconductor device, and semiconductor chip |
-
2006
- 2006-02-16 JP JP2006039135A patent/JP2007220870A/en active Pending
-
2007
- 2007-02-14 KR KR1020070015267A patent/KR100858386B1/en not_active IP Right Cessation
- 2007-02-15 TW TW096105600A patent/TWI353028B/en not_active IP Right Cessation
- 2007-02-16 CN CNB2007100789972A patent/CN100468714C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097414A (en) * | 2010-11-24 | 2011-06-15 | 日月光半导体制造股份有限公司 | Semiconductor device with marked conduction columns |
| CN102097414B (en) * | 2010-11-24 | 2013-03-27 | 日月光半导体制造股份有限公司 | Semiconductor device with marked conduction columns |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007220870A (en) | 2007-08-30 |
| TW200739774A (en) | 2007-10-16 |
| CN100468714C (en) | 2009-03-11 |
| KR20070082535A (en) | 2007-08-21 |
| KR100858386B1 (en) | 2008-09-11 |
| TWI353028B (en) | 2011-11-21 |
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