TW201338092A - Air gap forming method for semiconductor - Google Patents

Abstract

The present invention provides an air gap forming method for semiconductor, which includes the following steps: forming a plurality of trenches and at least one groove not parallel to the trenches on a substrate; forming a plurality of columns between the trenches, and each column contains a metal layer; next, depositing a third insulation layer and a top barrier layer within the trenches and the grooves; defining a deposition region corresponding to the positions of the trenches and the columns and a related non-deposition region; removing the top barrier layer of the non-deposition region; finally, etching and removing the third insulation layer through the non-deposition region to form an air gap between the columns and the top barrier layer. Thus, the present invention may control the thickness of the third insulation layer for controlling the size of the air gap, so as to obtain a semiconductor structure with a high air gap ratio.

Description

Method for forming air gap of semiconductor

The present invention relates to an air gap of a semiconductor, and more particularly to a method of forming an air gap of a semiconductor.

As the size of semiconductor components is gradually reduced, the spacing between the wires is also reduced, which in turn increases the parasitic capacitance effect between the wires. Because of the parasitic capacitance effect, the signal generates a RC delay problem, which causes the wafer operation speed to slow down and reduce the performance of the chip.

The parasitic capacitance is linearly related to the dielectric constant. Low dielectric constant dielectric materials reduce the capacitance of the parasitic capacitance of the wafer, reduce the RC delay of the signal, and improve wafer performance. Reducing the overall capacitance also reduces power consumption. At present, air is a good material for low dielectric constant because its dielectric constant is only 1, which is much smaller than other materials such as cerium oxide having a dielectric constant of about 4.2. Therefore, in the semiconductor manufacturing process, it is attempted to reduce the parasitic capacitance effect between semiconductors by closing the gap between the metals to form an air gap. However, the air gap structure is not generally a solid structure, so that the overall stress intensity of the semiconductor device is weaker than that of the general structure, and the entire structure may be deformed in subsequent processes.

In order to solve the above problems, for example, the "internal connection structure and its formation method, and the semiconductor device having an air gap structure between the wires and the method of forming an air gap between the wires of the semiconductor device" are disclosed in the Republic of China Patent Publication No. I265639. A method of forming an air gap between interconnect structures to form a preferred stress support structure design. Another method of forming a gas-filled dielectric layer or a low-k dielectric layer and a semiconductor structure is disclosed in the Patent Publication No. I254408 of the Republic of China, which also discloses the use of etching a dielectric layer to form a void. A manner of stacking another dielectric layer on the dielectric layer to form an air gap semiconductor structure.

The size of the air gap determines the size of the parasitic capacitance, but it also controls the strength of the overall stress structure. If the air gap is too small, the effect of reducing the parasitic capacitance effect is poor, but if the air gap is too large, although the influence of the parasitic capacitance effect can be greatly reduced, the overall stress structure is easily damaged. In the above patent case, the position of the air gap is determined by the position of the semiconductor element, and the interval between the two semiconductor elements is fixed. Once the position is fixed, the size of the air gap space cannot be controlled and the air gap cannot be made. The size is balanced between the parasitic capacitance and the stress structure.

The main object of the present invention is to improve the Air Gap Ratio of a semiconductor structure.

Another object of the present invention is to solve the problem that the prior art cannot accurately control the size of the air gap.

To achieve the above object, the present invention provides a method for forming an air gap of a semiconductor, comprising the steps of:

S1: forming a plurality of trenches on a substrate and at least one recess that is non-parallel to the trenches and communicating with the trenches, and forming a plurality of columns between the trenches, the substrate includes a first insulating layer, the pillars The body includes a metal layer sequentially stacked and a second insulating layer adjacent to the first insulating layer;

S2: depositing a third insulating layer in the trenches and the recesses;

S3: forming a top isolation layer on the third insulating layer and the surface of the columnar body, the material of the top isolation layer is different from the third insulating layer;

S4: defining a pair of deposition areas where the trenches and the columns are located, and defining a pair of non-deposited areas where the grooves should be located;

S5: removing the top isolation layer of the non-deposited region; and

S6: etching and removing the third insulating layer through the non-deposited region by using an etchant to form an air gap between the pillar and the top spacer.

Further, the materials of the first insulating layer, the second insulating layer, the third insulating layer and the top isolation layer are selected from the group consisting of tantalum nitride, hafnium oxynitride, antimony oxide, antimony fluoride and antimony carbide. The group and its combination.

Further, in step S2, the third insulating layer is formed in the trenches and the recesses by means of dielectric spin coating.

Further, in step S2, the thickness of the third insulating layer must be equal to or greater than the height of the metal layer away from one end of the substrate.

Further, in step S5, the following steps are included:

S5A: forming an etch barrier layer on the deposition region of the top isolation layer;

S5B: etching the top isolation layer not protected by the etch barrier layer to expose the third insulation layer;

S5C: The etch stop layer is removed.

Further, in step S6, the etching of the third insulating layer is performed by wet etching, and the etching material has a high etching selectivity ratio to the third insulating layer.

Further, between step S1 and step S2, there is a step A1 of forming a fourth insulating layer on the surface of the columnar body, the trenches and the groove, and the material of the fourth insulating layer The material of the third insulating layer is easy to use. In more detail, the material of the fourth insulating layer is selected from the group consisting of tantalum nitride, lanthanum oxynitride, lanthanum oxide, lanthanum fluoride, and lanthanum carbide, and the combination thereof is A linear deposition is formed on the columns, the trenches, and the surface of the grooves.

It can be seen from the above description that the present invention etches and removes the recess and the third insulating layer in the trench through the non-deposited region, so that an air gap is formed between the pillars and the top spacer layer, thereby having a simple process, The air gap size is easy to control and the advantage of high air gap ratio.

The detailed description and technical contents of the present invention will now be described as follows:
Please refer to "Figure 1", "Figure 2A", "Figure 3A" and "Figure 4". "Figure 2A" to "Figure 2H" are schematic views of the AA cross-sectional view in Figure 1 and Figure 3A to "Fig. 3H" is a schematic view of the BB section viewing angle in "Fig. 1". The invention is a method for forming an air gap of a semiconductor, comprising the following steps:
S1: forming a plurality of trenches 11 and at least one recess 12, forming the trenches 11 on the substrate 10 and the recesses 12 that are non-parallel to the trenches 11 and communicating with the trenches 11. The trenches 11 are formed between the trenches 11 a plurality of columns 13 , the substrate 10 includes a first insulating layer 131 , the column 13 includes a metal layer 132 and a second insulating layer 133 , which are adjacent to the first layer An insulating layer 131. The material of the first insulating layer 131 and the second insulating layer 133 may be tantalum nitride (SiN), yttrium oxynitride (SiON), yttrium oxide (SiO, SiO2), yttrium fluoride (SiF) or tantalum carbide ( SiC) or the like, wherein the first insulating layer 131 is the same or different from the material of the second insulating layer 133. In the embodiment, the first insulating layer 131 and the metal are sequentially stacked on the substrate 10. The layer 132 and the second insulating layer 133 are then formed by etching to form the trench 11 and the recess 12.
A1: forming a fourth insulating layer 20, which is formed on the surfaces of the columnar bodies 13, the trenches 11, and the recesses 12, as shown in FIG. 2B and FIG. 3B. 20, the material of the fourth insulating layer 20 may be the same or different from the material of the first insulating layer 131 and the second insulating layer 133, that is, the material of the fourth insulating layer 20 may be tantalum nitride, Niobium oxynitride, cerium oxide, cerium fluoride or cerium carbide. In the embodiment, the fourth insulating layer 20 is formed on the surface of the column 13 , the trenches 11 and the grooves 12 by linear deposition. It should be noted that the purpose of the fourth insulating layer 20 is to adjust the width of the air gap 80 (shown in FIG. 2G) after completion. Please refer to FIG. 4, if the width of the air gap 80 is not adjusted, Step S2 can be directly performed by skipping step A1.
S2: forming a third insulating layer 30, as shown in FIG. 2C and FIG. 3C, depositing a third insulating layer 30 in the trenches 11 and the recesses 12, the third insulating layer 30 The material may be tantalum nitride, hafnium oxynitride, hafnium oxide, tantalum fluoride or tantalum carbide, etc., and in the present embodiment, the first form is formed by means of a spin-on-spinning (SOD) method. Three insulating layers 30 are in the trenches 11 and the recesses 12. In addition, if the step A1 is omitted in FIG. 4, the material of the third insulating layer 30 must be different from the materials of the first insulating layer 131 and the second insulating layer 133, thereby utilizing The high-selection etching material is subjected to subsequent different ranges of etching; if the step A1 is continued, only the material of the fourth insulating layer 20 and the material of the third insulating layer 30 are different, so that different ranges of etching options can be achieved. That is, the third insulating layer 20 may be made of the same material as the first insulating layer 131 or/and the second insulating layer 133. The thickness of the third insulating layer 30 is equal to or greater than the height of the metal layer 132 away from one end of the substrate 10 to ensure that the metal layer 132 between the adjacent pillars 13 is spaced apart from the third insulating layer 30.
S3: forming a top isolation layer 40, as shown in FIG. 2D and FIG. 3D, forming the top isolation layer 40 on the surface of the third insulating layer 30 and the columnar body 13, the top isolation layer The material of the material of 40 may be tantalum nitride, tantalum oxynitride, tantalum oxide, tantalum fluoride or tantalum carbide, and the material of the top isolation layer 40 needs to be different from the material of the third insulating layer 30.
S4: defining a pair of deposition areas 51 corresponding to the locations of the trenches 11 and the columnar bodies 13, and defining a pair of non-deposited areas 52 that should be positioned at the locations of the grooves 12;
S5: removing the top isolation layer 40 of the non-deposition region 52. In this embodiment, the method further includes the following steps:
S5A: forming an etch stop layer 60, as shown in FIG. 2E and FIG. 3E, forming the etch stop layer 60 on the deposition region 51 of the top isolation layer 40;
S5B: removing the top isolation, as shown in FIG. 3E, etching the top isolation layer 40 not protected by the etch barrier layer 60 to expose the third insulation layer 30; and S5C: removing the etch barrier layer 60, Please refer to "FIG. 2F" and "FIG. 3F" to remove the etch stop layer 60 to facilitate subsequent processing.
S6: removing the third insulating layer 30, as shown in FIG. 2G and FIG. 3G. In this embodiment, the third insulating layer is transparently etched through the non-depositing region 52 by using an etching material. The layer 30 is etched away to form an air gap 80 between the columnar body 13 and the top spacer layer 40, wherein the etchant has a high etching selectivity ratio to the third insulating layer 30 due to the first insulating layer 131. The material of the second insulating layer 133, the top isolation layer 40, and the fourth insulating layer 20 are different from the third insulating layer 30. Therefore, the first etching layer can be etched by selecting a high selectivity ratio. The third insulating layer 30 is etched into the first insulating layer 131, the second insulating layer 133, the fourth insulating layer 20, and the top isolation layer 40.
After the above steps are completed, a subsequent process can be performed. As shown in "Fig. 2H" and "Fig. 3H", an oxide layer 70 is deposited on the surface of the structure after the completion of the above process, and since the deposition only occurs in the vertical direction, it is located. The air gap 80 in the trench 11 does not affect.
In summary, the present invention has the following features:
1. Etching and removing the recess and the third insulating layer in the trench through the non-deposited region, so that an air gap is formed between the pillars and the top spacer layer, which has the advantages of simple process.
Second, by controlling the thickness of the third insulating layer, the height of the formed air gap is determined; controlling the thickness of the fourth insulating layer, determining the width of the formed air gap, has excellent operability.
Third, the formed air gap has high stability and has the advantage of high air gap ratio.
Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is made according to law, and the praying office grants the patent as soon as possible.
The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

10. . . Substrate

11. . . ditch

12. . . Groove

13. . . Columnar body

131. . . First insulating layer

132. . . Metal layer

133. . . Second insulating layer

20. . . Fourth insulating layer

30. . . Third insulating layer

40. . . Top isolation layer

51. . . Deposition area

52. . . Non-deposited area

60. . . Etch barrier

70. . . Oxide layer

80. . . Air gap

S1~S6, S5A~S5C, A1. . . step

1 is a top plan view of a preferred embodiment of the present invention.

2A-2H are schematic views of the cross-sectional process of the A-A view of FIG. 1.

3A-3H are schematic views of the cross-sectional process of the B-B viewing angle of FIG. 1.

4 is a schematic view showing the manufacturing steps of the present invention.

S1~S6, S5A~S5C, A1. . . step

Claims (11)

A method for forming an air gap of a semiconductor, comprising the steps of:
S1: forming a plurality of trenches on a substrate and at least one recess that is non-parallel to the trenches and communicating with the trenches, and forming a plurality of columns between the trenches, the substrate includes a first insulating layer, the pillars The body includes a metal layer sequentially stacked and a second insulating layer adjacent to the first insulating layer;
S2: depositing a third insulating layer in the trenches and the recesses;
S3: forming a top isolation layer on the third insulating layer and the surface of the columnar body, the material of the top isolation layer is different from the third insulating layer;
S4: defining a pair of deposition areas where the trenches and the columns are located, and defining a pair of non-deposited areas where the grooves should be located;
S5: removing the top isolation layer of the non-deposited region; and
S6: etching and removing the third insulating layer through the non-deposited region by using an etchant to form an air gap between the pillar and the top spacer. The method for forming an air gap of a semiconductor according to claim 1, wherein the material of the first insulating layer, the second insulating layer, the third insulating layer and the top isolation layer is selected from nitriding Groups of bismuth, bismuth oxynitride, cerium oxide, cerium fluoride, and cerium carbide and combinations thereof. The method for forming an air gap of a semiconductor according to claim 1, wherein a material of the third insulating layer is different from a material of the first insulating layer and the second insulating layer. The method for forming an air gap of a semiconductor according to the first aspect of the invention, wherein in the step S2, the third insulating layer is formed in the trenches and the recess by means of dielectric spin coating. The method for forming an air gap of a semiconductor according to claim 1, wherein in the step S2, the thickness of the third insulating layer is equal to or greater than a height of the metal layer away from one end of the substrate. The method for forming an air gap of a semiconductor according to claim 1, wherein in the step S5, the following steps are included:
S5A: forming an etch barrier layer on the deposition region of the top isolation layer;
S5B: etching the top isolation layer not protected by the etch barrier layer to expose the third insulation layer;
S5C: The etch stop layer is removed. The method for forming an air gap of a semiconductor according to claim 1, wherein in step S6, etching of the third insulating layer is performed by wet etching. The method for forming an air gap of a semiconductor according to claim 1, wherein in the step S6, the etching material has a high etching selectivity ratio to the third insulating layer. The method for forming an air gap of a semiconductor according to claim 1, wherein between step S1 and step S2, there is further a step A1: forming a fourth insulating layer on the columns, the trenches And a surface of the recess, the material of the fourth insulating layer is different from the material of the third insulating layer. The method for forming an air gap of a semiconductor according to claim 9 , wherein the material of the fourth insulating layer is selected from the group consisting of tantalum nitride, lanthanum oxynitride, lanthanum oxide, lanthanum fluoride and lanthanum carbide. Groups and combinations thereof. The method for forming an air gap of a semiconductor according to claim 9, wherein the fourth insulating layer is formed in a linear deposition manner on the columns, the trenches, and a surface of the recess.