TW201334432A - Timing calibration method and apparatus - Google Patents

Abstract

An apparatus, program and method, the apparatus comprising: a first timing element, a second timing element, a controller arranged to switch the apparatus between a lower-power mode with the second timing element powered down and a higher-power mode with both timing elements powered up, a transceiver operable to transmit or receive a signal externally to the apparatus when in the higher-power mode based on the second timing element, and a calibrator configured to perform a calibration of the first element relative to the second timing element during each of a plurality of phases of the higher-power mode between phases of the lower-power mode. The apparatus further comprises an estimator configured to control an aspect of the calibration performed in a current one of said phases in dependence on estimates from preceding ones of the calibrations earlier of the phases of the higher- power mode.

Description

Time correction method and device

The present invention relates to communication devices having a higher power mode and a lower power mode, and with respect to timing elements of the device during phase of the higher power mode.

The communication device can include a processor for performing signal processing coding, or "soft modem" encoding, such as a wireless transceiver configured to communicate via a wireless cellular network, such as a 3GPP network, through the device. In one arrangement, the processor may be in the form of a baseband processor configured to operate a soft baseband data machine, in which most or all of the operations in the fundamental frequency domain are performed in software, with dedicated radio frequencies (RF, Radio frequency) front end combined operation. The communication device typically has a high power mode in which the transceiver and processor are powered to be ready to communicate externally to the device via the network, and a low power mode wherein the processor is relatively inactive and the transceiver and processor are not External communication. Other types of wired and wireless communication devices may also have similar lower and higher power modes.

When the processor, such as the baseband processor, is in a low power mode, one or more high resolution clocks may be turned on to conserve power. In this mode, the only remaining timer is a low power, low frequency device such as a 32 kHz Real Time Counter (RTC). The exact frequency of the RTC is usually not pre-determined because it depends on external factors like temperature. In another aspect, the base frequency needs to wake up periodically to check for external activities such as incoming calls, SMS (short message service) messages, and the like. These activities are referred to as "paging activities." In order to ensure timely wake-up from low power mode, the RTC needs to be calibrated. For the required accuracy of the estimated frequency, for example, 2 ppm may be required to ensure that the fundamental frequency wakes up instantaneously to decode the call block within the RF receive window, however the value can be tolerated according to system design parameters such as wake up. Depending on the error. Sacrificing other factors such as additional processing and/or higher sensitivity to noise, etc., may tolerate larger errors. Thus other implementations can have different needs.

To correct the RTC, a stable, higher frequency but higher power device such as a Cellular Timer (CET), such as the 15.36 MHz clock, is used to determine the RTC. Each measurement consists in running the RTC and the CET at the same time and counting the values of the RTC and CET cycles, respectively. The CET/RTC cycle ratio is used to estimate the actual frequency of the RTC. These measurements preferably continue from wake-up to entering the higher power mode until the next entry returns to the low power mode (the CET is not available in the low power mode).

In order not to waste power, the RTC correction should be consistent with the call activity. For example, it is possible that the correction should not be longer than 8 ms because the shortest call activity can last 8 ms under the existing standards. However, the measurement inaccuracy of any individual 8ms correction of the RTC is currently greater than 8 ppm. Again, these 8ms and 8ppm requirements are system dependent. For example, for a 3G system, the call indicator may range from 66 μs to 533 μs in length. The remainder of the 8ms is for powering the transceiver, processing the results, and deciding to re-enter sleep; all of which can vary in other implementations. Despite this, there are still many problems, the required or at least the required accuracy cannot be achieved, or the natural wake-up time (such as the minimum time required for a call), which means that the wake-up time must be artificially extended. Or you must tolerate lower accuracy, or you must allocate more processing resources to the correction.

The present invention introduces a frequency drift estimator to determine how long the next corrected measurement should last in accordance with the estimated amount of drift experienced to produce a sufficient estimate for the correction of a time component such as the RTC.

According to one aspect of the invention, an apparatus is provided comprising: a first time component configured to generate a first time signal; a second time component, Arranging to generate a second time signal independent of the first time component; a controller configured to provide a lower power mode in which the first time component is powered and the second time component is powered down, and the first Switching the device between a higher power mode powered by the second time component; a transceiver operative to externally transmit or receive signals to the device when the higher power mode is based on the second time signal a corrector configured to perform correction of the first time signal relative to the second time signal during each phase of the complex phase of the higher power mode between phases of the lower power mode, each Each of the corrections performs a respective correction time for a plurality of cycles of the equal time signal, and each of the corrections produces a respective result indicative of the frequency of the first signal; and an estimator configured to compare Depending on the results of the previous corrections of the phases of the high power mode, the manner of the correction performed in the existing one of the phases is controlled.

In a particular embodiment, the estimator can include: a drift estimator configured to adapt to the drift in the results of the previous corrections from the earlier phase of the higher power mode The correction time of the correction in the existing one of the phases of the higher power mode, the aspect comprising the correction time.

The drift estimator can include a filter configured to receive the results of the prior corrections, and the drift estimator can be configured to adjust the correction time by adjusting an output of the filter This existing correction time depends on the drift.

The filter can include an averaging filter configured to maintain an average integral of the results of the previous corrections.

The filter can include an infinite impulse response filter.

The estimator can include: a frequency estimator configured to adjust the phases in the higher power mode based on the results of the previous corrections from the earlier phase of the higher power mode An estimate of the frequency of the first time signal in the existing one, the aspect comprising the frequency estimate.

The frequency estimator can include a filter configured to receive the previous calibration As a result of this, the frequency estimator is configured to adapt the existing estimate based on the previous results by adapting the estimate based on the output of the filter.

The filter can include an averaging filter configured to maintain an average integral from the results of the previous corrections.

The filter can include an infinite impulse response filter.

The filter can be set to maintain a weighted average whereby each of the previous results is weighted by a respective coefficient.

The frequency estimator can be configured to adapt the respective coefficients for each of the previously corrected correction times.

The apparatus can further include an override mechanism configured to measure the drift separately and to condition that the drift is greater than a threshold value, for which the correction time to be determined by the drift estimator is determined to be longer.

The apparatus can further include a number generator configured to vary the correction time by a random number and one of the numbers generated from the predetermined series, in addition to the adaptation resulting from the drift.

The transceiver is operative to externally communicate to the device via the network and is configured to check for external activity on the network during the higher power mode based on the second time signal.

The transceiver may be a wireless transceiver operative to externally communicate to the device via wireless medium and may be configured to check for external activity on the wireless medium during the higher power mode.

The transceiver may be a wireless transceiver operable to externally communicate to the device via a wireless network and may be configured to check for external activity on the wireless network during the higher power mode.

The transceiver can be configured to perform a call operation during the higher power mode based on the second time signal to check the activity by listening to a call indication.

The transceiver may be a wireless transceiver operative to externally communicate to the device via a wireless network and configured to perform a call operation during each of the phases of the higher power mode based on the second time signal Listening to the call And the respective correction times of the previous results may be dependent on the duration of the call operation in the phases of the higher power mode.

The first time signal can be used to maintain synchronization with the network in the lower power mode.

The first time signal can be used to maintain synchronization with the wireless network in the lower power mode.

The apparatus can include a processor configured to process signals transmitted or received by the transceiver, and the processing can be based on the second time signal.

The first time signal can be used to decode any call indications received during the call operation.

The first time signal may be at a higher resolution than the second time signal.

In accordance with another aspect of the present invention, a method of operating a device is provided, comprising a first time component configured to generate a first time signal, and a second time component configured to generate an unrelated first time component a second time signal; wherein the device switches between a lower power mode in which the first time component is powered and the second time component is powered down, and a higher power mode in which the first and second time components are powered; and The device externally transmits a signal to or receives a signal from the device when the high power mode is based on the second time signal; and wherein the method includes the step of: the higher between the phases of the lower power mode During each phase of the complex phase of the power mode, the correction of the first time signal is performed relative to the second time signal, each of the corrections performing a respective correction time for a plurality of cycles of the equal time signal, and each Each of the corrections thereby producing a respective result indicative of the frequency of the first signal; and the results of the previous corrections of the phases earlier than the higher power mode Set, in the conventional control execution of one of the phase correction of the aspect.

In a particular embodiment, the method may further comprise the step of any of the operations performed by any of the above described device features.

According to still another aspect of the present invention, a computer program product including an encoding is provided. When executed, the device is operated in accordance with any of the above methods or device features.

Referring to the first and second figures, there is shown a wireless communication device in accordance with an exemplary embodiment of the present invention.

Referring to the first figure, the device 2 includes an integrated circuit (IC) 4 including a processor 14 and a wireless transceiver 6 including an RF front end 8 and at least one antenna 10. The antenna 10 is coupled to the RF front end 8 and the RF front end 8 is coupled to the baseband processor 14. The device 2 further includes one or more memory devices 16, each of which includes a non-transitory computer readable storage medium or a plurality of media, such as a magnetic storage medium (eg, a hard disk) and/or an electronic storage medium (eg, EEPROM (electronically erasable stylized read-only memory), also known as "flash" memory). The memory may include an off-chip memory 16a that is external to the integrated circuit 4 of the processor 14, and/or a memory on the wafer 16b that is implemented in the same integrated form as the processor 14. On circuit 4. Each of the one or more memory devices is coupled to the processor 14.

The memory 16a and/or 16b stores signal processing codes, and the processor 14 is configured to capture and execute the signal processing code for external communication through the transceiver 6 (eg, through the RF front end 8 and the antenna 10) to The device 2. In a particular preferred application of the invention, the encoding is configured in accordance with one or more wireless cellular communication standards such as 2G, 3G or LTE (Long Term Evolution) 3GPP standards such that when executed, the device is operable Communication via a wireless cellular network such as 2G, 3G and/or LTE networks. The processor 14 is arranged to perform the encoding retrieved from the memory and thereby process the output data for transmission via the network via the transceiver 6, and/or process input data received from the network via the transceiver 6. .

Preferably, the processor 14 is programmed to be a software baseband data machine, and the front end 8 includes the RF (radio frequency) and any IF. (intermediate frequency, intermediate frequency) stage. That is, on the receiving side, all of the radio functions from the RF signal received from the antenna 10 up to and including mixing down to the fundamental frequency are implemented in the dedicated front end 8. Similarly, on the transmitting side, all of the functions from the mixing from the fundamental frequency to the output RF signal to the antenna 10 are implemented in the dedicated front end 8. However, all functions in the fundamental frequency domain are implemented by software stored in the memory 16a and/or 16b and executed by the processor 14. Although this is a preferred implementation, it is also possible, for example, that the RF and/or IF phases are not implemented in a dedicated front end 8.

In the preferred implementation, the dedicated hardware in the receiving portion of the front end 8 may include a low noise amplifier (LNA) for downconverting the received RF signal to The IF is downconverted from IF to the baseband mixer, RF and IF filter stages, and an analog to digital conversion (ADC) stage. For each complex received diversity branch, an ADC is provided on each of the in-phase and quadrature fundamental branches. The dedicated hardware in the transfer portion of the front end 15 may include a digital to analog conversion (DAC) stage for upconverting the baseband signal to IF and upconverting from IF to RF. The mixer, RF and IF filter stages, and a power amplifier (PA, Power amplifier). The front end 8 can be implemented in a dedicated hardware circuit, or some or all of the RF front end 8 can be implemented in software running on a separate dedicated RF processor. The interface between the front end 8 and the baseband processor 14 may be analogous to an RF interface or a digital radio interface such as a DigRF interface. Details of the required hardware for performing these radio functions will be apparent to those skilled in the art.

The software can then process functions such as modulation and demodulation, deinterleaving, rate matching and de-matching, channel estimation, equalization, separation multipath (rake) processing, bit-to-logarithm ratio ratio (LLR, Log) -likelihood ratio) calculation, transmit diversity processing, receive diversity processing, multiple transmit and receive antenna (MIMO) processing, speech codec, link adaptation via power control or adaptation modulation and coding ( Link Adaptation), as well as monomer measurements.

The device 2 further includes a first oscillator 12i and a second oscillator 12ii, typically a crystal oscillator. The frequency of the first oscillator 12i may, for example, be on the order of tens of kHz, and in this preferred example is 32.768 kHz. The frequency of the second oscillator may take a range of values, but may also be a factor of ten MHz. In the preferred embodiment, the second oscillator 12ii is selected from the group consisting of frequencies of 15.36 MHz, 19.2 MHz, 26.0 MHz, 38.4 MHz, and 52 MHz. The following example will use 15.36MHz.

Each of the oscillators 12 is arranged to generate a periodically oscillating reference signal for use by the time circuit 18 to generate a time signal in the form of a clock signal or a count signal. The first oscillator 12i is coupled to the first time circuit 18i and is configured to provide a first reference signal to be employed by the first time circuit to generate a first time signal, and the second oscillator 12ii is coupled to the second time circuit 18ii, and arranged to provide a second reference signal to be employed by the second time circuit to generate a second time signal.

Each of the first time circuit 18i and the second time circuit 18ii includes at least a clock circuit configured to receive the oscillation reference signal from its respective oscillator 12i or 12ii, and based thereon, to generate the respective oscillations The frequency of the 12i or 12ii is derived from the respective oscillator 12i or 12ii (e.g., an integer multiple or partial or rational fraction of the oscillator frequency) in the form of a binary clock signal (cycle between digital logic 1 and logic 0) Sexual transition). Each of the first time circuit 18i and the second time circuit 18ii may also include a counter that is arranged to periodically increase or periodically when clocked by the respective clock signal (usually from the edge of the clock signal) The respective count values are reduced to produce separate time signals in the form of respective count signals representing the respective count values. In addition, any count that needs to be done based on any of the clock signals can be implemented by software running on the processor 14. In general, a timer, time device, time element, clock, or the like may be used herein to refer to either a binary 0-1 clock or clock signal or a regularly increasing or decreasing counter or counting signal. With time Circuitry 18i and/or 18ii are implemented in their entirety, or potentially in a software portion that operates on the processor 14 that has operations such as counting or separating to be completed. Nonetheless, in the preferred embodiment, each of the RTC 18i and CET 18ii does include a separate hardware counter and associated circuitry, rather than just a substantially 1-0 clock. It should also be noted that in the case of a counter, the period, period, frequency or rate of the counter or the like refers to a count, i.e., a unit increase or decrease, rather than the overall wraparound range of the counter.

As shown in the first figure, the first and second time circuits 18i and 18ii may be included in the same integrated circuit 4 as the processor 14, but the outside of the chip using the external circuit of the IC 4 is not excluded. Or part of the wafer is implemented outside. Either way, the first time circuit 18i and the second time circuit 18ii are forward coupled to the processor 14 to provide the first and second time signals to the processor 14. For example, as mentioned, the second oscillator 12ii is selected from the group of frequencies 15.36 MHz, 19.2 MHz, 26.0 MHz, 38.4 MHz, and 52 MHz, such as 15.36 MHz in a particular implementation. The second time circuit can simultaneously include a phase-locked loop (PLL) that is arranged to multiply the frequency to generate an even higher rate time signal for timing the processor 14 and its associated logic, such as The GHz, tens of GHz, or hundreds of GHz levels; however, the CET counter can still be clocked at the base 15.36 MHz rate (or any of the fundamental rates of the oscillator 12ii).

In a preferred embodiment, the first oscillator 12i is arranged to provide a reference signal at a suitable frequency such that the first time circuit 18i operates as a Real-time Clock (RTC). That is, the clock used to measure "human time" is conventionally measured in seconds, minutes, and/or hours, that is, in humans at a human scale. The instant reference oscillator typically has two oscillations of the integer power of two oscillations per second, that is, 2 ⁿ oscillations per second (where n is an integer), since the separation is most convenient for units of one second. The most common is 32.786 kHz, which is 2 ¹⁵ oscillations per second, and is an example that will be used below.

The RTC 18i is preferably coupled to the second oscillator 12ii and the time circuit 18ii In contrast, it may be provided to time the processor 14 and/or other circuitry of the wafer 4 to control digital logic and/or program communication transmitted or received through the transceiver 6. For example, when the second clock circuit 18ii is driven by the reference signal from the second oscillator 12ii of a suitable frequency, it can be configured to provide a Cellular Timer (CET). This will typically have a much higher frequency, such as one thousand or more times the level of the RTC frequency, and no need to have a convenient number of integers or a number of cycles of two.

The description will be made hereinafter with reference to RTC 18i and CET 18ii, but it should be understood that the invention is also applicable to other arrangements of the first and second time elements.

The apparatus 2 also includes a power control module 20 coupled to each of the processors 14, CET 18ii and transceiver 6 (e.g., to the RF front end 8). The power controller 20 is shown in the first figure as including a dedicated hardware unit that is implemented on the same integrated circuit 4 as the processor 14, but more generally, the power controller 20 may be A module implemented on or under the wafer and/or any combination of software disposed on the processor 14.

In operation, the power controller 20 is configured to switch the device 2 between a first higher power or power mode and a second lower power or power down mode. In the power mode, the second time circuit 18ii, in this case the CET, is enabled to generate the second time signal. The transceiver 6 is also enabled to be ready to transmit and/or receive signals over the network, typically by powering the RF front end 8. Moreover, the processor 14 is operative to process signals at least based on the time signal received from the CET 18ii of the enabled energy, including at least the signals transmitted and/or received by the transceiver 6. In this power mode, the processor 14 can also be enabled to perform other general processing functions. On the other hand, in the power down mode, the CET 18ii is disabled to not generate the second time signal. The transceiver 6 is also inhibited so that it is not in a state that can be used to transmit or receive signals over the network, typically because the RF front end 8 is powered down. Again, the processor 14 suppresses at least the processing of signals transmitted or received through the transceiver 6, and can be inhibited from executing any processing function. However, unlike the CET 18ii, the RTC 18i At the same time, the power supply mode and the power-off mode remain enabled. Thus, in the power or higher power mode, all of the RTC 18i, CET 18ii, processor 14 and transceiver 6 are activated; however, in the power down or lower power mode, the RTC 18i remains enabled. However, the CET 18ii and the transceiver 6 are deactivated and the processor is at least partially deactivated at least with respect to the processing signals used to communicate through the transceiver 6. In a particular embodiment, the processor 14 can completely suppress any encoding from being performed at all. Details of suitable techniques for enabling and disabling these various components to conserve power in themselves are well known to those skilled in the art. It should also be noted that these two modes do not need to be the only power mode of the processor, but at least two modes of this type will be considered for the following purposes.

The power controller 20 is configured to communicate with the baseband processor 14 to wake up at least when the processor 14 needs to communicate via the network via the network, whether or not the signal is transmitted and/or received via the network. Device 2 enters the power mode. Conversely, the power controller 20 is configured to communicate with the processor 14 to power down the device 2 into the power down mode when it does not need to communicate via the network. The power controller 20 can alternately switch the device 2 between the phase of the power down mode and the phase of the power mode.

In a particular preferred application of the invention, the power control device 20 is arranged to wake the device 2 into the power mode to perform a call operation, i.e., to check for a call indication from the network on the network. External activities. Such call operations may include checking incoming communications, such as incoming calls or text messages. The power controller 20 will then power down the device 2 into the lower power mode when idle between call operations. The power controller 20 is preferably arranged to wake up the device 2 to periodically perform a call operation, i.e. at regular time intervals.

In the idle phase, when the device 2 is powered down such that the CET 18ii is unusable and the processor 14 does not communicate externally or listen to the call through the transceiver 6, the remaining RTC 18i is used to maintain synchronization with the network. . Monitoring of the RTC 18i may be accomplished by the power controller 20 or by some minimal software that remains on the power down processor 14 and triggers the power controller 20. Either In the manner, once the specific duration of the idle phase has elapsed as determined by the RTC 18i, the device will be woken up to check the call indication.

When the device is in the power mode, the CET 18ii is used for time operations performed by the processor 14 when actually communicating or listening for communication, such as for use as a clock signal or for decoding a call block. The basis of the clock signal.

The second figure shows the device 2 in more detail. The apparatus includes a baseband processing module 22; a correction driver 24 coupled to the RTC 18i, CET 18ii, and the baseband processing module 22; a frequency estimator 26 and a drift estimator 27 coupled to the The correction driver 24; and in a particular embodiment, a random number generator coupled to the correction driver 24. The baseband processing module 22 can include a drift measurement feedback module 30. In the illustrated implementation, each of these components is implemented as a software module that is stored on one or more of the memory devices 16a and/or 16b and is configured to be executed on the processor 14. However, some or all of these modules may be implemented in part or in whole in a dedicated hardware circuit.

To ensure timely wake-up from low power mode, the RTC 18i needs to be corrected and kept calibrated. To this end, the correcting driver 24 utilizes the operating CET 18ii to correct the RTC 18i each time the device 2 re-enters the power mode. That is, in order to generate a corrected time signal, it has a time derived from the immediate output time signal of the RTC, but the time is adjusted based on the correction. As mentioned above, the frequency of the RTC 18i is usually not pre-determined because it depends on external factors such as temperature. The required accuracy for the estimated frequency is preferably 2 ppm (to ensure that the base frequency wakes up in time to decode the call block within the RF receive window).

To correct the RTC, a device having a stable higher frequency but higher power, such as the CET 18ii, such as a 15.36 MHz clock, is employed by the correction driver 24 to determine the RTC 18i. Each measurement consists in running the RTC 18i and the CET 18ii simultaneously for the same time and counting the value of the RTC and the value of the CET period. The ratio of the CET period to the RTC period is then used to estimate the RTC 18i Actual frequency. These measurements are preferably continued from wake-up to entering the higher power mode until the next item returns to the low power mode.

In order not to waste power, the RTC correction should preferably be consistent with the call activity. For best accuracy, the count begins and stops on the RTC clock edge, so the inaccuracy is a CET clock period during the measurement period. For example, in the case of the 15.36 MHz CET clock (during the 65 ns period) and the 8 ms measurement, the accuracy is +/- 65 ns / 8 ms, which is 8.14 ppm. Therefore, if the shortest call activity lasts 8 ms, it should preferably be no longer than 8 ms to correct the RTC (however, it should be noted again that the shortest call activity is dependent on the system implementation, as the required accuracy). However, the measurement inaccuracy for any individual 8 ms correction of the RTC is currently greater than 8 ppm.

In an effort to address this problem, an exemplary embodiment of the present invention provides one or both of frequency estimator 26 and drift estimator 27 that are configured to operate as follows. The frequency estimator 26 and the drift estimator 27 can be implemented separately or in combination with each other.

Each time the correction driver 24 corrects the RTC 18i, two counts are obtained: - the value of the _RTC ticks n _RTC ; and the value of the CET engraving point n _CET .

From these two counts, the correction driver 24 can calculate the final estimate of the actual RTC frequency f _RTC (since the CET frequency f _CET can be accurately known relative to the RTC). This is the unfiltered (original) RTC frequency estimate: f _RTC (t) = f _CET (n _RTC / n _CET )

The frequency estimator 26 is arranged to receive the original frequency estimates of the RTC 18i, i.e., the value of f _{RTC for} each time t is corrected.

The drift estimator 27 is arranged to receive a difference between the most recent original frequency estimate of the RTC 18i and a previous original frequency estimate of the RTC (by dividing by the elapsed time between the two measurements into a rate of change), That is, the original input drift d can be expressed as:

Where k is the discrete index of the window in which the correction is performed.

Preferably, the frequency estimator 26 and the drift estimator 27 each comprise a respective filter configured to be consistent with one of the following specific embodiments, and in a particularly preferred embodiment, the frequency estimator Both the 26 and the frequency estimator 27 comprise an Infinite impulse Response (IIR) filter. The filter of the frequency estimator 26 preferably attributes the weight to the last measurement based on the duration of the measurement (long measurement is more reliable).

The frequency estimator 26 filters the original frequency estimate of the RTC 18i in a particular embodiment that preferably has an adaptation factor. The frequency estimator 26 has been introduced to eliminate the error of the original measurement.

The average of the corrected samples provides a good approximation of the actual RTC crystal frequency. When a sample is sent to the averaging filter, an option may be to use a moving average filter for averaging purposes. For ubiquitous tasks, the moving average filter is optimal: reduce random noise while retaining a large step response. There is indeed noise in the calibration sample (because of the crystal phase jitter and the CET period rounding value), and there is a need in the art to respond to large steps (if there is a high temperature gradient, the crystal frequency can be greatly increased) Variety).

If f _RTC (t _k ) is the kth original (unfiltered) corrected sample and F _RTC (t _k ) is the kth filtered frequency estimate, then the moving average filter is convolution The implementation can be defined by the following finite impulse filter (FIR, Finite Impulse Filter):

Where M is the number of samples for which the average is calculated.

The moving average filter works well under random conditions of the noise system. However, in a particular embodiment of the invention, the use of a moving average filter may not be preferred for a particular use of crystal correction because it weights the calibration samples according to a certain correlation criterion (e.g., the duration of the correction). Not provided Easy way. In addition, the moving average filter requires some memory of the previously corrected samples, and it takes M corrected samples before the filter can output an average.

An average filter for crystal correction will be simple, an average can be output from the first corrected sample, and can be included in the fact that the error on the corrected sample can be estimated from the corrected duration. Therefore, the following first-order Infinite Impulse Response (IIR) averaging filter is used in the preferred embodiment of the present invention: F _RTC ( t _k )=(1 - a _k ) F _RTC ( t _{k -1} )+ a _k f _RTC ( t _k )

Where F ₀ = f ₀ and a _k belongs to [0, 1]

In the above formula, a _k is the first order coefficient of the IIR filter, and is determined according to the meaning of the correction sample f _RTC (t _k ).

The output F can be represented by the frequency estimator 26 as an absolute frequency, or preferably as a difference in ideal or general frequency relative to the RTC crystal 12i, such as in parts per million (parts per million). As discussed above, the filtered estimate F can then be employed for the unfiltered frequency f or for any use that has been taken.

As the duration of the correction increases, the error on the corrected sample shrinks, making the corrected sample more significant. Thus, in a particularly preferred embodiment, the frequency estimator 26 is configured to adapt the first order coefficient a _n depending on the duration of the corresponding measurement. When a tends to tend to 1, the weight of the new corrected sample is higher. Conversely, when a tends to approach 0, the weight of the new corrected sample is lower, and the history of the filter has a greater contribution to the average.

The weighting of the new measurements on the IIR frequency filter is calculated as: a ( t ) = 1 - βe ^{(- t / τ )}

t is expressed in RTC cycle, and β and τ are selected such that: a(250)=0.05

a(1250)=0.5

Another possibility would be to employ a discontinuous adaptation of the coefficients a, that is, the duration is compared to a small group of discontinuities defining a group of discrete bins. The thresholds, each mapped to a corresponding value of a, are used for the duration that is tied to the respective slot. For example: a=0.05 if cal_time<=1000, a=0.75 if cal_time>1000

Turning now to the drift estimator 27, this filters the difference between the most recent original frequency estimate of the RTC 18i and the previous original frequency estimate of the RTC (by dividing by the elapsed time between the two measurements into a rate of change) . The filter structure can be the same as the frequency estimator 26, but the coefficients of the filter are preferably fixed.

The drift estimator 27 has been imported to calculate how long the next measurement should last to produce a valid estimate of the RTC frequency. If necessary, the fundamental frequency must remain out of the low power mode to ensure that the actual measurement duration is longer than the required minimum. Initially there is no knowledge of the RTC frequency, so the measurement should be long. After the first measurement, the duration of the next measurement can be shortened. The drift estimator is used to determine how the estimated frequency changes. If the drift is small, the duration of the next measurement can be shortened. If the drift is large, the duration of the next measurement should be increased.

Preferably, the drift estimator filter has the same form as the frequency estimator except that it is preferably fixed coefficient, such as a = 0.1. For example, if D _RTC (t _k ) is the filtered drift and d _RTC (t _k ) is the original unfiltered drift: D _RTC ( t _k )=0.9. D _RTC ( t _{k -1} ) +0.1 d _RTC ( t _k )

Once the filtered drift D is estimated, then the estimated drift that is determined based on past measurements can be used to adapt the duration of the next corrected measurement. An exemplary embodiment of doing so may operate as follows, which may be performed by the drift estimator 27 operating in conjunction with the correction driver 24.

In a particular embodiment, the drift estimator 27 defines a set of different discontinuous modes of operation, each mode corresponding to a different time for the next corrected measurement, and the next mode is drifted according to the determined And choose. Example In other words, the drift estimator can define three modes of operation, for example, it may be as follows.

- Acquisition mode: Initial mode, where the shortest duration of measurement is 130ms. If the drift is below 1 ppm/second, the drift estimator 27 switches to the next mode.

- Placement mode: Intermediate mode, where the shortest duration of measurement is 30ms. If the drift is below 0.1 ppm/second, the estimator switches to the next mode.

- Stable mode: The shortest duration of measurement is 6.5ms.

The drift estimator 27 is reset to the acquisition mode for any measurement over 5 seconds. This ensures that all previous memories of the actual frequency of the RTC are lost, for example, after prolonged activity, when the temperature may have changed significantly.

This is an example and alternative embodiments may define more modes of operation and/or employ different parameters.

In other alternative embodiments, the next measurement duration may be determined based on a continuous relationship between duration and drift: next measurement duration = function (drift) (function (drift))

The preferred form of the function may depend on the particular communication network being modeled and may be determined empirically based on the simulation.

The drift estimator 26 supplies the determined measurement duration to the correction driver 24, which is configured to adapt the duration of the next correction measurement accordingly.

As a further improvement as needed, the correction driver 24 can be coupled to the numerical generator 28 to provide a corrected duration diversity feature. The generator can include a random number generator 28 configured to generate a random value based on a suitable randomization procedure and supply the generated value to the correction driver 24 to introduce further changes into the corrected measurement duration ( It is above the adaptation discussed above). As will be appreciated by those skilled in the art, the procedure employed by the random number generator 28 to generate the random number may not be truly random, but the reverse may be based on a virtual stochastic program that fits the model.

In the case of 32 kHz RTC crystal 12i and 15.36 MHz CET crystal 12ii, the CET/RTC ratio is typically determined by temperature T and ranges from 468.75 (T = 25 C) to 468.76 (T = 0 C). The decimal portion of the ratio is therefore always very close to 3/4.

For example, at T = 30C, the ratio has been found to be ~468.7504. If the RTC 12i is corrected for 400 cycles, it means ~187500.16 CET cycles, but only the integer part thereof can be measured. The initial RTC/CET offset when the calibration system is started to be random, but the chance of losing the 0.16 CET period during this measurement is high. Thus, if we always correct for 400 cycles, there is a risk of getting a static offset of an average of 0.16 CET periods => 0.85 PPM.

In order to introduce a certain diversity in the correction and exclude the static offset in the above example, the duration of the correction is artificially extended by a random number of RTC periods between 0 and 3 (which is generated by the random number generator 28). . These [0-3] extra cycles help remove the static offset incurred by the fact that the decimal portion of the CET/RTC ratio is close to 3/4.

Using this, the correction driver 24 randomly aligns the duration of the correction by adding an arbitrary number of RTC cycles to the measurement immediately before stopping the measurement.

Another way of performing calibration duration alignment without using a random number generator is by following a predetermined series such as the series 0, 1, 2, 3, 0, 1, 2, 3, 0, ..., produces an RTC period of this arbitrary value.

Although this example is based on a 32 kHz RTC crystal 12i and a 15.36 MHz CET crystal 12ii, it should be understood that other settings of the oscillator 12 may experience a non-integer period ratio, and may also benefit from random variations in correcting the measurement duration to resemble the above. The way to explain this non-integer remainder in its ratio.

For further improvement as desired, the baseband processing module 22 can include a drift measurement feedback block 30 in the physical layer that is configured to measure the frequency drift with the drift estimator 27 when possible, and This feedback to this correction Driver 24. The block 30 is capable of providing this feedback from the base frequency 22 of the UE 2 because when it receives the call signal, it can measure the time offset of the received signal using the actual received information. For example, it can do this based on the received pilot signal, such as a universal pilot signal, such as by searching for the CPICH signal in 3G, or by employing the Normal Burst (2G) A midamble is used to decode the cluster. Thus, the block 30 can accurately estimate whether the time has drifted since the previous call cycle by the respective mechanisms for the drift estimator 27. This can be accurate to a few microseconds or better in a good signal state.

In addition to the drift estimator 27, this can be used to provide a "fail safe" or "back up" mechanism. The filter 24 in the drift estimator does not actually "know" whether or not the accurate measurement of the RTC frequency is successfully provided, which is based solely on the automatic procedure that automatically changes the duration based on the value output by the algorithm, but There is no feedback on the results of the program. Thus, the introduction of a feedback mechanism 30 that can explicitly measure the drift may be advantageous, and if so exceeds the filter 24 and triggers only "one-shot" correction. The drift measurement feedback block 30 can do this because it is implemented in the physical layer of the fundamental frequency 22 and can determine the drift from the processed information derived from the received signal, rather than just the counting period. The ratio.

To compensate for small time drift, the RF window is generally slightly wider when waking up from low power mode. This allows the fundamental frequency 22 to measure a small time drift and feed back the time drift information to the correction driver 24, which can then determine if the duration of the next measurement should be increased when the drift exceeds a predetermined threshold.

The drift threshold varies depending on the currently used random access technology (RAT, Random Access Technology). In 2G, the drift threshold is defined as 7 microseconds. The drift threshold is defined as 120 quarter chips in 3G.

If the drift reported by the physical layer exceeds the critical value (absolute value), then The frequency and drift estimator switches to the acquisition state.

The upper graph of the third graph shows a simulation of the clock correction under the aggressive temperature step. The y-axis is derived from the drift of the ideal 32.768 kHz clock (in PPM), which is the time. The following information depicts: - the smooth solid line is the true (actual) RTC frequency, - the solid line is the output of the correction filter, - the small dots are the original frequency estimates, which are from the short 8ms The measurements are calculated, and - these large dots are the original frequency estimates, which are calculated from the longer 40 ms measurement.

In the lower graph, the error between the estimated frequency and the straight frequency can be seen, and will not exceed 1.5 PPM under this positivity scheme.

It should be understood that the above specific embodiments have been described by way of example only. Other variations will be apparent to those skilled in the art given the disclosure herein.

For example, although the above has been described in relation to a 3GPP wireless network, the principles described herein can be applied to any communication device that performs any external communication, such as in wireless network operation according to different communication standards or even Wake up on a wired network. Wherein the specific elements are coupled to each other, which means that they are effectively coupled, and are not necessarily intended to be directly connected to elements that are not intervening. Also, wherein it refers to a memory device, which may refer to any storage medium or plural media that is embodied in any one or more of the physical units; and wherein the reference is in the form of one or more processing cores in the same combination A processor on a circuit or a different integrated circuit. The invention is not limited to the specific embodiments described, but is limited to the scope of the appended claims.

2‧‧‧ device

4‧‧‧ integrated circuit; wafer

6‧‧‧Wireless transceiver; transceiver

8‧‧‧RF (radio frequency) front end; front end

10‧‧‧Antenna

12‧‧‧Oscillator

12i‧‧‧ first oscillator; RTC (instant counter) crystal

12ii‧‧‧second oscillator; CET (honeycomb timer) crystal

14‧‧‧ processor; baseband processor

16‧‧‧ memory device

16a‧‧‧Out-of-chip memory; memory; memory device

16b‧‧‧ memory on the chip; memory; memory device

18‧‧‧ time circuit

18i‧‧‧first time circuit; RTC (instant counter)

18ii‧‧‧second time circuit; CET (honeycomb timer); time circuit; second clock circuit

20‧‧‧Power control module; power controller

22‧‧‧Baseband processing module; fundamental frequency

24‧‧‧Correction drive; filter

26‧‧‧ frequency estimator

27‧‧‧ drift estimator

28‧‧‧Numerical generator; random number generator

30‧‧‧drift measurement feedback module; drift measurement feedback block; block; feedback mechanism

In order to better understand the present invention and show how it can be implemented, reference is made to the accompanying drawings, in which: the first figure is a schematic block diagram of a communication device, The second figure is another schematic block diagram of the communication device, and a chart of the simulation results of the third figure.

2‧‧‧ device

6‧‧‧Wireless transceiver; transceiver

8‧‧‧RF (radio frequency) front end

10‧‧‧Antenna

12i‧‧‧~kHz crystal

12ii‧‧~MHz crystal

14‧‧‧ processor; baseband processor

16‧‧‧ memory device

18i‧‧‧RTC (Instant Counter)

18ii‧‧‧CET (Hive Timer)

20‧‧‧Power Controller

22‧‧‧ fundamental frequency processing

24‧‧‧Correction drive

26‧‧‧ frequency estimator

27‧‧‧ drift estimator

28‧‧‧ Random Value Generator

30‧‧‧ Drift measurement feedback

Claims (47)

An apparatus includes: a first time component configured to generate a first time signal; a second time component configured to generate a second time signal independent of the first time component; a controller configured to Switching the device between a lower power mode in which the first time component is powered and the second time component is powered down, and a higher power mode in which the first and second time components are powered; a transceiver Based on the second time signal, when in the higher power mode, operable to externally transmit or receive a signal to the device; a corrector configured to be at a higher level between phases of the lower power mode During each phase of the complex phase of the power mode, one of the first time signals is corrected relative to the second time signal, each of the corrections performed at the respective correction times being corresponding to a plurality of cycles of the equal time signal And each of the corrections thereby producing a respective result indicative of a frequency of the first signal; and an estimator configured to be responsive to the earlier phase of the higher power mode The result of such other constant correction, the phase control performed in one aspect of the correction of one of the existing one. The apparatus of claim 1, wherein the estimator comprises: a drift estimator configured to comply with one of the results of the aforementioned corrections from the earlier phases of the higher power mode Depending on the drift, the correction time of the correction in the existing one of the phases of the higher power mode is adapted, the aspect including the correction time. The apparatus of claim 2, wherein the drift estimator includes a filter configured to receive the results of the prior corrections, the drift estimator being configured to be adapted by outputting one of the filters The correction time, and the existing correction time is adapted according to the drift. The apparatus of claim 3, wherein the filter comprises an averaging filter configured to maintain an average of the results of the prior corrections integral. The device of claim 3, wherein the filter comprises an infinite impulse response filter. The apparatus of claim 1, wherein the estimator comprises: a frequency estimator configured to be responsive to the results of the aforementioned corrections from the phase of the higher power mode earlier than the phase And adjusting one of the frequencies of the first time signal in the existing one of the phases of the higher power mode, the aspect comprising the frequency estimate. The apparatus of claim 6, wherein the frequency estimator comprises a filter configured to receive the results of the prior corrections, the frequency estimator being configured to be output by one of the filters The estimate is adapted and the existing estimate is adapted to the previous results. The apparatus of claim 7, wherein the filter comprises an averaging filter configured to maintain an average integral from the results of the prior corrections. The device of claim 7 or 8, wherein the filter comprises an infinite impulse response filter. A device as claimed in clause 7, 8 or 9, wherein the filter is arranged to maintain a weighted average whereby each of the prior results is weighted by a respective coefficient. The apparatus of claim 10, wherein the frequency estimator is configured to adapt the respective coefficients for each of the previously corrected correction times. The device of claim 2, wherein the device further comprises an override mechanism configured to measure the drift separately, and when the drift is measured above a threshold, the existing correction is applied A longer correction time will be determined by the drift estimator. The device of claim 2, wherein the device further comprises a value generator configured to be by a random value and one of a value generated from a predetermined series, except for the adaptation caused by the drift. Change the Correction time. The device of claim 1, wherein the transceiver is operative to externally communicate to the device via a network and is configured to check on the network during the higher power mode based on the second time signal External activities. The device of claim 1, wherein the transceiver is a wireless transceiver operative to externally communicate to the device via a wireless medium and configured to check on the wireless medium during the higher power mode External activities. The device of claim 1, wherein the transceiver is a wireless transceiver operative to externally communicate to the device via a wireless network and configured to check the wireless network during the higher power mode External activities on the road. The device of claim 16, wherein the transceiver is configured to perform a call operation during the higher power mode based on the second time signal to check the activity by listening to a call indication. The device of claim 10, wherein the transceiver is a wireless transceiver operative to externally communicate to the device via a wireless network and configured to be based on the second time signal at the higher power Performing a call operation during each of the modes to listen for a call indication; and wherein the respective correction times of the prior results are dependent on the call operation in the phases of the higher power mode One depends on the duration. The device of claim 14, wherein the first time signal is used to maintain synchronization with the network in the lower power mode. The device of claim 16, wherein the first time signal is used to maintain synchronization with the wireless network in the low power mode. The apparatus of claim 1, comprising a processor configured to process a signal transmitted or received by the transceiver, the processing being based on the second time signal. The apparatus of claim 17 wherein the first time signal is used to decode any call indications received during the call operation. The device of claim 1, wherein the first time signal is at a higher resolution than the second time signal. A method of operating a device, comprising: a first time component configured to generate a first time signal, and a second time component configured to generate a second time signal independent of the first time component; wherein the device Switching between a lower power mode in which the first time component is powered down and the second time component is powered off, and a higher power mode in which the first and second time components are powered; and when based on the second In the higher power mode of the time signal, the device externally transmits a signal to or receives a signal from the device; and wherein the method includes the step of: comparing the phase between the phases of the lower power mode During each complex phase of the high power mode, performing one of the first time signals relative to the second time signal, each of the corrections performing a respective correction time corresponding to some period of the equal time signal, And each of the corrections produces a respective result indicative of a frequency of the first signal; and the previous ones of the phases earlier than the higher power mode The result may be positive such, one aspect to control the correction performed prior to the phase of one of the. The method of claim 24, wherein the controlling comprises: adapting to a drift in the results of the previous corrections from the earlier phase of the higher power mode, the adjusting is performed on the comparison The correction time of the correction in the existing one of the phases of the high power mode, the aspect including the correction time. The method of claim 25, wherein the adapting comprises filtering the results of the prior corrections, and adapting the existing correction time by adjusting the drift of the correction time by one of the outputs of the filter . The method of claim 26, wherein the filtering comprises averaging the one of the results of maintaining the prior corrections. The method of claim 26, wherein the filtering comprises using none Limited impulse response filter. The method of claim 24, wherein the controlling comprises: depending on the results of the prior corrections from the earlier phase of the higher power mode, the higher power mode In the existing one of the equal phases, one of the frequencies of the first time signal is adjusted, the aspect comprising the frequency estimate. The method of claim 29, wherein the adapting comprises filtering the results of the prior corrections, and adapting the estimate by one of the outputs of the filter, and adapting the existing estimate to the previous results . The method of claim 29, wherein the filtering comprises maintaining an average integral of the results from the prior corrections. The method of claim 31, wherein the filtering comprises maintaining a weighted average, whereby each of the prior results is weighted by a respective coefficient. The method of claim 32, wherein the individual coefficients are adapted to each of the previously corrected correction times. The method of claim 29, wherein the filtering comprises using an infinite impulse response filter. The method of claim 25, further comprising the steps of: providing a transcendental mechanism to separately measure the drift, and when the drift is measured above a threshold, applying the existing correction to the existing correction The adjustment determines a longer correction time. The method of claim 25, further comprising the step of varying the correction time by a random value and one of the values generated from a predetermined series, in addition to the adaptation resulting from the drift. The method of claim 24, wherein the device communicates externally via a network and checks for external activity on the network during the higher power mode based on the second time signal. The method of claim 24, wherein the device communicates externally via a wireless medium and checks for external activity on the wireless medium during the higher power mode. The method of claim 24, wherein the device communicates externally via a wireless network and checks for external activity on the wireless network during the higher power mode. The method of claim 39, wherein the device performs a call operation during the higher power mode based on the second time signal to check the activity by listening to a call indication. The method of claim 33, wherein the device communicates externally via a wireless network and performs a call operation during each of the higher power modes based on the second time signal to listen a call indication; and wherein the respective correction times of the prior results are dependent on a duration of the call operation in the phases of the higher power mode. The method of claim 37, wherein the first time signal is used to maintain synchronization with the network in the lower power mode. The method of claim 39, wherein the first time signal is used to maintain synchronization with the wireless network in the low power mode. The method of claim 24, wherein the apparatus includes a processor configured to process a signal transmitted or received by the transceiver, the processing being based on the second time signal. The method of claim 40, wherein the first time signal is used to decode any call indications received during the call operation. The method of claim 24, wherein the first time signal is at a higher resolution than the second time signal. A computer program product comprising a code, when executed, operates the device in accordance with the steps described in any of the patent applications 24 to 46.