MXPA98000061A - Receiving portion of a radiocommunication device - Google Patents

Abstract

The present invention relates to a receiving portion of a radio communication device including a circuit that is periodically moved to a "sleep" mode of operation, the circuit periodically exits from sleep mode in response to a reactivation signal; first clock signal, the clock pulses are counted in the first clock signal, the reactivation signal is generated each time the number of clock pulses counted in the first clock reaches an updateable number, a second one is generated a clock signal having a frequency higher than the frequency of the first clock signal, the clock pulses in the second clock signal are counted during each time interval determined by the first clock signal, a frequency error is calculated of the first clock signal with respect to the frequency of that of the second clock signal, based on a result of the counting of the clock pulses in the second clock signal, the updateable number is set in response to the calculated error of the frequency of the first alarm signal

Description

RECEIVING PORTION OF A RADIOCOMMUNICATION DEVICE BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a receiving portion of a radio communication device, such as a mobile telephone device.

Description of Related Art Some mobile telephone devices have receiving portions that fall periodically in a "sleep" mode of operation. When the receiving portion is in "sleep" mode of operation, most circuits in the receiving portion are disabled to save electrical power. At an expected time of transmission of station interrogation signals from a base station, the receiving portion changes from the "sleep" mode it is in, to an "awake" mode of operation (a normal mode or a standby mode) . United Kingdom Patent Application GB 2297884 A, which corresponds to Japanese Unexamined Patent Application, published, 8-251655, discloses an energy saving device in a mobile telephone. In UK patent application GB 2297884 A, the mobile telephone has a high frequency system clock and a processor arranged to process interrogation signals received while the telephone is in its standby condition. When the interrogation signals are not received, it is possible that the telephone is placed in a "sleeping" condition by deactivating the system clock. Reactivation occurs in response to a calibrated number of clock cycles produced by a low-frequency "sleep" clock. When it is reactivated, the system clock counters, which specify the periods below the frame and frame periods, are reloaded, so that they can be reactivated in the required phase. The phase of these meters is compared with the signals received from the base stations and modifications are made to the system accounts as required. The degree to which such modifications are required is also used to recalibrate the sleeping clock. In a power saving device of UK patent application GB 2297844 A, the time control of reactivation is determined by the sleep clock. The reactivation includes the reactivation of the processing of the received signal. Consequently, a minimum increment or a minimum decrement (a minimum variation unit) of the reactivation time control of the received signal processing corresponds to the period of the dormant clock. Thus, it is difficult to vary the control of reactivation time of the processing of the received signal in a unit smaller than the period of the sleeping clock.

In the energy saving device of the application of the United Kingdom GB 2297884 fi, the sleep clock is recalibrated in response to the comparison between the phase of the system clock counters and the phase of the signals received. from the base stations, as long as a frequency error is not detected in the sleeping clock.

BRIEF DESCRIPTION OF THE INVENTION It is an object of this invention to provide an improved receiving portion of a radio communication device. A first aspect of this invention provides a receiving portion of a radio communication device, comprising a circuit that moves periodically to a sleep mode of operation; periodically leaving the circuit of the sleeping mode of operation in response to a reactivation signal; first means for generating a first clock signal; second means for counting the clock pulses at the first clock signal and generating the wake-up signal each time the number of the clock pulses counted on the first clock reaches a current adjustable number; third means for generating a second clock signal having a frequency greater than a frequency of the first clock signal; quarters means for counting the clock pulses on the second clock signal, during each time interval determined by the first clock signal; fifth means for calculating an error in the frequency of the first clock signal, with respect to the frequency of the second clock signal, on the basis of a? counting result by the fourth means; and sixth means to fix the updatable number in response to the error calculated by the fifth means. A second aspect of this invention is based on its first aspect and provides a receiving portion further comprising a receiving processing unit; seventh means for activating the third means in response to the reactivation signal, and then activating the receiving processing unit at a time that follows a moment of the activation of the third means in an updateable time; and eighth means to set the updateable time in response to the error calculated by the fifth means. A third aspect of this invention is based on s? first aspect and provides a receiving portion additionally comprising a receiving processing unit, which is periodically moved to a dormant operating mode; the receiving processing unit of the dormant operating mode in response to the reactivation signal is periodically left. A fourth aspect of this invention is based on s? third aspect and provides a receiving portion which additionally comprises seventh means for comparing a segment of the error calculated by the fifth means, with a predetermined value corresponding to a search window width, of multiple paths, used in the unit reception processor; and eighth means to change the updatable number in response to a result of the comparison made by the seventh means. A fifth aspect of this invention provides a receiving portion of a radio communication device, comprising a circuit that moves periodically to a sleep mode of operation; periodically leaving the circuit of the sleeping mode of operation in response to a reactivation signal; first means for generating a first clock signal; a frequency divider for generating a second clock signal in response to the first clock signal generated by the first means; the second clock signal having a frequency lower than the frequency of the first clock signal; second means for counting clock pulses at the first clock signal and generating the wake-up signal each time the number of clock pulses counted at the first clock reaches an updateable number; third means for generating a third clock signal having a frequency higher than the frequency of the first clock signal; fourths means for counting the clock pulses of the third clock signal during each time interval determined by the second clock signal; fifth means for calculating an error in the frequency of the first clock signal with respect to the frequency of the third clock signal, based on a count result effected by the fourth means; and sixth means to fix the updatable number in response to the error calculated by the fifth means. A sixth aspect of this invention is based on its fifth aspect and provides a receiving portion further comprising a receiving processing unit; Seventh means to activate the third means in response to the reactivation signal and then activate the reception processing unit at a time that comes after a moment of the activation of the third means, in an updateable time; and eighth means to set the updateable time in response to the error calculated by the fifth means. A seventh aspect of this invention is based on its fifth aspect and provides a receiving portion further comprising a receiving processing unit that moves periodically to a sleep mode of operation; the receiving processor unit periodically comes out of sleep mode in response to the reactivation signal. An eighth aspect of this invention is based on its seventh aspect and provides a receiving portion which additionally comprises seventh means for comparing a segment of the error calculated by the fifth means, with a predetermined value, corresponding to a window width of multiple path search, used in the reception processing unit; and eighth means to change the updatable number in response to a result of the comparison made by the seventh means.

A ninth aspect of this invention provides a receiving portion of a radio communication device comprising a controller that moves periodically to a dormant operating mode; periodically leaving the controller out of sleep mode of operation in response to a reactivation signal; first means for generating a first clock signal; second means for counting clock pulses at the first clock signal and generating the wake-up signal each time the number of clock pulses counted at the first clock reaches an updateable number; third means for generating a second clock signal having a frequency greater than the frequency of the first clock signal; and fourth means for counting the clock pulses of the second clock signal during each time interval determined by the first clock signal; wherein the controller comprises fifth means for calculating error of the frequency of the first clock signal with respect to the frequency of the second clock signal, based on a result of counting by the fourth means; and sixth means to fix the updatable number, in response to the error calculated by the fifth means. A tenth aspect of this invention provides a receiving portion of a radio communication device, comprising a circuit that moves periodically to a sleep mode of operation; periodically leaving the circuit of the sleeping mode of operation in response to a reactivation signal; first means for generating a first clock signal; second means for generating a second clock signal having a frequency greater than the frequency of the first clock signal; the second clock signal having a frequency accuracy greater than a frequency precision of the first clock signal; third means for periodically detecting a relation between the frequency of the first clock signal and the frequency of the second clock signal; and fourth means for periodically generating the reactivation signal in response to the first clock signal, in a time control that depends on the ratio detected by the third means BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a prior art energy saving device for a mobile telephone. Figure 2 is a block diagram of a portion of a radio communication device according to a first embodiment of this invention. Figure 3 is a flowchart of a segment of a program related to a controller of Figure 2. Figure 4 is a diagram in the time domain, the states of the circuits and the processes in the radio communication device of Figure 2 Figure 5 is a block diagram of a portion of a radio communication device according to a second embodiment of this invention; and Figure 6 is a flowchart of a segment of a program related to a controller of Figure 5.

DESCRIPTION OF THE PREFERRED MODALITIES A prior art energy-saving device for a mobile telephone, which is described in UK patent application GB 2297884 A, will be further explained so that this invention can be better understood. Figure 1 shows the prior art energy-saving device of UK patent application GB 2297884 A, which includes a system clock 41 and its associated counters 42, 43 and 44. The system clock 41 It outputs a clock signal that has a frequency of 16.8 MHz. The system clock 41 and the counters 42, 43 and 44 communicate with a digital signal processor 61. The processor 61 receives external time control signals, from base stations, by means of an input line 62. The processor 61, the system clock 41 and the counters 42, 43 and 44 can be placed in a sleeping mode, during which the system clock 41 stops operating until it is reactivated by an interrupt signal supplied in an interrupt line 63 to the processor 61, from an adjustable counter 64. The adjustable counter 64 receives clock pulses for sleep, from a 65 low frequency sleep clock, operating at approximately 32 kHz. In the prior art energy saving device of FIG. 1, the clock signal fed from the system clock 41 controls the time to the processor 61 by means of a time control line 66. The counter 42 counts the clock pulses from the system clock 41, to generate indications of the beginning of periods inferior to the frame or arc, which are supplied to the processor 61 by a data line 67. The period below the frame or frame corresponds to a frequency of 336 kHz. The reduced frequency clock pulses are supplied from the counter 42 to the counter 43, which supplies indications of the start of rack periods to the processor 61, by a data line 68. The frame or frame period corresponds to a frequency of 50 Hz. The counter 44 receives the output signal from the counter 43, which gives indications of the beginning of the periods superior to the frame or frame, which are supplied to the processor 61, through a data line 69. period greater than the frame or frame corresponds to a frequency of 1.38 Hz. In the prior art energy saving device of Figure 1, the processor 61 is designed to supply new count values to the counters 42, 43 and 44 by the data lines 70, 71 and 72, respectively. That way, after what is the system clock 41 in s? Asleep mode, the system phase can be reset by downloading new account values to counters 42, 43 and 44. Then counters 42, 43 and 44 can be reactivated so that they continue to count pulses directly or indirectly generated by the clock 41 of the system. In the prior art energy saving device of FIG. 1, the processor 61 serves to check whether the counters 42, 43 and 44 are in phase with the signals received from the base stations by means of the input line 62. Thus, the processor 61 can compare its local system phase with the network system phase and, when appropriate, modify the account values through the data lines 70, 71 and 72, in order to carry the values from account to phase with the general network. In the prior art energy saving device of FIG. 1, the sleep timer 65 generates sleep clock pulses that are counted by the variable counter 64. The processor 61 supplies an account value to the variable counter 64. by means of a data line 73. Accordingly, the variable counter 64 is controlled by means of the processor 61. The variable counter 64 produces trigger pulses by reducing the pulse frequency of the sleep clock. After counting a number of sleep pulses, defined by the value supplied on the data line 73, the variable counter 64 outputs a wake-up pulse on the interrupt line 63. The wake-up pulse instructs the processor 61 to reactivate the system, if the system had been put in sleep mode. The prior art energy-saving device of FIG. 1 operates as follows: During the sleep mode, the system clock 41 is inactive and the processor 61 is waiting for a wake-up pulse. When the processor 61 receives a wake-up pulse from the variable counter 64, via the interruption line 63, the system clock 41 is activated. After the activation of the system clock 41, a brief interval will be provided during which the circuit is allowed to be powered and stabilized, so that normal processing can be resumed. Before resuming normal processing, counters 42, 43 and 44 are reloaded with new values via data lines 70, 71 and 72, and the operation of processor 61 and system clock is re-established. 41, as if he had not put them in sleep mode. Thus, the processor 61 system clock 41 is placed in the dormant ear to the point in time at which it is reactivated. The period between the reactivation points in time is specified in terms of a calibrated number of sleeping clock pulses. After the counters 42, 43 and 44 have been loaded with the new values, they are enabled at the appropriate time point, in order to bring them to phase with the operating environments. The phase of the counters 42, 43 and 44 ee compared with the external time control signals, received by the input line 62. The duration of a sleeping clock pulse will not tend to represent an integer number of clock pulses of the clock. system. Thus, the points in time for the reactivation will tend to move with reference to the optimal time point defined in terms of system clock pulses; and, consequently, a recalibration is continually required. A recalibration procedure is performed in each cycle, referring to the degree to which the counters 42, 43 and 44 are out of phase with the external time control signals received by the input line 62. The phase comparison provides a determination of whether the sleep timer has been delayed or accelerated. When the sleep timer has been delayed, the variable counter 64 requires more accounts to reactivate the system clock at the optimum time point. When the sleep timer has been accelerated the variable counter 64 requires fewer accounts to reactivate the system clock at the optimal point in time. Even while the sleep timer 65 remains oscillating at a constant frequency, the trigger point in time will tend to shift. Therefore, occasionally a cycle is required in which fewer accounts are made by the variable counter 64 or that the variable counter 64 performs more accounts. Then the account is reset in the next cycle and the process continues. Thus, the trigger point in time is determined by the variable counter 64; it can move slightly with reference to the optimum point in time, defined in terms of system clock pulses. On the other hand, the point of activation in time, defined by the sleep clock, does not move beyond a degree in which the processor 51 can recover the situation with reference to the signals received externally. After the sleep clock is calibrated and a new account number is supplied to the variable counter 54, a decision is made as to whether the sleeping operation ode should be maintained or not. Specifically, the data received in the interrogation download is examined. When this data calls for the establishment of a connection with a base station, it is decided that the operating mode should not be kept asleep. In that case, the active mode of operation in which the system clock 41 is kept operational and measures to establish a call is started. When the establishment of a connection with a base station is not required, it is decided that the operating mode should be kept asleep. In that case, the system clock 41 is deactivated and the system returns to its sleep mode. In the prior art energy saving device of FIG. 1, the period between the time points for reactivation is specified in terms of a calibrated number of dorrni clock pulses. The reactivation includes the reactivation of the processing of the received signal. Consequently, a minimum increment or a minimum decrement (a minimum unit of variation) of the time control of the reactivation in the processing of the received signal corresponds to the period of the sleep timer. Thus, it is difficult to vary the time control of the reactivation of the processing of the received signal, in a smaller unit than the period of the dormant clock. In the energy-saving device of the figure 1, the sleep timer is calibrated again in response to the result of the comparison between the phase of the counters 42, 43 and 44 and the phase of the external time control signals, received via the input line 62, while no frequency error is detected in the sleep clock.

FIRST MODALITY With reference to Figure 2 a radio communication device of a first embodiment of this invention includes a high frequency clock oscillator 1, a counter 2, a pulse generator 3, a low frequency clock oscillator 4,? N counter 5, a controller 6 and a transmission / reception processing unit 7. For example, the radio communication device of Figure 2 corresponds to a mobile station in a radio communication network. The high frequency clock oscillator 1 is connected to the counter 2, the controller 6 and the transmission / reception processing unit 7. The counter 2 is connected to the pulse generator 3 and the controller 6. The pulse generator 3 is connected to the low frequency clock oscillator 4. The low frequency clock oscillator 4 is connected to the counter 5. The counter 5 is connected to the controller 6. The controller 6 is connected to the transmission / reception processor unit 7. The high frequency clock oscillator 1 generates a high frequency clock signal having a frequency, for example, of 12.5 MHz. It is preferable that the high frequency clock oscillator 1 has a high frequency stability and a high accuracy of frequency. . The frequency stability and the frequency accuracy of the high frequency clock oscillator 1 are better than those of the low frequency clock oscillator 4. For example, the high frequency clock oscillator 1 uses a compensated temperature crystal oscillator. The high frequency clock oscillator 1 outputs a high frequency clock signal to the counter 2 and the transmission / reception processor unit 7. The transmit / receive processing unit 7 processes a transmission signal and a received signal, in response to a high frequency clock signal. Specifically, the transmit / receive processor unit 7 demodulates a received radio signal to a baseband signal. The transmit / receive processor unit 7 informs the controller 6 of the baseband signal that generally contains an introgation signal. The low frequency clock oscillator 4 generates a low frequency clock signal having a frequency lower than the frequency of the high frequency clock signal generated by the high frequency clock oscillator 1. The frequency of the low frequency clock signal is equal, for example, to 500 kHz. The low frequency clock oscillator 4 outputs the low frequency clock signal to the pulse generator 3 and the counter 5. The pulse generator 3 periodically outputs a pulse to the counter 2, in response to the clock signal of low frequency. Each pulse that comes out of the pulse generator 3 corresponds, in length of time (duration, or pulse amplitude) to a predetermined number of pulses of the low frequency clock signal. The default number, for example, is equal to 27,500. The pulse generator 3 includes, for example, a counter or a frequency divider. The counter 2 is preferably of the 20 bit type. The counter 2 counts the pulses of the high frequency clock signal for a period equal to the width (duration) of each pulse that leaves the pulse generator 3. Thus, the counter 2 detects or rnides the width (the duration) of each pulse that leaves the pulse generator 3. The number of counted pulses occurring at the end of each count period represents the width (the duration) of each pulse that comes out of the pulse generator 3. The counter 2 informs the controller 6 of the number of counted pulses, which represents the width (the duration) of each pulse that the pulse generator 3 went out. Immediately after the counter 2 informs the controller 6 of the width (the duration) of each pulse output from the pulse generator 3, the counter 2 resets the number of pulses counted. The counter 5 counts the pulses of the low frequency clock signal and periodically generates a reactivation signal (a reset signal) in response to the low frequency clock signal. The counter 5 outputs the reactivation signal to the controller 6. Specifically, the counter 5 is loaded with information of an updateable reference number. Each time the number of counted pulses of the low frequency clock signal reaches the reference number, the counter 5 outputs a reactivation signal and then resets the number of counted pulses. The controller 6 includes a PSD (Digital Signal Processor), a UPC (central processing unit) or a similar circuit having a combination of an input / output port, a processing section, a read only memory (ROM) and a random access memory (RAM). The controller 6 operates in accordance with a program stored in its internal ROM.

The controller 6 can switch between a sleep mode of operation and an awake operation mode (normal odo). According to the program, the controller 6 switches from the sleep mode of operation to the awake operation mode in response to the wake-up signal of the counter 5. According to the program, the controller 6 controls the activation and deactivation of the oscillator 1 of high frequency clock and of the processing unit 7 of transmission / reception. According to the program, the controller 6 periodically calculates a new reference number and, periodically, loads the counter 5 with information of the new reference number. The radio communication device of Figure 2 may be in an intermittent reception operation mode, which has the alternation of an awake operation mode (a normal mode) and a sleep mode of operation. During the intermittent reception operation mode, the oscillator 4 of the low frequency clock and the counter 5 are still active. Thus, oscillator 4 of the low frequency clock and counter 5 remain in operation even during sleep mode. In the case where the frequencies of the high frequency clock signal and the low frequency clock signal are exactly equal to 12.5 MHz and 500 kHz, respectively, oscillator 1 of the high frequency clock generates 25 pulses while the oscillator 4 of the low frequency clock generates a pulse. An error in the frequency of the low frequency clock signal, with respect to the frequency of the high frequency clock signal, is corrected in the following manner. The counter 2 counts the pulses of the high frequency clock signal during each period corresponding in time duration to the predetermined number (for example, 27,500) of pulses of the low frequency clock signal. The number of counted pulses that occurs at the end of each count period represents the length in time corresponding to the predetermined number (eg, 27,500) of pulses of the low frequency clock signal. The counter 2 informs the controller 6 of the number of counted pulses, which represents the length in time corresponding to the predetermined number (for example, 27,500) of pulses of the low frequency clock signal. According to the program, the controller 6 compares the counted pulse number with a predetermined pulse number (equal, for example, to 687,500 = 25 x 27,500) which corresponds to a condition in which an error of the frequency of the pulse is absent. the low frequency clock signal, with respect to the frequency of the high frequency clock signal. Then the controller 6 calculates a mean frequency error or an average frequency error of the low frequency clock signal per pulse of the low frequency clock signal, of the aforementioned comparison result. According to the program, the controller 6 periodically sets a new reference number in response to the calculated average frequency error and periodically loads the counter 5 with information of the new reference number. Additionally, the controller 6 controls the activation of the oscillator 1 of the high frequency clock and of the transmission / reception processor unit 7. As indicated previously, controller 6 operates according to a program stored in its internal ROM. Figure 3 is a flowchart of a segment of the program which refers to the intermittent reception operation mode. As shown in FIG. 3, a first step SI of the program segment for a reactivation signal produced in the counter 5. When the step SI perceives that a reactivation signal is output from the counter 5, the program progresses from step YES to step S2. Step S2 changes controller 6 from a sleep mode to an awake operation mode (a normal mode). A step S3, after step S2, cancels the operation suspension of oscillator 1 of the high frequency clock and, consequently, reactivates oscillator 1 of the high frequency clock. Additionally, step S3 cancels the operation stop of counter 2 and pulse generator 3 and, therefore, reactivates counter 2 and pulse generator 3. A step S4, subsequent to step S3, changes the transmit / receive processing unit 7, from a sleep mode to an awake operation mode (normal mode). In 79 other words, step 54 reactivates the transmission / reception processor unit 7. When there is a change of sleeping mode of operation, the transmission / reception processor unit 7 makes preparations for the awake operation mode. After the preparations have been made, the transfer / reception processing unit 7 falls into the awake operation mode, in which the transmission / reception processing unit 7 receives an interrogation radio signal from a base station, and desinodulates the received signal, at a baseband signal. Step S4 receives the baseband signal from the transmit / receive processor unit 7. Additionally, step 4 reads the information of the fractional part of a value- "0" from the RAM inside the controller 6. The value "0" has been calculated during the immediately preceding execution cycle of the progi-arna segment . Step S4 controls the time of reactivation of the transmission / reception processing unit 7, in response to the fractional part of the value "0". Specifically, step S4 delays the moment of reactivation of the transmission / reception processing unit 7, from an uncorrected reference moment, in a time corresponding to the fractional part of the value "0". A step 55, after step S4, decides whether a call to the current mobile station is present or absent, referring to the baseband signal. When it is decided that a call is present to the present mobile station, the program proceeds from step S5 to block S20 to establish a connection to the base station. When it is decided that a call to the present mobile station is absent, the program proceeds from step S5 to step S6. Step 86 changes the transmit / receive processing unit 7 to a sleeping mode of operation. In other words, step S6 deactivates transmission / reception processor unit 7. A step S7, subsequent to the step SS, r-ecibe a signal from the counter 2, which represents a counted pulse number, indicator of a length of time corresponding to the predetermined number (for example, 27,500) pulses of the signal of low frequency clock. A step S8, which follows step S7, calculates a ratio between the number of counted pulses and the predetermined number of pulses (equal, for example, to 687,500 x 25 x 27,500). The predetermined number of pulses corresponds to a condition in which an error of the frequency of the low frequency clock signal with respect to the frequency of the high frequency clock signal is absent. Then step S8 calculates a mean frequency error or an average frequency error "n" of the low frequency clock signal, per pulse of the low frequency clock signal, from the calculated pulse-number ratio. Specifically, the mean frequency error "n" is expressed as "n = Cp / Pp", where "Cp" denotes the counted number of pulses and "Pp" denotes the predetermined number of pulses (equal, for example, to 687,500 = 25 x 27,500). In that case, the actual frequency of the low frequency clock signal is given by "500 ph" kHz. Step 88 calculates a value "0" which is expressed as "0 = LpdOOpn", where "L" denotes a desired time interval, measured by counter 5. The value "0" is composed of an integral part of a fractional part. Step S8 establishes a new reference number for the integral part of the value "0". Step 88 loads counter 5 with information of the new reference number. The counter 5 uses the new reference number to generate a next reactivation signal. Step 88 stores information of the fractional part of the value "0" in the RAM within the controller 6, as a control parameter of the time controller, for a next execution cycle of the program segment. A step 89, subsequent to step 88, deactivates the high frequency clock oscillator 1. In other words, step 89 suspends the operation of oscillator 1 of the high frequency clock. One step 810, which follows step S9, switches controller 6 to sleep mode. After step S10, the program returns to step YES. With reference to Figure 4, the mode of operation of the system, which receives intermittently (the radio communication device of Figure 2) has the alternation of an awakened operation mode and a sleep mode of operation. During the operating mode that it receives intermittently, oscillator 4 of the low frequency clock and counter 5 continue to be in connected states (active states). On the other hand, the oscillator 1 of the high frequency clock changes periodically between a connected state (an active state) and a disconnected state (an inactive state). Oscillator 1 of the high-frequency clock switches to the connected state before the sleeping mode of the system is replaced by the awake operating mode of the system. The high frequency clock oscillator 1 changes to the disconnected state after the awake operating state of the system is replaced by the sleeping mode of the system. A radio signal r-eceptor process, implemented by the transmission / reception processor unit 7, periodically changes between a connected state (active state) and a disconnected state (inactive state). The radio signal receiving process, effected by the transmit / receive processing unit 7, changes to the connected state before the sleep mode of the system is replaced by the awake operation method of the system, but after the clock oscillator 1 High frequency switch to the connected state. The r-eceptor process of the radio signal, performed by the transmit / receive processing unit 7, changes to the disconnected state when the awake operation mode of the system is replaced by the sleep mode of the system.

The baseband processing implemented by the transmission / reception processing unit 7 changes periodically between a connected state (an active state) and a disconnected state (an inactive state). The baseband processing effected by the transmit / receive processing unit 7 changes to the connected state before the system's sleeping operation mode is? -supposed by the awake operating system of the system. The change of the baseband processing to the connected state is concurrent with the change of the processing of the radio signal to the connected state. The baseband processing effected by the transmit / receive processing unit 7 changes to the disconnected state after the awake operating state of the system is replaced by the operating mode of the system, but before the high clock oscillator 1 frequency change to disconnected state. The radio communication device of figure 2 has the following advantage with respect to the energy-saving device of the prior art, of figure 1. In the radio communication device of figure 2 the moment of reactivation of the processing unit 7 is controlled. Transmission / reception in response to the fractional part of the value "0". Thus, it is possible to vary the time of the reactivation of the transmission / reception processor unit 7 in a unit smaller than the period of the low frequency clock signal. Consequently, the radio communication device of FIG. 2 provides a much finer time control, with respect to the reactivation of the transmission / eception processing unit 7.

SECOND MODALITY Figure 5 shows a second embodiment of this invention, which is similar to the embodiment of Figure 2, except for the design changes indicated below. The embodiment of Figure 5 includes a controller 6A and a transmit / receive processor unit 7A, in place of the controller 6 and the transmit / receive processing unit 7 of Figure 1, respectively. In the embodiment of Figure 5 the counter 5 is connected to the transmission / reception processing unit 7A. In the embodiment of FIG. 5, the counter 5 periodically outputs a reactivation signal to the controller 6A and to the transmission / reception processing unit 7A. The transmission / reception processing unit 7A is designed for AMDC (multiple access with code division). The transmit / receive processing unit 7A restarts its operation in response to a wake-up signal fed from the counter 5. The controller 6A operates in accordance with a program stored in its internal ROM. Figure 6 is a flowchart of a segment of the program related to the controller 6A. The program segment of figure 6 is similar to the program segment of figure 3, except for the design changes indicated below. The program segment of figure 6 includes steps S4A and S8A, instead of steps 84 and 88 of figure 3, respectively. Step S4A follows step S3 and precedes step S5. Step S4A receives a baseband signal from the transmit / receive processing unit 7A. Step S8A follows step 87 precedes step S9. Step S8A calculates the relationship between the number of counted pulses and the predetermined number of pulses (equal, for example, to 687,500 = 25 x 27,500). The predetermined number of pulses corre sponds to a condition in which an error of the frequency of the low frequency clock signal is absent, with respect to the frequency of the high frequency clock signal. Then step 88A calculates an average frequency error or an average frequency error "n" of the low frequency clock signal per pulse of the low frequency clock signal, from the calculated ratio pulse-number. Specifically, the mean frequency error "n" is expressed as "n = Cp / Pp", where "Cp" denotes the number of pulses counted and "Pp" denotes the predetermined number of pulses (equal, for example, to 687,500 = 25 x 27,500). In that case, the frequency of the low frequency clock signal is given by "500 pn" kHz. Step S8A calculates a value "0" which is expressed as "0 = LpSOOpn", where L denotes a desired time interval, measured by counter 5. The value "0" is composed of an integral part and a fractional part . Step S8A compares the fractional part of the value "0" with a window width time for a multipath search, implemented by the transmit / receive processing unit 7A. When the fractional part of the value "0" is equal to or greater (longer) than the time of the width of the search window, step S8A includes a first sequence of processes. On the other hand, when the fractional part of the value "0" is smaller (shorter) than the time of the width of the search window, the step 88A involves a second sequence of processes. During the first sequence of processes, step 88A establishes a new reference number for the integral part of the value "0". Step S8A loads counter 5 with information of the new reference number. During the second sequence of processes, step S8A signals a new reference number, equal to the integral part of the value "0" rnenos "1". This results in an earlier time in which the counter 5 outputs a next reactivation signal. Step S8A loads counter 5 with information of the new reference number. As previously indicated, the transmit / receive processor unit 7A restarts its operation in response to a wake-up signal powered from the counter 5. When it is reset, the transmit / receive processor unit 7a performs the reacquisition (reset) of the transmitter / receiver processing unit 7a. Wafer synchronization and RAKE finger assignment, as preparation for the awake operation procedure. Additionally, the transmit / receive processing unit 7A requires a parallel search by a plurality of sliding correlators, multipath demodulator signals and execution of a RAKE combiner process to give a resulting combination signal. The transmit / receive processor unit 7A derives a baseband signal from the resulting combination signal. The transmit / receive processing unit 7A outputs the baseband signal to the controller 6A. A frequency error of the low frequency clock signal, with respect to the high frequency clock signal, is corrected as in the embodiment of FIG. 1. This frequency error correction allows the transmission processing unit 7 / reception reliably implement the RAKE reception.

Claims (10)

NOVELTY OF THE INVENTION CLAIMS

1. - A receiver portion of a radio communication device, characterized in that it comprises: a circuit that moves periodically to a sleeping mode of operation; periodically leaving the circuit of the sleeping mode of operation in response to a reactivation signal; first means for generating a first clock signal; second means for counting clock pulses at the first r-eloj signal and generating the reactivation signal each time the number of clock pulses counted at the first clock reaches an updateable number; third means for generating a second clock signal having a frequency greater than a frequency of the first clock signal; fourth means for counting clock pulses at the second clock signal, during each time interval determined by the first clock signal; fifth means for calculating - an error of the frequency of the first clock signal, with respect to the frequency of the second clock signal, based on a result of counting by the fourth means; and sixth means to establish the updatable number, in response to the error calculated by the fifth means.

2. A receiving portion according to claim 1, further characterized in that it comprises: a receiving processing unit; seventh means to activate-third means, in response to the reactivation signal; and then activate- the reception processing unit at a moment that comes after a moment of the activation of the third media, in an updateable time; and eighth means to establish the updateable time in response to error-calculated by the fifth means.

3. A receiving portion according to claim 1, further characterized in that it comprises a receiving processing unit that moves periodically to a sleeping mode of operation; the reception processing unit of the sleep operation mode periodically comes out in response to the reactivation signal.

4. A receiving portion according to claim 3, further characterized in that it comprises additionally: seventh means for comparing a segment of the error calculated by the fifth means, with a predetermined value, corresponding to a search window width, of trajectories multiple, used in the reception processing unit; and eighth means to change the updatable number in response to a result of the comparison made by the seventh means.

5. A receiver portion of a radio communication device, characterized in that it comprises: a circuit that moves periodically to a sleeping mode of operation; periodically leaving the sleeping operation circuit in response to a reactivation signal; first means for generating a first clock signal; a frequency divider for generating a second clock signal, in response to the first clock signal generated by the first means; the second clock signal having a lower frequency than a frequency of the first clock signal; second means for counting the clock pulses at the first clock signal and generating the wake-up signal each time the number of clock pulses counted at the first clock reaches an updateable number; third means for generating a third clock signal having a frequency greater than the frequency of the first clock signal; fourths means for counting the clock pulses of the third clock signal during each time interval determined by the second clock signal; fifth means for calculating an error of the frequency of the first clock signal with respect to the frequency of the third clock signal, based on a result of counting by the fourth means; and sixth means to establish the updatable number in response to the error calculated by the fifth means.

6. A receiving portion according to claim 5, further characterized in that it comprises additionally: a receiving processing unit.; seventh means for activating the third means in response to the reactivation signal and then activating the reception processor-a unit at a time that is subsequent to a moment of the activation of the third means, in an updateable time; and eighth means to establish the updateable time in r-espuesta to the error calculated by the fifth means.

7. A receiving portion according to claim 5, further characterized in that it further comprises a receiving processor-a unit, which is periodically moved to a sleeping operating mode; periodically the receiving processor unit leaves the sleep mode of operation, in response to the reactivation signal.

8. A receiving portion according to claim 7, further characterized in that it further comprises: seventh means for comparing a segment of the error-calculated by the fifth means with a predetermined value corresponding to a window width of multi-path search , used in the reception processing unit; and eighth means to change the updatable number, in response to the result of the comparison made by the seventh means.

9. A receiver portion of a radio communication device, characterized in that it comprises: a controller that moves periodically to a sleeping mode of operation; periodically leaving the operating mode controller dormant in response to a reactivation signal; first means pa? -a generating a first clock signal; second means for counting the clock pulses of the first clock signal and generating the wake-up signal each time the number of clock pulses counted on the first clock reaches an updateable number; third means for generating a second clock signal having a frequency greater than the frequency of the first clock signal; and fourth means for counting the clock pulses in the second clock signal during each time interval determined by the first clock signal; wherein the controller comprises fifth means for calculating an error of the frequency of the first clock signal with respect to the frequency of the second clock signal, based on a count result of the fourth means; and sixth means to indicate the updatable number in response to the error calculated by the fifth means.

10. A receiver portion of a radio communication device, characterized in that it comprises: a circuit that moves periodically to a sleeping mode of operation; periodically leaving the operating mode circuit dormant in response to a reactivation signal; first means for generating a first clock signal; second means for generating a second clock signal having a frequency higher than the frequency of the first clock signal; the second clock signal having a frequency accuracy greater than a frequency accuracy of the first clock signal; third means for periodically perceiving a relation between the frequency of the first clock signal and the frequency of the second clock signal; and fourth means for periodically generating the reactivation signal in response to the first clock signal, in a time which depends on the ratio detected by the third means.