DE102013001076A1 - Time calibration method and apparatus - Google Patents

Abstract

A device, a program and a method, the device comprising: a first timer element, a second timer element, a controller configured to switch the device between a lower power mode in which the second timer element is turned off and a mode with In the case of higher power in which both timing elements are turned on, a transmitter / receiver configured to send or receive a signal external to the device when in the higher power mode based on the second one Timer element, and a calibration device configured to perform a calibration of the first element relative to the second timer element during each of a plurality of phases of the higher power mode between phases of the lower power mode. The apparatus further comprises an estimator configured to control an aspect of the calibration performed in a current phase of the phases, based on estimates from previous calibrations, prior to the phases of the higher power mode.

Description

Field of the invention

The present invention relates to a communication device having a higher power mode and a lower power mode, and relates to calibrating a timing element of the device during a higher power mode phase.

background

A communication device optionally includes a processor for executing a signal processing code or "soft modem" code suitable, for example, to communicate over a wireless radio network, such as a 3GPP network, via a wireless transceiver of the device. In one embodiment, the processor may take the form of a baseband processor configured to execute a software-based baseband modem code, with most or all of the baseband domain functions being performed in software, such operation being in conjunction with a particular radio frequency (RF). Entrance area is done. A communication device is typically provided with a higher power mode in which the transceiver and the processor are powered to be ready for external communication with the device via the network, and a low power mode is provided in which the processor is relatively inactive and the transceiver and the processor are not communicating externally. Other types of wired or wireless communication devices may also be provided with a similar low power mode and a higher power mode.

When a processor, such as a baseband processor, is in a low power mode, one or more high resolution clock signals may be faded to save power. In this mode, the only remaining timer is a low power and low frequency device, such as a 32 kHz real-time counter (RTC). The exact frequency of the RTC can not usually be determined in advance because it depends on external factors such as temperature. On the other hand, the baseband must be regularly activated to check for external activities such as incoming calls, SSM messages, etc. These activities are called "paging activities". To ensure timely startup from low power mode, the RTC must be calibrated. For example, the required accuracy in terms of the estimated frequency may be 2 ppm to ensure that the baseband is activated in a timely fashion to decode paging blocks within the RF receive window, although the number is dependent on system design parameters, such as how large an error may be when booting from standby mode. Optionally, a larger error could be tolerated to the detriment of other factors, such as additional processing overhead and / or noise sensitivity, etc. Therefore, other implementations may have different requirements.

However, to calibrate the RTC, a higher-frequency stable but higher-power device such as the radio clock (CET), for example, with a clock of 15.36 MHz, is used to measure the RTC. Each measurement is that both the RTC and the CET are active for the same time and that the number of RTC cycles or CET cycles is counted. The ratio of CET / RTC cycles is used to estimate the actual frequency of the RTC. Preferably, these measurements progress continuously from initialization from the standby state to the higher power mode until the next transition back to the low power mode (the CET is not available in low power mode).

To avoid wasting energy, the RTC calibration should fit into a paging activity. For example, it may be desirable for the calibration to take no longer than 8 ms because the shortest paging activities in current standards take 8 ms. However, the measurement inaccuracy at each individual 8 ms calibration of the RTC is currently greater than 8 ppm. It should again be noted that the requirements of 8 ms and 8 ppm are system-dependent. For example, for a 3G system, the paging indicator may have a length of about 66 μs to 533 μs. The remainder of the 8 ms is used to turn on the transceiver, process the results, and decide to go back to sleep, all of which may be different in other implementations. However, in many cases, there remains a problem that the required or at least the desired accuracy can not be reliably achieved in the time that would otherwise be the natural wake-up time (for example, the minimum time required for paging activity) means that the wake-up time or initialization time must be artificially extended, or else lower accuracy must be tolerated, or processing resources must be assigned to the calibration.

overview

The present invention provides a frequency drift estimator to determine how long a next calibration measurement should last to obtain a sufficient estimate for the calibration of a timing element, such as the RTC, in response to an estimated amount of drift that is currently being sensed , to create.

According to one aspect of the present invention, there is provided an apparatus comprising: a first timer element configured to generate a first timer signal; a second timer element configured to generate a second timer signal independently of the first timer element; a controller configured to switch the device from a low-power mode in which the first timer element is turned on while the second timer element is turned off to a higher-power mode and vice versa in which the first and second timer elements are turned on are; a transmitter / receiver configured to transmit or receive a signal external to the device when in the higher power mode, based on the second timer signal; a calibrator configured to perform a calibration of the first timer signal relative to the second timer signal during each phase of a plurality of higher power mode phases between lower power mode phases, each calibration corresponding to a number of times over a corresponding calibration time Cycles of the timer signals, and wherein each of the calibrations thereby produces a corresponding result representative of a frequency of the first signal; and an estimator configured to control an aspect of the calibration performed in a current phase of the phases depending on the results of previous calibrations prior to the phases of the higher power mode.

In embodiments, the estimator comprises: a drift estimator configured to calibrate the calibration performed in the current phase of the higher power mode phases in response to a drift of the results of previous calibrations from earlier phases of the higher power mode The aspect includes the calibration time.

The drift estimator optionally includes a filter configured to receive the results of the previous calibrations, and the drift estimator is configured to adjust the current calibration time in response to the drift by adjusting the calibration time in response to an output of the filter.

The filter optionally comprises a mean value filter configured to preserve an average integral of the results of the previous calibrations.

The filter may comprise an infinite impulse response filter.

The estimator may include: a frequency estimator configured to set an estimate of the frequency of the first timer signal in the current phase of the higher power mode phases in response to the results of the previous earlier phase calibrations of the higher power mode; Aspect includes the frequency estimation.

The frequency estimator may further include a filter configured to receive the results of the previous calibrations, wherein the frequency estimator is configured to adjust the current estimate depending on the previous results by adjusting the estimate in response to an output of the filter.

The filter may include a mean value filter configured to preserve an average integral from the results of the previous calibrations.

The filter may comprise an infinite impulse response filter.

The filter may be configured to maintain a weighted average, thereby weighting each of the previous results by a corresponding coefficient.

The frequency estimator may be configured to adjust the corresponding coefficient depending on the calibration time of each of the previous calibrations.

The apparatus may further include a superordinate mechanism configured to separately measure the drift and, assuming that the drift is greater than a threshold, provide a longer calibration time for the current calibration Adjusting the calibration time determined by the drift estimator.

The apparatus may further comprise a number generator, which is formed, the Calibration time in addition to the adjustment due to the drift by means of a random number or a number generated from a predetermined number to vary.

The transceiver may be configured to externally connect to the device via a network, and may be configured to search for external activity in the network during the higher power mode based on the second timing signal.

The transceiver may be a wireless transceiver configured to communicate or connect externally to the device via a wireless medium, and may be configured to communicate with the wireless medium during the higher power mode of an external one To seek activity.

The transceiver may be a wireless transceiver configured to communicate externally with the device via a wireless network, and may be configured to seek external activity on the wireless network during the higher power mode.

The transceiver may be configured to perform a paging operation during the higher power mode based on the second timer signal to search for the activity by listening for a paging indication.

The transceiver may be a wireless transceiver configured to communicate with the device externally over a wireless network, and may be configured to perform a paging operation to search for a paging indication during each of the phases of the higher power mode based on the second timing signal, and the corresponding calibration times of the previous results may depend on a duration of the paging operation in the phases of the higher power mode.

The first timer signal may be used to stay in sync with the network in the lower power mode.

The first timer signal may be used to stay in sync with the wireless network in the low power mode.

The apparatus may include a processor configured to process a signal transmitted by or received from the transceiver, and the processing may be based on the second timer signal.

The first timer signal may be used to decode paging indications received during the paging operation.

The first timer signal may have a higher resolution than the second timer signal.

According to another aspect of the present invention, there is provided a method of operating a device comprising a first timer element configured to generate a first timer signal and a second timer signal configured to generate a second timer signal independent of the first timer element ; the apparatus switching between a low power mode in which the first timer element is turned on while the second timer element is turned off and a higher power mode in which the first and second timer elements are turned on; and the device receives or transmits a signal externally from the device when in the higher power mode, based on the second timer signal; and wherein the method comprises the steps of: performing a calibration of the first timer signal relative to the second timer signal during each of a plurality of higher power mode phases between lower power mode phases, each of the calibrations counting according to a number over a corresponding calibration time Cycles of the timer signals, and wherein each of the calibrations thereby produces a corresponding result representing a frequency of the first signal; and controlling an aspect of the calibration performed in a current phase of the phases, depending on the results of previous calibrations of before the phases of the higher power mode.

In embodiments, the method further comprises steps in accordance with the functions performed by any of the above device features.

According to another aspect of the invention, there is provided a computer program product comprising code that, when executed, functionally provides a device according to the aforementioned method or device features.

Brief description of the drawings

For a better understanding of the present invention and to demonstrate how this may be carried, reference is made, by way of example, to the accompanying drawings, in which:

1 is a schematic block diagram of a communication device,

2 Another schematic block diagram of a communication device is, and

3 is a graph with simulation results.

Detailed description of preferred embodiments

It is now on the 1 and 2 referring to a wireless communication device according to an illustrative embodiment of the present invention.

According to 1 includes the device 2 an integrated circuit (IC) 4 with a processor 14 and a wireless transmitter / receiver 6 with an RF input area or front area 8th and at least one antenna 10 , The antenna 10 is with the RF input area 8th coupled or connected and the RF input range 8th is with the baseband processor 14 coupled or connected. The device 2 further comprises one or more memory devices 16 each comprising one or more tangible computer-readable storage media, such as a magnetic storage medium (eg, a hard disk) and / or an electronic storage medium (eg, an EEPROM, also referred to as a "flash" storage). The memory can be off-chip memory 16a that outside the integrated circuit 4 of the processor 14 is set up, and / or an on-chip memory 16b that on the same integrated circuit 4 like the processor 14 is set up. Each of the one or more memory devices is associated with the processor 14 connected.

The memory 16a and or 16b stores a signal processing code, and the processor 14 is configured to fetch and execute the signal processing code to communicate externally with the device 2 over the transmitter / receiver 6 for example via the RF input area 8th and the antenna 10 to communicate or to connect. In a particularly preferred application of the present invention, the code is arranged to communicate in accordance with one or more wireless wireless communication standards, such as the 2G, 3G, or LTE (long-term evolution) 3GPP standard, such that when the code to operate the device is completed Communication takes place over a wireless wireless network, such as a 2G, 3G and / or LTE network. The processor 14 is configured to execute the code fetched from memory and thereby outgoing data for transmission over the network via the transceiver 6 to process and / or incoming data coming from the network via the transceiver 6 be received, process.

Preferably, the processor 14 programmed as a software-based baseband modem or soft baseband modem, the input range 8th contains the RF (radio frequency) and any IF (intermediate frequency) stages. That is, on the receive side, all radio functions are from receiving RF signals from the antenna 10 up to and including down baseband in the special entrance area 8th set up. Similarly, on the transmit side, all functions are from mixing up from baseband to outputting RF signals to the antenna 10 in the associated entrance area 8th set up. However, the entire function in the baseband area is software stored in memory 16a and or 16b is stored, set up and used by the processor 14 executed. Although this is a preferred embodiment, solutions are also possible in which, for example, the RF and / or IF stages are not in a particular input range 8th are set up.

In the preferred embodiment, a special hardware or device component in the receiving part of the input area comprises 8th a low noise amplifier (LNA), mixer for downconverting the received RF signals into the IF and downconverting from the IF to the baseband, RF and IF filter stages and an analog to digital converter (ADC) stage. An ADC is respectively present at the respective in-phase and quadrature baseband branches for each of a plurality of receive diversity branches. The special hardware in the transmitting part of the input area 15 comprises a digital-to-analog converter (DAC) stage, mixer for upconverting the baseband signals in IF and upconverting from the IF to the RF, RF and IF filter stages and a power amplifier (PA). The entrance area 8th may be configured as a special hardware circuit, or some or all of the RF side components of the input area 8th can be set up as software that runs on a separate dedicated RF processor. The interface between the entrance area 8th and the baseband processor 14 may be an analog RF interface or a digital radio interface, such as DigRF interface. Details of the hardware required to perform these functions are known to those skilled in the art.

The software can then handle functions such as modulation and demodulation, interleaving and deinterleaving, rate matching and inverse rate matching, channel estimation, equalization, arithmetic processing, bit-wise Likelihood ratio (LLR) calculation, transmit diversity processing, receive diversity processing, multiple transmit and receive antenna (MIMO) processing, speech encoder / decoder, link adaptation via power control or adaptive modulation and coding, and cell measurements.

The device 2 further comprises a first oscillator 12i and a second oscillator 12ii which are typically crystal oscillators. The frequency of the first oscillator 12i is, for example, on the order of several 10 kHz, and in a preferred example is 32.768 kHz. The frequency of the second oscillator can be in a wide range of values but is on the order of several tens of MHz. In the preferred example, the second oscillator is 12ii selected from a group with frequencies of 15.36 MHz, 19.2 MHz, 26.0 MHz, 38.4 MHz and 52 MHz. The following example uses 15.36 MHz.

Each of the oscillators 12 is formed, a periodic oscillating reference signal for use by a timer circuit 18 to generate thereby a timer signal in the form of a clock signal or counter signal. The first oscillator 12i is with the first timer circuit 18i connected and configured to provide a first reference signal, which is used by the first timer circuit when generating a first timer signal, and the second oscillator 12ii is with the second timer circuit 18ıı connected and configured to provide a second reference signal, which is used by the second timer circuit in generating a second timer signal.

The first timer circuit 18i and the second timer circuit 18ıı In each case, at least one clock signal circuit, which is formed, comprises the oscillating reference signal from the corresponding oscillator 12i respectively. 12ii and based thereon, generate a corresponding timing signal in the form of a binary clock signal (which periodically toggles between a logic 1 and a logic 0 state) which is the frequency of the corresponding oscillator 12i respectively. 12ii or from the corresponding frequency of the oscillator 12i respectively. 12ii is derived (for example, an integer multiple or integer part or a fraction of the oscillator frequency). The first timer circuit 18i and the second timer circuit 18ıı each comprise a counter arranged to periodically increase or decrease a corresponding count value at the timing of the respective clock signal (typically at an edge of the clock signal), thereby generating a corresponding timer signal in the form of a corresponding count signal representing the associated count value represents. Alternatively, counting that must be performed based on a respective one of the two clock signals may also be implemented in software resident on the processor 14 is processed. Generally, the terms timer, timer means, timer, clock or the like are used herein to denote a binary 0-1 clock or a clock signal or to designate a regularly rising or falling counter or count signal which is either completely in the timer circuit 18i and or 18ıı or may be partially set up as software running on the processor in which there are operations, such as counting or dividing, to be executed. Nevertheless, in preferred embodiments, each of the RTCs includes 18i and the CET 18ıı a corresponding hardware counter and associated circuitry and not a basic 1-0 clock. It should also be noted that in the case of a counter, the period, cycle, frequency or rate of the counter or the like refers to a single counting unit, that is, to a unit of increase or decrease and not to the total area of the meter.

As in 1 2 are the first and second timer circuits 18i and 18ıı in the same integrated circuit 4 like the processor 14 although an off-chip or partial off-chip implementation is implemented using circuitry outside the IC 4 is not excluded. In any case, the first timer circuit 18i and the second timer circuit 18ıı continue with the processor 14 connected to the processor 14 to provide the first and second timing signals. As mentioned previously, for example, the second oscillator is 12ii selected from a group having frequencies of 15.36 MHz, 19.2 MHz, 26.0 MHz, 38.4 MHz and 52 MHz, for example, implemented in a specific embodiment with a frequency of 15.36 MHz. The second timer circuit may additionally include a phase locked loop (PLL) configured to multiply that frequency to thereby provide an even higher rate clock signal for clocking the processor 14 and its associated logic circuits, for example, on the order of GHz, some 10 GHz, or 100s of GHz, although the CET counter continues to operate at the fundamental rate of 15.36 MHz (or whatever the fundamental frequency of the oscillator 12ii is) clocked.

In a preferred embodiment, the first oscillator 12i configured to provide a reference signal at a suitable frequency such that the first timer circuit 18i as a real-time clock (RTC) works. That is, a clock signal for measuring "human-related time", conventional Manner in seconds, minutes and / or hours, ie, in a unit of time that is understandable to persons on a personal scale. Real-time reference oscillators typically have an integer power frequency of 2 cycles per second, ie, 2 ⁿ cycles per second, where n is an integer most convenient for dividing down to a single second unit. The most common is 32.786 KHz, which equates to 2 ¹⁵ cycles per second, and this is used as an example for the following.

The RTC 18i is preferably significantly different from the second oscillator 12ii and the timer circuit 18ıı to the clocking of the processor 14 and / or other circuits of the chip 4 are provided to the digital logic circuit and / or process communications via the transceiver 6 be sent or received to control. For example, the second clock circuit 18ıı if from the reference signal from the second oscillator 12ii is driven with a suitable frequency, designed to provide a cell timer or radio timer (CET). This typically has a significantly higher frequency, for example on the order of 1000 times or more of the RTC frequency, and does not necessarily have to be an appropriate integer or power of 2 in number of cycles per second.

The following will be in relation to an RTC 18i and a CET 18ıı however, it should be understood that the invention is also applicable to other embodiments of the first and second timing elements.

The device 2 further comprises a power control module 20 , each with the processor 14 , the CET 18ıı and the transceiver 6 (For example, with the RF input range 8th ) connected is. The power control 20 is in 1 shown to include a special hardware unit in the same integrated circuit 4 like the processor 14 is established, but generally the power control 20 A module may be any combination of hardware on or off the chip and / or software running on the processor 14 is processed, can be set up.

In operation is the power control 20 designed so that the device 2 is switched between a first switched-mode and a higher-power mode and a second switched-off mode or mode with a lower power. In the on mode, the second timer circuit is 18ıı , in this case the CET, is activated to generate the second timer signal. The transceiver is also activated to be ready to transmit and / or receive signals over the network, typically by selecting the RF input range 8th is activated. Further, the processor 14 active to process signals, including at least the signals transmitted through the transceiver 6 to be transmitted and / or received, based on the timing of the timing signal from the activated CET 18ıı Will be received. In the on mode, the processor is 14 also active to perform other general processing functions. In the off mode, on the other hand, the CET 18ıı disabled so as not to generate the second timer signal. The transceiver is also disabled so that it is not in a state in which it is usable to transmit or receive signals over the network, typically the RF input range 8th is switched off. Further, the processor 14 at least for the processing of signals disabled via the transmitter / receiver 6 to be sent or received, and may also be disabled for performing other processing functions. Unlike the CET 18ıı remains however the RTC 18i active in both on and off modes. Thus, in the on mode or the higher power mode, both the RTC 18i , the CET 18ıı , the processor 14 and the transceiver is active; while in the off mode or the lower power mode, the RTC 18i remains active during the CET 18ıı and the transceiver is deactivated and the processor is at least partially deactivated, at least with regard to the processing of signals for communication via the transceiver 6 , In embodiments, the processor is 14 completely disabled for executing any commands. Details of suitable techniques for activating and deactivating these various energy-saving components are known to those skilled in the art. Note that these two modes need not be the only power modes of the processor, but at least two modes of this kind will be considered for the purpose of the following discussion.

The power control 20 is designed with the baseband processor 14 to contact the device 2 in the switched-on mode at least to activate or wake up when the processor 14 over the network via the sender / receiver 6 to communicate, whether to send and / or receive signals over the network. On the other hand, the power control 20 trained, with the processor 14 such that when no communication over the network is required, the device 2 is put into the switched-off mode. The power control 20 can the device 2 alternately switch between a phase of the deactivated mode and a phase of the switched-on mode.

In a particularly preferred embodiment of the present invention is the power control 20 trained, the device 2 to activate the paused mode to perform paging, that is, to search for external activity on the network by listening for paging indications from the network. Such paging operations may include checking for incoming communications, such as an incoming call or a text message. The power control 20 then activates the device 2 in the lower power mode when idle between paging operations. Preferably, the power control is 20 trained, the device 2 to enable paging operations periodically, ie, at regular intervals.

In the idle phases or waiting phases, when the device 2 shut down or shut down so that the CET 18ıı is not available and the processor 14 not externally communicated or not according to pager information about the transmitter / receiver 6 searches, the remaining RTC becomes 18i used to stay in sync with the network. The monitoring of the RTC 18i could be from the power control 20 or some minimal software on the shutdown or shutdown processor 14 continues to be actively processed and the power control 20 activated. In any case, after a certain amount of time has elapsed, it will be in the waiting phase, as in accordance with the RTC 18i is set, the device is reinitialized to check for paging information.

When the device is in the on mode, the CET becomes 18ıı used to perform operations by the processor 14 For example, the CET will be executed, scheduled to time out when actually communicating or searching for communication events 18ıı is used as a clock signal generator based on a clock signal for decoding paging blocks.

2 shows the device in more detail. The apparatus comprises: a baseband processing module 22 ; a calibration driver 24 that with the RTC 18i , the CET 18ıı and the baseband processing module 22 connected is; a frequency estimator 26 and a drift estimator 27 , each with the calibration driver 24 are connected; and in certain embodiments, a random number generator coupled to the calibration driver 24 connected is. The baseband processing module 24 optionally includes a drift measurement feedback module 30 , In the illustrated embodiment, each of these elements is implemented as a module in software stored in one or more of the memory devices 16a and or 16b are stored and trained and by the processor 14 Alternatively, some or all of these modules may alternatively be partially or fully implemented in a particular hardware circuit.

To ensure a timely wake-up or reboot from low-power mode, the RTC 18i be calibrated and remain calibrated. This uses every time the device 2 returns to the on mode, the calibration driver 24 advantageously the active CET 18ıı off to the RTC 18i to calibrate; ie, to generate a calibrated timing signal at a timing derived from the timing signal output directly from the RTC, but with the timing set based on the calibration. As mentioned previously, the frequency of the RTC 18i usually not fixed in advance since it depends on various external factors such as temperature. The required accuracy for the estimated frequency is preferably 2 ppm (to ensure that the baseband is reinitialized in time to decode paging blocks within the RF receive window).

To calibrate the RTC will be a stable device with higher frequency but higher power, such as the CET 18ıı For example, with a 15.36 MHz clock from the calibration driver 24 used to the RTC 18i to eat. Each measurement is that both the RTC 18i as well as the CET 18ıı for the same amount of time and the number of RTC cycles and the number of CET cycles are measured. The ratio of CET cycles to RTC cycles is then used to estimate the actual frequency of the RTC 18i estimate. These measurements typically occur continuously from waking or initializing to the higher power mode until the next return to low power mode.

To avoid wasting energy, the RTC calibration should preferably be done within a paging activity. For the highest accuracy, counting begins and ends on an RTC clock edge so that the uncertainty is one CET clock cycle over the measurement period. For example, in the case of a 15.36 MHz CET clock signal (period of 65 ns) and an 8 ms measurement, the accuracy is +/- 65 ns / 8 ms, ie, 8.14 ppm. Thus, if the shortest paging activities take 8 ms, preferably no more than 8 ms should be required to calibrate the RTC (although again, note that the shortest Paging activity depends on the system implementation as well as on the desired accuracy). However, the measurement uncertainty for each individual 8 ms calibration of the RTC is currently greater than 8 ppm.

To address this problem, exemplary embodiments of the present invention provide a frequency estimator 26 or a drift estimator 27 or both, which are designed to work in the following manner. The frequency estimator 26 and the drift estimator 27 can be set up separately or together.

• – die Anzahl an RTC-Zähleinheiten, n_RTC; und
• – die Anzahl an CET-Zähleinheiten, n_CET.

Every time the calibration driver 24 the RTC 18i calibrated, two counts are needed:

• The number of RTC counts, n _RTC ; and
• - the number of CET counting units, n _CET .

These two values can be used by the calibration driver 24 calculate the last estimate of the actual RTC frequency f _RTC (since the CET frequency f _{CET is} accurately known relative to the RTC). This is the unfiltered (raw) RTC frequency estimate: f _RTC (t) = f _CET (n _RTC / n _CET )

The frequency estimator 26 is formed, the raw or untreated frequency estimates of the RTC 18i that is, to receive a value of f _RTC for each time t at which calibration is performed.

wobei k ein diskreter Index des Fensters ist, in welchem die Kalibrierung ausgeführt wird.The drift estimator 27 is formed the difference between the most recent raw frequency estimate of the RTC 18i and receive the previous raw frequency estimate of the RTC (which is converted to a rate of change by dividing by the elapsed time between these two measurements), ie, the raw input drift d can be expressed as:

where k is a discrete index of the window in which the calibration is performed.

Preferably, the frequency estimator includes 26 and the drift estimator 27 a respective filter formed according to one of the following embodiments, and in a particularly preferred embodiment each comprise the Frequenzabschätzeinrichtung 26 and the frequency estimator 27 a filter with infinite impulse response (IIR). The filter of the frequency estimator 26 preferably gives the last measurement a weight corresponding to the length of the measurement (long measurements are more reliable than short measurements).

The frequency estimator 26 filters the raw or unhandled frequency estimates of the RTC 18i and preferably has adaptive coefficients in embodiments. The frequency estimator 26 was introduced to smooth the error of the raw measurements.

The average of calibration values provides a good approximation of the actual RTC crystal frequency. One option could be to use a moving-average filter for the purpose of generating an average when continuously feeding calibration values to the mean value filter. A moving average filter is optimal for a common task: reducing random noise while maintaining a sharp step response. There is indeed noise in the calibration values (due to a phase jitter of the crystal and rounding of the CET cycles), and there is a need to respond to sharp steps (the crystal frequency can change very abruptly if there is a high temperature gradient) ,

wobei M die Anzahl an Werten ist, aus der der Mittelwert berechnet wird.If f _RTC (t _k ) is the k-th high (unfiltered) calibration value and F _RTC (t _k ) is the k-th filtered frequency estimate, then the implementation of convolution of a moving average filter can be done by the following finite impulse filter (FIR). To be defined:

where M is the number of values from which the average is calculated.

Moving average filters work well in circumstances where the noise is random. However, in embodiments of the present invention using a moving average filter, it may not be advantageous for the particular purpose of the crystal calibration because it does not provide a simple means for weighting the calibration values with respect to some relevance criteria (eg duration of calibration). Further, the moving average filter requires some memory for previous calibration values and M calibration values are required before the filter can output a mean value.

By contrast, a more suitable averaging filter for crystal calibration is simple, capable of averaging from the first calibration value and be able to account for the fact that the error for a calibration value can be estimated from the calibration period. Therefore, in preferred embodiments of the invention, the following first-order infinite impulse response (IIR) averaging filter is used: F _RTC (t _k ) = (1-a _k ) F _RTC (t _k-1 ) + a _k f _RTC (t _k ) where F ₀ = f ₀ , and a _k from the interval [0,1].

In the above formula, a _{k is} the first order coefficient of the IIR filter and is determined by the significance of the calibration value f _RTC (t _k ).

The output value F can be determined by the frequency estimator 26 as an absolute frequency or, more advantageously, as a difference relative to the ideal or nominal frequency of the RTC crystal 12i , for example in ppm (parts per million). The filtered estimate F can then be used for any purpose for which the unfiltered frequency f would have been used, as previously explained.

The error for a calibration value decreases with increasing duration of the calibration process, so that the calibration value becomes more significant. Therefore, in particularly preferred embodiments, the frequency estimator 26 is designed so that the coefficient is adapted to the first order as a function of the duration of the corresponding measurement. When a goes to direction 1, the weight of the new calibration value increases. On the other hand, if a goes to 0, the weight of the new calibration value becomes smaller, and the history of the filter has a greater influence on the average value.

The weight of a new reading for the IIR frequency filter is calculated as follows: a (t) = 1 - βe ^{(-t / τ)} where t in RTC cycles and β and τ are chosen such that:
a (250) = 0.05
a (1250) = 0.5

Another possibility would be to apply a discrete adaptation of the coefficients a, ie the duration is compared to a small set of discrete thresholds corresponding to a small set of discrete intervals, each associated with a corresponding value of a for further use if the duration is within the appropriate interval. For example:
a = 0.05 if cal_time <= 1000,
a = 0.75 if cal_time> 1000

Let it be the drift estimator 27 referenced; this filters the difference between the most recent raw frequency estimate of the RTC 18i and the previous raw frequency estimate of the RTC (which is converted to a rate of change by dividing by the elapsed time between these two measurements). The filter structure may be the same as the frequency estimator 26 However, the coefficients of this filter are preferably fixed.

The drift estimator 27 was introduced to determine how long the next measurement should take to produce a valid estimate of the RTC frequency. If necessary, the baseband must remain out of low power mode to ensure that the actual measurement time is longer than the required minimum. First, there is no knowledge about the RTC frequency, so the measurement should take a long time. After the first measurement, the duration of the next measurements can be shortened. The drift estimator is used to determine how the estimated frequency fluctuates. If the drift or deviation is small, the duration of the next measurement can be shortened. If the drift is large, the duration of the next measurement should be increased.

Preferably, the drift estimation filter takes the same form as that of the frequency estimator except that predetermined coefficients are preferably used, for example, a = 0.1. For example, if the D _RTC (t _k ) is the filtered drift and d _RTC (t _k ) is the raw unfiltered drift: D _RTC (t _k) = 0.9.D _RTC (t _k-1) + 0.1d _RTC (t _k)

Once the filtered drift D is estimated, this estimated drift, which is determined as a function of past measurements, can be used to adjust the time length of the next calibration measurement. One illustrative embodiment to accomplish this works as follows, by the drift estimator 27 in conjunction with the calibration driver 24 can be set up.

In embodiments, the drift estimator defines 27 a group of different discrete modes of operation, each mode corresponding to a different length of time to be used for the next calibration measurement, and wherein the next mode is selected depending on the detected drift.

• – Akquisitionsmodus: ein anfänglicher Modus, in welchem die minimale Dauer einer Messung 130 ms beträgt. Die Driftabschätzeinrichtung 27 schaltet in den nächsten Modus um, wenn die Drift kleiner als 1 ppm/Sekunde ist.
• – Einschwingmodus: ein Zwischenmodus, in welchem die minimale Dauer einer Messung 30 ms beträgt. Die Abschätzeinrichtung schaltet in den nächsten Modus um, wenn die Drift kleiner als 0,1 ppm/Sekunde ist.
• – Stabiler Modus: die minimale Dauer einer Messung ist 6,5 ms.

For example, the drift estimator may define three modes of operation that are approximately as follows.

• Acquisition mode: an initial mode in which the minimum duration of a measurement is 130 ms. The drift estimator 27 Switches to the next mode if the drift is less than 1 ppm / second.
• - Transient mode: an intermediate mode in which the minimum duration of a measurement is 30 ms. The estimator switches to the next mode when the drift is less than 0.1 ppm / second.
• - Stable mode: the minimum duration of a measurement is 6.5 ms.

At each measurement for more than 5 seconds, the drift estimator becomes 27 moved back to acquisition mode. This ensures that, for example, after a long activity in which the temperature may have changed, the entire previous memory of the actual RTC frequency is lost.

This is just one example, and in alternative embodiments, more modes of operation may be defined and / or other parameters used.

In other alternative embodiments, the next measurement duration is determined based on a continuous dependence between duration and drift: Next measurement duration = function (drift) wherein a preferred form of the function may depend on the particular communication network being modeled and determined empirically based on simulation.

The drift estimator 26 delivers the determined measurement duration to the calibration driver 24 adapted to adjust the duration of the next calibration measurement accordingly.

As an optional further improvement, the calibration driver 24 with a number generator 28 coupled to provide a versatility feature for the calibration period. The generator can be a random number generator 28 which is configured to generate a random number based on a suitable random process and the number obtained to the calibration driver 24 to introduce further variation for the calibration measurement duration (in addition to the adjustment discussed above). As those skilled in the art will recognize, the process of generating the random number by the random number generator 28 may not be truly random, but may instead be a pseudorandom process according to a suitable model.

In the case of a 32 kHz RTC crystal 12i and a 15.36 MHz CET crystal 12ii For example, the CET / RTC ratio is typically dependent on the temperature T and ranges from 468.75 (T = 25 ° C) to 468.76 (T = 0 ° C). The decimal place of the ratio is therefore very close to ¾.

For example, at T = 30 ° C, the ratio was found to be ~ 468.7504. If the RTC 12i for 400 cycles, this means ~ 187500, 16 CET cycles, but only the integer part can be measured. The initial RTC / CET offset at the beginning of a calibration is not random, but there is a high probability that the 0.16 CET cycles will not be detected during the measurement. Thus, if we always calibrate for 400 cycles, there is a risk of achieving a static offset of 0.16 CET cycles on average => 0.85 PPM.

In order to introduce some versatility for the calibration and to avoid the static offset in the above example, the duration of the calibration is artificially extended by means of a random number of RTC cycles between 0 and 3, this number being determined by the random number generator 28 is produced. These [0-3] additional cycles help resolve the static offset introduced by the fact that the fractional part of the CET / RTC ratio is close to ¾.

Using this, the calibration driver fits 24 randomize the duration of the calibration by adding an arbitrary number of RTC cycles to the measurement immediately before the end of the measurement.

An alternative way of setting or adjusting the calibration time without using a random number generator is that the number generator 28 generates the arbitrary number of RTC cycles by following a predetermined series, such as the series 0, 1, 2, 3, 0, 1, 2, 3, 0, ...

Although this example is based on a 32 kHz RTC crystal 12i and a 15.36 MHz CET crystal 12ii It should be noted that other arrangements of oscillators 12 may have non-integer cycle ratios and therefore may also benefit from random variation of the calibration measurement duration to account for the non-integer remainder in a similar fashion as described above.

As a further optional enhancement, the baseband processing module 22 a drift measurement feedback block 30 in the physical layer formed, the Frequency drift, if possible independent of the drift estimator 24 and that result to the calibration driver 24 feed back. The block 30 is designed, this feedback from the baseband 22 to the UE 2 in that, when receiving a paging signal, it can measure the time shift of the received signal using actually received information. For example, it may do so on the basis of a received pilot signal, such as a conventional pilot signal, for example by searching for the CPICH signal in 3G, or by using the middle portion of the normal signal pulse sequence (2G) to decode the signal pulse sequence. Therefore, the block 30 accurately estimate whether the time since the previous paging period has drifted, using a separate mechanism with respect to the drift estimator 27 he follows. This can be exactly up to an order of magnitude of several microseconds or even better, if good signal conditions prevail.

This can be used to provide a "failsafe" or "fallback" mechanism in addition to the drift estimator 27 provide. The filter in the drift estimator 24 Actually, it does not "know" whether it succeeds in providing an accurate measure of the RTC frequency - this is just an automated process that automatically varies the duration based on a number output by an algorithm, but in itself without feedback of the result of that process expires. It may therefore be advantageous to have a feedback mechanism 30 which can explicitly measure the drift and, if so, the filter 24 to go over and activate a "one-time" longer calibration. The drift measurement feedback block 30 can accomplish this because it is in the physical layer of the baseband 22 and can determine the drift or deviation from processed information derived from the received signal rather than counting only ratios of cycles.

To compensate for small time drifts, the RF window is slightly wider than usual when reinitializing out of the low power mode. This allows the baseband 22 to measure smaller time drifts and the time drift information to the calibration driver 24 which may then determine whether the duration of the next measurement should be increased in the event that the drift exceeds a predetermined threshold.

Drift thresholds differ depending on the currently used random access technology (RAT). In the 2G standard, the drift threshold is defined as 7 ms. In the 3G standard, the drift threshold is defined as 120 quarter-pulse cycles.

If the drift reported by the physical layer exceeds the threshold (in absolute values), then the frequency and drift estimator switches to the acquisition state.

• – die durchgezogene glatte Linie ist die reale (tatsächliche) RTC-Frequenz,
• – die durchgezogen gezeichnete Linie ist der Ausgabewert des Kalibrierfilters,
• – die kleinen Punkte sind rohe Frequenzabschätzungen, die aus kurzen 8 ms-Messungen ermittelt sind, und
• – die großen Punkte sind rohe Frequenzabschätzungen, die aus längeren 40 ms-Messungen erhalten wurden.

The top graph 3 shows a simulation of a clock calibration at a pronounced temperature step. The y-axis is the drift with respect to the ideal 32.768 kHz clock (expressed in ppm), the x-axis represents the time. The following information is shown:

• The solid smooth line is the real (actual) RTC frequency,
• The solid line is the output value of the calibration filter,
• The small dots are raw frequency estimates obtained from short 8 ms measurements, and
• - The big dots are raw frequency estimates obtained from longer 40 ms measurements.

In the bottom graph, it can be seen that the error between the estimated frequency and the actual frequency never exceeds 1.5 ppm in this demanding scenario.

It should be noted that the above embodiments are described as examples only. Other variations will be apparent to one skilled in the art in light of the present disclosure.

For example, although the above is described above in the context of a 3GPP wireless network, the principles described herein may also be applied to any communication device that performs external communication activities, such as deactivation in a wireless network operating according to another communication standard or even in one wired network. When it is said that certain elements are coupled together, this means that they are functionally coupled and this does not necessarily imply a direct connection without any intermediate components. Further, when referring to a storage device, it may designate any storage medium or media configured in one or more physical units; and, when referring to a processor, may be implemented as one or more processing cores, either in the same integrated circuit or in different integrated circuits. The invention is not limited by the described embodiments but only by the appended claims.

Claims (47)

A device with: a first timer element configured to generate a first timer signal; a second timer element configured to generate a second timer signal independently of the first timer element; a controller configured to switch the device between a low-power mode in which the first timer element is turned on while the second timer element is turned off and a higher-power mode in which the first and second timer elements are turned on; a transmitter / receiver configured to transmit or receive a signal outside the device when in the higher power mode based on the second timer signal; a calibrator configured to perform a calibration of the first timer signal with respect to the second timer signal during each of a plurality of higher power mode phases between lower power mode phases, each of the calibrations corresponding to a number of times over a corresponding calibration time Cycles of timer signals, and wherein each of the calibrations thereby generates a corresponding result representing a frequency of the first signal; and an estimator configured to control an aspect of the calibration performed in a current phase of the phases depending on the result of previous calibrations of prior to the phases of the higher power mode. The apparatus of claim 1, wherein the estimator comprises: a drift estimator configured to adjust the calibration time of the calibration performed in the current phase of the higher power mode phases depending on drift in the results of previous calibrations prior to the higher power mode phases; Calibration time includes. The apparatus of claim 2, wherein the drift estimator comprises a filter configured to receive the results of the previous calibrations, wherein the drift estimator is configured to adjust the current calibration time depending on the drift by adjusting the calibration time depending on an output of the filter becomes. The apparatus of claim 3, wherein the filter comprises an averaging filter configured to produce an averaged integral of the results of the previous calibrations. The device of claim 3 or 4, wherein the filter comprises an infinite impulse response filter. The apparatus of any preceding claim, wherein the estimator comprises: a frequency estimator configured to set an estimate of the frequency of the first timer signal in the current phase of the higher power mode phases based on the results of the previous calibrations from before the higher power mode phases, the aspect including frequency estimation. The apparatus of claim 6, wherein the frequency estimator comprises a filter configured to receive the results of the previous calibrations, wherein the frequency estimator is configured to adjust the current estimate depending on the previous results by estimating in accordance with an output of the filter is adjusted. The apparatus of claim 7, wherein the filter comprises an averaging filter configured to preserve an average integral from the results of the previous calibrations. The device of claim 7 or 8, wherein the filter comprises an infinite impulse response filter. The apparatus of claim 7, 8 or 9, wherein the filter is configured to generate a weighted average, each of the foregoing results being weighted by a corresponding coefficient. The apparatus of claim 10, wherein the frequency estimator is configured to adjust the corresponding coefficient depending on the calibration time of each of the previous calibrations. The apparatus of claim 2 or any claim dependent thereon, the apparatus further comprising a superordinate mechanism configured to independently measure the drift and a longer calibration time for the current one under the condition that the drift is measured greater than a threshold Calibration compared to that determined by the drift estimator. The apparatus of claim 2 or any claim dependent thereon, the apparatus further comprising a number generator configured to vary the calibration time in addition to the drift due to a random number or a number generated from a predetermined row. The apparatus of any preceding claim, wherein the transceiver is configured to communicate externally with the device via a network and configured to search for external activity in the network during the higher power mode based on the second timing signal. The apparatus of any preceding claim, wherein the transceiver is a wireless transceiver configured to communicate externally with the device over a wireless medium and arranged for external activity in the wireless medium during the higher power mode to search. The apparatus of any preceding claim, wherein the transceiver is a wireless transceiver configured to communicate externally with the device over a wireless network and arranged for external activity in the wireless network during the higher power mode to search. The apparatus of claim 16, wherein the transceiver is arranged to perform a paging operation during the higher power mode based on the second timer signal to search for the activity by searching for a paging indication. The apparatus of claim 10 or any claim dependent thereon, wherein the transceiver is a wireless transceiver configured to communicate externally with the device via a wireless network and arranged to perform a paging operation to respond to paging during to search each of the phases of the higher power mode based on the second timer signal; and wherein the respective calibration times of the previous results are dependent on a duration of the paging operation in the phases of the higher power mode. The apparatus of claim 14 or any claim dependent thereon, wherein the first timer signal is used to stay in sync with the network in the lower power mode. The apparatus of claim 16 or any claim dependent thereon, wherein the first timer signal is used to stay in sync with the wireless network in the lower power mode. The apparatus of any preceding claim, comprising a processor configured to process a signal transmitted or received by the transceiver, the processing being based on the second timer signal. The apparatus of claim 17 or any claim dependent thereon, wherein the first timer signal is used to decode paging information received during the paging operation. The apparatus of any preceding claim, wherein the first timer signal has a higher resolution than the second timer signal. A method of operating a device having a first timer element configured to generate a first timer signal and a second timer element configured to generate a second timer signal independent of the first timer element; the device switching between a lower power mode in which the first timer element is turned on while the second timer element is turned off and a higher power mode in which the first and second timer elements are turned off; and the device, when in the higher power mode, transmits or receives a signal external to the device based on the second timer signal; and the method comprising the steps of: Performing calibration of the first timing signal relative to the second timing signal during each of a plurality of higher power mode phases between lower power mode phases, each of the calibrations being performed for a corresponding calibration time in accordance with a number of cycles of the timer signals, and wherein each of the calibrations thereby generates a corresponding result representing a frequency of the first signal; and Controlling an aspect of the calibration that is performed in a current phase of the phase, based on the results of previous calibrations of the calibrations from before the phases of the higher power mode. The method of claim 24, wherein the controlling comprises: adjusting the calibration time of the calibration, which in the current phase of the higher-mode phases Power is performed, depending on a drift in the results of the previous calibrations from earlier phases of the higher power mode, the aspect comprising the calibration time. The method of claim 25, wherein the adjusting comprises: filtering the results of the previous calibrations and adjusting the current calibration time depending on the drift by adjusting the calibration time depending on an output of the filtering process. The method of claim 26, wherein the filtering comprises: maintaining an averaged integral of the results of the previous calibrations. The method of claim 26 or 27, wherein the filtering comprises: using an infinite impulse response filter. The method of any preceding claim, wherein the controlling comprises: Adjusting an estimate of the frequency of the first timing signal in the current phase of the higher power mode phases based on the results of the previous calibrations from earlier higher power mode phases, the aspect including frequency estimation. The method of claim 29, wherein the adjusting comprises: filtering the results of the previous calibrations and adjusting the current estimate depending on the previous results by adjusting the estimate depending on an output of the filtering process. The method of claim 29 or 30, wherein the filtering comprises: maintaining an average integral from the results of the previous calibrations. The method of claim 31, wherein the filtering comprises: maintaining a weighted average, thereby weighting each of the previous results with a corresponding coefficient. The method of claim 32, comprising: adjusting the corresponding coefficient depending on the calibration time of each of the previous calibrations. The method of any one of claims 29 to 33, wherein the filtering comprises using an infinite impulse response filter. The method of claim 25 or any claim dependent thereon, further comprising the steps of: providing a higher level mechanism for separately measuring the drift and on condition that the drift is measured greater than a threshold, applying a longer calibration time for the current calibration is determined by the adaptation. The method of claim 25 or any claim dependent thereon, further comprising the step of: varying the calibration time in addition to the adaptation due to the drift of a random number or a number generated from a predetermined row. The method of any one of claims 24 to 36, wherein the device communicates externally over a network and searches for external activity in the network during the higher power mode based on the second timing signal. The method of any of claims 24 to 37, wherein the device externally communicates over a wireless medium and seeks for external activity in the wireless medium during the higher power mode. The method of any of claims 24 to 38, wherein the device communicates externally over a wireless network and searches for external activity in the wireless network during the higher power mode. The method of claim 39, wherein the apparatus performs a paging operation during the higher power mode based on the second timer signal to search for the activity by searching for a paging indication. The method of claim 33 or any claim dependent thereon, wherein the device externally communicates over a wireless network and performs a paging operation to search for a paging indication during each of the higher power mode phases based on the second timer signal; and wherein the respective calibration times of the previous results are dependent on a duration of the paging operation in the phases of the higher power mode. The method of claim 37 or any claim dependent thereon, wherein the first timer signal is used to stay in sync with the network in the lower power mode. The method of claim 39 or any claim dependent thereon, wherein the first timer signal is used to operate in the mode less power to stay in sync with the wireless network. The method of any one of claims 24 to 43, wherein the apparatus comprises a processor configured to process a signal transmitted or received by the transceiver, the processing being based on the second timer signal. The method of claim 40 or any claim dependent thereon, wherein the first timer signal is used to decode paging information received during the paging operation. The method of any one of claims 24 to 45, wherein the first timer signal is at a higher resolution than the second timer signal. A computer program product having code that when executed causes the device to operate in accordance with the steps of any one of claims 24 to 46.

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