TW201330224A - Package module with package embedded therein and method for manufacturing the same - Google Patents

Abstract

A package, a package module with the package embedded therein, and a method for manufacturing the same are disclosed. The package includes a first semiconductor chip, a first electrical connection pad, and a first molding material. The package module mainly includes the package and a second semiconductor chip. The package can be tested to make sure its good function after being packaged and then brought to the module process, and thus, the package module can be maintained in a yield rate, and to prevent the low yield because of the no function package inside the package module.

Description

Package module with embedded package and manufacturing method thereof

The present invention relates to a package module and a package, and a method for manufacturing the same, and more particularly to a package without a core board, a package module in which the package is embedded, and a method of manufacturing the same.

With the rapid development of the electronics industry, electronic products tend to be light, thin and short in terms of type, and gradually become a high-function, high-performance, high-speed research and development direction in terms of functions. In order to meet the high integration and miniaturization requirements of semiconductor devices, the size of the embedded semiconductor wafer is also miniaturized, so the area of the electrode pads on the semiconductor wafer for electrical connection with the external is also the same. Shrinking, this situation increases the difficulty in electrically connecting and packaging the semiconductor wafer.

The semiconductor chip is electrically connected and packaged, and after the wafer carrier manufacturer transfers the carrier plate (such as the substrate or the lead frame) suitable for the semiconductor chip to the semiconductor package manufacturer, the semiconductor packager adheres the back surface of the semiconductor chip to the top of the package substrate. The surface is bonded by wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by Flip chip bonding, and the solder ball is implanted on the back surface of the substrate to electrically connect with other electronic devices or passive components.

However, if a plurality of semiconductor wafers having a large size difference are to be packaged in the above packaging process, the package yield is lowered due to difficulty in consistent control of the process; or, due to poor packaging of the semiconductor wafer or semiconductor The circuit in the carrier used in the chip is broken or short-circuited due to the small size, which causes the overall package module to be electrically ineffective.

Accordingly, if a packaging technology can be developed, it is possible to select a good-good die that has good function after testing, and then package the micro-semiconductor wafer without using a wafer carrier in the process. The yield and performance of the fabricated package module can also avoid linear failure caused by short circuit or open circuit in the carrier board.

The main object of the present invention is to provide a package body and a manufacturing method thereof, which mainly classify components to be packaged according to size and perform a packaging process in stages to ensure package yield, that is, to firstly size small components. After the components are first packaged into a package, they are packaged with the larger-sized components for subsequent module packaging, and the package is packaged using a well-tested package, and the metal foil is used in the packaging process. As a conductive seed layer in the electroplating or electroless plating process, the release film and the carrier are used at the same time, so that it is not necessary to use a wafer carrier as in the prior art, and the process can be produced through a simple and low-cost process. A package for the wafer carrier is required.

In order to achieve the above object, an aspect of the present invention provides a package having a first surface and a second surface opposite to each other, and includes: at least one first semiconductor wafer having a first active surface, a first a passive surface, and a first electrode pad on the first active surface, and the first passive surface faces the first surface; a first electrical connection pad is disposed on the first surface and electrically connected to the first surface An electrode pad; and a first encapsulating material, the first semiconductor wafer, the first electrical connection pad, and an electrical connection therebetween, wherein the first electrical connection pad is embedded in the first An encapsulating material, the first encapsulating material exposing the first electrical connection pad on the first surface.

The package of the present invention can be manufactured by the following method. The method can include the following steps: providing a carrier, wherein the surface of the carrier has a release film; and forming a pattern on the release film. a resist layer, wherein the resist layer has a plurality of openings; a first electrical connection pad is formed in the openings of the resist layer; the resist layer is removed to expose a wafer setup region; Locating at least one first semiconductor wafer, wherein the first semiconductor wafer has a first active surface, a first passive surface, and a first electrode pad on the first active surface, and the first semiconductor wafer The first passive surface is disposed in the wafer setting region; electrically connecting the first electrode pad of the first semiconductor wafer and the first electrical connection pad; and molding the first semiconductor wafer with a first encapsulation material, The first electrical connection pad and the electrical connection therebetween; and removing the carrier and the release film to expose the first electrical connection pad and forming a package, wherein the package Having a first surface and a The pair of the second surface, the first surface having the first conductive pads. In the package formed by the above method, the surface of the first electrical connection pad forms a coplanar with the first surface.

In addition, in the manufacturing method of the package, before the resist layer is formed on the release film, the method further includes the steps of: forming a conductive layer on the release film, and removing the carrier And removing the conductive layer while the release film is in use.

Compared with the prior art, the present invention sequentially applies the release film and the conductive layer on the surface of the carrier plate as a temporary support plate to facilitate the circuit fabrication in the packaging process. This temporary support board can be used as a conductive seed layer in addition to the support effect. Therefore, an electrical connection pad can be formed by combining the yellow light process and the plating, and the semiconductor wafer in the package can pass through the electricity. The connection pads are electrically connected to other components.

In a preferred embodiment of the present invention, the method for manufacturing the package further includes the steps of: forming a conductive layer on the release film before the resist layer is formed on the release film, and moving The conductive layer is removed in addition to the carrier and the release film. The conductive layer can be directly used as a seed layer in the electroplating process, so that the electrical connection pads can be directly formed. In addition, it is convenient for the electrical connection pad to form a multi-layer metal structure, such as a three-layer metal structure of gold/nickel/gold. In addition to having high strength, the multilayer metal structure is also beneficial for electrical connection with semiconductor wafers and other components. . Although the above invention forms an electrical connection pad, in fact, if necessary, a circuit layer including an electrical connection pad can be formed, in which case the circuit layer becomes a redistribution layer, so that the package can be The electrical connection pads are concentrated on one side, and the package is conveniently electrically connected to other components.

In addition, before the first semiconductor wafer is placed on the wafer setting area, the method further includes the following steps: forming an adhesive film on the first passive surface, and placing the adhesive film on the first semiconductor wafer and the first surface The adhesive film is embedded in the first encapsulating material and has a surface coplanar with the first surface.

In another preferred embodiment of the present invention, the method for manufacturing the package further includes the following steps: forming a conductive via that penetrates the first package material and connects the first electrical connection pad The first encapsulating material exposes the conductive via on the second surface.

Another object of the present invention is to provide a package module and a method of fabricating the same, in which a tested and well-functioning semiconductor chip package is used for continuous packaging, and a high yield and high performance are achieved by stacking the package and the wafer. The package module is a package in package with a package embedded therein.

In order to achieve the above object, another aspect of the present invention provides a package module comprising: a package having a first surface opposite to the second surface, and comprising: a first semiconductor wafer having a first An active surface, a first passive surface, and a first electrode pad on the first active surface, and the first passive surface faces the first surface; a first electrical connection pad disposed on the first surface And electrically connecting the first electrode pad; and a first encapsulating material, molding the first semiconductor wafer, the first electrical connection pad, and an electrical connection therebetween, wherein the first electrical property a connection pad embedded in the first encapsulation material, the first encapsulation material exposing the first electrical connection pad on the first surface; and a second semiconductor wafer having a second active surface, a second passive surface, And a second electrode pad on the second active surface, wherein the second active surface faces the second surface, and the second electrode pad is electrically connected to the first electrical connection pad.

In a preferred embodiment of the present invention, the package module further includes: a package substrate having a second electrical connection pad, wherein the second electrical connection pad is electrically connected to the first electrical connection pad; And a second encapsulating material, the package, the first electrical connection pad, the second semiconductor wafer, the second electrode pad, the second electrical connection pad, the first electrical connection pad and the An electrical connection between the second electrical connection pads and an electrical connection between the first electrical connection pads and the second electrode pads.

The package module of the present invention can be manufactured by the following method. The method can include the following steps: providing a package substrate, wherein the package substrate has a second electrical connection pad; and the package substrate has the second a second semiconductor wafer is stacked on the surface of the electrical connection pad, wherein the second semiconductor wafer has a second active surface, a second passive surface, and a second electrode pad on the second active surface, and The second passive surface faces the package substrate; a package body is stacked on the second active surface, wherein the package body has a first surface and a first surface opposite to the first active surface The second surface includes: a first semiconductor wafer having a first active surface, a first passive surface, and a first electrode pad on the first active surface, and the first passive surface faces the first a first electrical connection pad disposed on the first surface and electrically connected to the first electrode pad; and a first encapsulation material to mold the first semiconductor wafer and the first electrical connection pad And an electrical connection between the two, wherein the first electrical connection pad is embedded in the first encapsulation material, the first encapsulation material exposing the first electrical connection pad on the first surface; Connecting the first electrical connection pad and the second electrical connection pad and the first electrical connection pad and the second electrode pad; and molding the package with a second encapsulation material, the first electrical connection Electrical connection between the pad, the second semiconductor wafer, the second electrode pad, the second electrical connection pad, the first electrical connection pad and the second electrical connection pad, and the first An electrical connection between the connection pad and the second electrode pad.

In the above package module and the manufacturing method thereof, the package body of the present invention described above has similar advantages and effects. In addition, the package module of the present invention can protect the first semiconductor wafer sealed only by the first encapsulating material, avoiding the corrosion of the wafer or the electrical connection by external factors such as air humidity, and can also improve the structural strength of the package. The package is prevented from being damaged due to insufficient strength of the first package material.

In the manufacturing method of the package module, before the second semiconductor wafer stack is disposed on the surface of the package substrate having the second electrical connection pad, and before the package is stacked on the second active surface, The method further includes the step of forming a third adhesive film and a second adhesive film on the second passive surface and the second surface, respectively. In other words, the third adhesive film and the second adhesive film are respectively disposed between the second semiconductor wafer and the package substrate and between the package and the second semiconductor wafer.

Further, the above electrical connection is not particularly limited and may be wire bonding or flip chip bonding. In a preferred embodiment of the present invention, the electrical connection between the first electrical connection pad and the second electrical connection pad and the first electrical connection pad and the second electrode pad The electrical connection between them is wire bonding.

In a specific example of the present invention, a package having a conductive via is used in the package module, so that the electrical connection between the package and the second semiconductor wafer is achieved by the conductive via, that is, the The first electrical connection pad connects the second electrode pad via the conductive via.

The embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily appreciate the other advantages and advantages of the present invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the drawings show only the components related to the present invention, and the components shown therein are not in actual implementation, and the number of components, the shape, and the like in actual implementation are a selective design, and the component layout thereof. The pattern may be more complicated.

Embodiment 1

Referring to FIG. 1A to FIG. 1H, it is a schematic flow chart of manufacturing a package body according to the embodiment.

First, as shown in FIG. 1A, a carrier 9 is provided, and a release film 10 is attached to the surface of the carrier 9. The material of the release film 10 and the carrier 9 is not particularly limited, and materials commonly used in the present invention can be used. Next, as shown in FIG. 1B, a conductive layer 11 is attached to the surface of the release film 10, and a patterned resist layer 12 is formed on the surface of the conductive layer 11 by photolithography, wherein the resist layer 12 has a plurality of openings 121. In the present embodiment, a metal copper foil having a thickness of about 18 μm is used as the conductive layer 11, and the material used for the resist layer 12 is a photoresist material commonly used in the art.

As shown in FIG. 1C, the conductive layer 11 is used as a conductive seed layer, and a first electrical connection pad 13 is formed in the openings 121 of the resist layer 12, wherein the first electrical connection is performed. The connection pad 13 can be formed by multiple plating to form a connection pad of a multilayer metal layer structure, and the metal materials of the layers can be different. In this embodiment, the first electrical connection pad 13 is a connection pad having a three-layer structure of a gold layer/nickel layer/gold layer, which can facilitate subsequent wire bonding or other similar electrical connection. Next, as shown in FIG. 1D, the resist layer 12 is removed, thereby exposing a wafer set region Z.

Then, as shown in FIG. 1E, at least one first semiconductor wafer 15 is prepared. The first semiconductor wafer 15 has a first active surface 15a, a first passive surface 15b, and a first one located on the first active surface 15a. Electrode pad 151. An adhesive film 14 is attached to the first passive surface 15b of the first semiconductor wafer 15, and the first semiconductor wafer 15 is placed in the wafer setting region Z by the adhesive film 14. This also means that the first semiconductor wafer 15 is disposed in the wafer setting region Z with the first passive surface 15b. Further, the material of the adhesive film 14 is not particularly limited as long as the first semiconductor wafer 15 can be disposed in the wafer setting region Z.

As shown in FIG. 1F, the first electrode pad 151 of the first semiconductor wafer 15 and the first electrical connection pad 13 are bonded by wire bonding. Next, as shown in FIG. 1G, the first semiconductor wafer 15, the first electrical connection pad 13, and an electrical connection therebetween are molded by a first encapsulation material 17. Finally, as shown in FIG. 1H, the carrier 9 , the release film 10 , and the conductive layer 11 are removed to expose the first electrical connection pad 13 and form a package 1 , wherein mechanical properties can be simply used. The carrier plate 9 and the release film 10 are peeled off by an external force, but the conductive layer 11 is removed by etching or grinding.

Thus, the package 1 has a first surface 1a and a second surface 1b opposite thereto, and includes a first semiconductor wafer 15 having a first active surface 15a and a first passive surface 15b. And a first electrode pad 151 located on the first active surface 15a, and the first passive surface 15b faces the first surface 1a; a first electrical connection pad 13 is disposed on the first surface 1a and electrically Connecting the first electrode pad 151; a first encapsulating material 17 to mold the first semiconductor wafer 15, the first electrical connection pad 13 and an electrical connection therebetween, wherein the first electrical property The connection pad 13 is embedded in the first encapsulation material 17, the first encapsulation material 17 exposes the first electrical connection pad 13 on the first surface 1a, and an adhesive film 14 disposed on the first semiconductor wafer 15 Between the first surface 1a, the adhesive film 14 is embedded in the first encapsulating material 17, and the surface of the adhesive film 14, the first surface 1a, and the surface of the first electrical connecting pad 13 are formed together. flat.

Embodiment 2

Referring to FIG. 1A to FIG. 1I, it is a schematic flow chart of manufacturing a package body according to the embodiment.

The method for manufacturing the package 1' of the present invention is substantially similar to the first embodiment, except that the step of FIG. 1E is to place the adhesive film 14 in the wafer setting area Z, and then the first semiconductor. The wafer 15 is disposed on the first semiconductor wafer 15 in the wafer setting region Z in such a manner that the first passive surface 15b faces the adhesive film 14; and finally, corresponding to the first packaging material 17 as shown in FIG. a first conductive connecting hole 17 is formed in the first electrical connecting pad 17 and is connected to the first electrical connecting pad 13 , wherein the first encapsulating material 17 is exposed on the second surface 1 b. The conductive via 18 is provided. The manner of forming the conductive via 18 is not particularly limited, and may be filled with a metal paste such as silver paste or formed by plating.

Embodiment 3

Referring to FIG. 2A to FIG. 2C , it is a schematic flowchart of manufacturing a package module according to the embodiment.

First, as shown in FIG. 2A, a package substrate 30 and a second semiconductor wafer 20 are provided. The package substrate 30 has a second electrical connection pad 301, and the second semiconductor wafer 20 has a second active surface 20a. a second passive surface 20b and a second electrode pad 201 on the second active surface 20a. A third adhesive film 21 is attached to the second passive surface 20b of the second semiconductor wafer 20.

Next, as shown in FIG. 2B, the second semiconductor wafer 20 is disposed on the surface of the package substrate 30 having the second electrical connection pad 301 by the third adhesive film 21. In addition, a second adhesive film 22 is attached between the second surface 1b of the package 1 made in the first embodiment and the second active surface 20a of the second semiconductor wafer 20.

Finally, as shown in FIG. 2C, the first electrical connection pad 13 and the second electrical connection pad 301 and the first electrical connection pad 13 and the second electrode pad 201 are bonded by wires 31 and 32, respectively. And sealing the package body 1, the first electrical connection pad 13, the second semiconductor wafer 20, the second electrode pad 201, the second electrical connection pad 301, the first The electrical connection between the electrical connection pad 13 and the second electrical connection pad 301 and the electrical connection between the first electrical connection pad 13 and the second electrode pad 201 are electrically connected.

Accordingly, the package module comprises: a package body 1 having a first surface 1a and a second surface 1b opposite thereto, and comprising: a first semiconductor wafer 15 having a first active surface 15a, a first passive surface 15b, and a first electrode pad 151 on the first active surface 15a, and the first passive surface 15b faces the first surface 1a; a first electrical connection pad 13 is disposed on the first surface a first surface of the first semiconductor substrate 15 is electrically connected to the first electrode pad The first electrical connection pad 13 is embedded in the first encapsulation material 17. The first encapsulation material 17 exposes the first electrical connection pad 13 on the first surface 1a; and a second semiconductor wafer 20 has a a second active surface 20a, a second passive surface 20b, and a second electrode pad 201 on the second active surface 20a, wherein the second active surface 20a faces the second surface 1b, and the second electrode The pad 201 is electrically connected to the first electrical connection pad 13; a package substrate 30 has a second electrical connection Pad 301, wherein the second electrical connection pad 301 is electrically connected to the first electrical connection pad 13; a second encapsulation material 33, the package body 1, the first electrical connection pad 13, the first Electrical connection between the second semiconductor wafer 20, the second electrode pad 201, the second electrical connection pad 301, the first electrical connection pad 13 and the second electrical connection pad 301, and the first An electrical connection between the electrical connection pad 13 and the second electrode pad 201; and a third adhesive film 21 and a second adhesive film 22 are respectively disposed on the second semiconductor wafer 20 and the package substrate 30. Between and between the package 1 and the second semiconductor wafer 20.

Embodiment 4

Referring to FIG. 3, it is a schematic diagram of a package module of this embodiment.

The manufacturing process of the package module of the present embodiment is substantially similar to that of the third embodiment. The difference is that the package 1' of the second embodiment is used in the embodiment, and the package 1' and the second semiconductor wafer 20 are used. The electrical connection is not by wire bonding, but by using the conductive via 18 in the package 1', so that the surface of the conductive via 18 extends beyond the second surface 1b and directly with the second of the second semiconductor wafer 20. The electrode pads 201 are connected.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

1, 1’. . . Package

9. . . Carrier board

10. . . Release film

11. . . Conductive layer

12. . . Resistance layer

121. . . Opening

13. . . First electrical connection pad

Z. . . Wafer setup area

14. . . Adhesive film

15. . . First semiconductor wafer

15a. . . First active surface

15b. . . First passive surface

151. . . First electrode pad

16, 31, 32. . . line

17. . . First packaging material

18. . . Conductive through hole

20. . . Second semiconductor wafer

20a. . . Second active surface

20b. . . Second passive surface

201. . . Second electrode pad

twenty one. . . Third adhesive film

twenty two. . . Second adhesive film

30. . . Package substrate

301. . . Second electrical connection pad

33. . . Second encapsulating material

1A to FIG. 1I are schematic diagrams showing the process of manufacturing a package according to Embodiment 2 of the present invention.

2A to 2C are schematic diagrams showing the process of manufacturing a package module according to Embodiment 3 of the present invention.

3 is a schematic diagram of a package module according to a fourth embodiment of the present invention.

1. . . Package

13. . . First electrical connection pad

201. . . Second electrode pad

twenty one. . . Third adhesive film

twenty two. . . Second adhesive film

30. . . Package substrate

301. . . Second electrical connection pad

31, 32. . . line

33. . . Second encapsulating material

Claims (20)

A package module includes: a package having a first surface opposite to the second surface, and comprising: a first semiconductor wafer having a first active surface, a first passive surface, and a first surface a first electrode pad of the first active surface, and the first passive surface faces the first surface; a first electrical connection pad disposed on the first surface and electrically connected to the first electrode pad; An encapsulating material, the first semiconductor wafer, the first electrical connection pad, and an electrical connection therebetween, wherein the first electrical connection pad is embedded in the first encapsulation material An encapsulating material exposes the first electrical connection pad on the first surface; and a second semiconductor wafer having a second active surface, a second passive surface, and a second electrode pad on the second active surface The second active surface faces the second surface, and the second electrode pad is electrically connected to the first electrical connection pad. The package module of claim 1, further comprising: a package substrate having a second electrical connection pad, wherein the second electrical connection pad is electrically connected to the first electrical connection pad; And a second encapsulating material, the package, the first electrical connection pad, the second semiconductor wafer, the second electrode pad, the second electrical connection pad, the first electrical connection pad and the An electrical connection between the second electrical connection pads and an electrical connection between the first electrical connection pads and the second electrode pads. The package module of claim 2, further comprising: a third adhesive film and a second adhesive film respectively disposed between the second semiconductor wafer and the package substrate and the package and the package Between the second semiconductor wafers. The package module of claim 1, wherein the package further comprises: a conductive via extending through the first package material and connecting the first electrical connection pad, and the first package material is The second surface exposes the conductive via. The package module of claim 4, wherein the first electrical connection pad connects the second electrode pad via the conductive via. The package module of claim 1, wherein the surface of the first electrical connection pad forms a coplanar surface with the first surface. A method for manufacturing a package module includes the steps of: providing a package substrate, wherein the package substrate has a second electrical connection pad; and the package substrate has a surface of the second electrical connection pad, and a stack is disposed a second semiconductor wafer, wherein the second semiconductor wafer has a second active surface, a second passive surface, and a second electrode pad on the second active surface, and the second passive surface faces the package substrate Forming a package on the second active surface, wherein the package has a first surface and a second surface opposite to the first surface and facing the second active surface, and includes: a first a semiconductor wafer having a first active surface, a first passive surface, and a first electrode pad on the first active surface, and the first passive surface faces the first surface; a first electrical connection pad And electrically connecting the first electrode pad to the first surface; and a first encapsulating material, molding the first semiconductor wafer, the first electrical connection pad, and an electrical connection therebetween among them, The first electrical connection pad is embedded in the first encapsulation material, the first encapsulation material exposes the first electrical connection pad on the first surface; electrically connecting the first electrical connection pad and the second electrical connection a connection pad and the first electrical connection pad and the second electrode pad; and molding the package, the first electrical connection pad, the second semiconductor wafer, the second electrode pad, and a second encapsulation material Electrical connection between the second electrical connection pad, the first electrical connection pad and the second electrical connection pad, and between the first electrical connection pad and the second electrode pad Electrical connection. The method for manufacturing a package module according to claim 7, further comprising the step of: forming a second semiconductor wafer stack before the package substrate has a surface of the second electrical connection pad Three adhesive films are on the second passive surface. The method for manufacturing a package module according to claim 8, further comprising the step of forming a second adhesive film on the second surface before the package is disposed on the second active surface. The method of manufacturing the package module of claim 7, wherein the package further comprises: a conductive via extending through the first package material and connecting the first electrical connection pad, and the first The encapsulating material exposes the conductive via on the second surface, and the first electrical connecting pad connects the second electrode pad via the conductive via. The method of manufacturing a package module according to claim 7, wherein the surface of the first electrical connection pad forms a coplanar surface with the first surface. a package having a first surface opposite to the second surface, and comprising: a first semiconductor wafer having a first active surface, a first passive surface, and a first active surface An electrode pad, wherein the first passive surface faces the first surface; a first electrical connection pad disposed on the first surface and electrically connected to the first electrode pad; and a first encapsulating material that molds the The first semiconductor wafer, the first electrical connection pad, and the electrical connection therebetween, wherein the first electrical connection pad is embedded in the first package material, and the first package material is in the first The first electrical connection pad is exposed on the surface. The package of claim 12, further comprising: a conductive via extending through the first encapsulation material and connecting the first electrical connection pad, wherein the first encapsulation material is exposed on the second surface The conductive via. The package of claim 12, further comprising: an adhesive film disposed between the first semiconductor wafer and the first surface, wherein the adhesive film is embedded in the first packaging material and The surface forms a coplanar with the first surface. The package of claim 12, wherein the surface of the first electrical connection pad forms a coplanar surface with the first surface. A method for manufacturing a package, comprising the steps of: providing a carrier, wherein the surface of the carrier has a release film; forming a patterned resist layer on the release film, wherein the barrier layer has a plurality of layers Forming a first electrical connection pad in the openings of the resist layer; removing the resist layer to expose a wafer setting region; and placing a first semiconductor wafer on the wafer mounting region, wherein The first semiconductor wafer has a first active surface, a first passive surface, and a first electrode pad on the first active surface, and the first semiconductor wafer is disposed on the wafer with the first passive surface a first electrode pad and the first electrical connection pad electrically connected to the first semiconductor wafer; the first semiconductor wafer, the first electrical connection pad, and both thereof are encapsulated by a first encapsulation material And electrically connecting the carrier and the release film to expose the first electrical connection pad and form a package, wherein the package has a first surface opposite to the first a second surface having the first surface Electrically connected to the pad. The method for manufacturing a package according to claim 16, further comprising the step of: forming a conductive layer on the release film before the resist layer is formed on the release film, and removing the conductive layer The carrier layer and the release film are removed from the conductive layer. The method for manufacturing a package according to claim 16, further comprising the steps of: forming a conductive via, the conductive via extending through the first package material and connecting the first electrical connection pad, wherein The first encapsulating material exposes the conductive via on the second surface. The method for manufacturing a package according to claim 16, further comprising the step of: forming an adhesive film on the first passive surface before the first semiconductor wafer is placed on the wafer setting area, wherein the An adhesive film is embedded in the first encapsulating material and a surface thereof is coplanar with the first surface. The method of manufacturing a package according to claim 16, wherein the surface of the first electrical connection pad forms a coplanar surface with the first surface.