TW201330127A - Metal layer structure of semiconductor device as well as manufacturing method of metal layer structure and semiconductor device using metal layer structure - Google Patents

Abstract

The present invention relates to a metal layer structure of a semiconductor device as well as a manufacturing method of the metal layer structure and the semiconductor device using the metal layer structure. The metal layer structure of the semiconductor device comprises a first conductive layer located on a wafer, wherein the first conductive layer comprises one group of separated first conductive sub-layers, the group of separated first conductive sub-layers are provided with n different electric polarities, and n is more than or equal to 2; a first isolating layer arranged on the first conductive layer, wherein the first isolating layer comprises one group of first through holes for exposing the upper surfaces of the first conductive sub-layers selectively and partially; a second conductive layer located on the first isolating layer, wherein the second conductive layer comprises one group of separated second conductive sub-layers, the second conductive sub-layers are connected with the exposed upper surfaces of the first conductive sub-layers with the same electric polarity through the first through holes; a second isolating layer arranged on the second conductive layer and the first isolating layer, wherein the second isolating layer comprises one group of second through holes for exposing the upper surfaces of the second conductive sub-layers selectively and partially exposed; and a bump layer located at the second through holes for leading out the n different electric polarities.

Description

Metal layer structure of semiconductor device, manufacturing method and semiconductor device using same

The present invention relates to an integrated semiconductor device, and more particularly to a metal layer structure of a semiconductor device and a method of fabricating the same.

For high-current power integrated circuits, such as monolithic integrated voltage regulators, bump-connected flip-chip packages can be used to replace traditional lead-bonded wire bonding. Since the integrated device with the flip-chip package structure has a very low external connection resistance, the resistance of the internal connection structure of the device becomes critical. To reduce power loss for high efficiency, the resistance of the internal connection structure of the device must be reduced. Most power integrated circuits are manufactured using existing mature semiconductor manufacturing processes above 0.25 um. These mature semiconductor manufacturing processes use aluminum, including aluminum alloys, such as aluminum and copper, as the primary metal material for the joint structure. Since the thick metal layer can reduce the metal resistance, in order to lower the resistance of the connection structure, a thick aluminum metal layer such as an aluminum metal layer having a thickness of 2 um or more is usually employed as such an internal connection structure. Generally, of the multilayer metal layers of these mature manufacturing processes, only the topmost metal layer may be a thick aluminum metal layer.

Referring to FIG. 1a, there is shown a metal layer structure of a conventional semiconductor device using a bump structure. It includes a wafer 101, a metal pad 102 on the wafer, a first isolation layer 103 covering the remaining area of the wafer 101, and a via 103-1 on the first isolation layer 103 to the metal pad 102. Exposed; a bump under metal layer (UBM) 106 is deposited at the via hole 103-1; a bump (such as a solder ball) is disposed on the under bump metal layer UBM at the via hole 103-1 to bond the metal pad 102 The polarity of the electrode is taken out. It can be seen that with such a semiconductor device structure, only one metal layer is represented by the metal pad 102; and each bump 107 only allows a single metal pad 102 (electrode) and a via hole directly under it. 103-1; further, the size of the bump 107, the via hole 103-1, and the metal pad 102 is generally large, and the layout of the electrode on a metal layer represented by the electrode metal pad 102, The size and spacing are limited by the bumps directly above; therefore, such a semiconductor device metal layer structure, an optimized low impedance connection between different electrodes cannot be achieved.

Referring to FIG. 1b, there is shown another metal layer structure of a semiconductor device using a copper line redistribution layer (RDL). It includes a wafer 101, a metal pad 102 on the wafer, a first isolation layer 103 covering the remaining area of the wafer 101, and a via 103-1 on the first isolation layer 103 exposes the metal pad 102; A copper metal layer 104 is disposed on the first isolation layer 103 and electrically connected to the metal pad 102 through the via hole 103-1; the second isolation layer 105 covers the copper metal layer 104 and the first isolation layer The remaining area of 103, another via 105-1, acts as a new metal pad area to deposit bumps. Through the metal layer structure, the copper metal layer 103 is in contact with the original metal pad 102 on the wafer through the through hole 103-1 of the first isolation layer 103 in the vertical direction A-A'; and the new metal pad region 105 -1 is in the other vertical direction BB' to take the electrodes of the metal pad 102 from the other direction for external connection. Visible, using this The metal layer structure of the semiconductor device, directly under the via hole 105-1 where the bump can be deposited, cannot allow the presence of the via hole 103-1 on the first isolation layer 103; similar to the embodiment shown in FIG. 1a, the via 103 Both -1 and via 105-1 are relatively large in size and spacing, and therefore, the metal layer structure of such a semiconductor device with a copper metal layer cannot achieve an optimized low-impedance internal connection between different electrodes.

It can be seen that the low internal connection resistance cannot be obtained by the metal layer structure of the prior art semiconductor device. For high current semiconductor devices (such as power devices), this defect will be more significant and power loss will be greater.

However, for most power-integrated circuits, especially for integrated circuits with monolithic integrated power devices, two layers of lower resistance metal layers are required to achieve an optimized internal connection structure. Integrated power devices typically include thousands of device cells whose electrodes are connected together through a metal layer. Each device cell of the power device has two power electrodes through which a large current flows into or out of the power device. For example, for the most widely used integrated power device MOSFET lateral double-diffused metal oxide semiconductor field effect transistor, the two power electrodes are the drain and source of the device, respectively. If the metal layer structure of the integrated circuit device can include two layers of low resistance metal layers, and the layout of the electrodes on the two low resistance metal layers can ensure the low resistance metal layer and the device element An optimized direct connection between the two power electrodes of the cell reduces the overall connection resistance inside the device, thereby reducing power loss.

Some advanced semiconductor manufacturing processes, such as line widths of 0.18um or less, enable multiple low-resistance copper metal layers through the complex Damascus copper interconnect process. However, for most mature manufacturing processes where the line width is 0.25 um or less, the Damascus Copper Interconnect program cannot be used in these programs.

In view of the above, it is an object of the present invention to provide a bump-like device interior having a relatively low-impedance metal layer having two layers of low resistance in an existing mature semiconductor manufacturing process. Connection structure.

A method of fabricating a metal layer structure of a semiconductor device according to an embodiment of the invention includes the steps of: depositing a first conductive layer on a wafer, the first conductive layer comprising a plurality of separated first conductive sub-layers, the first A conductive sublayer has n different electrode properties, n Depositing a first isolation layer on the first conductive layer, the first isolation layer having a set of first via holes to selectively expose a portion of the upper surface of the first conductive sub-layer; Depositing a second conductive layer on the first isolation layer, the second conductive layer includes a set of separated second conductive sub-layers, the second conductive sub-layer passing through the first via and the same polarity a bare upper surface connection of a conductive sub-layer; a second isolation layer deposited on the second conductive layer and the first isolation layer, the second isolation layer having a set of second vias for selective Excluding a portion of the upper surface of the second conductive sub-layer, each of the second via holes directly above the plurality of the first via holes; depositing a bump at the second via hole to form a bump layer to extract the n different electrode properties.

Preferably, the second conductive sub-layer is connected to the exposed upper surface of the plurality of first conductive sub-layers.

Preferably, the second via hole is directly above the plurality of first conductive sub-layers of different polarity.

Preferably, the first conductive layer is a thick aluminum metal layer formed by a sputtering process.

Preferably, the first conductive layer and the wafer comprise one or more metal layers different from the first conductive layer.

Preferably, the first isolation layer comprises a passivation protective layer of the semiconductor device.

Preferably, the first isolation layer further comprises a polyimide layer on the passivation protective layer.

Preferably, the second conductive layer is a copper conductive layer formed by a plating process.

Preferably, the bump is a tin bump or a copper stud bump or a gold bump.

A metal layer structure of a semiconductor device according to an embodiment of the invention includes: a first conductive layer on a wafer, the first conductive layer comprising a plurality of separated first conductive sublayers, the first set The electron conducting layer has n different kinds of electrodes, n 2; a first isolation layer on the first conductive layer, the first isolation layer has a set of first via holes to selectively expose a portion of the upper surface of the first conductive sub-layer; a second conductive layer on the first isolation layer, the second conductive layer includes a plurality of separated second conductive sub-layers, and the second conductive sub-layer passes through the first via hole and has the same polarity a bare upper surface of a conductive sub-layer; a second isolation layer on the second conductive layer and the first isolation layer, the second isolation layer having a second set of vias for selective Excluding a portion of the upper surface of the second conductive sub-layer, the second via being directly above the plurality of the first vias; a bump layer at the second via to n different electrode conductances.

Preferably, the second via hole is directly above the plurality of first conductive sub-layers of different polarity.

Preferably, the first conductive layer is a thick aluminum metal layer formed by a sputtering process.

Further, the metal layer structure further includes one or more metal layers different from the first conductive layer between the first conductive layer and the wafer.

Preferably, the first isolation layer comprises a passivation protective layer of the semiconductor device.

Preferably, the first isolation layer further comprises a polyimide layer on the passivation protective layer.

Preferably, the second conductive layer comprises a copper metal layer formed by a plating process.

Preferably, the bump is a tin bump or a copper stud bump or a gold bump.

A semiconductor device according to an embodiment of the invention includes any of the above metal layer structures for guiding different electrodes of the semiconductor device outward through the bump layer.

Preferably, in the metal layer structure of the semiconductor device, edges of adjacent second conductive sub-layers are bent to form a protruding region, and the protruding regions are connected to the corresponding first through the first through holes. The protruding area of the electron guiding layer.

According to the metal layer structure of the semiconductor device and the method of connecting the same according to the embodiment of the present invention, the via holes on the second isolation layer are directly over the plurality of via holes of the first isolation layer; and, the plurality of different layers on the first conductive layer The first conductive sub-layer of the electrode is directly under the bump, so that the layout and size of the first conductive sub-layer on the first conductive layer of low resistance value and the spacing between the first conductive sub-layers are no longer convex The block limit reduces the resistance of the large current path and reduces the power loss. A very small internal connection resistance value is achieved for the integrated power device, which greatly reduces power loss and improves efficiency.

DETAILED DESCRIPTION OF THE INVENTION Several preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the invention is not limited to only these embodiments. The present invention encompasses any alternatives, modifications, equivalents and alternatives to the spirit and scope of the invention. The details of the invention are described in detail in the preferred embodiments of the present invention, and the invention may be fully understood by those skilled in the art.

Hereinafter, a method of manufacturing a metal layer structure of a semiconductor device according to the present invention will be described in detail with reference to specific embodiments.

A flowchart of a preferred embodiment of a method for fabricating a metal layer structure of a semiconductor device according to the present invention, and a schematic diagram of a method for fabricating a metal layer for implementing a semiconductor device, shown in FIGS. 3a-3e, in conjunction with FIG. The invention will be described in detail. In this embodiment, for convenience of illustration, only one of the metal layer structural units is shown, and those skilled in the art will appreciate that the metal layer structure of the semiconductor device includes a plurality of the metal layer structural units. A method of fabricating a metal layer structure according to this embodiment of the present invention includes the following steps: S201: depositing a first conductive layer on a wafer; the first conductive layer includes a set of separated first conductive sub-layers, the first A conductive sublayer has n different electrode properties, n 2: S202: depositing a first isolation layer on the first conductive layer; the first isolation layer has a set of first via holes to selectively expose a portion of the upper surface of the first conductive sub-layer; S203: depositing a second conductive layer on the first isolation layer; the second conductive layer includes a set of separated second conductive sub-layers, the second conductive sub-layer passing through the first via hole and having the same polarity a bare upper surface of the first conductive sub-layer is connected; S204: depositing a second isolation layer on the second conductive layer and the first isolation layer; the second isolation layer has a second pass a hole for selectively exposing a portion of the upper surface of the second conductive sub-layer; S205: depositing a bump at the second via to form a bump layer, thereby the n different kinds of electrodes Lead out.

Through the connection method between the conductive layers and the isolation layers shown in FIG. 2, the bump layers are used to electrically connect the electrodes on the wafer, thereby guiding the electrode signals for external electrical connection.

Wherein, in step S201, the first conductive layer 302 may be a metal layer formed by a sputtering process, such as a thick aluminum metal layer, or a multi-layer metal layer superposed by different properties. The thickness of the first conductive layer may be 3 um; the first conductive sub-layer 302-1 is sequentially arranged on the wafer 301 according to the size of the first via 303-1. For example, the size of the first through hole 303-1 is 40 um, which is smaller than the through hole size used in FIG. 1a in the prior art (for example, a solder ball bump having a diameter of 300 μm is used, and the through hole used in FIG. 1a is approximately 240um). Thus, the maximum distance between the two first conductive sub-layers 302-1 of the same electrode type in the first conductive layer does not exceed 50 um, regardless of the diameter of the upper bump.

In step S202, the size of the first via hole 303-1 is smaller than the size of the first conductive sub-layer 302-1 to selectively expose a part of the upper surface of the first conductive sub-layer 302-1. The first isolation layer 303 is completely covered by the first conductive layer 302 and removed from the area of the first via hole 303-1. The remaining bare areas of the wafer 301.

The first isolation layer 303 may be a passivation protective layer of a semiconductor device, such as a protective layer formed by a CVD process; the protective layer may be cerium oxide or phosphoric acid glass or tantalum nitride or SOG or any of them. combination.

Preferably, the first isolation layer 303 may further include a polyimide layer on the basis of the passivation protective layer to help planarize the uneven surface after the first conductive layer and the passivation protective layer are formed. . At this time, the first through hole 303-1 may be composed of two parts, wherein the first portion is the first isolated through hole on the passivation protective layer, and the second portion is the first on the polyimide layer Two isolation vias; the first isolation vias and the second isolation vias are aligned in a vertical direction, and both may be the same or different in size to collectively form the first vias 303-1.

The first isolation layer 303 can not only provide isolation for the first conductive layer 302 and the second conductive layer 304; and, can provide mechanical support for the second conductive layer 304 and the bump layer 306. The polyimide layer may release stress caused by the second conductive layer 304.

In addition, a first spacer layer composed of a polyimide layer and a passivation protective layer can help planarize the surface of the crucible to facilitate deposition of the subsequent second conductive layer 304.

Wherein, the passivation protective layer may be composed of 0.5 um phosphoric acid glass and 0.7 um tantalum nitride; the polyimide layer may have a thickness of 5 um.

In step S203, the formation of the second conductive layer 304 may be packaged. The method includes the steps of: depositing a lower under bump metal layer on the first isolation layer 303; depositing a photoresist on the under bump metal layer, etching the photoresist on the photoresist by using a reticle Forming a pattern to expose a portion of the under bump metal layer; plating a metal layer on the exposed under bump metal layer not covered by the photoresist; removing the remaining photoresist; etching The portion of the under bump metal layer covered by the metal layer is not formed to form a different second conductive sub-layer; the under bump metal layer and the metal layer together serve as the second conductive layer 304.

Wherein, the metal layer may be a copper metal layer formed by a plating process; the copper metal layer has a thickness of 10 um. The metal layer can help planarize the uneven surface of the first isolation layer and the first via hole, and provide a possibility for deposition of the bump layer 306 which is subsequently established over the plurality of via holes of the first isolation layer. .

The second conductive layer 304 completely covers the first through hole 302-1; the second conductive sub-layer 304-1 and the exposed upper surface of the plurality of first conductive sub-layers 302-1 of the same polarity connection.

In step S204, the second isolation layer 305 is a polyimide layer formed by a coating process; the second isolation layer 305 may have a thickness of 10 um.

In step S205, the bump layer 306 may be a tin bump, copper. a pillar bump, or a gold bump; wherein the tin bump may be formed by implanting solder in the second via region; the solder reflows and solidifies to form a solder ball.

In addition, before step S205, the method further includes: depositing another under bump metal layer and/or another metal layer on the second isolation layer 305 as an adhesion layer, a barrier layer, and a wet layer to improve the convexity. The reliability of the block connection.

According to the flowchart and the schematic diagram of the metal layer manufacturing method of the semiconductor device shown in FIG. 2 and FIG. 3a to FIG. 3e, the second via hole 305-1 on the second isolation layer 305 can be directly placed on the first isolation layer 303. a plurality of first via holes 303-1; and a plurality of first conductive sub-layers 302-1 on the first conductive layer 302 are disposed directly under the bumps 306; through these connection relationships and structural settings, A relatively low cost connection structure having two layers of low resistance conductive layers reduces the resistance of the large current path, reduces power loss, and improves efficiency.

The metal layer structure of a semiconductor device according to the present invention, which will be described in detail below in conjunction with the specific embodiments.

Through the metal layer structure manufacturing method of the above semiconductor device, a metal layer structure of a semiconductor device according to the present invention as shown in FIG. 3e is obtained. The metal layer structure of the semiconductor device according to the present invention will be described below in conjunction with the embodiment, the metal layer structure comprising: a first conductive layer 302 over the wafer 301, the first conductive layer having a set of separated A conductive sub-layer 302-1 having a different electrode polarity of not less than two.

a first isolation layer 303 over the first conductive layer 302, the first isolation layer 303 has a set of first vias 303-1 to selectively enable the first conductive sub-layer 302-1 a portion of the upper surface is bare; the size of the first through hole is smaller than the size of the corresponding first conductive sub-layer 302-1; and the first isolation layer 303 is completely covered by the area except the first through hole 303-1. A conductive layer 302 and remaining bare areas of the wafer 301.

a second conductive layer 304 over the first isolation layer 303, the second conductive layer 304 includes a plurality of second conductive sub-layers 304-1 separated from each other; the second conductive layer 304 completely covers the The first via hole 302-1 is connected to the exposed upper surface of the plurality of first conductive sub-layers 302-1 of the same polarity, so that the second conductive sub-layer 304-1 has a corresponding different polarity. .

a second isolation layer 305 over the remaining regions of the second conductive layer 304 and the first isolation layer 303, the second isolation layer 305 having a set of second vias 305-1, selected by bare a portion of the upper surface of the second conductive layer 304.

a set of bumps at the second via 305-1 to form a bump layer 306 over the second isolation layer 304, the bump layer 306 passing through the second via 305- 1 is electrically connected to the second conductive layer 304.

The first conductive layer 302 may be a metal layer formed by a sputtering process, for example, a 3 um thick aluminum metal layer; and the first conductive layer 302 and the wafer 301 may further include a plurality of metal layers.

The first isolation layer 303 can be passivated protection of a semiconductor device The layer, as may be a protective layer formed by a CVD process; the protective layer may be cerium oxide or phosphoric acid glass or tantalum nitride or SOG or any combination thereof.

Further, the first isolation layer 303 may further include a polyimine layer on the basis of the passivation protective layer. At this time, the first through hole 303-1 may be composed of two parts, wherein the first portion is the first isolated through hole on the passivation protective layer, and the second portion is the first on the polyimide layer Two isolation vias; the first isolation vias and the second isolation vias are aligned in a vertical direction, and both may be the same or different in size to collectively form the first vias 303-1.

The first isolation layer 303 can not only provide isolation for the first conductive layer 302 and the second conductive layer 304; and, can provide mechanical support for the second conductive layer 304 and the bump layer 306. The polyimide layer may release stress caused by the second conductive layer 304.

In addition, a first spacer layer composed of a polyimide layer and a passivation protective layer can help planarize the surface of the crucible to facilitate deposition of the subsequent second conductive layer 304.

Wherein, the passivation protective layer may be composed of 0.5 um phosphoric acid glass and 0.7 um tantalum nitride; the polyimide layer may have a thickness of 5 um.

The first conductive sub-layers 302-1 of different electrical properties are spaced apart from each other on the first conductive layer 302. For example, the size of the first through hole 303-2 may be 40 um, which is smaller than the commonly selected through hole size in the prior art; the first conductive sublayer 302-1 may be arranged at intervals of 40 um to 50 um. On the first conductive layer 302.

Preferably, the second conductive layer 304 may include a copper metal layer and an under bump metal layer formed by a plating process to realize the connection of the bump layer 306, and may planarize the surface of the germanium to facilitate the bump layer 306. Deposition.

The second isolation layer 305 may be a polyimide layer formed by a coating process and may have a thickness of 10 um.

Preferably, the second through holes 305-1 are directly above the plurality of the first through holes 303-1; and directly above the plurality of first conductive sub-layers 302-1 of different polarity.

The bump layer 306 may be a copper stud bump or a tin bump or a gold bump.

Preferably, another under bump metal layer and/or a metal layer, such as copper, is further included between the bump layer 306 and the second isolation layer 305 to assist in the formation of bumps and improve bump connections. Reliability.

With the metal layer structure of the semiconductor device according to an embodiment of the present invention shown in FIG. 3e, the second via hole 305-1 on the second isolation layer 305 is directly on the plurality of first via holes 303 of the first isolation layer 303. Above -1; and a plurality of different conductivity first conductive sub-layers 302-1 on the first conductive layer 302 are directly under the corresponding bumps 306. The layout, size and spacing of the first conductive sub-layers of different polarity on the first conductive layer of low resistance value are no longer limited by the bumps, reducing the resistance value of the large current path and reducing the power loss. Very small connection resistance values are achieved for integrated power devices.

Hereinafter, a semiconductor device using a metal layer structure according to an embodiment of the present invention will be described in detail in conjunction with a specific application embodiment.

Referring to FIG. 4A and FIG. 4B, there is shown a schematic structural view of a MOSFET lateral double-diffused metal oxide semiconductor field effect transistor having a metal layer structure according to an embodiment of the present invention and a cross-sectional view thereof.

The semiconductor device, ie, the MOSFET transistor, includes a first metal layer structure 401 and a second metal layer structure 402. The first metal layer structure 401 and the second metal layer structure 402 may be the metal layer structure shown in FIG. 3e or other metal layer structure according to the present invention in accordance with an embodiment of the present invention.

For convenience of explanation, in FIG. 4a, the first isolation layer and the second isolation layer are omitted, only the first conductive layer and the second conductive layer are shown; but in FIG. 4b, all of the metal layer structure is completely shown. component. The two electrodes of the MOSFET lateral double-diffused metal oxide semiconductor field effect transistor that need to flow a large current are the drain A and the source B, respectively. The first metal layer structure 401 is used to lead the drain electrode A, and the second metal layer structure 402 is used to lead the source electrode B.

In this embodiment, the first conductive sub-layer on the first conductive layer is distributed in the following manner:

In the first metal layer structure 401, the polarity of the set of first conductive sub-layers 401-1 separated from each other is the drain electrode A; the polarity of the first conductive sub-layer 401-2 of the remaining area is the source electrode B .

In the second metal layer structure 402, the polarity of the first set of first conductive sub-layers 402-1 separated from each other is the source electrode B; the polarity of the first conductive sub-layer 402-2 of the remaining area is the drain electrode A .

In this embodiment, the first through holes on the first isolation layer are distributed in the following manner:

In the first metal layer structure 401, the second conductive sub-layer 401-4 is electrically connected to the first conductive sub-layer 401-1 whose polarity is the gate electrode A through a set of first via holes 401-3.

In the second metal layer structure 402, the second conductive sub-layer 402-4 is electrically connected to the first conductive sub-layer 402-1 whose source is the source electrode B through a set of first via holes 402-3.

In this embodiment, in order to facilitate the extraction of the drain electrode A in the second metal layer structure 402 and the extraction of the source electrode B in the first metal layer structure 401, the first conductive sub-layer 401-2 and the first The electron-conducting layers 402-2 are spaced apart by a certain distance a, and the adjacent regions are disposed in complementary curved shapes. Correspondingly, the second conductive sub-layer 401-4 and the second conductive sub-layer 402-4 are also disposed in a bent shape with an interval b. The protruding region in the second conductive layer 401-4 in the first metal layer structure 401 passes through the first via hole 401-4- and the first conductive sub-layer 402-2 in the second metal layer structure 402 (dip electrode A) Electrical connection. The protruding region of the second conductive layer 402-4 in the second metal layer structure 402 passes through the first via hole 402-3-1 and the first conductive sub-layer 401-2 in the first metal layer structure 401 (source electrode B) ) Electrical connection.

Referring to the cross-sectional view of the MOSFET transistor shown in Fig. 4A shown in Fig. 4A along the axis A-A' and the axis B-B', the metal layer structure of the MOSFET transistor is as follows:

a first conductive layer 400B over the wafer 400A, the first conductive layer 400B comprising a plurality of separate first conductive sub-layers having different electrical properties, such as the first conductive sub-layer 401 in the first metal layer structure 401 -1 and 401-2, and the first conductive sub-layer 402-1 in the second metal layer structure 402 And 402-2.

a first isolation layer 400C over the first conductive layer 400B having a plurality of first vias thereon, including a first via 401-3 and a second metal layer 402 in the first metal layer structure 401 a second via hole 402-3 to selectively expose a portion of the upper surface of the first conductive sub-layer; the remaining first isolation layer region of the first via hole completely covers the first conductive layer and the bare portion The upper surface of the wafer area.

a second conductive layer 400D composed of a plurality of second conductive sub-layers of different polarity above the first isolation layer 400C; the first conductive sub-layer 401-4 of the first metal layer structure 401 and a second conductive sub-layer 402-4 in the second metal layer structure 402; the second conductive layer 400D is electrically connected to the first conductive sub-layer through the first through hole; the first through hole 401- 3-1 connecting the protruding region of the second conductive sub-layer 401-4 in the first metal layer structure 401 to the first conductive sub-layer 402-2 in the second metal layer structure 402; the first via 402-3- 1 The protruding region of the second conductive sub-layer 402-4 in the second metal layer structure 402 is connected to the first conductive sub-layer 401-2 in the first metal layer structure 401.

a second isolation layer 400E located on the second conductive layer 400D, having a second via hole 401-5 in the first metal layer structure 401 and a second via hole 402-5 in the second metal layer structure 402; The remaining second isolation layer region of the second via hole completely covers the remaining regions of the second conductive layer 400D and the exposed first isolation layer 400C; preferably, the second via hole is in the plurality of first vias Directly above the hole; preferably, the second through hole is in a plurality of different conductivity first conductive Directly above the sub-layer; the bump layer 400F at the second via hole includes the bump 401-6 in the first metal layer structure 401 and the bump 402-6 in the second metal layer structure 402, thereby transmitting the bump Block 401-6 draws the drain electrode A and pulls the source electrode B through the bump 402-6.

A person skilled in the art can easily know that the number of the second conductive sub-layers is not limited to two in the embodiment, and the number of the bumps is not limited to two in the embodiment, and the number of the two may be Actually you need to optimize the settings. Also, the shape of the second conductive sub-layer may be any suitable form of shape.

In addition, one or more layers of other types of metal layers may be further included between the wafer 400A and the first conductive layer 400B; and a bump under metal layer may be further included between the second conductive layer and the bump layer; The second conductive layer may include a copper metal layer and a bump under metal layer.

In this embodiment, the first conductive layer 400B has a rectangular shape. In the first metal layer structure 401, the first conductive sub-layer 401-1 having the polarity of the drain A is removed, and the remaining first conductive layer is of a polarity. The second conductive sub-layer 401-2 of the source B; those skilled in the art can easily know that the first conductive layer can be any suitable shape according to the teachings of the present invention; the arrangement of the first conductive sub-layer can also For other suitable forms of the way.

Optimizing the distribution of the drain electrode A and the source electrode B on the low-resistance first conductive layer, particularly the bumps, by using the MOSFET semiconductor device of the metal layer structure according to the present invention shown in FIGS. 4a and 4b The area below the layer. For integrated power devices with large currents with large bumps It is crucial, for example, that the size of the bump is 300um. In the existing semiconductor device structure, only one electrode under the bump is allowed on the first conductive layer, which means that the connection between the power device and the other electrodes in these regions is not a low resistance connection structure. However, in the present invention, the layout, size and spacing of the first conductive sub-layers of different polarity on the first conductive layer of low resistance value are no longer limited by the bumps; for example, the size of the first via hole is 40 um, which is smaller than In the prior art, as shown in the through-hole size of FIG. 1a, the electrodes may be sequentially spaced on the first conductive layer by 40 um to 50 um, thereby achieving a very small resistance value for the integrated power device.

In summary, the metal layer structure of the semiconductor device and the connection method thereof according to the present invention provide a relatively low cost connection of a conductive layer having two low-resistance values on the basis of the existing semiconductor manufacturing process. The structure reduces the resistance value of the large current path and reduces the power loss.

The metal layer structure and the connection method of the semiconductor device according to the preferred embodiment of the present invention have been described in detail above, and those skilled in the art can infer that other techniques or structures, circuit layouts, components, etc. can be applied to The embodiment is described.

The embodiments in accordance with the present invention are not described in detail, and are not intended to limit the invention. Obviously, many modifications and variations are possible in light of the above description. The present invention has been chosen and described in detail to explain the principles and embodiments of the present invention so that those skilled in the <RTIgt; The invention is limited only by the scope of the claims and the full scope and equivalents thereof.

301‧‧‧ wafer

302‧‧‧First conductive layer

302-1‧‧‧electrode

303‧‧‧First isolation layer

303-1‧‧‧First through hole

304‧‧‧Second conductive layer

305‧‧‧Second isolation

305-1‧‧‧Second through hole

306‧‧‧Bumps

1a shows a connection structure of a semiconductor device using the prior art; FIG. 1b shows a connection structure of another semiconductor device using the prior art; and FIG. 2 shows a method for manufacturing a metal layer of a semiconductor device according to the present invention. A flow chart of a preferred embodiment; FIGS. 3a-3e are schematic views showing the steps of the metal layer manufacturing method of the semiconductor device according to the present invention shown in FIG. 2; and FIG. 4a is a view of the present invention. A schematic structural view of an embodiment of a semiconductor device; and FIG. 4b is a cross-sectional view of the semiconductor device according to an embodiment of the present invention shown in FIG. 4a; in the following, the same reference numerals denote the same components.

Wafer 301; first conductive layer 302; electrode 302-1; first isolation layer 303; first via 303-1; second conductive layer 304; second isolation layer 305; second via 305-1; bump 306.

301‧‧‧ wafer

302‧‧‧First conductive layer

302-1‧‧‧electrode

303‧‧‧First isolation layer

303-1‧‧‧First through hole

304‧‧‧Second conductive layer

305‧‧‧Second isolation

305-1‧‧‧Second through hole

306‧‧‧Bumps

Claims (18)

A method of fabricating a metal layer structure of a semiconductor device, the method comprising: depositing a first conductive layer on a wafer, the first conductive layer comprising a plurality of separated first conductive sub-layers, the first conductive sub-layer having n different electrode properties, n Depositing a first isolation layer on the first conductive layer, the first isolation layer having a set of first via holes to selectively expose a portion of the upper surface of the first conductive sub-layer; Depositing a second conductive layer on the layer, the second conductive layer comprising a plurality of separated second conductive sub-layers, the second conductive sub-layer passing through the first via and the bare first of the first conductive sub-layers having the same polarity a surface connection; depositing a second isolation layer on the second conductive layer and the first isolation layer, the second isolation layer having a set of second vias to selectively select a portion of the upper surface of the second conductive sub-layer Exposed, the second via hole is directly above the plurality of the first via holes; and a bump is deposited at the second via hole to form a bump layer, thereby extracting the n different electrode properties. The method of manufacturing a metal layer structure of a semiconductor device according to claim 1, wherein the second via hole is directly above the plurality of first conductive sub-layers having different polarity. The method of manufacturing a metal layer structure of a semiconductor device according to claim 1, wherein the first conductive layer is a thick aluminum metal layer formed by a sputtering process. The method for fabricating a metal layer structure of a semiconductor device according to claim 1, wherein the first conductive layer and the wafer include one or more metal layers different from the first conductive layer. The method of fabricating a metal layer structure of a semiconductor device according to claim 1, wherein the first isolation layer comprises a passivation protective layer of the semiconductor device. The method for fabricating a metal layer structure of a semiconductor device according to claim 5, wherein the first isolation layer further comprises a polyimide layer on the passivation protective layer. The method for fabricating a metal layer structure of a semiconductor device according to claim 1, wherein the second conductive layer is a copper conductive layer formed by a plating process. The method for fabricating a metal layer structure of a semiconductor device according to claim 1, wherein the bump is a tin bump or a copper bump or a gold bump. A metal layer structure of a semiconductor device, comprising: a first conductive layer on a wafer, the first conductive layer comprising a plurality of separated first conductive sublayers, the set of first conductive sublayers having n different electrode properties, n 2; a first isolation layer on the first conductive layer, the first isolation layer has a set of first via holes to selectively expose a portion of the upper surface of the first conductive sub-layer; in the first isolation a second conductive layer on the layer, the second conductive layer comprising a plurality of separated second conductive sub-layers, the second conductive sub-layer passing through the first via and the bare first of the first conductive sub-layers having the same polarity a surface connection; a second isolation layer on the second conductive layer and the first isolation layer, the second isolation layer having a set of second vias to selectively select a portion of the upper surface of the second conductive sub-layer Exposed, the second via hole is directly above the plurality of the first via holes; and a bump layer located at the second via hole to extract the n different electrode characteristics. The metal layer structure of the semiconductor device according to claim 9, wherein the second via hole is directly above the plurality of first conductive sub-layers having different polarity. The metal layer structure of the semiconductor device according to claim 9, wherein the first conductive layer is a thick aluminum metal layer formed by a sputtering process. The metal layer structure of the semiconductor device of claim 9, further comprising one or more metal layers different from the first conductive layer between the first conductive layer and the wafer. The metal layer structure of the semiconductor device according to claim 9, wherein the first isolation layer comprises a passivation protective layer of the semiconductor device. The metal layer structure of the semiconductor device according to claim 13, wherein the first isolation layer further comprises a polyimide layer on the passivation protective layer. Gold of the semiconductor device according to claim 9 of the patent application scope The layer structure, wherein the second conductive layer comprises a copper metal layer formed by a plating process. The metal layer structure of the semiconductor device according to claim 9, wherein the bump is a tin bump or a copper bump or a gold bump. A semiconductor device comprising any of the metal layer structures as described in claim 9-16, wherein different electrodes of the semiconductor device are led out through the bump layer. The semiconductor device according to claim 17, wherein an edge of the adjacent second conductive sub-layer has a bent shape to form a protruding region, and the protruding region is connected to the corresponding first through the first through hole A protruding area of a conductive sub-layer.