TW201327797A - Pixel structure of organic electroluminescent display device - Google Patents

Pixel structure of organic electroluminescent display device Download PDF

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TW201327797A
TW201327797A TW100149756A TW100149756A TW201327797A TW 201327797 A TW201327797 A TW 201327797A TW 100149756 A TW100149756 A TW 100149756A TW 100149756 A TW100149756 A TW 100149756A TW 201327797 A TW201327797 A TW 201327797A
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opening
layer
disposed
thin film
film transistor
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TWI484628B (en
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jian-ying Peng
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Giantplus Technology Co Ltd
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Abstract

The present invention discloses a pixel structure of an organic electroluminescent display device, which includes a substrate, a thin film transistor and a pixel electrode, wherein the thin film transistor is disposed on the substrate, and has a gate, a source and a drain, and the thin film transistor further has a first opening, and the first opening is connected to the drain of the thin film transistor, the pixel electrode is connected to a second opening for the drain of the thin film transistor to electrically connect to the pixel electrode through the first opening and the second opening, wherein the second opening is stacked on the first opening, when overlooked, the second opening is located at the first opening edge, thereby reducing the circuit area of the thin film transistor to increase the aperture ratio of pixel structure.

Description

有機電激發光顯示裝置之畫素結構Pixel structure of organic electroluminescent display device

    本發明係有關於一種顯示裝置,特別是指一種有機電激發光顯示裝置之畫素結構。
The present invention relates to a display device, and more particularly to a pixel structure of an organic electroluminescent display device.

    有機電激發光顯示器(organic electroluminescent devices),又可稱為有機發光二極體(organic light emitting diode,OLED)顯示器,其包含複數畫素,每一畫素具有一陽極(電洞注入電極)、一陰極(電子注入電極)及一有機發光層,有機發光層設置於陽極與陰極之間,該發光層還包括一電子傳遞層(ETL)和一電洞傳遞層(HTL)以及用於增強發光效果之一電子注入層(EIL)和一電洞注入層(HIL)。當陽極之電洞和陰極之電子注入到發光層中時,電子與電動會在發光層中進行重組而配對,用以發光,電子與電洞會在發光之同時成對湮滅。由於有機電激發光顯示器之面板本身即具自發光性(self emission)元件,所以不需設置背光源,因此相較於液晶顯示器,有機電激發光顯示器具有輕薄、高對比、低消耗功率及廣視角等特性,且因有機電激發光顯示器之面板可陣列式顯示(dot matrix type display),因而具高解析度、反應時間短(fast response time)等特性,故,有機電激發光顯示器被視為下一世代之平面面板顯示器(flat panel display,FPD)。
    此外,一般發光層係選自於有機分子材料(依分子量大小可分為小分子材料(small molecule material)及聚合物材料(polymer material)),因此有機電激發光顯示器之面板更選自於輕薄、可撓曲之材質,因而讓有機電激發光面板具更寬廣之應用。但有機分子材料係有材質老化之問題,因而造成發光層之發光效率降低,所以現今有機電激發光顯示器之研發課題一般著重於如何補償發光層之發光效率,以避免材質老化之問題影響到發光層,藉此維持顯示器之發光效率,甚至改善發光效率。如此,現今為了改善老化之問題,遂發展出一補償電路,其利用複數薄膜電晶體提供補償電壓或補償電流,以補償發光層之老化問題所造成之發光效率降低的影響。
    此外,有機電激發光顯示器之每一畫素係藉由控制通過發光層之電流大小,以調整畫素亮度,且,為了使有機電激發光顯示器之亮度均一性變佳,一般每一畫素皆會設置補償電路,由於補償電路會額外佔用到單一畫素之使用面積,因而會嚴重影響單一畫素之開孔率。
    再者,無論有機發光顯示器之補償電路如何設計,薄膜電晶體連接至畫素電極之設置皆需經過兩開孔,如第一圖所示,習知有機發光二極體顯示器之畫素結構10具有一基板12、一薄膜電晶體14與一畫素電極16,薄膜電晶體14係具有一閘極142、一源極144與一汲極146,且汲極146經一第一開孔148連接至一第一導電層150,第一導電層150再經一第二開孔152連接至畫素電極16,由於習知畫素結構之布局設計需考慮第二開孔152之設置位置與其他元件錯開以及電路走線,以使第一開孔148與第二開孔152之設置位置分開甚遠,因而造成薄膜電晶體14之電路面積增加,導致畫素結構10之開孔率受到影響而降低。
    有鑑於此,本發明提出一種有機電激發光顯示裝置之畫素結構,其改善習知有機電激發光顯示裝置之畫素結構的開孔率降低的問題。
An organic electroluminescent device, which may also be referred to as an organic light emitting diode (OLED) display, includes a plurality of pixels, each of which has an anode (hole injection electrode), a cathode (electron injection electrode) and an organic light-emitting layer disposed between the anode and the cathode, the light-emitting layer further comprising an electron transport layer (ETL) and a hole transport layer (HTL) and for enhancing light emission One of the effects is an electron injection layer (EIL) and a hole injection layer (HIL). When the electrons of the anode and the cathode are injected into the light-emitting layer, the electrons and the motor are recombined and paired in the light-emitting layer to emit light, and the electrons and the holes are annihilated in pairs while emitting light. Since the panel of the organic electroluminescent display itself has a self-emission component, there is no need to provide a backlight, so the organic electroluminescent display has lightness, high contrast, low power consumption and wide compared with the liquid crystal display. The characteristics of the viewing angle and the like, and because of the dot matrix type display of the panel of the organic electroluminescent display, the characteristics of the high resolution and the fast response time are such that the organic electroluminescent display is regarded as Flat panel display (FPD) for the next generation.
In addition, the general light-emitting layer is selected from the group consisting of organic molecular materials (small molecule material and polymer material depending on the molecular weight), so the panel of the organic electroluminescent display is more selected from thin and light. The flexible material allows the organic electroluminescent panel to be used in a wider range of applications. However, organic molecular materials have the problem of aging of materials, which causes the luminous efficiency of the luminescent layer to decrease. Therefore, the research and development of organic electroluminescent display devices generally focus on how to compensate the luminous efficiency of the luminescent layer to avoid the problem of aging of the material. Layer, thereby maintaining the luminous efficiency of the display and even improving the luminous efficiency. Thus, in order to improve the aging problem, a compensating circuit is developed which uses a plurality of thin film transistors to provide a compensation voltage or a compensation current to compensate for the effect of the luminescence efficiency degradation caused by the aging problem of the luminescent layer.
In addition, each pixel of the organic electroluminescent display adjusts the brightness of the pixels by controlling the magnitude of the current passing through the light-emitting layer, and in order to make the brightness uniformity of the organic electroluminescent display better, generally every pixel The compensation circuit will be set up, and the compensation circuit will additionally occupy the use area of a single pixel, which will seriously affect the aperture ratio of a single pixel.
Furthermore, no matter how the compensation circuit of the organic light-emitting display is designed, the arrangement of the thin-film transistor to the pixel electrode needs to pass through two openings, as shown in the first figure, the pixel structure of the conventional organic light-emitting diode display 10 The substrate has a substrate 12, a thin film transistor 14 and a pixel electrode 16. The thin film transistor 14 has a gate 142, a source 144 and a drain 146, and the drain 146 is connected via a first opening 148. To the first conductive layer 150, the first conductive layer 150 is connected to the pixel electrode 16 via a second opening 152. The layout of the conventional pixel structure needs to consider the position and other components of the second opening 152. The staggered and circuit traces are spaced apart so that the first opening 148 and the second opening 152 are disposed far apart, thereby causing an increase in the circuit area of the thin film transistor 14, resulting in an decrease in the aperture ratio of the pixel structure 10.
In view of the above, the present invention provides a pixel structure of an organic electroluminescence display device which improves the problem of a decrease in the aperture ratio of a pixel structure of a conventional organic electroluminescence display device.

    本發明之主要目的,在於提供一種有機電激發光顯示裝置之畫素結構,其提供有機電激發光顯示裝置之畫素結構的開孔率上升。
    本發明之次要目的,在於提供一種有機電激發光顯示裝置之畫素結構,其提供補償電路減少使用面積。
    本發明係提供一種有機電激發光顯示裝置之畫素結構,其包含一基板、一薄膜電晶體、一第一絕緣層、一第二絕緣層與一畫素電極。薄膜電晶體設置於基板上,薄膜電晶體之一閘極電性連接一閘極線,薄膜電晶體之一源極電性連接一資料線,第一絕緣層設置於薄膜電晶體上,第一絕緣層具一第一開孔,第一開孔係連接薄膜電晶體之一汲極,第二絕緣層設置於第一絕緣層上,第二絕緣層具一第二開孔,第二開孔位於第一開孔上並連接畫素電極,畫素電極經第一開孔與第二開孔電性連接第二導電層。如此可使有機電激發光顯示器之補償電路佔用較小之畫素面積,而增加畫素之開孔率,進而可供尺寸較小之畫素結構,所以本發明之畫素結構可供製作出具較高解析度之顯示器。
    茲為使 貴審查委員對本發明之結構特徵及所達成之功效更有進一步之瞭解與認識,謹佐以較佳之實施例圖及配合詳細之說明,說明如後:
SUMMARY OF THE INVENTION A primary object of the present invention is to provide a pixel structure of an organic electroluminescence display device which provides an increase in the aperture ratio of a pixel structure of an organic electroluminescence display device.
A secondary object of the present invention is to provide a pixel structure of an organic electroluminescence display device that provides a compensation circuit to reduce the use area.
The invention provides a pixel structure of an organic electroluminescence display device, comprising a substrate, a thin film transistor, a first insulating layer, a second insulating layer and a pixel electrode. The thin film transistor is disposed on the substrate, one gate of the thin film transistor is electrically connected to a gate line, one source of the thin film transistor is electrically connected to a data line, and the first insulating layer is disposed on the thin film transistor, first The insulating layer has a first opening, the first opening is connected to one of the drains of the thin film transistor, the second insulating layer is disposed on the first insulating layer, the second insulating layer has a second opening, and the second opening The pixel is disposed on the first opening and connected to the pixel electrode, and the pixel electrode is electrically connected to the second conductive layer through the first opening and the second opening. In this way, the compensation circuit of the organic electroluminescent display can occupy a smaller pixel area, and the aperture ratio of the pixel is increased, thereby providing a pixel structure having a smaller size, so that the pixel structure of the present invention can be produced. Higher resolution display.
In order to give the review board members a better understanding and understanding of the structural features and the efficacies of the present invention, please refer to the preferred embodiment diagrams and the detailed descriptions as follows:

    請參閱第二圖,其為本發明之一實施例之的剖面圖。如圖所示,本發明之有機電激發光顯示裝置之畫素結構20係包含一基板22、一薄膜電晶體24與一畫素電極26。此外,薄膜電晶體24進一步包含一第一導電層242、一閘極介電層244、複數第二導電層246、一半導體層247、一第一絕緣層248、一第三導電層250與一第二絕緣層252,其中第二導電層246進一步分為一源極246a與一汲極246b,第一絕緣層248進一步具有一第一開孔248a,第二絕緣層252進一步具有一第二開孔252a。
    薄膜電晶體24設置於基板22上,依序為第一導電層242設置於基板22上,以形成薄膜電晶體24之閘極242a,閘極介電層244設置於基板22上並覆蓋第一導電層242,該些第二導電層246分別設置於閘極介電層244上,並分別形成源極246a與汲極246b,半導體層247係設置於源極246a與汲極246b之間,並連接源極246a與汲極246b,第一絕緣層248係設置於第二導電層246上,第一絕緣層248之第一開孔248a位於汲極246b之一側,第三導電層250係設置於第一開孔248a上並連接汲極246b,第二絕緣層252係設置於第一絕緣層248與第三導電層250上,第二絕緣層252之第二開孔252a係位於第三導電層250上,第三導電層250經第二開孔252a連接畫素電極26,也就是說薄膜電晶體24之汲極246b經第一開孔248a與第二開孔252a電性連接畫素電極26,且第一開孔248a之設置位置與第二開孔252a之設置位置重疊。較佳地,本實施例之第一開孔248a之孔徑大於第二開孔252a之孔徑。
    本實施例之薄膜電晶體24係以底閘極式薄膜電晶體做為舉例說明,也就是以部分第一導電層242做為薄膜電晶體24之閘極,藉由閘極之電壓控制半導體層247形成通道,進而控制源極246a與汲極246b之間導通或截止。薄膜電晶體24之源極246a係連接至資料線(圖未示),並由汲極246b連接至第一開孔248a,第二開孔252a係位於第一開孔248a上,且第二開孔252a之設置位置與第一開孔248a之設置位置重疊,所以第三導電層250之設置位置亦與第一開孔248a及與第二開孔252a之設置位置重疊,如此本發明之第三導電層250不需考慮面板之電路走線佈局而延伸,所以本發明之薄膜電晶體24即減少其使用面積,進而提高開口率。
    請參閱第三圖,其為本發明之另一實施例之剖面圖。其中第二圖與第三圖之差異在於第二圖之第一導電層242位於半導體層247下,第三圖之第一導電層346位於半導體層342上。如圖所示,本發明之畫素結構30係包含一基板32、一薄膜電晶體34與一畫素電極36。薄膜電晶體34進一步包含一半導體層342、一閘極介電層344、一第一導電層346、複數第二導電層348、一第一絕緣層350、一第三導電層352與一第二絕緣層354,其中閘極介電層344具一第一接觸孔344a與一第二接觸孔344b,第一絕緣層350具一第一開孔350a、第二絕緣層354具一第二開孔354a。較佳地,本實施例之第一開孔350a之孔徑大於第二開孔354a之孔徑。
    薄膜電晶體34係設置於基板32上,其中半導體層342係設置於基板32上,閘極介電層344係設置於半導體層342上並覆蓋基板32,閘極介電層344之第一接觸孔344a與第二接觸孔344b係分別位於半導體層342之頂部二側,第一導電層346係位於閘極介電層344上並對應於半導體層342,以作為薄膜電晶體34之閘極346a;該些第二導電層348分別位於第一導電層346之二側,並分別經第一接觸孔344a與第二接觸孔344b連接半導體層342,以分別做為薄膜電晶體34之源極348a與汲極348b,第一絕緣層350係設置於第一導電層346與第二導電層348上並進一步覆蓋閘極介電層344,第一絕緣層350之第一開孔350a係位於汲極348b上。此外,由於第三導電層352至畫素電極36之連接關係係同於前一實施例,因此不再贅述。
    本實施例之薄膜電晶體34係以背閘極式薄膜電晶體作為舉例說明,亦即本發明亦可讓採用背閘極式薄膜電晶體之有機電激發光顯示裝置可降低薄膜電晶體34之使用面積,進而提升開口率。
    綜上所述,本發明為一種有機電激發光顯示裝置之畫素結構,其藉由薄膜電晶體之汲極經重疊之第一開孔與第二開孔連接至畫素電極,以減少薄膜電晶體所使用之電路面積,因而提升畫素之開口率,進而應用於高解析度之小尺寸面板。
    雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
Please refer to the second drawing, which is a cross-sectional view of an embodiment of the present invention. As shown, the pixel structure 20 of the organic electroluminescent display device of the present invention comprises a substrate 22, a thin film transistor 24 and a pixel electrode 26. In addition, the thin film transistor 24 further includes a first conductive layer 242, a gate dielectric layer 244, a plurality of second conductive layers 246, a semiconductor layer 247, a first insulating layer 248, a third conductive layer 250, and a The second insulating layer 252 is further divided into a source 246a and a drain 246b. The first insulating layer 248 further has a first opening 248a, and the second insulating layer 252 further has a second opening. Hole 252a.
The thin film transistor 24 is disposed on the substrate 22, and the first conductive layer 242 is sequentially disposed on the substrate 22 to form a gate 242a of the thin film transistor 24. The gate dielectric layer 244 is disposed on the substrate 22 and covers the first a conductive layer 242, the second conductive layer 246 is respectively disposed on the gate dielectric layer 244, and respectively forms a source 246a and a drain 246b, and the semiconductor layer 247 is disposed between the source 246a and the drain 246b, and Connecting the source 246a and the drain 246b, the first insulating layer 248 is disposed on the second conductive layer 246, the first opening 248a of the first insulating layer 248 is located on one side of the drain 246b, and the third conductive layer 250 is disposed. The first opening 248a is connected to the drain 246b, the second insulating layer 252 is disposed on the first insulating layer 248 and the third conductive layer 250, and the second opening 252a of the second insulating layer 252 is located on the third conductive layer. On the layer 250, the third conductive layer 250 is connected to the pixel electrode 26 via the second opening 252a, that is, the drain 246b of the thin film transistor 24 is electrically connected to the pixel electrode via the first opening 248a and the second opening 252a. 26, and the position of the first opening 248a is overlapped with the position of the second opening 252a. Preferably, the aperture of the first opening 248a of the embodiment is larger than the aperture of the second opening 252a.
The thin film transistor 24 of the present embodiment is exemplified by a bottom gate type thin film transistor, that is, a part of the first conductive layer 242 is used as a gate of the thin film transistor 24, and the semiconductor layer is controlled by the voltage of the gate. 247 forms a channel that in turn controls conduction or turn-off between source 246a and drain 246b. The source 246a of the thin film transistor 24 is connected to a data line (not shown), and is connected to the first opening 248a by the drain 246b, and the second opening 252a is located on the first opening 248a, and the second opening The position of the hole 252a is overlapped with the position of the first opening 248a, so the position of the third conductive layer 250 is also overlapped with the position of the first opening 248a and the second opening 252a, so that the third aspect of the present invention The conductive layer 250 does not need to be considered in consideration of the circuit trace layout of the panel, so the thin film transistor 24 of the present invention reduces the area of use thereof, thereby increasing the aperture ratio.
Please refer to the third drawing, which is a cross-sectional view of another embodiment of the present invention. The difference between the second figure and the third figure is that the first conductive layer 242 of the second figure is located under the semiconductor layer 247, and the first conductive layer 346 of the third figure is located on the semiconductor layer 342. As shown, the pixel structure 30 of the present invention comprises a substrate 32, a thin film transistor 34 and a pixel electrode 36. The thin film transistor 34 further includes a semiconductor layer 342, a gate dielectric layer 344, a first conductive layer 346, a plurality of second conductive layers 348, a first insulating layer 350, a third conductive layer 352, and a second The insulating layer 354, wherein the gate dielectric layer 344 has a first contact hole 344a and a second contact hole 344b, the first insulating layer 350 has a first opening 350a, and the second insulating layer 354 has a second opening. 354a. Preferably, the aperture of the first opening 350a of the embodiment is larger than the aperture of the second opening 354a.
The thin film transistor 34 is disposed on the substrate 32. The semiconductor layer 342 is disposed on the substrate 32. The gate dielectric layer 344 is disposed on the semiconductor layer 342 and covers the substrate 32. The first contact of the gate dielectric layer 344 is provided. The holes 344a and the second contact holes 344b are respectively located on the top two sides of the semiconductor layer 342, and the first conductive layer 346 is located on the gate dielectric layer 344 and corresponds to the semiconductor layer 342 to serve as the gate 346a of the thin film transistor 34. The second conductive layers 348 are respectively disposed on two sides of the first conductive layer 346, and are respectively connected to the semiconductor layer 342 via the first contact hole 344a and the second contact hole 344b to serve as the source 348a of the thin film transistor 34, respectively. The first insulating layer 350 is disposed on the first conductive layer 346 and the second conductive layer 348 and further covers the gate dielectric layer 344. The first opening 350a of the first insulating layer 350 is located at the drain On 348b. In addition, since the connection relationship of the third conductive layer 352 to the pixel electrode 36 is the same as that of the previous embodiment, it will not be described again.
The thin film transistor 34 of the present embodiment is exemplified by a back gate thin film transistor, that is, the present invention can also reduce the thin film transistor 34 by using an organic electroluminescent display device using a back gate thin film transistor. Use the area to increase the aperture ratio.
In summary, the present invention is a pixel structure of an organic electroluminescence display device, which is connected to a pixel electrode by a first opening and a second opening of a thin film transistor, thereby reducing the film. The circuit area used by the transistor increases the aperture ratio of the pixel and is applied to a small-sized panel of high resolution.
While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10...畫素結構10. . . Pixel structure

12...基板12. . . Substrate

14...薄膜電晶體14. . . Thin film transistor

142...閘極142. . . Gate

144...源極144. . . Source

146...汲極146. . . Bungee

148...第一開孔148. . . First opening

150...第一導電層150. . . First conductive layer

152...第二開孔152. . . Second opening

16...畫素電極16. . . Pixel electrode

20...畫素結構20. . . Pixel structure

22...基板twenty two. . . Substrate

24...薄膜電晶體twenty four. . . Thin film transistor

242...第一導電層242. . . First conductive layer

244...閘極介電層244. . . Gate dielectric layer

246...第二導電層246. . . Second conductive layer

246a...源極246a. . . Source

246b...汲極246b. . . Bungee

247...半導體層247. . . Semiconductor layer

248...第一絕緣層248. . . First insulating layer

248a...第一開孔248a. . . First opening

250...第三導電層250. . . Third conductive layer

252...第二絕緣層252. . . Second insulating layer

252a...第二開孔252a. . . Second opening

26...畫素電極26. . . Pixel electrode

30...畫素結構30. . . Pixel structure

32...基板32. . . Substrate

34...薄膜電晶體34. . . Thin film transistor

342...半導體層342. . . Semiconductor layer

344...閘極介電層344. . . Gate dielectric layer

344a...第一接觸孔344a. . . First contact hole

344b...第二接觸孔344b. . . Second contact hole

346...第一導電層346. . . First conductive layer

348...第二導電層348. . . Second conductive layer

348a...源極348a. . . Source

348b...汲極348b. . . Bungee

350...第一絕緣層350. . . First insulating layer

350a...第一開孔350a. . . First opening

352...第三導電層352. . . Third conductive layer

354...第二絕緣層354. . . Second insulating layer

354a...第二開孔354a. . . Second opening

36...畫素電極36. . . Pixel electrode

第一圖為習知有機電激發光顯示裝置之剖面圖;
第二圖為本發明之一實施例之剖面圖;以及
第三圖為本發明之另一實施例之剖面圖。
The first figure is a cross-sectional view of a conventional organic electroluminescent display device;
2 is a cross-sectional view showing an embodiment of the present invention; and a third view is a cross-sectional view showing another embodiment of the present invention.

20...畫素結構20. . . Pixel structure

22...基板twenty two. . . Substrate

24...薄膜電晶體twenty four. . . Thin film transistor

242...第一導電層242. . . First conductive layer

244...閘極介電層244. . . Gate dielectric layer

246...第二導電層246. . . Second conductive layer

246a...源極246a. . . Source

246b...汲極246b. . . Bungee

247...半導體層247. . . Semiconductor layer

248...第一絕緣層248. . . First insulating layer

248a...第一開孔248a. . . First opening

250...第三導電層250. . . Third conductive layer

252...第二絕緣層252. . . Second insulating layer

252a...第二開孔252a. . . Second opening

26...畫素電極26. . . Pixel electrode

Claims (4)

一種有機電激發光顯示裝置之畫素結構,其包含:
一基板;
一薄膜電晶體,其設置於該基板上,該薄膜電晶體之一閘極電性連接一閘極線,該薄膜電晶體之一源極電性連接一資料線;
一第一絕緣層,其設置於該薄膜電晶體上,並具有一第一開孔,該第一開孔連接該薄膜電晶體之一汲極;
一第二絕緣層,其設置於該第一絕緣層上,並具有一第二開孔,該第二開孔位於該第一開孔上;以及
一畫素電極,其連接至該第二開孔,該畫素電極經該第一開孔與該第二開孔電性連接該汲極。
A pixel structure of an organic electroluminescence display device, comprising:
a substrate;
a thin film transistor, which is disposed on the substrate, a gate of the thin film transistor is electrically connected to a gate line, and one source of the thin film transistor is electrically connected to a data line;
a first insulating layer disposed on the thin film transistor and having a first opening, the first opening connecting one of the drains of the thin film transistor;
a second insulating layer disposed on the first insulating layer and having a second opening on the first opening; and a pixel electrode connected to the second opening a hole, the pixel electrode is electrically connected to the drain via the first opening and the second opening.
如申請專利範圍第1項所述之畫素結構,其中該薄膜電晶體係包含:
一第一導電層,其設置於該基板上,並形成該薄膜電晶體之該閘極;
一閘極介電層,其設置於該基板上並覆蓋該第一導電層;
一半導體層,其設置於該閘極介電層上;
複數第二導電層,其設置於該閘極介電層上並位於該半導體層之二側,以形成該薄膜電晶體之該源極與該汲極,該第一絕緣層設置於該半導體層與該些第二導電層上,該第一絕緣層之該第一開孔連接該汲極上;以及
一第三導電層,其設置於該些第一絕緣層上,並經該第一開孔連接該汲極,該第二絕緣層設置於該第三導電層上並覆蓋該第一絕緣層,該第二絕緣層之該第二開孔位於該第一開孔上並連接該第三導電層,該第三導電層經該第二開孔連接該畫素電極。
The pixel structure as claimed in claim 1, wherein the thin film electrocrystallization system comprises:
a first conductive layer disposed on the substrate and forming the gate of the thin film transistor;
a gate dielectric layer disposed on the substrate and covering the first conductive layer;
a semiconductor layer disposed on the gate dielectric layer;
a plurality of second conductive layers disposed on the gate dielectric layer and on two sides of the semiconductor layer to form the source and the drain of the thin film transistor, the first insulating layer being disposed on the semiconductor layer And the second conductive layer, the first opening of the first insulating layer is connected to the drain; and a third conductive layer is disposed on the first insulating layer and passes through the first opening Connecting the drain, the second insulating layer is disposed on the third conductive layer and covering the first insulating layer, the second opening of the second insulating layer is located on the first opening and connected to the third conductive a layer, the third conductive layer is connected to the pixel electrode via the second opening.
如申請專利範圍第1項所述之畫素結構,其中該薄膜電晶體係包含:
一半導體層,其設置於該基板上;
一閘極介電層,其設置於該半導體層上,該閘極介電層具至少一第一接觸孔與至少一第二接觸孔,該第一接觸孔與該第二接觸孔位於該半導體層頂部之二側;
一第一導電層,其設置於該閘極介電層上,並形成該薄膜電晶體之該閘極;
複數第二導電層,其設置於該閘極介電層上,該些第二導電層位於該第一導電層之二側並與該第一導電層分開,該些第二導電層分別經該第一接觸孔與該第二接觸孔連接該半導體層,以形成該源極與該汲極,該第一絕緣層設置於該第一導電層與該些第二導電層上,該第一絕緣層之該第一開孔連接該汲極;以及
一第三導電層,其設置於該第一開孔上,並經該第一開孔連接該汲極,該第二絕緣層設置於該第三導電層上並覆蓋該第一絕緣層,該第二絕緣層之該第二開孔位於該第一開孔上並連接該第三導電層,該第三導電層經該第二開孔連接該畫素電極。
The pixel structure as claimed in claim 1, wherein the thin film electrocrystallization system comprises:
a semiconductor layer disposed on the substrate;
a gate dielectric layer disposed on the semiconductor layer, the gate dielectric layer having at least one first contact hole and at least one second contact hole, wherein the first contact hole and the second contact hole are located in the semiconductor Two sides of the top of the layer;
a first conductive layer disposed on the gate dielectric layer and forming the gate of the thin film transistor;
a plurality of second conductive layers disposed on the gate dielectric layer, the second conductive layers being disposed on two sides of the first conductive layer and separated from the first conductive layer, the second conductive layers respectively passing through the The first contact hole and the second contact hole are connected to the semiconductor layer to form the source and the drain, the first insulating layer is disposed on the first conductive layer and the second conductive layer, the first insulation The first opening of the layer is connected to the drain; and a third conductive layer is disposed on the first opening, and the drain is connected via the first opening, and the second insulating layer is disposed on the first opening The first conductive layer is disposed on the third conductive layer, the second opening of the second insulating layer is located on the first opening and connected to the third conductive layer, and the third conductive layer is connected through the second opening The pixel electrode.
如申請專利範圍第1項所述之畫素結構,其中該第一開孔之孔徑大於該第二開孔之孔徑。The pixel structure of claim 1, wherein the aperture of the first opening is larger than the aperture of the second opening.
TW100149756A 2011-12-30 2011-12-30 Pixel structure of organic electroluminescent display device TW201327797A (en)

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