TW201324776A - Fin field effect transistor - Google Patents

Abstract

A fin field effect transistor including at least one fin type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is disposed above the blocking region. The gate strip is substantially perpendicular to the fin type semiconductor structure and covers thereon. The gate insulating layer is disposed between the gate strip and the fin type semiconductor structure.

Description

Fin field effect transistor

The present invention relates to a semiconductor component, and more particularly to a fin field effect transistor.

As the line width of the Metal-Oxide Semiconductor (MOS) process shrinks, the leakage current between the source and the drain away from the gate increases. Although the leakage current can be reduced by a thin gate dielectric layer, when the process line width is reduced to 0.1 μm or less, even a thin gate dielectric layer cannot reduce leakage current. For this problem, Professor Chen Ming Hu of the University of California at Berkeley pointed out two solutions. One is to fabricate a MOS field effect transistor using a very thin first-doped semiconductor substrate (Metal). -Oxide Semiconductor Field-Effect Transistor (MOSFET), so that there is no longer a distance away from the gate in the substrate, and the leakage current is completely eliminated. The second is to form a double gate, which is separated by a gate dielectric layer. The channel area is sandwiched so that the entire channel area is affected by the gate electric field, which increases the on-current of the component and reduces leakage current.

Therefore, the predecessors proposed a Fin Filed Effect Transistor (FinFET) that combines the above two concepts. In the current process of fin field effect transistors, a plurality of trenches are etched on the doped germanium substrate to form fins between the trenches, or directly doped germanium layers. Patterned as a fin, and then a gate insulating layer and a gate layer are formed over the fin to form a fin field effect transistor. That is to say, the two ends of the fins are respectively used as the source and the drain of the transistor, and the portion below the gate layer is used as the channel region. It can be seen that the channel width of the transistor is related to the height of the fin. For example, in a dual gate fin field effect transistor, the channel width is equal to twice the fin height. On the other hand, the channel width of a three-gate fin field effect transistor is equal to twice the height of the fin plus the width of the top of the fin.

However, due to process factors, the fins of conventional FinFETs have the same height, so the channel width can only be adjusted by increasing or decreasing the number of fins, making it difficult to create a channel that is consistent with actual needs. Fin-type field effect transistor.

In view of this, the present invention provides a fin field effect transistor that elastically determines the width of the channel region according to various needs.

The present invention provides a fin field effect transistor comprising at least one fin-shaped semiconductor structure, a gate strip, and a gate insulating layer, wherein the fin-shaped semiconductor structure is doped with a first type dopant and has a channel region and a power blocking region. The galvanic region has a first doping concentration, the channel region has a second doping concentration, and the first doping concentration is greater than the second doping concentration. The power blocking area has a height, and the channel area is located above the power blocking area. The gate strip is substantially perpendicular to the first fin-shaped semiconductor structure and covers the channel region, and the gate insulating layer is disposed between the gate strip and the fin-shaped semiconductor structure.

In an embodiment of the invention, the fin field effect transistor has a more active structure and a drain structure, respectively doped with a second type dopant. The fin semiconductor structure described above is connected between the source structure and the drain structure.

In an embodiment of the invention, the gate strips conformally cover the finned semiconductor structure.

In an embodiment of the invention, the material of the gate strip is, for example, a polysilicon.

In an embodiment of the invention, the fin field effect transistor includes a plurality of fin-shaped semiconductor structures arranged in parallel, the fin-shaped semiconductor structures having the same height, and the power-blocking regions having different heights.

In an embodiment of the invention, the fin field effect transistor further includes a semiconductor substrate having a plurality of trenches substantially parallel to each other, and the finned semiconductor structures are surrounded by the adjacent trenches.

In an embodiment of the invention, the gate strip is formed on the semiconductor substrate in a flat manner and filled in the trenches to cover a portion of the fin-shaped semiconductor structure.

In an embodiment of the present invention, the fin field effect transistor further includes a plurality of isolation structures respectively disposed in the trenches, and the gate strips are located on the isolation structures, and the top of the power blocking region The surface is higher than the top surface of these isolation structures.

In an embodiment of the invention, the material of the gate strip is, for example, metal, and the material of the gate insulating layer is, for example, a high dielectric constant material.

In an embodiment of the present invention, the fin field effect transistor further includes an insulating layer disposed on a top surface of the gate insulating layer between the gate insulating layer and the gate strip, and the thickness of the insulating layer is greater than The thickness of the gate insulation layer.

The fin field effect transistor of the present invention forms a different depth and height of the electrical resistance region by performing different strength doping processes on the fin semiconductor structures, so that the channel widths provided by the fin semiconductor structures are inconsistent. In this way, a fin field effect transistor with a more flexible channel width can be provided.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A is a partial perspective view of a fin field effect transistor according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of the fin field effect transistor of FIG. 1A along line A-A'. Referring to FIG. 1A and FIG. 1B simultaneously, the FinFET 100 includes a fin-shaped semiconductor structure 110, a gate strip 120, and a gate insulating layer 130. It should be noted that although the present embodiment is described by taking two fin-shaped semiconductor structures 110 having the same height as an example, the present invention is not limited thereto. In other embodiments, the fin field effect transistor 100 may also include one or more than two fin semiconductor structures 110.

In the above, the fin-shaped semiconductor structure 110 is doped with a first type dopant and has a channel region 112 and a power blocking region 114, wherein the blocking region 114 is located at the root of the fin-shaped semiconductor structure 110 and is in a different fin-shaped semiconductor structure. 110 has different heights H1 and H2. The channel region 112 is located above the power blocking region 114. Moreover, the resistive region 114 has a first doping concentration, and the channel region 112 has a second doping concentration, wherein the first doping concentration is greater than the second doping concentration.

In addition, the fin field effect transistor 100 of the present embodiment further includes a source structure 116 and a drain structure 118, respectively doped with a second type dopant. Moreover, the fin semiconductor structure 110 is connected between the source structure 116 and the drain structure 118. Specifically, if an N-type field effect transistor is to be fabricated, a P-type dopant may be first doped in the fin-shaped semiconductor structure 110, and then an N-type doping may be incorporated in the source structure 116 and the gate structure 118. On the other hand, if a P-type FinFET is to be fabricated, an N-type dopant may be first doped in the fin-shaped semiconductor structure 110, and then a P-type doping may be incorporated in the source structure 116 and the gate structure 118. quality.

Further, in the process of the FinFET 100 of the present embodiment, for example, the substrate 102 is provided first, and then the dielectric layer 104 and the semiconductor layer (not shown) are formed on the substrate 102, wherein the semiconductor layer is The dielectric layer 104 is, for example, an insulating silicon on silicon (SOI) wafer disposed on the substrate 102.

The semiconductor layer is then patterned into one or more fin-shaped semiconductor structures 110 and the first type dopants are incorporated into the fin-shaped semiconductor structures 110. It is worth mentioning that in other embodiments, the first type dopant may be first doped into the semiconductor layer on the dielectric layer 104, and then the doped semiconductor layer is patterned to form one or more. The doped fin semiconductor structure 110.

In the above process, in the process of doping the first type dopant, for example, all the fin semiconductor structures 110 are first doped first, so that the fin semiconductor structures 110 are uniformly doped with the first type dopant. At this time, the doping concentration of each of the fin-shaped semiconductor structures 110 is the second doping concentration. Then, the second doping process is selectively performed on the finned semiconductor structures 110 with different intensities according to requirements, and the finned semiconductor structures 110 have the first doping concentration of the first type at different depths. The dopant is used as the electrical blocking region 114. The doping process of the source structure 116 and the drain structure 118 may be performed before or after the formation of the power blocking region 114, and the present invention is not limited thereto.

As can be seen from the above, in the FinFET 100 of the present embodiment, the power blocking regions 114 of the fin-shaped semiconductor structures 110 may have different heights depending on the doping depth of the first-type dopants of the second time. As shown in FIG. 1B, the different fin-shaped semiconductor structures 110 are, for example, electrically resistive regions 114 having heights H1 and H2, respectively, so that different fin-shaped semiconductor structures 110 can have different heights (C1 as shown in FIG. 1B). Channel area 112 of C2).

The gate strip 120 is a capped semiconductor region 110 that covers the channel region 112 and is substantially vertical. The gate insulating layer 130 is disposed between the gate strip 120 and the fin-shaped semiconductor structure 110. In the present embodiment, the material of the gate strip 120 is, for example, a polysilicon, and it conformally covers the fin-shaped semiconductor structures 110, but the invention is not limited thereto. In other embodiments, the gate strips 120 may also be planarly overlying the fin-shaped semiconductor structure 110.

In each of the fin-shaped semiconductor structures 110, since the first doping concentration of the resistive region 114 is greater than the second doping concentration of the channel region 112, the source structure 116 when a voltage is applied to the gate strip 120 The charge within it will move to the drain structure 118 via the channel region 112 above the resistive region 114. That is, the channel width provided by the fin-shaped semiconductor structure 110 is related to the heights C1 and C2 of the channel region 112.

It is worth mentioning that, since the second doping process of the first type dopant is performed selectively, the Fin field effect transistor 100 of the embodiment may also include not performing the second doping. The finned semiconductor structure 140. Since the fin-shaped semiconductor structure 140 is subjected to the doping process of the first-type dopant only once, the resistive region 114 is not provided. That is, the width of the channel that the fin-shaped semiconductor structure 140 can provide is related to its total height C3.

In detail, the Fin field effect transistor 100 of the present embodiment is, for example, a tri-gate type FinFET, so that each of the fin-shaped semiconductor structures 110 provides a channel width of two of the channel regions 112. The double height plus the width W1 at the top of the channel region 112, the width of the channel provided by the fin-shaped semiconductor structure 140 is twice its total height C3 plus the width W2 of its top. Therefore, the fin field effect transistor 100 of the present embodiment can determine the height of the power blocking region 114 according to the required channel width, and elastically determine the channel width when all the fin semiconductor structures 110 are equal in height. size.

In another embodiment of the present invention, as shown in FIG. 2, the fin field effect transistor 200 may also be a double-gate type FinFET, which is on the top of the gate insulating layer 130. An insulating layer 240 is disposed on the surface such that the insulating layer 240 is located between the gate insulating layer 130 and the gate strip 120. Specifically, the insulating layer 240 may be made of the same material in the same process as the gate insulating layer 130. Alternatively, after the gate insulating layer 130 is formed, another process may be performed to form the insulating layer 240.

As described above, in the FinFET 200, the pitch h1 between the gate strip 120 and the top surface of each of the fin-shaped semiconductor structure 110 and the fin-shaped semiconductor structure 140 is much larger than that of the fin-shaped semiconductor structure 110 and the fin-shaped semiconductor. The pitch h2 of the sidewalls of the structure 140, and thus the voltage applied to the gate strip 120, is difficult to induce charge in the source structure 116 to flow to the drain structure 118 via the top surfaces of the fin semiconductor structures 110 and the fin semiconductor structures 140. That is, each of the fin-shaped semiconductor structures 110 of the present embodiment provides an effective channel width that is twice the height of the channel region 112, and the fin-shaped semiconductor structure 140 provides an effective channel width that is twice its total height C3.

The foregoing embodiments all pattern the semiconductor layer into a plurality of individual fin-shaped semiconductor structures, but in other embodiments, the fin-shaped semiconductor structures may also be connected in parallel with each other. The embodiment will be described below.

3A is a partial perspective view of a fin field effect transistor according to another embodiment of the present invention, and FIG. 3B is a schematic cross-sectional view of the Fin field effect transistor of FIG. 3A along the B-B' line. Referring to FIG. 3A and FIG. 3B simultaneously, the fin field effect transistor 300 of the present embodiment is substantially the same as the fin field effect transistor 100 of the foregoing embodiment, and the differences between the two will be described below.

The fin field effect transistor 300 includes a semiconductor substrate 302, a gate strip 320, and a gate insulating layer 330, wherein the semiconductor substrate 302 has a plurality of trenches 303 substantially parallel to each other, and a plurality of adjacent trenches 303 are enclosed The fin semiconductor structures 310 are the same height, and the fin semiconductor structures 310 are connected in parallel to each other, for example, through the semiconductor substrate 302. Although two fin-shaped semiconductor structures 310 are illustrated herein, the present invention is not limited in number. In other embodiments, the fin field effect transistor 300 may also include one or more fin-shaped semiconductor structures 310.

The finned semiconductor structures 310 have a channel region 312 and a resistive region 314, respectively, and the different fin-shaped semiconductor structures 310 are, for example, electrical blocking regions 314 having different heights (H1 and H2 as indicated in FIG. 3B). In other words, the different fin semiconductor structures 310 also have different channel widths C1 and C2. Specifically, the method for forming the channel region 312 and the power blocking region 314 is the same as or similar to the method for forming the channel region 112 and the power blocking region 114 of the foregoing embodiment, and details are not described herein again. In addition, the fin field effect transistor 300 also includes a source structure 316 and a drain structure 318, and the fin semiconductor structure 310 is connected between the source structure 316 and the drain structure 318. The method of forming the source structure 316 and the drain structure 318 and the impurities incorporated therein are also the same as or similar to the source structure 116 and the drain structure 118 of the previous embodiment.

3A and 3B, the gate strip 320 is substantially perpendicular to the fin-shaped semiconductor structure 310, and is formed, for example, flat on the semiconductor substrate 302 to cover a portion of the fin-shaped semiconductor structure 310 and fill the trench 303. That is, the upper surface of the gate strip 320 is located at a single horizontal plane and is higher than the top surface of the fin-shaped semiconductor structure 310. In other embodiments of the present invention, the gate strip 320 may also conformally cover the fin-shaped semiconductor structure 310 and fill the trench 303, which is not limited in the present invention.

The gate insulating layer 330 is disposed between the gate strip 320 and the fin-shaped semiconductor structure 310. In this embodiment, the material of the gate strip 320 is, for example, a metal such as a titanium aluminum alloy. The material of the gate insulating layer 330 is, for example, a high dielectric constant material such as aluminum oxide (Al ₂ O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), yttrium ruthenate. Oxygen compound (HfSiO ₄ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₃ ), zirconium dioxide (ZrO ₂ ), barium titanate (SrTiO ₃ ), zirconium oxynitride (ZrSiO ₄ ), etc. High dielectric constant materials or combinations thereof.

In particular, the FinFET 300 of the present embodiment may further include a plurality of isolation structures 304 respectively disposed in the trenches 303 of the semiconductor substrate 302 for electrically isolating the semiconductor substrate 302 and formed thereon. Gate strip 320. Here, the material of these isolation structures 304 is, for example, an oxide. It should be noted that, as shown in FIG. 3B, in the fin-shaped semiconductor structure 310 of the present embodiment, the bottom surface of the power blocking region 314 is, for example, aligned with the top surface of the isolation structure 304, but the present invention is not limited thereto. In other embodiments, the bottom surface of the power blocking region 314 may also be lower than the top surface of the isolation structure 304, and the top surface of the power blocking region 314 is higher than the top surface of the isolation structure 304.

In addition, the fin field effect transistor 300 may also include a fin-shaped semiconductor structure 340, which is surrounded by the adjacent trenches 303 as well as the fin-shaped semiconductor structure 310, and the fin-shaped semiconductor structure 340 does not undergo the first type of dopant The second doping does not have a resistive region 314. It can be seen that in the FinFET 300, when the voltage applied to the gate strip 320 is greater than the threshold voltage of the channel region 312, only the channel region 312 is available in each of the fin-shaped semiconductor structures 310. The carrier flows from the source structure 316 to the drain structure 318, and the fin semiconductor structure 340 is available for the carrier to flow from the source structure 316 to the drain structure 318 at a portion above the top surface of the isolation structure 304. That is, in the FinFET 300, the width of the channel provided by each of the fin-shaped semiconductor structures 310 is related to the heights C1 and C2 of the channel region 312, and the width of the channel provided by the fin-shaped semiconductor structure 340 is higher. The height C3 of the portion of the top surface of the isolation structure 304 is related.

Although the above description is based on the three-gate fin field effect transistor 300 illustrated in FIGS. 3A and 3B, those skilled in the art should know that a trench 303 is formed on the semiconductor substrate 302 to surround the fin semiconductor. The structure of the technology can also be applied to the double gate fin field effect transistor, which will not be described here.

In summary, the fin field effect transistor of the present invention can perform different intensity doping processes for each fin semiconductor structure under the condition that the fin semiconductor structures are equally high, so as to form different depth and height resistances. The regions, in turn, cause the channel widths provided by the finned semiconductor structures to be inconsistent to provide a fin field effect transistor with a more flexible channel width.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100, 200, 300. . . Fin field effect transistor

102. . . Base

104. . . Dielectric layer

110, 140, 310, 340. . . Fin semiconductor structure

112, 312. . . Channel area

114, 314. . . Electrical resistance zone

116, 316. . . Source structure

118,318. . . Bungee structure

120. . . Gate strip

130, 330. . . Brake insulation

240. . . Insulation

302. . . Semiconductor substrate

303. . . ditch

304. . . Isolation structure

320. . . Gate strip

C1, C2, C3, H1, H2. . . height

W1, W2. . . width

H1, h2. . . spacing

1A is a partial perspective view of a fin field effect transistor in accordance with an embodiment of the present invention.

1B is a cross-sectional view of the fin field effect transistor of FIG. 1A taken along line A-A'.

2 is a cross-sectional view of a fin field effect transistor in accordance with another embodiment of the present invention.

3A is a partial perspective view of a fin field effect transistor according to another embodiment of the present invention.

3B is a cross-sectional view of the fin field effect transistor of FIG. 3A taken along line B-B'.

300. . . Fin field effect transistor

302. . . Semiconductor substrate

303. . . ditch

304. . . Isolation structure

310, 340. . . Fin semiconductor structure

312. . . Channel area

314. . . Electrical resistance zone

320. . . Gate strip

330. . . Brake insulation

C1, C2, C3, H1, H2. . . height

Claims (10)

A fin field effect transistor includes: at least one fin-shaped semiconductor structure doped with a first type dopant, and the at least one fin semiconductor structure has a channel region and a resistance region, wherein the resistance region has a first a doping concentration, the channel region has a second doping concentration, and the first doping concentration is greater than the second doping concentration, and the blocking region has a height, the channel region is located above the blocking region; a gate strip substantially perpendicular to the at least one first fin-shaped semiconductor structure and covering the channel region; and a gate insulating layer disposed between the gate strip and the at least one fin-shaped semiconductor structure. The fin field effect transistor of claim 1, further comprising a source structure and a drain structure, wherein the at least one fin semiconductor structure is connected between the source structure and the drain structure, And the source structure and the drain structure are respectively doped with a second type dopant. The fin field effect transistor of claim 1, wherein the gate strip conformally covers a portion of the at least one fin semiconductor structure. The fin field effect transistor of claim 1, wherein the material of the gate strip comprises polysilicon. The fin field effect transistor of claim 1, comprising a plurality of fin-shaped semiconductor structures arranged in parallel, the fin-shaped semiconductor structures having the same height, and the resistances of the fin-shaped semiconductor structures The zones have different heights. The fin field effect transistor of claim 1, further comprising a semiconductor substrate having a plurality of trenches substantially parallel to each other, and enclosing the at least one fin semiconductor between the adjacent trenches structure. The fin field effect transistor of claim 1, wherein the gate strip is formed flat on the semiconductor substrate to fill the trenches and cover the channel region. The fin field effect transistor according to claim 6, further comprising a plurality of isolation structures respectively disposed in the trenches, wherein the gate strips are located on the isolation structures, and the top of the power blocking region The surface is higher than the top surface of the isolation structures. The fin field effect transistor of claim 6, wherein the material of the gate strip comprises a metal, and the material of the gate insulating layer comprises a high dielectric constant material. The fin field effect transistor of claim 1, further comprising an insulating layer disposed on a top surface of the gate insulating layer between the gate insulating layer and the gate strip.