TWI593111B - Semiconductor device - Google Patents

Description

Semiconductor device

The present invention relates to a non-planar semiconductor device, and more particularly to a non-planar semiconductor device having an epitaxial structure.

As the size of field effect transistors (FETs) components continues to shrink, the development of conventional planar field effect transistor components has faced process limitations. In order to overcome process limitations, non-planar field effect transistor components, such as multi-gate MOSFET components and fin field effect transistor (Fin FET) components Replacing planar transistor components has become the mainstream trend. Since the three-dimensional structure of the non-planar transistor element can increase the contact area between the gate and the fin structure, the control of the gate to the carrier channel region can be further increased, thereby reducing the source-induced energy band reduction of the small-sized component. The (drain induced barrier lowering, DIBL) effect can suppress the short channel effect (SCE). In addition, compared to planar field effect transistor components, non-planar transistor components have a wider channel width at the same gate length and thus provide double drain drive current.

On the other hand, the so-called "strained-silicon technology" has been developed in the industry to further increase the carrier mobility of the transistor components. For example, one of the mainstream strain enthalpy techniques is that the lattice constant of bismuth (SiGe) or germanium carbon (SiC) is different from that of single crystal Si. The structure is disposed in a source/drain region of the semiconductor element. Since the lattice constants of the germanium epitaxial structure and the germanium carbon epitaxial structure are larger and smaller than the single crystal germanium, respectively, the carrier channel adjacent to the epitaxial structure will feel the applied stress, and the lattice and the band are correspondingly generated. A change in the structure of the band. Under this circumstance, the carrier mobility and the speed of the corresponding field effect transistor can be effectively improved.

However, as the scale of semiconductor components continues to shrink, even with the use of non-planar field effect transistor components and strain enthalpy technology, all technical deficiencies cannot be solved. For example, two adjacent epitaxial structures generally generate unnecessary lattice defects due to excessive growth of the epitaxial layer, which reduces the stress that can be generated by the epitaxial structure. Therefore, how to eliminate the lattice defects of the epitaxial structure becomes an important issue.

In view of the above, it is an object of the present invention to provide a semiconductor device having an epitaxial layer to reduce lattice defects and improve stress values applied to the channel region.

In order to achieve the above object, according to a preferred embodiment of the present invention, there is provided a semiconductor device comprising at least a two fin structure, a gate structure, at least two epitaxial structures, and a cap layer. The fin structure is disposed on the substrate, and the gate structure covers the fin structure. The epitaxial structures are disposed on one side of the gate structure, and each directly contacts each of the fin structures, wherein the epitaxial structures are separated from each other. The cap layer is simultaneously coated with an epitaxial structure.

According to another preferred embodiment of the present invention, there is provided a semiconductor device comprising at least a two fin structure, a gate structure, at least two epitaxial structures, and a cap layer. The fin structure is disposed on the substrate, and the gate structure covers the fin structure. The epitaxial structures are disposed on one side of the gate structure, and each directly contacts each of the fin structures, wherein the epitaxial structures have an overlapping portion, and each of the epitaxial structures has a width, an overlap portion, and a width ratio The value is substantially between 0.001 and 0.25. The cover layer will simultaneously cover the epitaxial structure.

10‧‧‧Base

10a‧‧‧ surface

12‧‧‧Fin structure

14‧‧‧ top surface

16‧‧‧ side

20‧‧‧Insulation structure

30‧‧‧ gate structure

32‧‧‧Sacrificial electrode layer

34‧‧‧ bottom layer

36‧‧‧ top

38‧‧‧ cover

40‧‧‧ Sidewall

46‧‧‧ etching process

60‧‧‧ Groove

66‧‧‧ epitaxial structure

68‧‧‧矽 Cover

68a‧‧‧ top

70‧‧‧Interlayer dielectric layer

72‧‧‧Contact hole

74‧‧‧Contact plug

H1‧‧‧ Height

H2‧‧‧ Height

O‧‧‧Overlap

P‧‧‧ plane

S‧‧‧ distance

T1‧‧‧ thickness

W‧‧‧Width

X‧‧‧ first direction

Y‧‧‧second direction

Z‧‧‧ third direction

1 to 8 are schematic views showing a method of fabricating a fin field effect transistor device according to a preferred embodiment of the present invention.

9 to 10 are schematic views showing a method of fabricating a fin field effect transistor device according to another preferred embodiment of the present invention.

11 is a schematic view showing a method of fabricating a fin field effect transistor device according to another preferred embodiment of the present invention.

In the following, specific embodiments of the semiconductor device of the present invention are set forth so that those skilled in the art can implement the present invention. The specific embodiments may be referred to the corresponding drawings, such that the drawings form part of the embodiments. Although the embodiments of the present invention are disclosed as follows, they are not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention.

1 to 8 are schematic views showing a method of fabricating a semiconductor device according to a first preferred embodiment of the present invention. Referring to FIG. 1, FIG. 1 is a perspective view of the semiconductor device in an initial stage. As shown in FIG. 1, in the initial stage of the process, the semiconductor device has a substrate 10 and a plurality of fin-like structures 12 disposed on the substrate 10. The major surface 10a of the substrate 10 may have a predetermined crystal plane, and the major axis of the fin structure 12 is parallel to a crystal orientation. For example, for a germanium substrate, the predetermined crystal plane may be a (100) crystal plane, and the fin structure 12 may extend along the <110> crystal orientation, but the crystal plane and crystal orientation are not limited thereto. In addition to the bulk substrate, the substrate 10 described above may also be, for example Is a germanium-containing substrate, a group of three or five semiconductor semiconductor substrates (such as GaAs-on-silicon), a graphene-on-silicon or a silicon-on-insulator (SOI) substrate. A semiconductor substrate.

In detail, the method for preparing the fin-shaped structure 12 may include the following steps, but is not limited thereto. For example, a piece of substrate (not shown) is first provided and a hard mask layer (not shown) is formed thereon. The hard mask layer is then patterned using photolithography and an etch process to define the location of the fin-like structure 12 to be subsequently formed. Next, an etching process is performed to transfer the pattern defined in the hard mask layer into the bulk substrate to form the desired fin-like structure 12. Finally, the hard mask layer is selectively removed to obtain the structure as shown in Fig. 1. In this case, the fin-like structures 12 can be considered to extend from one main surface 10a of the substrate 10 and have the same composition as each other, such as a single crystal germanium. On the other hand, when the substrate is not selected from the above-mentioned bulk substrate, but is selected from the three-five semiconductor semiconductor substrate, the main composition of the fin-shaped structure is the same as that of the three-five semiconductor of the substrate.

In this embodiment, since the hard mask layer (not shown) can be selectively removed after the fin-like structure 12 is formed, the fin-like structure 12 and the subsequently formed gate dielectric layer can be Three direct contact faces (including two contact sides 16 and one contact top surface 14). In general, a field effect transistor having the three direct junction faces is also referred to as a three-gate field-effect transistor (tri-gate MOSFET). Since the three direct contact surfaces in the three-gate field effect transistor can serve as a channel for providing carrier flow, the three-gate field effect transistor will have the same gate length as compared with the planar field effect transistor. Having a wider carrier channel width results in a doubled drain drive current at the same drive voltage. In addition, this embodiment can also selectively retain a hard mask layer (not shown), and form another multi-gate field effect transistor with a fin structure in a subsequent process (multi-gate). MOSFET), also known as fin field effect transistor (Fin FET). For a fin field effect transistor, since it retains a hard mask layer (not shown), there are only two contact sides between the fin structure 12 and the subsequently formed gate dielectric layer.

Referring to FIG. 2, FIG. 2 is a perspective view of the semiconductor device after forming the gate structure. As shown in FIG. 2, an insulating structure 20 is formed on the substrate 10 and covers the lower portion of each fin-like structure 12 to electrically insulate the subsequently formed transistors. The insulating structure 20 can be, for example, a shallow trench isolation (STI) structure, which can be fabricated by a shallow trench isolation process. Since the detailed formation method is well known to those skilled in the art, it will not be described again, but the invention is not limited thereto.

Continuing, as shown in FIG. 2, a gate dielectric layer (not shown), a sacrificial electrode layer (not shown), and a cap layer (not shown) are sequentially formed from bottom to top to cover Substrate 10 and fin-like structure 12. Subsequently, a cap layer (not shown), a sacrificial electrode layer (not shown), and a gate dielectric layer (not shown) are patterned to form a gate dielectric layer (not shown), a sacrifice The electrode layer 32 and a cap layer 38 are on the substrate 10 and the fin structure 12. The patterned gate dielectric layer, sacrificial electrode layer 32, and cap layer 38 can form a gate structure 30 that spans each fin structure 12 and covers the insulating structure 20 between the fin structures 12. According to this embodiment, the gate structure 30 will span the second fin structure 12 to form the structure as shown in FIG. Specifically, the gate structure 30 covers a portion of the top surface 14 and the two side surfaces 16 of each of the fin structures 12 and covers a top surface of the portion of the insulating structure 20. In addition, the gate structure 30 preferably extends along a first direction X, and the fin structure 12 preferably extends along a second direction Y and protrudes the substrate 10 along a third direction Z. The first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but are not limited thereto.

In order to facilitate the clear disclosure of the present invention, only a single gate structure 30 is illustrated in Figures 2 through 8, however, the number may be increased depending on the needs of different products. For example, more than one and parallel gate structures may be provided on the substrate such that the same fin structure may be covered by more than one gate structure. In addition, the same gate structure 30 is preferably used as a gate of the same conductivity type transistor, for example, as a gate of a PMOS transistor or a gate of an NMOS transistor.

In this embodiment, a gate-last for high-K last process is taken as an example, so that the gate structure 30 can also be regarded as a dummy gate structure. ). In other words, the gate dielectric layer will be replaced by a high dielectric constant gate dielectric layer in a subsequent process, and the sacrificial electrode layer 32 will be replaced with a conductive metal layer. In this embodiment, the gate dielectric layer can be only a sacrificial material that is generally convenient for removal in subsequent processes, such as an oxide layer. The composition of the sacrificial electrode layer 32 may be a polycrystalline semiconductor material such as polycrystalline germanium, but is not limited thereto. The cap layer may include a single layer or a multilayer structure composed of a nitride layer or an oxide layer or the like as a patterned hard mask. In this embodiment, the cap layer 38 is a two-layer structure, which may include a bottom layer 34 and a top layer 36 from bottom to top, and the bottom layer 34 is, for example, a nitride layer, and the top layer 36 may be, for example, an oxide layer. Not limited to this.

The above is a description of the implementation of the post-high dielectric constant gate process. However, the embodiment is not limited thereto, and a gate-last for high-K first gate may be used. Process. In this aspect, the gate dielectric layer can be a high dielectric constant gate dielectric layer, which can be selected from hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO ₄ ). , hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ) , yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate (SrTiO ₃ ), zirconium silicate (ZrSiO ₄ ), yttrium zirconate (hafnium zirconate, HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and titanium A group consisting of barium strontium titanate (BaxSr _1-x TiO ₃ , BST), but the invention is not limited thereto. In addition, a barrier layer (not shown) may be formed on the gate dielectric layer to protect the gate dielectric layer as an etch stop layer when the sacrificial electrode layer is removed, and may be prevented from subsequently being placed thereon. The metal component diffuses downward to contaminate the gate dielectric layer. The barrier layer may be, for example, a single layer structure or a composite layer structure of tantalum nitride (TaN), titanium nitride (TiN) or the like.

Please refer to Figure 3. After forming the gate structure described above, a sidewall 40 can be formed on one of the sidewalls of the gate structure 30 as shown in FIG. 3 to define the location of the subsequently formed epitaxial structure. The sidewalls 40 of the present embodiment are preferably formed on each side of the gate structure 30 and cover a portion of each of the fin structures 12. In detail, the method of forming the sidewalls 40 may be, for example, first, a material layer (not shown) is deposited on the gate structure 30 and the substrate 10, and then an etching process is performed to form a desired layer. Side wall 40 contour. The structure of the sidewalls 40 may include a single layer structure or a multilayer structure, such as a single layer structure composed of tantalum nitride, hafnium oxynitride, or the like, or a double layer structure composed of hafnium oxide/tantalum nitride, etc., but not This is limited to this. The sidewalls 40 referred to in this embodiment are used to define and form the sidewalls of the epitaxial structure. Therefore, before or after the sidewall spacers 40 are formed, other thinner sidewalls may be additionally formed to form a lightly doped source. / drain region (not shown) or otherwise form other thicker sidewalls to form a source/drain region (not shown) or the like.

Referring to FIG. 4, FIG. 4 is a perspective view of the semiconductor device after etching the fin-shaped structure. As shown in FIG. 4, an etching process 46 can be selectively performed over the gate structure 30 and the sidewalls 40 to etch the fin-like structures 12 and fin fins on at least one side of the gate structure 30. A recess 60 is formed in the structure 12. In detail, the etching may include at least one dry etching step or/and at least one wet etching step, for example, first etching the fin structure 12 in a dry etching step up to a predetermined depth, and then laterally etching in a wet etching step to form The outline of the groove 60 is required, but is not limited thereto. In this embodiment, one of the grooves 60 has a concave cross-sectional structure, but not limited thereto, and the grooves may have different cross-sectional structures as needed.

Referring to FIG. 5 and FIG. 6, FIG. 5 is a perspective view of the semiconductor device after forming the epitaxial structure, and FIG. 6 is a cross-sectional view taken along line AA' of FIG. As shown in FIG. 5, after the recess 60 is selectively formed, an epitaxial growth process can be performed to form an epitaxial structure 66 in the corresponding recess 60. According to this embodiment, each of the epitaxial structures 66 are preferably disposed independently of each other, that is, without a merge. For example, for each pitch fin structure 12 having a pitch of between 10 nm and 14 nm, when the height H1 of the epitaxial structure 66 is between 300 angstroms and 600 angstroms, each epitaxial layer The structure 66 will have a distance S, or a gap, between about 30 angstroms and 150 angstroms, so that the epitaxial structures 66 will not merge, but are not limited thereto. The epitaxial growth process may be, for example, a molecular beam epitaxy (MBE), a co-flow epitaxial growth process, or a cyclic selective epitaxial growth process (cyclic selective). Epitaxial growth process) or other similar epitaxial process.

In addition, according to different conductivity type semiconductor devices, correspondingly adjustable The composition of the epitaxial structure 66 described above is varied to apply appropriate stresses to specific regions within the semiconductor device. For example, for a P-type semiconductor device, since the epitaxial structure 66 is preferably used to provide compressive stress to adjacent channel regions, its composition may be, for example, with or without dopants, such as boron dopants. , the layer of 。. Moreover, the epitaxial structure 66 may have a cladding structure having a plurality of layers of different concentrations from inside to outside or/and from bottom to top. For example, the epitaxial structure may include at least one epitaxial layer having a relatively low germanium concentration, at least one epitaxial layer having a relatively high germanium concentration, an adhesive layer, and the like from bottom to top. On the other hand, for an N-type semiconductor device, since the epitaxial structure 66 is preferably used to provide tensile stress to an adjacent channel region, the composition thereof may be, for example, a bismuth phosphorus component (SiP) or a bismuth carbon component ( SiC), or a phosphorus-doped cerium carbon component or the like, but is not limited thereto.

Refer to Figure 7 for details. As shown in FIG. 7, another epitaxial process is performed to form another epitaxial layer on the surface of each epitaxial structure 66, for example, a cap layer 68 composed of a single crystal germanium or a polycrystalline germanium. During the epitaxial process, the cap layer 68 will continue to grow on the surface of each epitaxial structure 66 and gradually fill the space between the epitaxial structures 66 until the adjacent cap layer 68 merges. And the structure as shown in Fig. 7 is formed. In other words, in order to merge the cover layers 68, their respective thicknesses T1 must be at least 1/2 greater than the distance S. For example, when the distance S falls within the range of 10 nm to 20 nm, the thickness T1 of the cover layer 68 may fall between 6 nm and 11 nm, but the thickness may also be greater than 11 nm. This depends on the product requirements. As still shown in FIG. 7, the merged cover layer 68 will cover the surface of each of the epitaxial structures 66 and will generally have a periodic continuous concavo-convex surface pattern. The top portions 68a of the respective capping layers 68 may be substantially at the same height H2, or substantially on the same plane P, and the plane P may be substantially parallel to the main surface 10a of the substrate 10 or the insulating structure 20, but is not limited thereto.

Please refer to FIG. 8 , after forming the above epitaxial structure, optionally Subsequent semiconductor processes, such as metal gate replacement processes and contact structure processes. For the metal gate replacement process, the gate structure composed of polysilicon is replaced by a metal gate structure, and the process generally includes two cases of high dielectric constant front and high dielectric constant rear. For example, for a metal gate replacement process using a high dielectric constant post, the process may include: (1) depositing an interlevel dielectric layer 70 to surround the gate structure (not shown); 2) removing the gate structure to leave a trench (not shown); (3) forming a gate dielectric layer (not shown) to cover the sidewalls and bottom of the trench in a compliant manner; 4) forming a metal gate (not shown) to fill the trench, wherein the metal gate may include a barrier layer (not shown), a work function metal layer, and a low A resistive metal layer (not shown), but is not limited thereto.

Next, still refer to Fig. 8. After the metal gate replacement process is performed, the subsequent contact structure process can be continued to form a contact structure electrically connecting the epitaxial structure 66, such as the contact plug 74, and the epitaxial structure 66 is electrically connected to the subsequently formed external line. (not shown). As shown in FIG. 8, for example, the contact plug process can include forming at least one contact hole 72 in the interlayer dielectric layer 70 to exhibit a circular or elongated shape to expose the corresponding cap layer. 68 areas. Then, a barrier/adhesive layer (not shown), a seed layer (not shown), and a conductive layer (not shown) are formed in the contact hole 72 to cover the cap layer 68. The contact plug 74 is required. Wherein, the barrier/adhesive layer is conformally filled into the contact hole 72, and the conductive layer completely fills the contact hole 72.

It should be noted that in the above contact plug process, a metallization process can be performed to form a metal halide (see not shown) having better conductivity in the cap layer 68. For example, after forming the contact hole 72 and filling the conductive layer, a metal source layer (not shown) may be first filled into the contact hole 72, and then subjected to a rapid temperature annealing (RTA) process to cause the metal. The source layer and the cover layer 68 partially or completely react to form A metal telluride layer is followed by removal of the unreacted metal source layer to complete the illustrated germanium metal process. The contact plug process described above can then be continued to complete the desired structure. The metal source layer described above may include a metal material such as cobalt (Co), titanium (Ti), nickel (Ni), or platinum (Pt) or an alloy thereof, but is not limited thereto.

According to the above, the semiconductor device of the first preferred embodiment of the present invention is completed. Other variations of the above-described embodiments are further described below, and the following description is mainly for the sake of simplification of the description, and the details are not repeated. In addition, the same elements in the respective embodiments are denoted by the same reference numerals to facilitate the comparison between the embodiments.

According to a first variant embodiment of the invention, a semiconductor device having an epitaxial structure is also provided. However, the main difference between this variant embodiment and the first preferred embodiment described above is that the epitaxial structures have been merged with each other prior to forming the cap layer, rather than being independent of one another. In detail, as shown in FIG. 9, after performing an epitaxial process similar to that described in the first preferred embodiment, the epitaxial structures 66 located in the respective recesses 60 are partially merged with each other to form a continuous Epitaxial structure. Further, between the epitaxial structures 66, there may be an overlap O, or a connection, to physically connect the two adjacent epitaxial structures 66. In addition, the overlap portion O and the width W of each of the epitaxial structures 66 may have a proportional relationship. For example, the ratio of the two may be between 0.001 and 0.25, preferably between 0.001 and 0.05. At this ratio, even if two adjacent epitaxial structures 60 are somewhat merged, each epitaxial structure 66 can maintain its single crystal structure without causing excessive defect structures in the overlap O.

Following the reference to Figure 10. After completing the structure as described in FIG. 9, another epitaxial process as described in the first preferred embodiment may be continued to form another epitaxial The layer, for example, is a cap layer 68 composed of a single crystal germanium or a polycrystalline germanium. It should be noted that the cap layer 68 of the modified embodiment is a continuous layer on each epitaxial structure 66. Therefore, the thickness T1 is not limited to a specific value, and only needs to form a continuous layer. Just fine. Similarly, the cover layer 68 will have a surface pattern of periodic continuous relief, and the top 68a of the cover layer 68 will be substantially at the same height H2, or substantially on the same plane P, and the plane P will be substantially parallel. The main surface 10a of the substrate 10 or the insulating structure 20 is not limited thereto.

Further, according to a second variant embodiment of the present invention, a semiconductor device having an epitaxial structure is also provided. However, the main difference between the modified embodiment and the first preferred embodiment is that each of the epitaxial structures directly grows on the surface of each of the fin-shaped structures, that is, the fin-shaped structures do not have grooves therein. . In detail, referring to FIG. 11 , since the variation embodiment does not perform the process of etching the fin-shaped structure, after performing the epitaxial process similar to that described in the first preferred embodiment, each epitaxial structure 66 will directly contact and cover each of the fin structures 12, and each of the epitaxial structures 66 will have a distance S independently of each other. Thereafter, a further epitaxial layer, such as a cap layer 68 composed of a single crystal germanium or a polycrystalline germanium, may be formed on each of the epitaxial structures 66, such that adjacent capping layers 68 are merged to form an image as shown in FIG. The structure of the show. It should be noted that the epitaxial structures of the modified embodiment may also be slightly combined before the formation of the cap layer, so that the subsequent cap layer becomes a continuous film having a thickness of approximately uniform. Since the structure of this aspect is substantially similar to the first preferred embodiment described above, it will not be described herein.

It should be noted that the epitaxial structure in each of the above embodiments and the capping layer formed thereon are preferably disposed in the source/drain regions of the same conductivity type transistor. For example, the epitaxial structure of germanium and the capping layer thereon may be disposed in the P-type transistor structure, and it is at least in the source/drain region on one side of the gate structure.

In summary, various embodiments of the present invention provide a semiconductor device. In each semiconductor device, two adjacent epitaxial structures are separated or partially merged, and another epitaxial layer on each epitaxial structure fills the spacing between two adjacent epitaxial structures or is continuously distributed. On the surface of each epitaxial structure. With this structure, it is possible to prevent the defect structure from being present in each epitaxial structure or in the overlapping portion of the two adjacent epitaxial structures, thereby increasing the stress value that each epitaxial structure can provide, thereby improving the semiconductor device. efficacy.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Base

10a‧‧‧ surface

20‧‧‧Insulation structure

66‧‧‧ epitaxial structure

68‧‧‧矽 Cover

68a‧‧‧ top

H1‧‧‧ Height

H2‧‧‧ Height

P‧‧‧ plane

S‧‧‧ distance

T1‧‧‧ thickness

Claims (20)

A semiconductor device comprising: at least two fin structures disposed on a substrate; a gate structure covering the fin structures; at least two epitaxial structures disposed on one side of the gate structures, and each directly Contacting each of the fin structures, wherein the epitaxial structures are separated from each other; a cap layer covering the epitaxial structures at the same time; a dielectric layer covering the gate structure and the cap layer; and at least one A contact structure is disposed within the dielectric layer and directly contacts the cap layer. The semiconductor device of claim 1, further comprising at least two recesses, each of which is provided with one end of each of the fin structures, wherein each of the epitaxial structures fills the corresponding one of the recesses. The semiconductor device of claim 1, wherein the epitaxial structures each cover one end of each of the fin structures. The semiconductor device of claim 1, further comprising at least one insulating layer disposed between the epitaxial structures. The semiconductor device of claim 4, wherein the cap layer directly contacts the insulating layer between the epitaxial structures. The semiconductor device of claim 1, wherein each of the epitaxial structures comprises a low-doped epitaxial layer, a highly doped epitaxial layer, and an adhesive layer from bottom to top. The semiconductor device of claim 1, wherein the material of the epitaxial structures comprises bismuth, antimony or antimony carbon. The semiconductor device of claim 1, wherein each of the epitaxial structures comprises a top surface, and the top surfaces are substantially in the same plane. The semiconductor device of claim 1, wherein the cap layer has a contour of a concavo-convex. The semiconductor device according to claim 1, wherein the material of the cap layer is a single crystal germanium. A semiconductor device comprising: at least two fin structures disposed on a substrate; a gate structure covering the fin structures; at least two epitaxial structures disposed on one side of the gate structures, and each directly Contacting each of the fin structures, wherein the epitaxial structures have an overlap portion, and each of the epitaxial structures has a width, wherein a ratio of the overlap portion to the width is substantially between 0.001 and 0.25; The cover layer covers the epitaxial structure at the same time. The semiconductor device of claim 11, further comprising two recesses respectively disposed at one end of each of the fin structures, wherein each of the epitaxial structures fills the corresponding one of the recesses. The semiconductor device of claim 11, wherein the epitaxial structures each cover one end of each of the fin structures. The semiconductor device of claim 11, further comprising a space between the substrate and a corresponding epitaxial structure. The semiconductor device of claim 14, wherein the cover layer is filled in the space. The semiconductor device of claim 11, wherein each of the epitaxial structures comprises a low-doped epitaxial layer, a highly doped epitaxial layer, and an adhesive layer from bottom to top. The semiconductor device according to claim 11, wherein the material of each of the epitaxial structures comprises bismuth, antimony or antimony carbon. The semiconductor device of claim 11, wherein the cover layer has a contour of a concavo-convex. The semiconductor device according to claim 11, wherein the material of the cap layer is a single crystal germanium. The semiconductor device of claim 11, further comprising: a dielectric layer covering the gate structure and the cap layer; and at least one contact structure disposed in the dielectric layer and directly contacting the cap Floor.