TW201321876A - Pixel structure, active array substrate and liquid crystal display panel - Google Patents

Abstract

The invention discloses a pixel structure, an active array substrate and a liquid crystal display panel. The active array substrate includes a substrate, data lines, first gate lines, second gate lines, first pixel electrodes, second pixel electrodes and shielding electrodes. Each of the first pixel electrodes is electrically connected to one of the data lines and one of the second gate lines. Each of the second pixel electrodes is electrically connected to one of the data lines and one of the first gate lines. Each of the shielding electrodes has a connective segment and a plurality of branch segments. Each of the shielding electrodes is located between two adjacent data lines. Each connective segment is located between one of the first pixel electrodes and one of the second pixel electrodes. Each of the branch segments is located between one of the first pixel electrodes and one of the first gate lines, or between one of the second pixel electrodes and one of the second gate lines.

Description

Pixel structure, active array substrate and liquid crystal display panel

The present disclosure relates to a display panel, and more particularly to an active array substrate of a display panel and a pixel structure thereof.

With the development of display process technology, most of the digital display panels currently have the advantages of lightness, low cost, high efficiency, etc. Among them, the various components of the digital display panel (such as the drive circuit, the substrate, the connection line) are mostly highly integrated through various advanced processes. In order to achieve the best display at the minimum volume and lowest cost.

In order to achieve the above object, many manufacturing technologies of display devices have been developed. A conventional display panel needs to be provided with a large number of source drivers and gate drivers for vertical and horizontal directions. Picture driven. The half source driver (HSD) design doubles the number of gate lines so that a single data line (source line) can simultaneously correspond to two rows of adjacent pixels, thereby saving half of the source driver chips. . If further combined with the active on-board (GOA) design, the cost of the source drive wafer can be saved without increasing the cost of the gate drive wafer.

Please refer to FIG. 1 , which is a top plan view of an active array substrate 100 using a half source driving design in the prior art. As shown in Fig. 1, under the spatial arrangement of the half-source drive design, the upper and lower gate lines G1, G2 are respectively responsible for operating the pixel electrode P11 and the pixel electrode P12 on both sides of the data line D1. In the current pixel design, a parasitic capacitance is formed between the pixel electrode and the surrounding conductive line segment, for example, a pixel gate parasitic capacitance Cpg1 between the pixel electrode P11 and the gate line G2. The pixel gate parasitic capacitance Cpg2 between the pixel electrode P12 and the gate line G1 and the pixel side parasitic capacitance Cpp between the pixel electrode P12 and the pixel electrode P21, and the parasitic capacitance may make the voltage of the pixel electrode Bit distortion.

For example, if the actual circuit uses the pre-charge driving method to drive the two gate lines G1 and G2, when the gate line G2 of the pixel electrode P12 is turned off, the coupling of the pixel gate parasitic capacitance Cpg1 will be transmitted. The effect affects the pixel electrode P11, so that the pixel electrode P11 will be pulled by the additional gate line closing voltage, which causes the voltage levels of the pixel electrode P11 and the pixel electrode P12 to be different at the same common voltage. , resulting in a bright dark line in the vertical direction.

In another practical example, the pixel side parasitic capacitance Cpp will be present because no data line is provided between the pixel electrode P12 and the pixel electrode P21. Wherein, the pixel electrode P12 and the pixel electrode P21 are charged differently. If the pixel electrode P12 is first charged, when the pixel electrode P21 is subsequently charged, the coupling effect of the pixel-side parasitic capacitance Cpp is affected to affect the pixel electrode P12. The voltage level is generated, resulting in distortion, mixed color pictures or vertical bright lines.

In order to solve the above problems, the present invention discloses an active array substrate of a display panel and a pixel structure thereof. Wherein, the active array substrate is provided with a plurality of shielding electrodes, the shielding electrode has a connecting line segment and a branch line segment, and the connecting line segment is located between the two pixel electrodes for eliminating the pixel lateral parasitic capacitance therebetween, and the branch line segment is located in the pixel Between the electrode and the gate line, to eliminate the parasitic capacitance of the pixel gate between them. The active array substrate can further adopt a half-source driving design. Through the setting of the shielding electrodes, the adjacent pixel electrodes can be prevented from interfering with each other, and problems such as distortion, mixed color picture or vertical bright line can be avoided.

One aspect of the present disclosure is to provide a pixel structure disposed on a substrate, the pixel structure including a first data line, a second data line, a first gate line, a second gate line, and a first A pixel electrode, a second pixel electrode, and a mask electrode. The first data line and the second data line are disposed in parallel on the substrate. The first gate line and the second gate line are disposed on the substrate in parallel, and intersect the first data line and the second data line to define a first pixel area and a second pixel area. Between a data line and the second data line, and between the first gate line and the second gate line. The first pixel electrode is disposed on the substrate of the first pixel region, and the first pixel electrode is electrically connected to the first data line and the second gate line. The second pixel electrode is disposed on the substrate of the second pixel region, and the second pixel electrode is electrically connected to the second data line and the first gate line. The shielding electrode is disposed on the substrate, the shielding electrode has a connecting line segment, a first branch line segment and a second branch line segment, the connecting line segment is located between the first pixel electrode and the second pixel electrode, the first A branch line segment is located between the first pixel electrode and the first gate line, and the second branch line segment is located between the second pixel electrode and the second gate line.

According to an embodiment of the present disclosure, the first pixel area is adjacent to the first data line, and the second pixel area is adjacent to the second data line.

According to an embodiment of the present disclosure, the pixel structure further includes a first active device having a first gate, a first source, and a first drain. The first gate is electrically The first gate is electrically connected to the first data line, and the first drain is electrically connected to the first pixel electrode. In this embodiment, the pixel structure further includes a first extension electrode electrically connected to the first drain and overlapping with a second protrusion of the second gate line.

According to an embodiment of the present disclosure, the pixel structure further includes a second active device having a second gate, a second source, and a second drain. The second gate is electrically The first gate line is electrically connected to the second gate line, and the second source is electrically connected to the second pixel electrode. In this embodiment, the pixel structure further includes a second extension electrode electrically connected to the second drain and overlapping with a first protrusion of the first gate line.

According to an embodiment of the present disclosure, the pixel structure further includes a common electrode disposed on the substrate and overlapping the edge portion of the first pixel electrode and the second pixel electrode.

In accordance with an embodiment of the present disclosure, the common electrode and the first gate line and the second gate line are formed of the same layer of material.

According to an embodiment of the present disclosure, the shielding electrode is composed of the same material layer and the first data line and the second data line.

According to an embodiment of the present disclosure, the first branch line segment of the shielding electrode shields an electric field of the first gate line from the first pixel electrode, and the second branch line segment shielding portion of the shielding electrode And dividing the electric field of the second gate line to the second pixel electrode.

According to an embodiment of the present disclosure, a first pulse signal and a second pulse signal are respectively transmitted to the first gate line and the second gate line, wherein the first pulse signal and the second pulse signal are respectively Some clocks overlap.

Another aspect of the present disclosure is to provide an active array substrate including a first substrate, a plurality of data lines, a plurality of first gate lines and a plurality of second gate lines, and a plurality of first pixel electrodes a plurality of second pixel electrodes and a plurality of shielding electrodes. A plurality of data lines are disposed in parallel on the first substrate. A plurality of first gate lines and a plurality of second gate lines are alternately arranged in parallel on the first substrate, intersecting the data lines, and defining a plurality of first pixel regions and a plurality of second pixel regions Located between two adjacent data lines and adjacent between the first gate line and the second gate line. Each of the first pixel electrodes is disposed on the first substrate of the first pixel region, and each of the first pixel electrodes is electrically connected to the data line and the second gate line. Each of the second pixel electrodes is disposed on the first substrate of the second pixel region, and each of the second pixel electrodes is electrically connected to the data line and the first gate line. A plurality of shielding electrodes are disposed on the first substrate, each of the shielding electrodes having a connecting line segment, a plurality of first branch line segments and a plurality of second branch line segments, each shielding electrode being located between two adjacent data lines And between the first pixel electrodes and the second pixel electrodes, each of the first branch line segments is correspondingly located between the first pixel electrode and the first gate line, each of the The second branch line segment is correspondingly located between the second pixel electrode and the second gate line.

Another aspect of the present disclosure is to provide a liquid crystal display panel including a first substrate, a plurality of data lines, a plurality of first gate lines and a plurality of second gate lines, and a plurality of first pixel electrodes a plurality of second pixel electrodes, a plurality of shielding electrodes, a second substrate, and a liquid crystal layer. A plurality of data lines are disposed in parallel on the first substrate. A plurality of first gate lines and a plurality of second gate lines are alternately arranged in parallel on the first substrate, intersecting the data lines, and defining a plurality of first pixel regions and a plurality of second pixel regions Located between two adjacent data lines and adjacent between the first gate line and the second gate line. Each of the first pixel electrodes is disposed on the first substrate of the first pixel region, and each of the first pixel electrodes is electrically connected to the data line and the second gate line. Each of the second pixel electrodes is disposed on the first substrate of the second pixel region, and each of the second pixel electrodes is electrically connected to the data line and the first gate line. A plurality of shielding electrodes are disposed on the first substrate, each of the shielding electrodes having a connecting line segment, a plurality of first branch line segments and a plurality of second branch line segments, each shielding electrode being located between two adjacent data lines And between the first pixel electrodes and the second pixel electrodes, each of the first branch line segments is correspondingly located between the first pixel electrode and the first gate line, each of the The second branch line segment is correspondingly located between the second pixel electrode and the second gate line. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate.

Please refer to FIG. 2, which is a top plan view of an active array substrate 300 according to an embodiment of the invention. The active array substrate 300 includes a substrate 302, a plurality of data lines, a plurality of first gate lines and a plurality of second gate lines, a plurality of pixel electrodes, and a plurality of shielding electrodes. A schematic diagram of a partial embodiment of the active array substrate 300 illustrated in FIG. 2 to illustrate the pixel and driving circuit layout of the active array substrate 300, wherein three data lines D1, D2, D3, and three lines are exemplarily illustrated. a gate line G1, G3, G5, three second gate lines G2, G4, G6, eighteen groups of pixel electrodes (arranged in a 3*6 array manner) and two shielding electrodes S1, S2, but the present invention Not limited to this, the general knowledge in the field can be appropriately changed according to the needs, and will not be described here.

The present invention also provides that the display resolution corresponding to the active array substrate 300 is set to a different number of pixel electrodes, and the corresponding relationship between the corresponding number of driving lines (data lines and gate lines) and the shielding electrodes is set. Similar to Fig. 2, it can be derived from the configuration of Fig. 2, and it is also within the scope of the present invention.

In FIG. 2, a plurality of data lines D1, D2, D3, and the like are disposed in parallel on the substrate 302. A plurality of first gate lines G1, G3, G5 and the like are alternately arranged in parallel with the plurality of second gate lines G2, G4, G6 and the like on the substrate 302, and intersect with the data lines D1, D2, D3.

As shown in FIG. 2, the active array substrate 300 of the present embodiment adopts a half source driver (HSD) design. Compared with the conventional display driving architecture, the active array substrate 300 halved the number of data lines, for example, for example. For the pixel electrodes P11, P12, P21, P22, P31, and P32 of the same row, the first gate line G1 and the second gate line G2 are disposed on the upper and lower sides, and each pixel has two pixel electrodes. The gate line corresponds to it. A single data line (source line) can simultaneously correspond to two rows of adjacent pixels, thereby saving half of the source drive chips. For example, the upper and lower first and second gate lines G1, G2 are respectively responsible for operating the pixel electrode P11 and the pixel electrode P12 on both sides of the data line D1. Therefore, for the entire active array substrate 300, the number of data lines can be approximately half of the number of pixel electrodes, whereby the power and cost of the source driving wafer can be saved.

However, when the number of data lines in the half-source drive design becomes half, the switching circuit corresponding to each pixel electrode has its gate turned on half time, thereby halving the charging time of the pixel electrode. On the resolution panel, in order to ensure that the active array substrate 300 can have sufficient charging time to raise the pixel electrode to the correct voltage level, in this embodiment, the pre-charge can be further used in the gate line. The way to drive. For example, please refer to FIG. 3, which is a schematic diagram showing the relationship between pulse signals of two adjacent gate lines according to an embodiment of the present invention. As shown in FIG. 2, the first and second gates are shown. The first pulse signal Sp1 and the second pulse signal Sp2 transmitted by the lines G1 and G2 respectively operate the pixel electrode P11 and the pixel electrode P12 on both sides of the data line D1, wherein the first pulse signal transmitted by the first gate line G1 Sp1 and the second pulse signal Sp2 transmitted by the second gate line G2 overlap the partial clocks of the conduction interval (as shown in FIG. 3), that is, when the first gate line G1 is still in the high level state, The second gate line G2 has started to charge and switches to the high level state.

As shown in Fig. 2, due to the half-source drive design, the data lines D1, D2, D3, etc. are arranged at intervals, that is, one data line is arranged for each two columns of pixel electrodes. However, a parasitic capacitance will be formed between the pixel electrode and the surrounding conductive line segments, for example, a pixel gate parasitic capacitance (Cpg1) between the pixel electrode P11 and the gate line G2, and a pixel electrode P12 and gate. The pixel gate parasitic capacitance (Cpg2) between the polar line G1 and the pixel lateral capacitance (Cpp) between the pixel electrode P12 and the pixel electrode P21 (refer to FIG. 1), and the above parasitic capacitance may make The voltage level distortion of the pixel electrode, especially when the pre-charged driving mode is used, will make the adjacent pixel electrodes interfere with each other more seriously.

In this embodiment, two pixel electrodes are disposed between each two data lines. In this embodiment, a shielding electrode, such as a shielding electrode S1, S2, etc., is disposed between the two pixel electrodes, wherein the shielding electrode S1 is disposed. The main setting direction of S2 is substantially the same as the data line, and the number is approximately close to the data line. For example, two pixel electrodes P12 and P21 are disposed between the data lines D1 and D2, and the shielding electrode S1 is further disposed between the pixel electrodes P12 and P21. The shielding electrode in this embodiment can be used to eliminate the aforementioned parasitic capacitance.

The specific detailed structure of the active array substrate 300 in the present embodiment will be described below by using the local pixel structure 304 on the active array substrate 300. Please refer to FIG. 4, which is a partially enlarged schematic view of a pixel structure 304 in accordance with an embodiment of the present invention.

As shown in FIG. 4, the pixel structure 304 is disposed on the substrate 302, for example, between the data line D1, the data line D2, the first gate line G1, and the second gate line G2. The first pixel area 304a and the second pixel area 304b are defined by the data line D1, the data line D2 and the parallel first gate line G1 and the second gate line G2 arranged in parallel, wherein the first pixel area 304a may be located on the left adjacent data line D1, and the second pixel area 304b may be located on the right adjacent data line D2. The horizontal position of the first pixel area 304a and the right second pixel area 304b is preferably located between the data line D1 and the data line D2, and the vertical position of the first pixel area 304a and the right second pixel area 304b are compared. Preferably, it is located between the first gate line G1 and the second gate line G2.

The pixel electrode P12 may be disposed on the substrate 302 of the first pixel region 304a, and the pixel electrode P21 may be disposed on the substrate 302 of the second pixel region 304b. The pixel structure 304 further includes a first active component 320a and a second active component 320b.

The pixel electrode P12 is electrically connected to the data line D1 and the second gate line G2 through the first active device 320a, and the pixel electrode P21 is electrically connected to the data line D2 and the first gate line through the second active device 320b. G1.

In this embodiment, the pixel structure 304 further includes a common electrode 360. The common electrode 360 is disposed on the substrate 302. The common electrode 360 overlaps the edge of the pixel electrode P12 and the pixel electrode P21, thereby forming a storage capacitor.

Please refer to FIG. 5, FIG. 6 and FIG. 7 together, wherein FIG. 5 is a cross-sectional view of the pixel structure 304 in FIG. 4 along the section line AA, and FIG. 6 is a diagram showing the pixel structure in FIG. 304 is a schematic cross-sectional view along the section line BB, and FIG. 7 is a schematic cross-sectional view of the pixel structure 304 along the section line CC in FIG.

As shown in FIG. 4 and FIG. 5, the first active device 320a of the present embodiment has a first gate 324a, a first source 322a and a first drain 326a, which are respectively disposed on the substrate 302, respectively. A gate 324a is electrically connected to the second gate line G2, the first source 322a is electrically connected to the data line D1, and the first drain 326a is electrically connected to the pixel electrode P12. In this embodiment, the first drain 326a is provided with a through hole 328a (or a contact window) for electrically connecting the first drain 326a and the pixel electrode P12 through the through hole 328a.

In addition, as shown in FIG. 4, the first extension electrode 330a extends from the right side of the first drain 326a of the pixel structure 304, the first extension electrode 330a is electrically connected to the first drain electrode 326a, and the first extension electrode 330a It overlaps with the protruding portion 332a of the second gate line G2. By this design, the parasitic capacitance (Cgd) between the first drain 326a and the second gate line G2 can be kept constant, and the pixel flicker can be avoided by changing the parasitic capacitance due to the process offset.

As shown in FIG. 4, the second active device 320b in this embodiment has a second gate 324b, a second source 322b and a second drain 326b, and the second gate 324b is electrically connected to the first gate line G1. The second source 322b can be electrically connected to the data line D2, and the second drain 326b can be electrically connected to the pixel electrode P21. In this embodiment, the second drain 326b can be provided with a through hole 328b for electrically connecting the second drain 326b and the pixel electrode P21 through the through hole 328b. The cross-sectional structure of the second active component 320b is substantially symmetric with the first active component 320a, and reference may be made to the cross-sectional schematic relationship of FIG.

In addition, as shown in FIG. 4, the second extension electrode 330a extends from the left side of the second drain 326a of the pixel structure 304, the second extension electrode 330a is electrically connected to the second drain electrode 326a, and the second extension electrode 330a It overlaps with the protruding portion 332b of the first gate line G1.

The shielding electrode S1 is disposed on the substrate 302. The shielding electrode S1 has a connecting line segment 340, a first branching line segment 342 and a second branching line segment 344. The connecting line segment 340 extends substantially in a vertical direction and can be located at the pixel electrode P12 and the pixel electrode P21. The first branch line segment 342 is located between the pixel electrode P12 and the first gate line G1, and the second branch line segment 344 is located between the pixel electrode P21 and the second gate line G2. The shielding electrode S1 and the data lines D1, D2, D3 and the like may be the same layer or different layers, and are preferably made of the same layer and composed of the same material and process, thereby reducing the manufacturing cost.

FIG. 6 is a schematic cross-sectional view showing the first branch line segment 342 between the pixel electrode P12 and the first gate line G1. As shown in FIGS. 4 and 6, the horizontal position and the vertical position of the first branch line segment 342 of the shield electrode S1 are located between the pixel electrode P12 and the first gate line G1. The shielding electrode S1 is preferably made of a conductive metal material such as copper, aluminum, silver, gold, molybdenum, titanium, chromium, tungsten or the like, or an alloy thereof and a laminate. In a variant embodiment, the shielding electrode S1 may also be made of a transparent conductive material such as indium tin oxide or the like. Thereby, the first branch line segment 342 shields the electric field of the majority of the first gate line G1 from the pixel electrode P12. That is to say, the first branch line segment 342 can serve as a conductive shield between the first gate line G1 and the pixel electrode P12, reducing the pixel gate parasitic capacitance between the two.

Similarly, the second branch line segment 344 is located between the pixel electrode P21 and the second gate line G2 and has a corresponding similar cross-sectional structure, and the second branch line segment 344 of the shielding electrode S1 shields part of the second gate line G2. The electric field to the pixel electrode P21. The second branch line segment 344 can serve as a conductive shield between the second gate line G2 and the pixel electrode P21, reducing the pixel gate parasitic capacitance between the two.

FIG. 7 is a schematic diagram showing the cross-sectional position of the connecting line segment 340 between the pixel electrode P12 and the pixel electrode P21. As shown in FIGS. 4 and 7, the horizontal position of the connecting line segment 340 is located between the pixel electrode P12 and the pixel electrode P21. The shielding electrode S1 may be made of a conductive metal material, whereby the connecting line segment 340 is shielded. The mutual electric field between most of the pixel electrode P12 and the pixel electrode P21.

It should be noted that, in the above FIG. 5 to FIG. 7 , the common electrode 360 and the first gate line G1 and the second gate line G2 are composed of the same layer of material in the embodiment, and the practical application is common. The electrode 360 and the first gate line G1 and the second gate line G2 may be the same metal material layer (for example, the M1 metal layer) in the process.

On the other hand, in this embodiment, the shielding electrode S1 and the data line D1 and the data line D2 may be composed of the same layer of material. In practice, the shielding electrode S1 and the data line D1 and the data line D2 may be the same in the process. A layer of metallic material (eg, an M2 metal layer).

In FIG. 4, the pixel structure 304 is described by the range of the data line D1, the data line D2, the first gate line G1, the second gate line G2, the pixel electrode P12, and the pixel electrode P21. However, 2 The internal arrangement of the pixel structure 304 at other positions on the active array substrate 300 in the figure can be similar to that of FIG. 4, and can be analogously repeated from the configuration of FIG. 4, and is also within the scope of implementation of the present invention. In another embodiment, the pixel structure 304 disclosed in FIG. 4 can also be applied to various active array substrates or display devices, and is not limited to the embodiment depicted in FIG.

Please refer to FIG. 8 , which is a cross-sectional view showing a liquid crystal display panel 500 according to another embodiment of the present invention. As shown in FIG. 8 , the present invention also provides a liquid crystal display panel 500 including a first substrate 502 , a second substrate 506 , and a liquid crystal layer 508 . The first substrate 502 is, for example, an active device array substrate, and the second substrate 506 is, for example, a color filter substrate. The first substrate 502 is disposed opposite to the second substrate 506 , and the liquid crystal layer 508 is disposed between the first substrate 502 and the second substrate 506 . The first substrate 502 can be provided with a plurality of pixel structures. For the detailed structure of the first substrate 502 and the pixel structure disposed above the embodiment, reference may be made to the pixel structure 300 of the active array substrate 300 shown in FIGS. 2 and 4 in the previous embodiment. The structure and details are roughly similar, and will not be further described here.

The first substrate 502 may be an active device array substrate. As shown in FIG. 8 and referring to FIGS. 2 and 4, the first substrate 502 is provided with a plurality of first gate lines G1, G3, and the like. The second gate lines G2 and G4 and the like, the plurality of data lines D1 to D3, and the like, the plurality of first pixel electrodes, the plurality of second pixel electrodes, and the plurality of shielding electrodes S1 and S2. A plurality of data lines D1 to D3 and the like are disposed in parallel on the first substrate 502, and a plurality of first gate lines G1 and G3 and a plurality of second gate lines G2 and G4 are alternately arranged in parallel on the first substrate 502. Upper, intersecting with the data lines D1~D3, etc., defining a plurality of first pixel regions and a plurality of second pixel regions, located between two adjacent data lines, and adjacent to the first Between a gate line and the second gate line. Each of the first pixel electrodes P12 and the like is disposed on the first substrate 502 of the first pixel region, and each of the first pixel electrodes P12 and the like is electrically connected to the data line D1 and the like. Two gate lines G2 and so on. Each of the second pixel electrodes P21 and the like is disposed on the first substrate 502 of the second pixel region, and each of the second pixel electrodes P21 and the like is electrically connected to the data line D2 and the like. A gate line G1 and so on. A plurality of shielding electrodes S1 and the like are disposed on the first substrate 502. Each of the shielding electrodes S1 and the like has a connecting line segment 340, a plurality of first branch line segments 342 and a plurality of second branch line segments 344, and each shielding electrode is located at a phase Between the two adjacent data lines, and each of the connecting line segments 340 is located between the first pixel electrodes P12 and the second pixel electrodes P21, and each of the first branch line segments 342 is correspondingly located at the first Between a pixel electrode P12 and the first gate line G1, each of the second branch line segments 344 is correspondingly located between the second pixel electrode P21 and the second gate line G2.

The detailed structure of the first substrate 502 and the upper pixel structure 504 thereof is substantially similar to the active array substrate 300 and the pixel structure 304 in the previous embodiment, and the details of the previous embodiment and the second to seventh figures can be referred to. I will not repeat them here.

In summary, the present invention discloses an active array substrate of a display panel and a pixel structure thereof, which are provided with a plurality of shielding electrodes, each shielding electrode has a connecting line segment and a branch line segment, and the connecting line segment is located between the two pixel electrodes In order to eliminate the lateral parasitic capacitance of the pixel, the branch line segment is located between the pixel electrode and the gate line to eliminate the parasitic capacitance of the pixel gate between them. The active array substrate can further adopt a half-source driving design. Through the setting of the shielding electrodes, the adjacent pixel electrodes can be prevented from interfering with each other, and problems such as distortion, mixed color picture or vertical bright line can be avoided.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

100,300. . . Active array substrate

500. . . LCD panel

302, 502, 504. . . Substrate

D1, D2, D3. . . Data line

G1, G3, G5. . . First gate line

G2, G4, G6. . . Second gate line

P11~P36. . . Pixel electrode

Cpp. . . Pixel lateral parasitic capacitance

Cpg1, Cpg2. . . Pseudo gate parasitic capacitance

S1, S2. . . Masking electrode

Sp1. . . First pulse signal

Sp2. . . Second pulse signal

304,504. . . Pixel structure

304a. . . First pixel area

304b. . . Second pixel area

320a. . . First active component

322a. . . First source

324a. . . First gate

326a. . . First bungee

328a, 328b. . . Through hole

330a. . . First extension electrode

332a, 332b. . . Protruding

320b. . . Second active component

322b. . . Second source

324b. . . Second gate

326b. . . Second bungee

330b. . . Second extension electrode

340. . . Connecting line segment

342. . . First branch line segment

344. . . Second branch line segment

360. . . Common electrode

508. . . Liquid crystal layer

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood.

1 is a schematic top plan view of an active array substrate using a half source driving design in the prior art;

2 is a top plan view of an active array substrate according to an embodiment of the invention;

3 is a schematic diagram showing the relationship of pulse signals of two adjacent gate lines in an embodiment of the present invention;

4 is a partially enlarged schematic view showing a pixel structure according to an embodiment of the present invention;

5, 6 and 7 respectively show cross-sectional views of the pixel structure in Fig. 4 along section line A-A, section line B-B and section line C-C;

FIG. 8 is a cross-sectional view showing a liquid crystal display panel according to another embodiment of the present invention.

302. . . Substrate

D1, D2. . . Data line

G1. . . First gate line

G2. . . Second gate line

P12, P21. . . Pixel electrode

S1. . . Masking electrode

304. . . Pixel structure

304a. . . First pixel area

304b. . . Second pixel area

320a. . . First active component

322a. . . First source

324a. . . First gate

326a. . . First bungee

328a, 328b. . . Through hole

330a. . . First extension electrode

332a, 332b. . . Protruding

320b. . . Second active component

322b. . . Second source

324b. . . Second gate

326b. . . Second bungee

330b. . . Second extension electrode

340. . . Connecting line segment

342. . . First branch line segment

344. . . Second branch line segment

360. . . Common electrode

Claims (13)

A pixel structure is disposed on a substrate, including: a first data line and a second data line disposed in parallel on the substrate; a first gate line and a second gate line are disposed in parallel a first pixel region and a second pixel region are defined on the substrate, and the first data line and the second data line are defined between the first data line and the second data line, and the first Between a gate line and the second gate line; a first pixel electrode disposed on the substrate of the first pixel region, the first pixel electrode electrically connecting the first data line and the a second gate electrode; a second pixel electrode disposed on the substrate of the second pixel region, the second pixel electrode electrically connecting the second data line and the first gate line; and a The shielding electrode is disposed on the substrate, the shielding electrode has a connecting line segment, a first branching line segment and a second branching line segment, the connecting line segment is located between the first pixel electrode and the second pixel electrode, a first branch line segment is located between the first pixel electrode and the first gate line, and the second branch line segment Between the second pixel electrode and the second gate line. The pixel structure of claim 1, wherein the first pixel region is adjacent to the first data line, and the second pixel region is adjacent to the second data line. The pixel structure of claim 1, further comprising a first active device, the first active device having a first gate, a first source and a first drain, the first gate electrical Connecting the second gate line, the first source is electrically connected to the first data line, and the first drain is electrically connected to the first pixel electrode. The pixel structure of claim 3, further comprising a first extension electrode electrically connected to the first drain and overlapping with a second protrusion of the second gate line. The pixel structure of claim 1, further comprising a second active device, the second active device having a second gate, a second source and a second drain, the second gate electrical Connecting the first gate line, the second source is electrically connected to the second data line, and the second drain is electrically connected to the second pixel electrode. The pixel structure of claim 5, further comprising a second extension electrode electrically connected to the second drain and overlapping with a first protrusion of the first gate line. The pixel structure of claim 1, further comprising a common electrode disposed on the substrate and overlapping the edge portion of the first pixel electrode and the second pixel electrode. The pixel structure of claim 1, wherein the common electrode and the first gate line and the second gate line are formed of the same layer of material. The pixel structure of claim 1, wherein the shielding electrode is formed of the same material layer as the first data line and the second data line. The pixel structure of claim 1, wherein the first branch line segment of the shielding electrode shields an electric field of the first gate line from the first pixel electrode, and the second branch line segment of the shielding electrode Blocking an electric field of the second gate line to the second pixel electrode. The pixel structure of claim 1, wherein the first pulse signal and the second pulse signal are respectively transmitted to the first gate line and the second gate line, wherein the first pulse signal and the second pulse signal are respectively The pulse signal partially overlaps the clock. An active array substrate includes: a first substrate; a plurality of data lines disposed in parallel on the first substrate; and a plurality of first gate lines and a plurality of second gate lines arranged alternately in parallel at the first On the substrate, intersecting the data lines, defining a plurality of first pixel regions and a plurality of second pixel regions, located between two adjacent data lines, and adjacent to the first gate Between the line and the second gate line; a plurality of first pixel electrodes, each of the first pixel electrodes being respectively disposed on the first substrate of the first pixel region, and each of the first pixels The electrode is electrically connected to the data line and the second gate line correspondingly; the plurality of second pixel electrodes, each of the second pixel electrodes is respectively disposed on the first substrate of the second pixel region, and each a second pixel electrode correspondingly electrically connecting the data line and the first gate line; and a plurality of shielding electrodes disposed on the first substrate, each of the shielding electrodes having a connecting line segment and a plurality of a branch line segment and a plurality of second branch line segments, each shielding electrode being located between two adjacent data lines, Each of the connecting line segments is located between the first pixel electrodes and the second pixel electrodes, and each of the first branch line segments is correspondingly located between the first pixel electrode and the first gate line. Each of the second branch line segments is correspondingly located between the second pixel electrode and the second gate line. A liquid crystal display panel comprising: a first substrate; a plurality of data lines disposed in parallel on the first substrate; a plurality of first gate lines and a plurality of second gate lines alternately arranged in parallel at the first On the substrate, intersecting the data lines, defining a plurality of first pixel regions and a plurality of second pixel regions, located between two adjacent data lines, and adjacent to the first gate Between the line and the second gate line; a plurality of first pixel electrodes, each of the first pixel electrodes being respectively disposed on the first substrate of the first pixel region, and each of the first pixels The electrode is electrically connected to the data line and the second gate line correspondingly; the plurality of second pixel electrodes, each of the second pixel electrodes is respectively disposed on the first substrate of the second pixel region, and each a second pixel electrode is electrically connected to the data line and the first gate line; a plurality of shielding electrodes are disposed on the first substrate, each of the shielding electrodes has a connecting line segment and a plurality of first a branch line segment and a plurality of second branch line segments, each of the shielding electrodes being located between adjacent two data lines, and each The connecting line segment is located between the first pixel electrode and the second pixel electrodes, and each of the first branch line segments is correspondingly located between the first pixel electrode and the first gate line, and each The second branch line segment is correspondingly located between the second pixel electrode and the second gate line; a second substrate is disposed opposite to the first substrate; and a liquid crystal layer is disposed on the first substrate and the Between the second substrates.