CN114355684A - Array substrate, manufacturing method and display panel - Google Patents
Array substrate, manufacturing method and display panel Download PDFInfo
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- CN114355684A CN114355684A CN202111603071.7A CN202111603071A CN114355684A CN 114355684 A CN114355684 A CN 114355684A CN 202111603071 A CN202111603071 A CN 202111603071A CN 114355684 A CN114355684 A CN 114355684A
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- 239000000758 substrate Substances 0.000 title claims abstract description 140
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004973 liquid crystal related substance Substances 0.000 claims description 15
- 230000000149 penetrating effect Effects 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 abstract description 22
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- 238000003825 pressing Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 15
- 239000010408 film Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 230000002411 adverse Effects 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
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Abstract
The application is applicable to the technical field of display, and provides an array substrate, a manufacturing method and a display panel, wherein the array substrate comprises a substrate, a grid electrode and a common electrode, wherein the grid electrode and the common electrode are arranged on the substrate; the shielding electrode is different from the grid electrode and the common electrode and has the same potential as the common electrode, and at least one part of the projection of the shielding electrode on the substrate is positioned in the gap between the grid electrode and the common electrode; the shielding electrode can effectively avoid light leakage at a gap between the grid electrode and the common electrode, improve the problem of uneven pressing and ensure that the display panel has a good display effect; meanwhile, the width of the black matrix on the color film substrate for shielding the gap can be set smaller, which is beneficial to ensuring high aperture opening ratio.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display panel.
Background
The thin film transistor liquid crystal display has the advantages of low radiation, small volume, low energy consumption and the like, and is widely applied to various electronic information products. In the current VA (Vertical Alignment) mode display screen, the liquid crystal at the gate and data line positions may be disordered and cause light leakage around the gate and data line, in order to prevent the light leakage, a BM (Black Matrix) is designed on the opposite color film substrate to perform shading treatment.
Disclosure of Invention
An object of the embodiments of the present application is to provide an array substrate, which includes a shielding electrode disposed in a different layer from a gate electrode and a common electrode but maintaining the same potential as the common electrode, and at least a portion of a projection of the shielding electrode on a substrate is located in a gap between the gate electrode and the common electrode, so as to solve a technical problem that an existing display panel is prone to uneven pressing at the gap between the gate electrode and the common electrode when pressed obliquely.
The embodiment of the present application is implemented as follows, an array substrate, including:
a substrate base plate; and
the grid electrode and the common electrode are arranged on the substrate base plate;
the array substrate further includes:
and the shielding electrode is different from the grid electrode and the common electrode and has the same potential as the common electrode, and at least one part of the projection of the shielding electrode on the substrate is positioned in the gap between the grid electrode and the common electrode.
In one embodiment, the array substrate further includes a first insulating layer disposed on the gate electrode and the common electrode, and a source electrode and a drain electrode disposed on the first insulating layer, a first via hole penetrating through the first insulating layer to the common electrode is disposed on the first insulating layer, the shielding electrode is disposed on the first insulating layer and on the same layer as the source electrode and the drain electrode, and the shielding electrode is connected to the common electrode through the first via hole.
In one embodiment, the array substrate further includes a first insulating layer disposed on the gate and the common electrode, a source and a drain disposed on the first insulating layer, a second insulating layer disposed on the source and the drain, and a pixel electrode disposed on the second insulating layer, a first via hole penetrating through the first insulating layer to the common electrode is disposed on the first insulating layer, a second via hole communicating with the first via hole is disposed on the second insulating layer, the shielding electrode is disposed on the second insulating layer and on the same layer as the pixel electrode, and the shielding electrode is connected to the common electrode through the first via hole and the second via hole.
In one embodiment, the spacing between the shield electrode and the pixel electrode is greater than or equal to 2.5 microns.
In one embodiment, the second insulating layer is a passivation layer or a color resist layer.
In one embodiment, the substrate base plate is further provided with a plurality of gate lines, each gate line is parallel to and arranged at intervals, and the pixel electrode is arranged on one side of each gate line; the common electrode surrounds the periphery of the pixel electrode; the shielding electrodes are arranged between the other pixel electrodes and the two gate lines on the two sides of the pixel electrodes except the last pixel electrode.
In one embodiment, a projection of the shielding electrode on the substrate base plate is connected with or spaced from an edge of the gate electrode close to the common electrode.
In one embodiment, a projection of the shielding electrode on the substrate base plate is at least partially overlapped with, spaced from or connected with an edge of the common electrode close to the grid electrode.
Another objective of the present application is to provide a method for manufacturing an array substrate, including:
providing a substrate, and forming a grid electrode and a common electrode on the substrate;
forming a first insulating layer on the gate electrode and the common electrode;
forming an active layer, a source electrode and a drain electrode on the first insulating layer;
forming a second insulating layer on the source electrode and the drain electrode, and forming a first through hole penetrating to the drain electrode on the second insulating layer; and
forming a pixel electrode on the second insulating layer, the pixel electrode being connected to the drain electrode via the first via hole;
the manufacturing method of the array substrate further comprises the following steps:
forming a shielding electrode on the same layer as the drain electrode on the first insulating layer, or forming a shielding electrode on the same layer as the pixel electrode on the second insulating layer; the shielding electrode and the common electrode are in the same potential, and at least one part of the projection of the shielding electrode on the substrate base plate is positioned in the gap between the grid electrode and the common electrode.
Another objective of the embodiments of the present invention is to provide a display panel, which includes the array substrate, a color filter substrate spaced from and facing the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
The array substrate, the manufacturing method and the display panel provided by the embodiment of the application have the beneficial effects that:
according to the array substrate provided by the embodiment of the application, the shielding electrode which keeps the same potential with the common electrode is arranged, at least one part of the projection of the shielding electrode on the substrate is used for covering the gap between the grid electrode and the common electrode, and liquid crystal molecules corresponding to the shielding electrode cannot deflect, so that light leakage at the gap between the grid electrode and the common electrode can be avoided, even if a black matrix on the color film substrate is staggered and does not completely shield the gap when the shielding electrode is pressed obliquely from one side of the color film substrate, the light leakage can be effectively avoided by the shielding electrode, further, the push mura problem is improved, and the display panel is ensured to have a good display effect; meanwhile, the width of the black matrix on the color film substrate for shielding the gap can be set smaller, and the array substrate is applied to the display panel, so that the high aperture opening ratio of the display panel is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic plan view of an array substrate provided in an embodiment of the present application;
FIG. 2 is an enlarged view at B in FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line A-A of FIG. 1;
FIG. 4 is a schematic view of another cross-sectional structure taken along line A-A of FIG. 1;
fig. 5 is a flowchart illustrating a step of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 6 is a flowchart illustrating another step of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present application.
The designations in the figures mean:
400-display panel, 300-color film substrate, 3001-second substrate, 3002-black matrix, 3003-second common electrode; 200-a liquid crystal layer;
100-an array substrate; 10-a thin film transistor; 11-a first substrate base plate; 12-a gate; 13-a gate line;
14-a first common electrode; 15-a first insulating layer, 150-a second via;
16-an active layer; 17-a source electrode; 18-a drain electrode; 19-a data line;
20-a second insulating layer, 201-a first via, 202-a third via;
21-a pixel electrode; 22-shielding electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to or disposed on the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the patent. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.
Referring to fig. 1 and fig. 2, an embodiment of the present invention first provides an array substrate 100, which specifically includes: a first substrate 11, a gate electrode 12 and a first common electrode 14 (for clarity of illustration, the first common electrode 14 in fig. 1 and 2 is a range shown by a dotted line) provided on the first substrate 11, a first insulating layer 15 provided on the first common electrode 14, an active layer 16 provided on the first insulating layer 15, a source electrode 17 and a drain electrode 18 provided on the active layer 16, a second insulating layer 20 provided on the source electrode 17 and the drain electrode 18, and a pixel electrode 21 provided on the second insulating layer 20. A thin film transistor 10 is formed of a gate electrode 12, an active layer 16, a source electrode 17 and a drain electrode 18.
The gate electrode 12 and the first common electrode 14 are disposed in the same layer and formed by the same photo-masking process. The gate electrode 12 and the first common electrode 14 are spaced apart from each other by a different potential.
In this embodiment, as shown in fig. 1 and 3, the array substrate 100 further includes a shielding electrode 22, the shielding electrode 22 is layered separately from the gate electrode 12 and the first common electrode 14 and is kept at the same potential as the first common electrode 14, and at least a part of a projection of the shielding electrode 22 on the first substrate 11 is located in a gap between the gate electrode 12 and the first common electrode 14.
Since the shielding electrode 22 and the first common electrode 14 are kept at the same potential, they are kept at the same potential with the second common electrode 3003 on the color filter substrate 300 (see fig. 7). When a voltage is applied to the pixel electrode 21, a portion of the liquid crystal molecules in the liquid crystal layer 200 corresponding to the pixel electrode 21 rotates, and a portion of the liquid crystal molecules corresponding to the shielding electrode 22 does not rotate, so that light does not exit through the liquid crystal layer 200 there.
In addition, the shielding electrode 22 and the gate 12 and the first common electrode 14 are disposed in different layers, that is, formed separately by two photomasks, and the relative positions of the shielding electrode 22, the gate 12 and the first common electrode 14 projected on the first substrate 11 are not limited by the process requirement of one photomask process, and the problem of mutual short circuit between the shielding electrode 22 and the gate 12 and the first common electrode 14 is not considered. The design of the shielding electrode 22 herein is equivalent to reducing or even eliminating the gap between the gate electrode 12 and the first common electrode 14, so that light leakage at the gap can be effectively avoided.
For the gap, it is usually necessary to shield the gap by disposing a black matrix 3002 on the color filter substrate 300 to further prevent light from leaking from the gap, and the black matrix 3002 needs to partially overlap with the gate electrode 12 and the first common electrode 14 to completely shield the gap, as shown in fig. 7.
As shown in fig. 7, since the black matrix 3002 is disposed on the color filter substrate 300 and the liquid crystal layer 200 needs to be disposed between the color filter substrate 300 and the array substrate 100, when a user presses the color filter substrate 300 obliquely toward one side of the array substrate 100, the color filter substrate 300 may deform, and the positions of the black matrix 3002 relative to the gate 12 and the first common electrode 14 may shift. However, in the present application, due to the arrangement of the shielding electrode 22, even if the black matrix 3002 is misaligned with respect to the gate electrode 12 and the first common electrode 14, so that a gap is generated between the black matrix 3002 and the gate electrode 12 or the first common electrode 14, the shielding electrode 22 can still ensure that no light leaks from the gap between the gate electrode 12 and the first common electrode 14.
Moreover, based on the arrangement of the shielding electrode 22, the overlapping portion between the black matrix 3002 and the gate 12 and the first common electrode 14 can be designed to be as small as possible, that is, the width of the black matrix 3002 can be designed to be as small as possible, so as to avoid the area for shielding the pixel electrode 21 from being too large, and further, the design of the shielding electrode 22 of the present application can avoid influencing the aperture opening ratio of the array substrate 100, and ensure that the array substrate 100 has high aperture opening ratio and light transmittance.
As shown in fig. 1, a first via 201 penetrating to the drain electrode 18 is disposed on the second insulating layer 20, and the pixel electrode 21 is connected to the drain electrode 18 through the first via 201.
Referring to fig. 1 to 3, the gate 12 and the first common electrode 14 are spaced apart from each other and are not connected to each other. Typically, the gap between the gate electrode 12 and the first common electrode 14 is at least 5 microns, and typically at least 6 microns, to ensure the process and reliable insulation therebetween. In a specific application, the width of the gap between the gate electrode 12 and the first common electrode 14 may be determined according to product or design requirements, and is not particularly limited herein.
In an alternative embodiment, as shown in fig. 1 and 2, the width W of the shielding electrode 22 is greater than or equal to 5 μm to ensure the process, and to ensure the structural continuity of the shielding electrode 22 itself without the problem of open circuit.
As described above, at least a part of the projection of the shield electrode 22 on the first substrate 11 is located in the gap between the gate electrode 12 and the first common electrode 14, which includes the following cases.
In one embodiment, the projection of the shield electrode 22 on the first substrate base 11 may be entirely within the gap (the projection of the shield electrode 22 on the first substrate base 11 is spaced from both the edge of the gate electrode 12 and the edge of the first common electrode 14). At this time, the width W of the shield electrode 22 is smaller than the width of the gap between the gate electrode 12 and the first common electrode 14. Although the shield electrode 22 does not completely cover the gap, the width of the gap between the projection of the shield electrode 22 and the gate electrode 12 and the width of the gap between the projection of the shield electrode 22 and the line of the first common electrode 14 may be as small as to completely avoid light leakage.
Or, in another embodiment, the projection of the shielding electrode 22 on the first substrate 11 is spaced apart from one of the gate electrode 12 and the first common electrode 14, and meets or even at least partially overlaps the other of the gate electrode 12 and the first common electrode 14. It can be understood that the gap on the projection side of the shielding electrode 22 can be still as small as to completely avoid light leakage.
Still alternatively, in another embodiment, the shielding electrode 22 completely covers the gap between the gate electrode 12 and the first common electrode 14, in other words, the projection of the shielding electrode 22 on the first substrate 11 meets or coincides with the gate electrode 12 (the edges of the two are shown in vertical dashed lines in fig. 3 and 4 are aligned), and the projection of the shielding electrode 22 on the first substrate 11 meets or coincides with the first common electrode 14.
Wherein, in an alternative embodiment, the projection of the shielding electrode 22 on the first substrate 11 is connected to or spaced from the gate electrode 12. The purpose of this arrangement is that, since the voltages of the shielding electrode 22 and the gate electrode 12 are different, the shielding electrode 22 and the gate electrode 12 do not overlap with each other, so as to avoid generating a parasitic capacitance therebetween, thereby avoiding affecting the voltage applied to the gate electrode 12, and further avoiding adversely affecting the display effect of the array substrate 100.
In one embodiment, the projection of the shielding electrode 22 onto the first substrate base 11 is in contact with, spaced from, or at least partially overlapping the first common electrode 14. In the present embodiment, the projection of the shielding electrode 22 on the first substrate 11 at least partially overlaps the first common electrode 14 to completely eliminate the gap between the first common electrode 14 and the shielding electrode.
The shield electrode 22 is substantially connected to the first common electrode 14 so that the same potential can be maintained between the two at all times.
Referring to fig. 3, in one embodiment, the shielding electrode 22 is in the same layer as the pixel electrode 21.
Specifically, the first insulating layer 15 is a gate insulating layer, a second via hole 150 penetrating to the first common electrode 14 is disposed on the gate insulating layer, as shown in fig. 3, a third via hole 202 communicating with the second via hole 150 is disposed on the second insulating layer 20, and the shielding electrode 22 is disposed on the second insulating layer 20 and connected to the first common electrode 14 through the second via hole 150 and the third via hole 202.
In an alternative embodiment, the distance between the shielding electrode 22 and the pixel electrode 21 is greater than or equal to 2.5 μm, so as to reduce or even eliminate the gap between the shielding electrode 22 and the first common electrode 14 as much as possible on the basis of ensuring the implementation of the process and avoiding the formation of short circuit with the pixel electrode 21. Further, the spacing between the shielding electrode 22 and the pixel electrode 21 may be selected to be greater than or equal to 4 microns, and may even be greater than or equal to 5 microns.
Alternatively, referring to fig. 4, in one embodiment, the shielding electrode 22 is on the same layer as the source electrode 17 and the drain electrode 18.
Specifically, the first insulating layer 15 is a gate insulating layer, and a second via 150 penetrating through the first common electrode 14 is disposed on the gate insulating layer. The shield electrode 22 is disposed on the gate insulating layer and connected to the first common electrode 14 through the second via 150. A second insulating layer 20 is provided on the source electrode 17, the drain electrode 18, and the shield electrode 22.
Alternatively, in other embodiments, the shielding electrode 22 may be disposed in a different layer from the first common electrode 14 through another layer structure, so long as the shielding electrode 22 and the first common electrode 14 are always kept at the same potential. For example, the array substrate 100 may further include an alignment layer (not shown) disposed on the pixel electrode 21, and the shielding electrode 22 is disposed on the alignment layer. In this case, the shielding electrode 22 may extend to a non-display area (not shown) on the first substrate 11 along an area avoiding the pixel electrode 21 to be connected to the driving module, and the driving module directly provides a common voltage having the same potential as the first common electrode 14, and the like.
The second insulating layer 20 may be a passivation layer. Alternatively, the second insulating layer 20 is a Color resist layer, and thus, the Array substrate 100 is a COA (Color on Array) type Array substrate.
Referring to fig. 1, in one embodiment, the first substrate 11 further has a plurality of gate lines 13, the gate lines 13 are parallel and sequentially arranged at intervals, and the pixel electrode 21 is disposed on one side of each adjacent gate line 13. For example, taking the orientation shown in fig. 1 as an example, the lower side of each gate line 13 is provided with a pixel electrode 21 connected thereto through a thin film transistor 10. The first common electrode 14 is in a closed frame shape and surrounds the periphery of the pixel electrode 21. This makes every first common electrode 14 except the last first common electrode 14 have the upper and lower sides spaced from one gate 12, that is, every first common electrode 14 except the last first common electrode 14 has the same spacing with two adjacent gates 12, and the last first common electrode 14 may be spaced from only one gate 12 on one side.
Therefore, in the present embodiment, except for the last first common electrode 14, a shielding electrode 22 is disposed between each first common electrode 14 and two adjacent gate electrodes 12; the last first common electrode 14 may be provided with a shield electrode 22 only between it and the gate electrode 12 on its upper side.
As shown in fig. 1, in one embodiment, the array substrate 100 further includes a plurality of data lines 19 disposed on the first insulating layer 15 and connected to the source electrodes 17. The data lines 19 are arranged perpendicular to the gate lines 13 and are sequentially spaced apart.
Referring to fig. 5 and fig. 6, an embodiment of the present invention further provides a method for manufacturing an array substrate, which includes the following steps.
Step S1, providing a first substrate 11, and forming a gate electrode 12 and a first common electrode 14 on the first substrate 11;
step S2, forming a first insulating layer 15 on the gate electrode 12 and the first common electrode 14;
step S3, forming an active layer 16 on the first insulating layer 15, and forming a source electrode 17 and a drain electrode 18 on the active layer 16;
step S4, forming a second insulating layer 20 on the source electrode 17 and the drain electrode 18, and forming a first via hole 201 penetrating to the drain electrode 18 on the second insulating layer 20; and
in step S5, a pixel electrode 21 is formed on the second insulating layer 20, and the pixel electrode 21 is connected to the drain 18 through the first via 201, as shown in fig. 1.
Wherein, in this embodiment, further include: a shield electrode 22 is formed in a layer different from the gate electrode 12 and the first common electrode 14, the shield electrode 22 is kept at the same potential as the first common electrode 14, and at least a part of the projection of the shield electrode 22 on the first substrate 11 is located in the gap between the gate electrode 12 and the first common electrode 14.
In the manufacturing method of the array substrate provided by the embodiment of the application, by forming the shielding electrode 22 which is different from the first common electrode 14 and keeps the same potential as the first common electrode 14, a part of liquid crystal molecules in the liquid crystal layer 200 corresponding to the shielding electrode 22 cannot deflect; the shielding electrode 22 is arranged in a different layer with the gate 12 and the first common electrode 14, the projection relative position between the shielding electrode 22 and the gate 12 and the first common electrode 14 is not limited by the process requirement, and the problem of mutual short circuit between the shielding electrode 22 and the gate 12 and the first common electrode 14 is not considered, the design of the shielding electrode 22 is equivalent to reducing or even eliminating the gap between the gate 12 and the first common electrode 14, so that the light leakage at the gap can be effectively avoided; in addition, when a user presses the color filter substrate 300 obliquely towards one side of the array substrate 100 and causes deformation of the color filter substrate 300, even if the black matrix 3002 is offset or misaligned relative to the gate 12 and the first common electrode 14 to cause a gap between the black matrix 3002 and the gate 12 or the first common electrode 14, the shielding electrode 22 can still ensure that no light leaks from the gap between the gate 12 and the first common electrode 14, on this basis, an overlapping portion between the black matrix 3002 and the gate 12 and the first common electrode 14 can be designed to be as small as possible, that is, a width of the black matrix 3002 can be designed to be as small as possible to avoid an excessively large area for shielding the pixel electrode 21, further avoid affecting an aperture opening ratio of the array substrate 100, and ensure that the manufactured array substrate 100 has a high aperture ratio.
Referring to fig. 1 to 3, the gap between the gate 12 and the first common electrode 14 is at least 6 μm.
In an alternative embodiment, as shown in fig. 1, the width W of the shielding electrode 22 is greater than or equal to 5 μm to ensure the process is performed, and to ensure the structural continuity of the shielding electrode 22 without the problem of open circuit.
In one embodiment, the projection of the shielding electrode 22 on the first substrate base 11 may be entirely within the gap, i.e., the projection of the shielding electrode 22 on the first substrate base 11 is spaced from both the edge of the gate electrode 12 and the edge of the first common electrode 14).
Or, in another embodiment, the projection of the shielding electrode 22 on the first substrate 11 is spaced apart from one of the gate electrode 12 and the first common electrode 14, and meets or even coincides with the other of the gate electrode 12 and the first common electrode 14.
Still alternatively, in another embodiment, the shielding electrode 22 completely covers the gap between the gate electrode 12 and the first common electrode 14, and includes that the projection of the shielding electrode 22 on the first substrate 11 is connected to or overlapped with the gate electrode 12, and the projection of the shielding electrode 22 on the first substrate 11 is connected to or overlapped with the first common electrode 14.
Wherein, in an alternative embodiment, the projection of the shielding electrode 22 on the first substrate 11 is connected to or spaced from the gate electrode 12. The purpose of this arrangement is that, since the voltages of the shielding electrode 22 and the gate electrode 12 are different, the shielding electrode 22 and the gate electrode 12 do not overlap with each other, so as to avoid generating a parasitic capacitance therebetween, thereby avoiding affecting the turn-on voltage applied to the gate electrode 12, and further avoiding adversely affecting the display effect of the array substrate 100.
The projection of the shielding electrode 22 on the first substrate 11 is connected to, spaced from, or partially overlapped by the first common electrode 14. In the present embodiment, the projection of the shielding electrode 22 on the first substrate 11 at least partially overlaps the first common electrode 14.
In one embodiment, as shown in fig. 5, the step of forming the shielding electrode 22 is performed in step S3, that is, the shielding electrode 22 and the drain 18 are formed in the same layer and by the same masking process.
Correspondingly, in step S2, a second via 150 penetrating to the first common electrode 14 is also formed on the first insulating layer 15 at the same time, please refer to fig. 4, and after step S3, the shielding electrode 22 is connected to the first common electrode 14 through the second via 150.
In another embodiment, as shown in fig. 6, the step of forming the shielding electrode 22 is performed in step S5, that is, the shielding electrode 22 and the pixel electrode 21 are formed in the same layer and by the same masking process.
Correspondingly, in step S2, a second via hole 150 penetrating to the first common electrode 14 is also formed on the first insulating layer 15 at the same time, and in step S4, a third via hole 202 corresponding to the second via hole 150 is also formed on the second insulating layer 20 at the same time, please refer to fig. 3; after step S5, the shielding electrode 22 is connected to the first common electrode 14 through the second via 150 and the third via 202.
Alternatively, in other embodiments, the shield electrode 22 is formed in other steps. For example, the manufacturing method of the array substrate further includes: an alignment layer is formed on the pixel electrode 21, and the shielding electrode 22 is formed on the alignment layer. The shielding electrode 22 may extend to the non-display region along a region avoiding the pixel electrode 21 to be connected to the driving module, and the driving module directly provides the common voltage having the same potential as the first common electrode 14.
In step S2, the first insulating layer 15 is a gate insulating layer. In step S4, the second insulating layer 20 may be a passivation layer; alternatively, the second insulating layer 20 is a Color resist layer, and thus, the Array substrate 100 obtained is a COA (Color on Array) type Array substrate.
In one embodiment, referring to fig. 1, in step S1, a plurality of gate lines 13 are formed simultaneously, and the gate lines 13 are connected to the gate 12. The gate lines 13 are arranged in parallel and sequentially at intervals, and the pixel electrode 21 is disposed at one side of each adjacent gate line 13. Taking the orientation shown in fig. 1 as an example, the lower side of each gate line 13 is provided with a pixel electrode 21 connected thereto through a thin film transistor 10. The first common electrode 14 is in a closed frame shape and surrounds the periphery of the pixel electrode 21. This makes each of the first common electrodes 14, except the last first common electrode 14, have upper and lower sides spaced from one of the gate electrodes 12, that is, each of the first common electrodes 14, except the last first common electrode 14, has a space between two adjacent gate electrodes 12.
In the present embodiment, except for the last first common electrode 14, a shielding electrode 22 is disposed between each first common electrode 14 and two adjacent gate electrodes 12; the last first common electrode 14 may be provided with a shield electrode 22 only between it and the gate electrode 12 on one side.
Referring to fig. 1, in an embodiment, the method for manufacturing the array substrate further includes: in step S3, a plurality of data lines 19 are formed simultaneously, the data lines 19 are connected to the source electrodes 17 at the same layer, and the data lines 19 are perpendicular to the gate lines 13 and are sequentially arranged at intervals.
As shown in fig. 7, an embodiment of the present application further provides a display panel 400, which includes the array substrate 100, the color filter substrate 300 spaced from and opposite to the array substrate 100, and the liquid crystal layer 200 disposed between the array substrate 100 and the color filter substrate 300.
The color filter substrate 300 includes a second substrate 3001, a black matrix 3002 disposed on the second substrate 3001, and a second common electrode 3003 disposed on the black matrix 3002. The black matrix 3002 is used to shield an area around the pixel electrode 21.
In the display panel 400 provided in the embodiment of the present application, the array substrate 100 is provided with the shielding electrode 22 maintaining the same potential as the first common electrode 14, and at least a part of the projection of the shielding electrode 22 on the first substrate 11 is used to cover the gap between the gate 12 and the first common electrode 14, the liquid crystal molecules corresponding to the shielding electrode 22 do not deflect, and light leakage at the gap between the gate 12 and the first common electrode 14 can be avoided, so that even if the black matrix 3002 is dislocated and the gap is not completely blocked when the display panel 400 is pressed from one side of the color filter substrate 300, the shielding electrode 22 can also effectively avoid light leakage, thereby improving the push mura problem, and the display panel 400 has a good display effect; meanwhile, the width of the black matrix 3002 on the color filter substrate 300 for shielding the gap between the gate electrode 12 and the first common electrode 14 may be set to be smaller, and the display panel 400 has a high aperture ratio and a high light transmittance.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An array substrate, comprising:
a substrate base plate; and
the grid electrode and the common electrode are arranged on the substrate base plate;
characterized in that, the array substrate still includes:
and the shielding electrode is different from the grid electrode and the common electrode and has the same potential as the common electrode, and at least one part of the projection of the shielding electrode on the substrate is positioned in the gap between the grid electrode and the common electrode.
2. The array substrate according to claim 1, wherein the array substrate further comprises a first insulating layer disposed on the gate electrode and the common electrode, and a source electrode and a drain electrode disposed on the first insulating layer, wherein a first via hole penetrating to the common electrode is disposed on the first insulating layer, the shielding electrode is disposed on the first insulating layer and is in the same layer as the source electrode and the drain electrode, and the shielding electrode is connected to the common electrode through the first via hole.
3. The array substrate according to claim 1, wherein the array substrate further comprises a first insulating layer disposed on the gate electrode and the common electrode, a source electrode and a drain electrode disposed on the first insulating layer, a second insulating layer disposed on the source electrode and the drain electrode, and a pixel electrode disposed on the second insulating layer, wherein a first via hole penetrating to the common electrode is disposed on the first insulating layer, a second via hole communicating with the first via hole is disposed on the second insulating layer, the shielding electrode is disposed on the second insulating layer and on the same layer as the pixel electrode, and the shielding electrode is connected to the common electrode through the first via hole and the second via hole.
4. The array substrate of claim 3, wherein a spacing between the shielding electrode and the pixel electrode is greater than or equal to 2.5 microns.
5. The array substrate of claim 3, wherein the second insulating layer is a passivation layer or a color resist layer.
6. The array substrate of claim 3, wherein the substrate further has a plurality of gate lines formed thereon, the gate lines being arranged in parallel and spaced apart, the pixel electrodes being formed on one side of the gate lines; the common electrode surrounds the periphery of the pixel electrode; the shielding electrodes are arranged between the other pixel electrodes and the two gate lines on the two sides of the pixel electrodes except the last pixel electrode.
7. The array substrate of any one of claims 1 to 6, wherein a projection of the shielding electrode on the substrate is contiguous with or spaced apart from an edge of the gate electrode adjacent to the common electrode.
8. The array substrate of any one of claims 1 to 6, wherein the projection of the shielding electrode on the substrate at least partially overlaps, is spaced apart from, or is contiguous with an edge of the common electrode near the gate electrode.
9. A manufacturing method of an array substrate comprises the following steps:
providing a substrate, and forming a grid electrode and a common electrode on the substrate;
forming a first insulating layer on the gate electrode and the common electrode;
forming an active layer, a source electrode and a drain electrode on the first insulating layer;
forming a second insulating layer on the source electrode and the drain electrode, and forming a first through hole penetrating to the drain electrode on the second insulating layer; and
forming a pixel electrode on the second insulating layer, the pixel electrode being connected to the drain electrode via the first via hole;
the manufacturing method of the array substrate is characterized by further comprising the following steps:
forming a shielding electrode on the same layer as the drain electrode on the first insulating layer, or forming a shielding electrode on the same layer as the pixel electrode on the second insulating layer; the shielding electrode and the common electrode are in the same potential, and at least one part of the projection of the shielding electrode on the substrate base plate is positioned in the gap between the grid electrode and the common electrode.
10. A display panel comprising the array substrate of any one of claims 1 to 8, a color filter substrate spaced opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
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| CN115685629A (en) * | 2022-11-07 | 2023-02-03 | Tcl华星光电技术有限公司 | Display panel, manufacturing method thereof and display device |
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