CN105489617B - A kind of array substrate, display panel and display device - Google Patents
A kind of array substrate, display panel and display device Download PDFInfo
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- CN105489617B CN105489617B CN201610039762.1A CN201610039762A CN105489617B CN 105489617 B CN105489617 B CN 105489617B CN 201610039762 A CN201610039762 A CN 201610039762A CN 105489617 B CN105489617 B CN 105489617B
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- 239000000758 substrate Substances 0.000 title claims abstract description 82
- 239000010409 thin film Substances 0.000 claims abstract description 30
- 239000003990 capacitor Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 208000003351 Melanosis Diseases 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a kind of array substrate, display panel and display devices, comprising: data line and thin film transistor (TFT) on underlay substrate is arranged in underlay substrate；The source electrode of thin film transistor (TFT) includes the first component pole and the second component pole；First component pole and the second component pole are connect with data line respectively；The drain electrode of thin film transistor (TFT) includes the first son drain electrode；First son drain electrode is between the first component pole and the second component pole；First component pole and the second component pole form effective channel region with the first son drain electrode respectively.Since the first component pole and the second component pole are parallel to each other and connect respectively with data line, i.e. the first component pole and the second component pole can reduce the overlapping area of source electrode and grid, overlap capacitance reduced, to reduce load without intersection；It is much larger than the influence of resistance to the influence of charge rate due to capacitor again, thus uses array substrate provided in this embodiment, can suitably reduce line width, increasing opening rate, while ensuring charge rate.
Description
Technical field
The present invention relates to field of display technology, espespecially a kind of array substrate, display panel and display device.
Background technique
Currently, large scale ultra high-definition TV (Ultra High Definition Television, abbreviation UHD) product is
The focus development direction of tv product, resolution ratio can reach 3840x 2160, especially array substrate row and drives (Gate
Driver on Array, abbreviation GOA) ultra high-definition tv product.And UHD GOA product is because the charging time is short, GOA drives in addition
Energy power limit, undercharge is a great problem.
In order to meet charge rate, generally by using increase thin film transistor (TFT) (Thin-film Transistor, abbreviation
TFT) breadth length ratio value increases line width (such as width of the width of data line, grid), fills to reduce the methods of resistance to meet
Electric rate requirement.However TFT breadth length ratio value and line width can make further to decline with regard to lesser pixel aperture ratio originally, to influence face
The transmitance of plate increases backlight power consumption.
General large scale ultra high-definition shows product frequently with single gap mask plate (Single Slit Mask, SSM) technology
Or single gap mask plate (Modified Single Slit Mask, MSM) technology is improved, in the structure of SSM TFT, such as
Shown in Fig. 1, the spacing very little (2um or so) of grid and source electrode, and the resolution ratio of exposure machine is generally higher than 2um, channel region benefit
Semi-transparent region is formed with optical grating diffraction, narrow channel is formed after exposed development etching technics, to increase breadth length ratio value, entirely
U-typed channel region is effective channel region 01, but SSM TFT channel bottom be easy to happen cracking it is bad or it is short-circuit not
It is good.In order to solve the bad of SSM TFT, trench bottom is improved, as MSM TFT, in MSM TFT structure, such as
Shown in Fig. 2 and Fig. 3, trench bottom space is larger, and MSM channel two sides are consistent with SSM, although in this way, it is possible to prevente effectively from channel
The bad or poor short circuit that cracks occurs for bottom, but the blank area active layer (Active) is formed after exposed development etching technics,
The two side areas of U-typed is effective channel region 02, and U-typed trench bottom is invalid channel region 03, so that channel
Overlapping area between bottom source and grid is very big, causes the overlap capacitance between source electrode and grid very big, leads to load very
Greatly.And in order to meet charge rate, line width need to be significantly increased, decline to a great extent so as to cause aperture opening ratio, also, to the driving energy of GOA
Power also forms challenge.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of array substrate, display panel and display device, source electrode can reduce
With the overlapping area of grid, overlap capacitance is reduced, to reduce load.
Therefore, the embodiment of the invention provides a kind of array substrate, the number on the underlay substrate is arranged in underlay substrate
According to line and thin film transistor (TFT)；
The source electrode of the thin film transistor (TFT) includes the first component pole and the second component pole；First component pole and described
Two component poles are connect with the data line respectively；
The drain electrode of the thin film transistor (TFT) includes the first son drain electrode；It is described first son drain electrode be located at first component pole and
Between second component pole；
First component pole and second component pole form effective channel region with the first son drain electrode respectively.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, the source electrode is also
Including the third component pole for connecting first component pole and the data line.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, third
Orthographic projection no overlap region of the grid of orthographic projection of the source electrode on underlay substrate and the thin film transistor (TFT) on underlay substrate.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, the source electrode is also
Including the 4th component pole for connecting second component pole and the data line.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, the 4th son
Orthographic projection no overlap region of the grid of orthographic projection of the source electrode on underlay substrate and the thin film transistor (TFT) on underlay substrate.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, the drain electrode is also
Including draining for connecting the first son drain electrode and the second son of the pixel electrode in the array substrate.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, second son
Orthographic projection no overlap region of the grid of the orthographic projection and the thin film transistor (TFT) that drain on underlay substrate on underlay substrate.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, first son
Source electrode and the second component pole are parallel to each other.
In one possible implementation, in above-mentioned array substrate provided in an embodiment of the present invention, first son
Source electrode and the second component pole are vertical with the data line respectively.
The embodiment of the invention also provides a kind of display panels, including above-mentioned array substrate provided in an embodiment of the present invention.
The embodiment of the invention also provides a kind of display devices, including above-mentioned display panel provided in an embodiment of the present invention.
The beneficial effect of the embodiment of the present invention includes:
A kind of array substrate, display panel and display device provided in an embodiment of the present invention, comprising: underlay substrate, setting
Data line and thin film transistor (TFT) on underlay substrate；The source electrode of thin film transistor (TFT) includes the first component pole and the second component pole；
First component pole and the second component pole are connect with data line respectively；The drain electrode of thin film transistor (TFT) includes the first son drain electrode；First son
Drain electrode is between the first component pole and the second component pole；First component pole and the second component pole are formed with the first son drain electrode respectively
Effective channel region.Since the first component pole and the second component pole are parallel to each other and connect respectively with data line, i.e. the first component
Pole and the second component pole can reduce the overlapping area of source electrode and grid, overlap capacitance reduced, to reduce load without intersection；
It is much larger than the influence of resistance to the influence of charge rate due to capacitor again, thus uses array substrate provided in this embodiment, can fit
When reduction line width, increasing opening rate, while ensuring charge rate.
Detailed description of the invention
Fig. 1 is in the prior art using the structural schematic diagram of the array substrate of SSM technology；
Fig. 2 is in the prior art using the structural schematic diagram of the array substrate of MSM technology；
Fig. 3 is partial enlarged view in Fig. 2；
Fig. 4 is the structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 5 is one of partial enlarged view in Fig. 4；
Fig. 6 is two of partial enlarged view in Fig. 4.
Specific embodiment
With reference to the accompanying drawing, to the specific reality of array substrate provided in an embodiment of the present invention, display panel and display device
The mode of applying is described in detail.
Wherein, the size and shape of each structure does not reflect the actual proportions of array substrate in attached drawing, and purpose is only illustrated to say
Bright the content of present invention.
The embodiment of the invention provides a kind of array substrates, as shown in Figure 4 and Figure 5, comprising: underlay substrate, setting are serving as a contrast
Data line 1 and thin film transistor (TFT) on substrate；
The source electrode 2 of thin film transistor (TFT) includes the first component pole 21 and the second component pole 22；First component pole 21 and the second son
Source electrode 22 is connect with data line 1 respectively；
The drain electrode 3 of thin film transistor (TFT) includes the first son drain electrode 31；First son drain electrode 31 is located at the first component pole 21 and second
Between component pole 22；
First component pole 21 and the second component pole 22 form effective channel region 100 with the first son drain electrode 31 respectively.
In above-mentioned array substrate provided in an embodiment of the present invention, due to the first component pole and the second component pole respectively with data
Line connection, i.e. the first component pole and the second component pole without intersection, the first component pole and the second component pole respectively with data line one by one
It is corresponding, it can reduce the overlapping area of source electrode and grid, overlap capacitance reduced, to reduce load；Again since capacitor is to charging
The influence of rate is much larger than the influence of resistance, thus uses array substrate provided in this embodiment, can suitably reduce line width, promotion is opened
Mouth rate, while ensuring charge rate.
In the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in fig. 6, source electrode 2 can be with
Including the third component pole 23 for connecting the first component pole 21 and data line 1, i.e. the first component pole 21 can pass through third
Source electrode 23 and data line 1 are electrically connected, which does not form effective channel region with drain electrode 3.
Further, in the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in fig. 6, the
Orthographic projection no overlap area of the grid 4 of orthographic projection and thin film transistor (TFT) of the three component poles 23 on underlay substrate on underlay substrate
Domain, i.e. third component pole and grid no overlap area, further reduced overlap capacitance, to reduce load；It needs to illustrate
Be, the shape of third component pole can according to the actual situation depending on, can be linear, fold-line-shaped or other shapes, herein not
It limits.The edge of grid according to the setting of third component pole, can be increased far from the distance of channel region overlay area, such as schemed
6 to show shortest distance L of the gate edge nearest from data line away from channel region overlay area larger, can be to avoid melanism
Mura is bad.
In the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in fig. 6, source electrode 2 can be with
Including the 4th component pole 24 for connecting the second component pole 22 and data line 1, i.e. the second component pole 22 can pass through the 4th son
Source electrode 24 and data line 1 are electrically connected, and the 4th component pole 24 does not form effective channel region with drain electrode 3.
Further, in the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in fig. 6, the
Orthographic projection no overlap area of the grid 4 of orthographic projection and thin film transistor (TFT) of the four component poles 24 on underlay substrate on underlay substrate
Domain, i.e. the 4th component pole and grid no overlap area, further reduced overlap capacitance, to reduce load；It needs to illustrate
Be, the shape of the 4th component pole can according to the actual situation depending on, can be linear, fold-line-shaped or other shapes, herein not
It limits.The edge of grid according to the setting of the 4th component pole, can be increased far from the distance of channel region overlay area, such as schemed
6 to show shortest distance L of the gate edge nearest from data line away from channel region overlay area larger, can be to avoid melanism
Mura is bad.
In the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in fig. 6, drain electrode 3 further includes
For connecting second son drain electrode 32 of the first son drain electrode 31 with the pixel electrode 5 in array substrate, i.e., the first son drain electrode 31 can be with
It is electrically connected by the second son drain electrode 32 with pixel electrode 5, which does not form effective channel region with source electrode 2.
Further, in the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in fig. 6, the
Orthographic projection no overlap area of the grid 2 of orthographic projection and thin film transistor (TFT) of the two son drain electrodes 32 on underlay substrate on underlay substrate
Domain, i.e., the second son drain electrode and grid no overlap area, further reduced overlap capacitance, to reduce load；It needs to illustrate
Be, second son drain electrode shape can according to the actual situation depending on, can be linear, fold-line-shaped or other shapes, herein not
It limits.
In the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, as shown in figure 5, the first component pole
21 and second component pole 22 can be set to be parallel to each other, and since the first son drain electrode 31 is located at the first component pole 21 and the second son
Between source electrode 22, i.e., the first son drain electrode 31 and the first component pole 21 and the second component pole 22 can be set to parallel construction,
It is distributed the source electrode and drain electrode of thin film transistor (TFT) more.
In the specific implementation, in above-mentioned array substrate provided in an embodiment of the present invention, the first component pole and the second component
Pole respectively positional relationship corresponding with data line can there are many, in order to guarantee aperture opening ratio, as shown in Figure 5, it is preferable that
One component pole 21 and the second component pole 22 respectively can be vertical with data line 1, can not only increase aperture opening ratio, can also simplify system
Make technique.
By taking 49inch UHD GOA product as an example, array substrate provided in an embodiment of the present invention is more existing to use MSM skill
The array substrate load reduction about 15% of art, aperture opening ratio improves about 8%, while charge rate can be promoted to 99% by 98.6%.
In the specific implementation, generally can also have such as gate insulation layer in array substrate provided in an embodiment of the present invention, have
Other film layer structures such as active layer and protective layer, and the structures such as grid line, public electrode wire are also generally formed on underlay substrate,
These specific structures can there are many implementations, it is not limited here.
Based on the same inventive concept, the embodiment of the invention also provides a kind of display panels, including the embodiment of the present invention to mention
The above-mentioned array substrate supplied.
Based on the same inventive concept, the embodiment of the invention also provides a kind of display devices, including the embodiment of the present invention to mention
The above-mentioned display panel supplied, the display device can be with are as follows: mobile phone, tablet computer, television set, display, laptop, number
Any products or components having a display function such as photo frame, navigator.For other essential compositions of the display device
Part is it will be apparent to an ordinarily skilled person in the art that having, and this will not be repeated here, also should not be used as to of the invention
Limitation.The implementation of the display device may refer to the embodiment of above-mentioned display panel, array substrate, and overlaps will not be repeated.
A kind of array substrate, display panel and display device provided in an embodiment of the present invention, comprising: underlay substrate, setting
Data line and thin film transistor (TFT) on underlay substrate；The source electrode of thin film transistor (TFT) includes the first component pole and the second component pole；
First component pole and the second component pole are connect with data line respectively；The drain electrode of thin film transistor (TFT) includes the first son drain electrode；First son
Drain electrode is between the first component pole and the second component pole；First component pole and the second component pole are formed with the first son drain electrode respectively
Effective channel region.Since the first component pole and the second component pole are parallel to each other and connect respectively with data line, i.e. the first component
Pole and the second component pole can reduce the overlapping area of source electrode and grid, overlap capacitance reduced, to reduce load without intersection；
It is much larger than the influence of resistance to the influence of charge rate due to capacitor again, thus uses array substrate provided in this embodiment, can fit
When reduction line width, increasing opening rate, while ensuring charge rate.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (7)
1. a kind of array substrate, comprising: data line and thin film transistor (TFT) on the underlay substrate is arranged in underlay substrate；Its
It is characterized in that,
The source electrode of the thin film transistor (TFT) includes the first component pole and the second component pole；First component pole and second son
Source electrode is connect with the data line respectively；The source electrode further includes for connecting first component pole and the data line
The grid of three component poles, orthographic projection of the third component pole on underlay substrate and the thin film transistor (TFT) is on underlay substrate
Orthographic projection no overlap region；It further include the 4th component pole for connecting second component pole and the data line, it is described
Orthographic projection of the grid of orthographic projection of the 4th component pole on underlay substrate and the thin film transistor (TFT) on underlay substrate is without friendship
Folded region；
The drain electrode of the thin film transistor (TFT) includes the first son drain electrode；The first son drain electrode is located at first component pole and described
Between second component pole；
First component pole and second component pole form effective channel region with the first son drain electrode respectively.
2. array substrate as described in claim 1, which is characterized in that the drain electrode further includes for connecting the first son leakage
Second son of the pixel electrode on pole and the array substrate drains.
3. array substrate as claimed in claim 2, which is characterized in that orthographic projection of the second son drain electrode on underlay substrate
With the orthographic projection no overlap region of the grid of the thin film transistor (TFT) on underlay substrate.
4. array substrate as described in claim 1, which is characterized in that first component pole and the second component are extremely mutually flat
Row.
5. array substrate as claimed in claim 4, which is characterized in that first component pole and the second component pole respectively with institute
It is vertical to state data line.
6. a kind of display panel, which is characterized in that including array substrate as described in any one in claim 1-5.
7. a kind of display device, which is characterized in that including display panel as claimed in claim 6.
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| CN201610039762.1A CN105489617B (en) | 2016-01-21 | 2016-01-21 | A kind of array substrate, display panel and display device |
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| CN201610039762.1A CN105489617B (en) | 2016-01-21 | 2016-01-21 | A kind of array substrate, display panel and display device |
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| CN105489617B true CN105489617B (en) | 2019-07-05 |
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| CN111522182B (en) * | 2020-05-29 | 2022-08-12 | 厦门天马微电子有限公司 | Liquid crystal display panel and array substrate thereof |
| CN112925136B (en) * | 2021-03-29 | 2023-03-10 | 绵阳惠科光电科技有限公司 | Control switch of drive circuit, array substrate and display panel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102884633A (en) * | 2010-05-13 | 2013-01-16 | 夏普株式会社 | Circuit board and display device |
| CN103730512A (en) * | 2013-12-31 | 2014-04-16 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102906636B (en) * | 2010-07-09 | 2013-11-13 | 夏普株式会社 | Liquid crystal display device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102884633A (en) * | 2010-05-13 | 2013-01-16 | 夏普株式会社 | Circuit board and display device |
| CN103730512A (en) * | 2013-12-31 | 2014-04-16 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor and display device |
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