CN105489617A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN105489617A CN105489617A CN201610039762.1A CN201610039762A CN105489617A CN 105489617 A CN105489617 A CN 105489617A CN 201610039762 A CN201610039762 A CN 201610039762A CN 105489617 A CN105489617 A CN 105489617A
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- component pole
- source electrode
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- base palte
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses an array substrate, a display panel and a display device. The array substrate comprises an underlying substrate, and data lines and thin-film transistors which are arranged on the underlying substrate. The source electrode of each thin-film transistor comprises a first child source electrode and a second child source electrode. The first child source electrode and the second child source electrode are respectively connected with the data lines. The drain electrode of each thin-film transistor comprises a first child drain electrode which is arranged between the first child source electrode and the second child source electrode. Effective channel regions are respectively formed by the first child source electrode and the second child source electrode and the first child drain electrode respectively. The first child source electrode and the second child source electrode are mutually parallel and are respectively connected with the data lines, i.e. the first child source electrode and the second child source electrode are not intersected so that overlapping area of the source electrode and the gate electrode can be reduced, overlapping capacitance can be reduced and thus load can be reduced; besides, influence of capacitance on chargeability is far greater than influence of resistance so that linewidth can be properly reduced, aperture ratio can be enhanced and chargeability can be ensured by using the array substrate.
Description
Technical field
The present invention relates to Display Technique field, espespecially a kind of array base palte, display floater and display unit.
Background technology
At present, large scale ultra high-definition TV (UltraHighDefinitionTelevision, being called for short UHD) product is the focus development direction of tv product, its resolution can reach 3840x2160, especially array base palte row cutting (GateDriveronArray is called for short GOA) ultra high-definition tv product.And UHDGOA product because of the charging interval short, in addition GOA driving force restriction, undercharge is a great problem.
In order to meet charge rate, general by adopting increase thin-film transistor (Thin-filmTransistor, be called for short TFT) breadth length ratio value, increase live width (width of such as data wire, the width of grid), thus the methods such as reduction resistance meet charge rate requirement.But TFT breadth length ratio value and live width can make originally just less pixel aperture ratio decline further, thus affect the transmitance of panel, increase backlight power consumption.
General large scale ultra high-definition display product often adopts single gap mask plate (SingleSlitMask, SSM) technology or improve single gap mask plate (ModifiedSingleSlitMask, MSM) technology, in the structure of SSMTFT, as shown in Figure 1, the spacing of grid and source electrode is very little (about 2um), and the resolution of exposure machine is generally greater than 2um, channel region utilizes optical grating diffraction to form semi-transparent region, narrow raceway groove is formed after exposure imaging etching technics, thus increase breadth length ratio value, whole " U " type raceway groove region is effective channel region 01, but easily there is the bad or poor short circuit that ftractures in SSMTFT trench bottom.In order to solve the bad of SSMTFT, trench bottom is improved, be MSMTFT, in MSMTFT structure, as shown in Figures 2 and 3, trench bottom space is larger, MSM raceway groove both sides are consistent with SSM, like this, although can effectively avoid trench bottom that the bad or poor short circuit of cracking occurs, but after exposure imaging etching technics, be formed with active layer (Active) clear area, the two side areas of " U " type is effective channel region 02, and " U " type trench bottom is invalid channel region 03, make the overlapping area between trench bottom source electrode and grid very large like this, cause the overlap capacitance between source electrode and grid very large, cause load very large.And in order to meet charge rate, live width significantly need be increased, thus cause aperture opening ratio to decline to a great extent, and, also challenge is formed to the driving force of GOA.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of array base palte, display floater and display unit, can reduce the overlapping area of source electrode and grid, reduces overlap capacitance, thus reduces load.
Therefore, embodiments provide a kind of array base palte, underlay substrate, be arranged on the data wire on described underlay substrate and thin-film transistor;
The source electrode of described thin-film transistor comprises the first component pole and the second component pole; Described first component pole is connected with described data wire respectively with described second component pole;
The drain electrode of described thin-film transistor comprises the first son drain electrode; Described first son drain electrode is between described first component pole and described second component pole;
Described first component pole and described second component pole drain with described first son respectively and form effective channel region.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, described source electrode also comprises the 3rd component pole for connecting described first component pole and described data wire.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the orthographic projection on underlay substrate of the grid of the orthographic projection of described 3rd component pole on underlay substrate and described thin-film transistor is without overlapping region.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, described source electrode also comprises the 4th component pole for connecting described second component pole and described data wire.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the orthographic projection on underlay substrate of the grid of the orthographic projection of described 4th component pole on underlay substrate and described thin-film transistor is without overlapping region.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the second son that described drain electrode also comprises for connecting the pixel electrode on described first son drain electrode and described array base palte drains.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, the orthographic projection on underlay substrate of the grid of the described second son orthographic projection of drain electrode on underlay substrate and described thin-film transistor is without overlapping region.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, described first component pole and the second component pole are parallel to each other.
In a kind of possible implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, described first component pole is vertical with described data wire respectively with the second component pole.
The embodiment of the present invention additionally provides a kind of display floater, comprises the above-mentioned array base palte that the embodiment of the present invention provides.
The embodiment of the present invention additionally provides a kind of display unit, comprises the above-mentioned display floater that the embodiment of the present invention provides.
The beneficial effect of the embodiment of the present invention comprises:
A kind of array base palte, display floater and display unit that the embodiment of the present invention provides, comprising: underlay substrate, be arranged on the data wire on underlay substrate and thin-film transistor; The source electrode of thin-film transistor comprises the first component pole and the second component pole; First component pole is connected with data wire respectively with the second component pole; The drain electrode of thin-film transistor comprises the first son drain electrode; First son drain electrode is between the first component pole and the second component pole; First component pole and the second component pole drain with the first son respectively and form effective channel region.Because the first component pole is parallel to each other with the second component pole and is connected with data wire respectively, namely the first component pole and the second component pole are without intersection, can reduce the overlapping area of source electrode and grid, reduce overlap capacitance, thus reduce load; Again because electric capacity is on the impact of the impact of charge rate much larger than resistance, the array base palte thus adopting the present embodiment to provide, suitably can reduce live width, increasing opening rate, guarantee charge rate simultaneously.
Accompanying drawing explanation
Fig. 1 is the structural representation of the array base palte adopting SSM technology in prior art;
Fig. 2 is the structural representation of the array base palte adopting MSM technology in prior art;
Fig. 3 is partial enlarged drawing in Fig. 2;
The structural representation of the array base palte that Fig. 4 provides for the embodiment of the present invention;
Fig. 5 is one of partial enlarged drawing in Fig. 4;
Fig. 6 is partial enlarged drawing two in Fig. 4.
Embodiment
Below in conjunction with accompanying drawing, the embodiment of array base palte, display floater and display unit that the embodiment of the present invention provides is described in detail.
Wherein, in accompanying drawing, the size and shape of each structure does not reflect the actual proportions of array base palte, and object just signal illustrates content of the present invention.
Embodiments provide a kind of array base palte, as shown in Figure 4 and Figure 5, comprising: underlay substrate, be arranged on the data wire 1 on underlay substrate and thin-film transistor;
The source electrode 2 of thin-film transistor comprises the first component pole 21 and the second component pole 22; First component pole 21 is connected with data wire 1 respectively with the second component pole 22;
The drain electrode 3 of thin-film transistor comprises the first son drain electrode 31; First son drain electrode 31 is between the first component pole 21 and the second component pole 22;
First component pole 21 and the second component pole 22 drain with the first son respectively and 31 form effective channel region 100.
At the above-mentioned array base palte that the embodiment of the present invention provides, because the first component pole is connected with data wire respectively with the second component pole, namely the first component pole and the second component pole are without intersection, first component pole and the second component pole respectively with data wire one_to_one corresponding, the overlapping area of source electrode and grid can be reduced, reduce overlap capacitance, thus reduce load; Again because electric capacity is on the impact of the impact of charge rate much larger than resistance, the array base palte thus adopting the present embodiment to provide, suitably can reduce live width, increasing opening rate, guarantee charge rate simultaneously.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, source electrode 2 can also comprise the 3rd component pole 23 for connecting the first component pole 21 and data wire 1, namely the first component pole 21 can be electrically connected with data wire 1 by the 3rd component pole 23, and the 3rd component pole 23 does not form effective channel region with drain electrode 3.
Further, in the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, the orthographic projection on underlay substrate of the grid 4 of the orthographic projection of the 3rd component pole 23 on underlay substrate and thin-film transistor is without overlapping region, namely the 3rd component pole and grid are without overlapping area, reduce further overlap capacitance, thus reduce load; It should be noted that, the shape of the 3rd component pole can be determined according to actual conditions, can be linear, fold-line-shaped or other shape, not limit at this.According to the setting of the 3rd component pole, can increase the distance of edge far from channel region overlay area of grid, the gate edge that such as Fig. 6 shows from data wire is nearest is comparatively large apart from the beeline L of channel region overlay area, and melanism Mura can be avoided bad.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, source electrode 2 can also comprise the 4th component pole 24 for connecting the second component pole 22 and data wire 1, namely the second component pole 22 can be electrically connected with data wire 1 by the 4th component pole 24, and the 4th component pole 24 does not form effective channel region with drain electrode 3.
Further, in the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, the orthographic projection on underlay substrate of the grid 4 of the orthographic projection of the 4th component pole 24 on underlay substrate and thin-film transistor is without overlapping region, namely the 4th component pole and grid are without overlapping area, reduce further overlap capacitance, thus reduce load; It should be noted that, the shape of the 4th component pole can be determined according to actual conditions, can be linear, fold-line-shaped or other shape, not limit at this.According to the setting of the 4th component pole, can increase the distance of edge far from channel region overlay area of grid, the gate edge that such as Fig. 6 shows from data wire is nearest is comparatively large apart from the beeline L of channel region overlay area, and melanism Mura can be avoided bad.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, the second son that drain electrode 3 also comprises for connecting the pixel electrode 5 on the first son drain electrode 31 and array base palte drains 32, namely the first son drain electrode 31 can be electrically connected with pixel electrode 5 by the second son drain electrode 32, and this second son drain electrode 32 does not form effective channel region with source electrode 2.
Further, in the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 6, the orthographic projection on underlay substrate of the grid 2 of the second son orthographic projection of drain electrode 32 on underlay substrate and thin-film transistor is without overlapping region, namely the second son drain electrode is with grid without overlapping area, reduce further overlap capacitance, thus reduces load; It should be noted that, the shape of the second son drain electrode can be determined according to actual conditions, can be linear, fold-line-shaped or other shape, not limit at this.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, as shown in Figure 5, first component pole 21 and the second component pole 22 can be set to be parallel to each other, again because the first son drain electrode 31 is between the first component pole 21 and the second component pole 22, namely the first son drain electrode 31 and the first component pole 21 and the second component pole 22 all can be set to parallel construction, and the source electrode of thin-film transistor and drain electrode distribution are more simplified.
In the specific implementation, in the above-mentioned array base palte that the embodiment of the present invention provides, corresponding with the data wire respectively position relationship in first component pole and the second component pole can have multiple, in order to can aperture opening ratio be ensured, as shown in Figure 5, preferably, the first component pole 21 respectively can be vertical with data wire 1 with the second component pole 22, not only can increase aperture opening ratio, can also manufacture craft be simplified.
For 49inchUHDGOA product, the array base palte load reduction about 15% of the array base palte that the embodiment of the present invention provides more existing employing MSM technology, aperture opening ratio improves about 8%, and charge rate can be promoted to 99% by 98.6% simultaneously.
In the specific implementation; generally other film layer structures such as such as gate insulation layer, active layer and protective layer also can be had in the array base palte that the embodiment of the present invention provides; and also the structure such as grid line, public electrode wire is generally formed with on underlay substrate; these concrete structures can have multiple implementation, do not limit at this.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display floater, comprises the above-mentioned array base palte that the embodiment of the present invention provides.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display unit, comprise the above-mentioned display floater that the embodiment of the present invention provides, this display unit can be: any product or parts with Presentation Function such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.Other requisite part for this display unit is and will be understood by those skilled in the art that to have, and does not repeat at this, also should as limitation of the present invention.The enforcement of this display unit see the embodiment of above-mentioned display floater, array base palte, can repeat part and repeats no more.
A kind of array base palte, display floater and display unit that the embodiment of the present invention provides, comprising: underlay substrate, be arranged on the data wire on underlay substrate and thin-film transistor; The source electrode of thin-film transistor comprises the first component pole and the second component pole; First component pole is connected with data wire respectively with the second component pole; The drain electrode of thin-film transistor comprises the first son drain electrode; First son drain electrode is between the first component pole and the second component pole; First component pole and the second component pole drain with the first son respectively and form effective channel region.Because the first component pole is parallel to each other with the second component pole and is connected with data wire respectively, namely the first component pole and the second component pole are without intersection, can reduce the overlapping area of source electrode and grid, reduce overlap capacitance, thus reduce load; Again because electric capacity is on the impact of the impact of charge rate much larger than resistance, the array base palte thus adopting the present embodiment to provide, suitably can reduce live width, increasing opening rate, guarantee charge rate simultaneously.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. an array base palte, comprising: underlay substrate, is arranged on the data wire on described underlay substrate and thin-film transistor; It is characterized in that,
The source electrode of described thin-film transistor comprises the first component pole and the second component pole; Described first component pole is connected with described data wire respectively with described second component pole;
The drain electrode of described thin-film transistor comprises the first son drain electrode; Described first son drain electrode is between described first component pole and described second component pole;
Described first component pole and described second component pole drain with described first son respectively and form effective channel region.
2. array base palte as claimed in claim 1, it is characterized in that, described source electrode also comprises the 3rd component pole for connecting described first component pole and described data wire.
3. array base palte as claimed in claim 2, is characterized in that, the orthographic projection on underlay substrate of the grid of the orthographic projection of described 3rd component pole on underlay substrate and described thin-film transistor is without overlapping region.
4. array base palte as claimed in claim 1, it is characterized in that, described source electrode also comprises the 4th component pole for connecting described second component pole and described data wire.
5. array base palte as claimed in claim 4, is characterized in that, the orthographic projection on underlay substrate of the grid of the orthographic projection of described 4th component pole on underlay substrate and described thin-film transistor is without overlapping region.
6. array base palte as claimed in claim 1, is characterized in that, the second son that described drain electrode also comprises for connecting the pixel electrode on described first son drain electrode and described array base palte drains.
7. array base palte as claimed in claim 6, is characterized in that, the orthographic projection on underlay substrate of the grid of the orthographic projection of described second son drain electrode on underlay substrate and described thin-film transistor is without overlapping region.
8. array base palte as claimed in claim 1, it is characterized in that, described first component pole and the second component pole are parallel to each other.
9. array base palte as claimed in claim 8, it is characterized in that, described first component pole is vertical with described data wire respectively with the second component pole.
10. a display floater, is characterized in that, comprises the array base palte as described in any one of claim 1-9.
11. 1 kinds of display unit, is characterized in that, comprise display floater as claimed in claim 10.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610039762.1A CN105489617B (en) | 2016-01-21 | 2016-01-21 | A kind of array substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610039762.1A CN105489617B (en) | 2016-01-21 | 2016-01-21 | A kind of array substrate, display panel and display device |
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| CN105489617A true CN105489617A (en) | 2016-04-13 |
| CN105489617B CN105489617B (en) | 2019-07-05 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111522182A (en) * | 2020-05-29 | 2020-08-11 | 厦门天马微电子有限公司 | Liquid crystal display panel and array substrate thereof |
| CN112925136A (en) * | 2021-03-29 | 2021-06-08 | 绵阳惠科光电科技有限公司 | Control switch of drive circuit, array substrate and display panel |
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| CN102884633A (en) * | 2010-05-13 | 2013-01-16 | 夏普株式会社 | Circuit board and display device |
| US20130069921A1 (en) * | 2010-07-09 | 2013-03-21 | Yuhichi Saitoh | Liquid crystal display device |
| CN103730512A (en) * | 2013-12-31 | 2014-04-16 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor and display device |
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2016
- 2016-01-21 CN CN201610039762.1A patent/CN105489617B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102884633A (en) * | 2010-05-13 | 2013-01-16 | 夏普株式会社 | Circuit board and display device |
| US20130069921A1 (en) * | 2010-07-09 | 2013-03-21 | Yuhichi Saitoh | Liquid crystal display device |
| CN103730512A (en) * | 2013-12-31 | 2014-04-16 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor and display device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111522182A (en) * | 2020-05-29 | 2020-08-11 | 厦门天马微电子有限公司 | Liquid crystal display panel and array substrate thereof |
| CN111522182B (en) * | 2020-05-29 | 2022-08-12 | 厦门天马微电子有限公司 | Liquid crystal display panel and array substrate thereof |
| CN112925136A (en) * | 2021-03-29 | 2021-06-08 | 绵阳惠科光电科技有限公司 | Control switch of drive circuit, array substrate and display panel |
| CN112925136B (en) * | 2021-03-29 | 2023-03-10 | 绵阳惠科光电科技有限公司 | Control switch of drive circuit, array substrate and display panel |
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| CN105489617B (en) | 2019-07-05 |
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