TW201318197A - Method for fabricating p-type semiconductor substrate, solar cell and method for fabricating thereof - Google Patents

Abstract

A method for fabricating a p-type semiconductor substrate including follow steps is provided. A carrier is provided, and the carrier includes aIII-V compounds semiconductor layer and a III element layer disposed on the III-V compounds semiconductor layer. Si powders are disposed on the III element layer of the carrier. The carrier is heated to make the Si powders and the III element layer of the carrier form a p-type poly-Si layer. Otherwise, a solar cell and a method of fabricating thereof are also provided.

Description

Method for manufacturing P-type semiconductor substrate, solar cell and manufacturer thereof law

The present invention relates to a method of manufacturing a semiconductor substrate, a battery, and a method of manufacturing the same, and more particularly to a method of manufacturing a P-type semiconductor substrate, a solar cell, and a method of manufacturing the same.

The energy supply of fossil fuels is becoming scarcer and the burning of fossil fuels will bring environmental and air pollution. Although nuclear power generation can supply high power density, it has safety concerns about nuclear radiation and nuclear waste storage. Both of them have the problem of increasing social costs. Therefore, under the consideration and demand of open source and energy saving and development of non-polluting/low-pollution new energy industrial technologies, renewable energy is gradually gaining importance. Countries are actively studying the use of renewable energy as an alternative. The feasibility of energy.

Among the above renewable energy sources, solar cells can convert sunlight into electricity, and solar energy has become one of the mainstream energy sources. According to the current solar cell technology, it can be roughly classified into single crystal silicon, polycrystalline silicon solar cell, amorphous silicon (a-Si) thin film solar cell, and III-V solar energy. Battery and organic solar cells. In the case of polycrystalline germanium solar cells, the process steps are cumbersome, including acid-base etching, high-temperature furnace tube diffusion, plasma-assisted chemical vapor deposition, electrode screen printing, and sintering. The above processes require a large amount of equipment, energy and time costs, and the cost of this type of solar cell cannot be greatly reduced. In more detail, conventional polycrystalline germanium solar cells include a P-type semiconductor substrate. Polycrystalline germanium layer on P-type semiconductor substrate The cost accounts for more than half of the total polycrystalline silicon solar cell cost. The main reason is that nearly 90% of the polycrystalline germanium material is wasted during the slicing and polishing process of the P-type semiconductor substrate, so that the cost of the conventional polycrystalline silicon solar cell cannot be greatly reduced.

The present invention provides a method of manufacturing a P-type semiconductor substrate, which can reduce the manufacturing cost of a P-type semiconductor substrate.

The present invention provides a method of manufacturing a solar cell, which can reduce the manufacturing cost of the solar cell.

The present invention provides a method of manufacturing a P-type semiconductor substrate, which comprises the following steps. A carrier is provided which includes a III-V compound semiconductor layer and a Group III element layer on the III-V compound semiconductor layer. The tantalum powder is placed on the layer III element layer of the carrier. The carrier is heated to form a P-type polycrystalline germanium layer with the cerium powder and the group III element layer of the carrier.

The present invention provides a method of manufacturing a solar cell comprising the following steps. A carrier is provided which includes a III-V compound semiconductor layer and a Group III element layer on the III-V compound semiconductor layer. The tantalum powder is placed on the layer III element layer of the carrier. The carrier is heated to form a P-type polycrystalline germanium layer with the cerium powder and the group III element layer of the carrier. An N-type semiconductor layer is formed on the P-type polysilicon layer.

The present invention provides a solar cell comprising a carrier, a P-type polysilicon layer, and an N-type semiconductor layer. The carrier includes a III-V compound semiconductor layer. The p-type polysilicon layer is on the III-V compound semiconductor layer. The p-type polysilicon layer is between the N-type semiconductor layer and the carrier.

In one embodiment of the invention, the above method of providing a carrier comprises the following steps. A group III element substrate is provided. The group V element powder is placed on the group III element substrate. The group III element substrate is heated such that a portion of the group III element substrate forms a III-V compound layer with the group V element powder, and another portion of the group III element substrate remains on the group III-V compound layer. Heating the base of the group III element to the melting point of the group III element, and forming a portion of the portion of the group III element substrate with the group III-V compound to form a group III-V compound semiconductor layer, and the other portion Another portion of the Group III element substrate is the Group III element layer.

In one embodiment of the invention, the above method of placing a Group V element powder on a Group III element substrate comprises the following steps. The group V element powder is mixed with a solvent to form a mixed solution. This mixture was sprayed evenly onto the group III element substrate.

In one embodiment of the invention, the above method of placing the tantalum powder on the Group III element layer of the support comprises the following steps. The cerium powder is mixed with a solvent to form a mixed solution. This mixture was sprayed onto the Group III element layer of the carrier.

In one embodiment of the present invention, the step of heating the carrier to form the P-type polycrystalline germanium layer between the tantalum powder and the group III element layer of the carrier is: heating the carrier to 1400 ° C or higher, and causing the tantalum powder and the carrier group III The element layer forms a P-type polycrystalline germanium layer.

In one embodiment of the invention, the above method of providing a carrier comprises the following steps. A group III element substrate is provided. A group V element is implanted into the group III element substrate. The group V element is activated, and the group V element forms a carrier with the group III element substrate.

In an embodiment of the invention, the method for activating a group V element Including: activation of group V elements by induction heating, electromagnetic waves or optical heating.

In one embodiment of the present invention, the III-V compound semiconductor layer can be selectively removed after forming the P-type polysilicon layer described above.

In an embodiment of the invention, the method for fabricating the P-type semiconductor substrate may further include: dividing the P-type polysilicon layer into a plurality of sub-P-type polysilicon layers.

In an embodiment of the invention, the method for fabricating the P-type semiconductor substrate may further include: performing an annealing process on the sub-P-type polysilicon layer.

In an embodiment of the invention, the III-V compound semiconductor layer comprises a P-type aluminum phosphide layer, a P-type aluminum arsenide layer, a P-type aluminum telluride layer or a P-type aluminum nitride layer, and the III group The element layer includes a layer of aluminum element.

In an embodiment of the invention, the material of the N-type semiconductor layer comprises: N-type germanium oxide (n ⁺ -Si/O) supercrystal (surperlattice)

In an embodiment of the invention, the above method for manufacturing a solar cell may further include the following steps. A transparent conductive electrode is formed on the N-type semiconductor layer, and the N-type semiconductor layer is between the P-type polysilicon layer and the transparent conductive electrode.

In an embodiment of the invention, the above method for manufacturing a solar cell may further include the following steps. A reflective film is formed on the P-type polysilicon layer. The P-type polysilicon layer is between the reflective film and the N-type semiconductor layer.

In an embodiment of the invention, the solar cell described above may further comprise a transparent conductive electrode. The N-type semiconductor layer is between the P-type polysilicon layer and the transparent conductive electrode.

In an embodiment of the invention, the solar cell described above may further comprise a reflective film. The P-type polysilicon layer is between the reflective film and the N-type semiconductor layer.

Based on the above, in the process of the P-type semiconductor substrate and the solar cell according to an embodiment of the present invention, the tantalum powder is placed on the group III element layer, and the carrier is heated, so that the tantalum powder and the group III element layer form a P-type polycrystalline layer. . Therefore, compared with the prior art, the process of the P-type semiconductor substrate and the solar cell according to an embodiment of the present invention does not require sawing and grinding a large number of polycrystalline germanium layers, thereby reducing the waste of a large amount of polycrystalline germanium materials, thereby greatly reducing the P-type. Manufacturing costs of semiconductor substrates and solar cells.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a flow chart showing the manufacture of a P-type semiconductor substrate according to an embodiment of the present invention. Referring to FIG. 1, a method of manufacturing a P-type semiconductor substrate of the present embodiment includes the following steps. A carrier is provided which includes a III-V compound semiconductor layer and a group III element layer on the III-V compound semiconductor layer (step S100). The tantalum powder is placed on the group III element layer of the carrier (step S200). The carrier is heated to form a P-type polysilicon layer with the cerium powder and the Group III element layer of the carrier (step 300). Hereinafter, the manufacturing process of the P-type semiconductor substrate according to an embodiment of the present invention will be described in detail with reference to the drawings.

2 is a schematic view showing a manufacturing process of a P-type semiconductor substrate according to an embodiment of the present invention. 3A to 3F are manufacturing flows corresponding to the semiconductor substrate of FIG. Schematic diagram of the section. Referring to FIG. 2, first, a carrier 110 is provided. The carrier 110 includes a III-V compound semiconductor layer (not shown in FIG. 2) and a group III element layer (not shown in FIG. 2) on the III-V compound semiconductor layer. The III-V compound semiconductor layer of the carrier 110 has good heat resistance, and the carrier 110 can be used as a good carrier in the process of the P-type semiconductor substrate.

Hereinafter, a method of providing a carrier according to an embodiment of the present invention will be described in detail with reference to FIG. 2 and FIG. 3A to FIG. 3C. Referring to step 1 of FIG. 2 and FIG. 3A, first, a group III element substrate 102 is provided. Next, a graphite fiber belt G is formed on the group III element substrate 102. Referring to step 2 of FIG. 2 and FIG. 3B, next, the group V element 104 is implanted with the group III element substrate 102. Referring to step 3 and FIG. 3C of FIG. 2, then, the group V element 104 is heated and activated, and the group V element 104 and the group III element substrate 102 are formed into the carrier 110. In detail, as shown in FIG. 3C, after the group V element 104 is activated, a portion of the group III element substrate 102 forms a group III-V compound semiconductor layer 106 of the carrier 110 with the group V element 104, and the other portion. The portion of the group III element substrate 102 is the group III element layer 108 on the group III-V compound semiconductor layer 106. In the present embodiment, the III-V compound semiconductor layer 106 is, for example, a P-type aluminum phosphide layer, a P-type aluminum arsenide layer or a P-type aluminum nitride layer, and the III-element layer 108 is, for example, an aluminum element layer. However, the invention is not limited thereto.

As shown in step 3 of FIG. 2 and FIG. 3C, in the present embodiment, the group V element 104 can be activated by induction heating. Specifically, the induction heating coil 200 can be used to activate the V. Family element 104. In the present embodiment, the group V element 104 can be heated to 300 degrees in a chamber A. However, the present invention is not limited thereto, and in other embodiments, the group V element 104 may be activated by electromagnetic waves or optical heating.

It should be noted that the method for providing an N/P carrier of the present invention is not limited to the above (Fig. 2 and Fig. 3A to Fig. 3C), and other methods may be used to provide an N/carrier in other embodiments. The following is exemplified in conjunction with FIGS. 4A to 4D.

4A through 4D illustrate a method of providing a carrier in accordance with another embodiment of the present invention. Referring to FIG. 4A, first, a group III element substrate 102 is provided. Referring to FIG. 4B, next, the group V element powder 104 is placed on the group III element substrate 102. In detail, in the present embodiment, the method of placing the group V element powder 104 on the group III element substrate 102 includes the following steps. First, the group V element powder 104 and the solvent 103 are mixed to form a mixed liquid 101. Next, the mixed liquid 101 is uniformly sprayed on the group III element substrate 102. By this method, the group V element powder 104 can be uniformly disposed on the group III element substrate 102, and the solvent 103 sprayed on the group III element substrate 102 can be volatilized in the subsequent heating process.

Referring to FIG. 4B and FIG. 4C, next, the group III element substrate 102 is heated to form a portion of the group III element substrate 102 and the group V element powder 104 to form the group III-V compound layer 105, and the group III-V compound layer 105 is formed. Another portion of the group III element substrate 102a remains. Referring to FIG. 4C and FIG. 4D, then, the melting points of the group III element to the group III element are heated, and another part of the group III element substrate 102a is formed with the group III-V compound layer 105. - group V compound semiconductor layer 106, and another portion of group III The other portion 102b of the element substrate 102a is the group III element layer 108. The carrier 110 can be provided here.

Referring again to step 4 of FIG. 2 and FIG. 3D, after the carrier 110 is provided, the tantalum powder 120 is then placed on the group III element layer 108 of the carrier 110. In detail, in the present embodiment, the method of placing the tantalum powder 120 on the group III element layer 108 includes the following steps. First, the tantalum powder 120 and the solvent 122 are mixed to form a mixed liquid 124. Next, the mixed solution 124 is sprayed onto the group III element layer 108 of the carrier 110. By this method, the tantalum powder 120 can be uniformly disposed on the group III element layer 108, thereby forming a P-type semiconductor substrate of excellent quality.

Referring to step 5 and FIG. 3E of FIG. 2 again, the carrier 110 is heated to form the P-type polysilicon layer 130 with the tantalum powder 120 and the group III element layer 108. Specifically, in the present embodiment, the step of heating the carrier 110 to form the P-type polysilicon layer 130 between the tantalum powder 120 and the group III element layer 108 is as follows: rapidly heating the carrier 110 to 1430 ° C (ie, reaching and exceeding the tantalum powder) 102 has a melting point of 1.414 ° C) or more, and the tantalum powder 120 and the group III element layer 108 form a p-type polysilicon layer 130. Thus, the process of the P-type semiconductor substrate 100 of the present embodiment is initially completed. It is worth mentioning that, compared with the prior art, the process of the P-type semiconductor substrate 100 of the present embodiment does not need to grind a large number of polysilicon layers, thereby reducing material waste, thereby greatly reducing the manufacturing cost of the P-type semiconductor substrate. .

Referring again to step 6 of FIG. 2 and FIG. 3E, a plurality of sub-P-type polysilicon layers 130a may be stacked in a cavity B filled with hydrogen (H ₂ ) and having a temperature of 1350 degrees for an annealing process. Referring again to steps 7 and 8 of FIG. 2, the sub-P-type polysilicon layer 130a in the cavity may be moved to another cavity C for cooling (steps 6 to 7), and then the sub-P-type polysilicon Layer 130a can be sequentially ejected from the cavity (steps 7 through 8).

Referring to step 9 of FIG. 2 and FIG. 3F, the manufacturer can visually determine the solar cell size required, and the P-type polysilicon layer 130 can be divided into a plurality of sub-P-type polysilicon layers 130a. In the present embodiment, the P-type polysilicon layer 130 may be divided into a plurality of sub-P-type polysilicon layers 130a using a laser. The size of the sub-P-type polysilicon layer 130a is, for example, 5 cm in 5 cm. Referring again to step 10 of FIG. 2, the cut sub-P-type polysilicon layer 130a is packaged and stored in pure nitrogen for transportation.

The P-type semiconductor substrate 100 of the present embodiment can be further fabricated as a solar cell. In detail, after the P-type polysilicon layer is completed, an N-type semiconductor layer can be formed on the P-type polysilicon layer to form a solar cell.

This will be described in detail below with reference to FIGS. 5A to 5B. 5A to 5B illustrate a process in which a P-type semiconductor substrate is fabricated into a solar cell according to an embodiment of the present invention.

As shown in FIG. 3F, after the P-type polysilicon layer 130 is completed, in the present embodiment, the manufacturer can divide the P-type polysilicon layer 130 into a plurality of sub-P-type polysilicon layers 130a depending on the actual required solar cell size.

Next, as shown in FIG. 5A, these sub-P-type polysilicon layers 130a may be subjected to an annealing process. Then, a plurality of N-type semiconductor layers 140 may be formed on the sub-P-type polysilicon layers 130a, respectively. The material of the N-type semiconductor layer 140 is, for example, an N-type germanium oxide (n ⁺ -Si/O) superlattice or other suitable material. It is worth mentioning that N-type niobium oxide (n ⁺ -Si/O) in 1.8 electron volt (eV) band or N-type aluminum telluride in n 2 electron volt (eV) band (n ⁺ -AlSb) can form a steep hetero-junction barrier with the P-type polysilicon layer 130 of the 1.1 electron volt (eV) band. This steep heterogeneous interface barrier can reduce the leakage of the solar cell with this barrier to increase the photoelectric conversion efficiency. In other words, a steep heterogeneous interface barrier can significantly reduce the cost per watt of solar cells.

In the present embodiment, the sub-P-type polysilicon layer 130a may be annealed using an Atomic Layer Deposition (ALD) instrument and an N-type semiconductor layer 140 may be formed on the sub-P-type polysilicon layer 130a. The N-type semiconductor layer 140 can be formed on the sub-P-type polysilicon layer 130a in a large amount and quickly by the ALD instrument.

As shown in FIG. 5B, after the N-type semiconductor layer 140 is formed on the sub-P-type polysilicon layer 130a, the transparent conductive electrode 150 can be selectively formed on the N-type semiconductor layer 140. The N-type semiconductor layer 140 is located between the sub-P-type polysilicon layer 130a and the transparent conductive electrode 150. Next, a reflective film 160 may be selectively formed on the sub-P-type polysilicon layer 130a. The sub-P-type polysilicon layer 130a is located between the reflective film 160 and the N-type semiconductor layer 140. The reflective film 160 can increase the transmission path of the incident light in the solar cell 100A, thereby increasing the photoelectric conversion efficiency of the solar cell 100A.

Fig. 5B shows a solar cell according to an embodiment of the present invention. The solar cell 100A of the present embodiment includes a carrier, a P-type polysilicon layer 130a, and an N-type semiconductor layer 140. The carrier 110 includes a III-V compound semiconductor layer 106. The sub-P-type polysilicon layer 130a is on the III-V compound semiconductor layer 106. The solar cell 100A of the present embodiment may further include a transparent conductive electrode 150. The N-type semiconductor layer 140 is located in the P-type polysilicon layer 130a and Between the transparent conductive electrodes 150. The solar cell 100A of the present embodiment further includes a reflective film 160. The P-type polysilicon layer 130a is located between the reflective film 160 and the N-type semiconductor layer 140. The solar cell 100A of the present embodiment has an advantage of low manufacturing cost and high photoelectric conversion efficiency.

In summary, in the process of the P-type semiconductor substrate and the solar cell according to an embodiment of the present invention, the tantalum powder is placed on the group III element layer, and the carrier is heated, so that the tantalum powder and the group III element layer form a P-type. Polycrystalline germanium layer. Therefore, compared with the prior art, the process of the P-type semiconductor substrate and the solar cell according to an embodiment of the present invention does not require sawing and wastes a large amount of polycrystalline germanium layer, thereby reducing the waste of a large amount of polycrystalline germanium material, thereby substantially reducing the P-type semiconductor. Manufacturing costs of substrates and solar cells.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧P type semiconductor substrate

100A‧‧‧ solar cells

101, 124‧‧‧ mixture

102‧‧‧III elemental substrate

102a‧‧‧Other part of the III element base

102b‧‧‧Another part of the other part of the group III element

103, 122‧‧‧ solvent

104‧‧‧V element (powder)

105‧‧‧III-V compound layer

106‧‧‧III-V compound semiconductor layer

108‧‧‧III elemental layer

110‧‧‧ Carrier

120‧‧‧矽 powder

130‧‧‧P-type polycrystalline layer

130a‧‧‧P-type polycrystalline layer

140‧‧‧N type semiconductor layer

150‧‧‧Transparent conductive electrode

160‧‧‧Reflective film

200‧‧‧Induction heating coil

A, B, C‧‧‧ cavity

G‧‧‧Graphite fiber conveyor belt

S100~S300‧‧‧Steps

1 is a flow chart showing the manufacture of a P-type semiconductor substrate according to an embodiment of the present invention.

2 is a schematic view showing a manufacturing process of a P-type semiconductor substrate according to an embodiment of the present invention.

3A to 3F are schematic cross-sectional views showing a manufacturing process of the semiconductor substrate corresponding to FIG. 2.

4A through 4D illustrate a method of providing a carrier in accordance with another embodiment of the present invention.

5A to 5B illustrate a process in which a P-type semiconductor substrate is fabricated into a solar cell according to an embodiment of the present invention.

102‧‧‧III elemental substrate

104‧‧‧V element (powder)

120‧‧‧矽 powder

A, B, C‧‧‧ cavity

G‧‧‧Graphite fiber conveyor belt

Claims (28)

A method for fabricating a P-type semiconductor substrate, comprising: providing a carrier comprising a III-V compound semiconductor layer and a group III element layer on the III-V compound semiconductor layer; placing a tantalum powder And constituting the group III element layer of the carrier; and heating the carrier to form a p-type polysilicon layer with the group III element layer of the carrier. The method for producing a P-type semiconductor substrate according to claim 1, wherein the method for providing the carrier comprises the steps of: providing a group III element substrate; and placing a group V element powder on the group III element substrate; Heating the group III element substrate to combine a portion of the group III element substrate with the group V element powder to form a group III-V compound layer, and leaving another portion of the group III element on the group III-V compound layer a substrate; and heating the group III element substrate to a melting point of the group III element such that a portion of the other group of the group III element substrate forms the group III-V compound with the group III-V compound a semiconductor layer, and another portion of the other portion of the group III element substrate is the group III element layer. The method for producing a P-type semiconductor substrate according to claim 2, wherein the method of placing the group V element powder on the group III element substrate comprises the steps of: using the group V element powder and a first solvent Mixing into a first mixed liquid; and uniformly spraying the first mixed liquid on the group III element substrate. The method for producing a P-type semiconductor substrate according to claim 1, wherein the method of placing the tantalum powder on the group III element layer of the carrier comprises the steps of: mixing the tantalum powder with a second solvent Forming a second mixed liquid; and spraying the second mixed liquid onto the group III element layer of the carrier. The method for producing a P-type semiconductor substrate according to claim 1, wherein the step of heating the carrier to form the P-type polysilicon layer with the lanthanum powder and the group III element layer of the carrier is: heating the carrier Up to 1400 ° C or higher, the bismuth powder and the group III element layer of the carrier form the P-type polysilicon layer. The method for producing a P-type semiconductor substrate according to claim 1, wherein the method for providing the carrier comprises the steps of: providing a group III element substrate; implanting a group V element into the group III element substrate; and activating The group V element causes the group V element to form the carrier with the group III element substrate. The method of manufacturing a P-type semiconductor substrate according to claim 6, wherein the method of activating the group V element comprises: activating the group V element by induction heating, an electromagnetic wave, or optical heating. The method of manufacturing a P-type semiconductor substrate according to claim 7, wherein when the group V element is activated, the group V element and the group III element substrate are allowed to enter a nitrogen chamber. The system for manufacturing a P-type semiconductor substrate as described in claim 1 The method further includes: removing the III-V compound semiconductor layer after forming the P-type polysilicon layer. The method of manufacturing a P-type semiconductor substrate according to claim 9, wherein the method of removing the III-V compound semiconductor layer comprises: reacting the III-V compound semiconductor layer with the water to form (III) ₂ O ₃ and H ₃ (V), wherein III represents a group III element and V represents a group V element. The method for fabricating a P-type semiconductor substrate according to claim 1, further comprising dividing the P-type polysilicon layer into a plurality of sub-P-type polysilicon layers. The method for fabricating a P-type semiconductor substrate according to claim 11, further comprising: performing an annealing process on the plurality of sub-P-type polysilicon layers. The method for fabricating a P-type semiconductor substrate according to claim 1, wherein the III-V compound semiconductor layer comprises a P-type aluminum phosphide layer, a P-type aluminum arsenide layer or a P-type aluminum nitride. a layer, and the group III element layer comprises an aluminum element layer. A method of manufacturing a solar cell, comprising: providing a carrier comprising a III-V compound semiconductor layer and a layer III element layer on the III-V compound semiconductor layer; placing a tantalum powder on the carrier On the group III element layer; heating the carrier to form a p-type polysilicon layer with the group III element layer of the carrier; and forming an N-type semiconductor layer on the p-type polysilicon layer. The method for producing a solar cell according to claim 14, wherein the method for providing the carrier comprises the steps of: providing a group III element substrate; placing a group V element powder on the group III element substrate; heating the a group III element substrate such that a portion of the group III element substrate forms a III-V compound layer with the group V element powder, and another portion of the group III element substrate remains on the group III-V compound layer; And heating the base of the group III element to a melting point of the group III element, and forming a portion of the group III element substrate of the other portion and the group III-V compound layer to form the group III-V compound semiconductor layer And another portion of the other portion of the group III element substrate is the group III element layer. The method for producing a solar cell according to claim 15, wherein the method of placing the group V element powder on the group III element substrate comprises the steps of: mixing the group V element powder with a first solvent to form a a first mixed liquid; and uniformly spraying the first mixed liquid on the group III element substrate. The method for manufacturing a solar cell according to claim 14, wherein the step of heating the carrier to form the P-type polysilicon layer with the lanthanum powder and the group III element layer of the carrier is: heating the carrier to 1400 Above the °C, the bismuth powder and the group III element layer of the carrier form the P-type polysilicon layer. The method for producing a solar cell according to claim 14, wherein the tantalum powder is placed on the group III element layer of the carrier. The method comprises the steps of: mixing the niobium powder with a second solvent to form a second mixture; and spraying the second mixture onto the group III element layer of the carrier. The method for producing a solar cell according to claim 14, wherein the method for providing the carrier comprises the steps of: providing a group III element substrate; implanting a group V element into the group III element substrate; and activating the V a group element such that the group V element forms a carrier with the group III element substrate. The method of manufacturing a solar cell according to claim 14, wherein the method of activating the group V element comprises: activating the group V element by induction heating, an electromagnetic wave or optical heating. The method for fabricating a solar cell according to claim 14, further comprising: removing the III-V compound semiconductor layer after forming the P-type polysilicon layer. The method for manufacturing a solar cell according to claim 14, further comprising: performing an annealing process on the P-type polysilicon layer. The method for manufacturing a solar cell according to claim 14, wherein the material of the N-type semiconductor layer comprises: N-type cerium oxide (n ⁺ -Si/O) superlattice. The method for manufacturing a solar cell according to claim 14, further comprising: forming a transparent conductive electrode on the N-type semiconductor layer, wherein the N-type semiconductor layer is located on the P-type polysilicon layer and the transparent conductive electrode between. The method for fabricating a solar cell according to claim 24, further comprising: forming a reflective film on the P-type polysilicon layer, the P-type polysilicon layer being located between the reflective film and the N-type semiconductor layer. A solar cell comprising: a carrier comprising a III-V compound semiconductor layer; a P-type polysilicon layer on the III-V compound semiconductor layer; and an N-type semiconductor layer, the P-type polysilicon layer being located Between the N-type semiconductor layer and the carrier. The solar cell of claim 26, further comprising: a transparent conductive electrode, the N-type semiconductor layer being located between the P-type polysilicon layer and the transparent conductive electrode. The solar cell of claim 26, further comprising: a reflective film, the P-type polysilicon layer being between the reflective film and the N-type semiconductor layer.