TW201318166A - Trenched power mosfet with enhanced breakdown voltage and fabrication method thereof - Google Patents

Abstract

A trenched power mosfet with enhanced breakdown voltage is provided. The trenched power mosfet has a first trench penetrating the body region located between two neighboring gate trenches. A polysilicon structure with a conductivity type identical to that of the body region is located in a lower portion of the first trench and spaced from the body region with a predetermined distance. A dielectric structure is located on the polysilicon structure and at least extended to the body region. Source regions are located in an upper portion of the body region. A heavily doped region located in the body region. A conductive structure is electrically connected to the heavily doped region and the source region.

Description

Trench type power semiconductor device for improving breakdown voltage and manufacturing method thereof

The present invention relates to a trench type power semiconductor device and a method of fabricating the same, and more particularly to a trench type power semiconductor device for improving a breakdown voltage and a method of fabricating the same.

Under the emphasis on energy saving, the application of power semiconductor components is also paying more and more attention to the performance of its on-resistance. In general, the improvement in on-resistance helps to reduce the conduction loss of the circuit operation, but the reduction in on-resistance is inevitably accompanied by a decrease in the breakdown voltage. Any adjustment of the on-resistance by adjusting the doping concentration or changing the thickness of the epitaxial layer may adversely affect the reliability of the structure.

Therefore, it is an important subject in the art to find a trench type power semiconductor device capable of increasing the breakdown voltage while ensuring the reliability of its structure.

In view of this, the main object of the present invention is to provide a trench type power semiconductor device which improves the breakdown voltage and a method of fabricating the same, while maintaining the reliability of its structure.

To achieve the above object, the present invention provides a trench type power semiconductor device that increases a breakdown voltage. In a preferred embodiment, the trench power semiconductor device for increasing the breakdown voltage includes a substrate, at least two gate trenches, a first dielectric layer, a first polysilicon structure, and at least a first trench, a second polysilicon structure, a first conductivity type body region, a second conductivity type source region, a first conductivity type heavily doped region and a source metal layer. Wherein the gate trench is located in the substrate. The first dielectric layer covers the inside surface of the gate trench. The first polysilicon structure is located within the gate trench. The first trench is located between adjacent two gate trenches. The body region of the first conductivity type is located between the gate trenches. The first groove extends through the body region and extends below the body region. The second polysilicon structure of the first conductivity type is filled into the lower portion of the first trench. The second polysilicon structure is located below the body region and spaced apart from the body region by a predetermined distance. The source region of the second conductivity type is located above the body region. The second conductivity type is opposite in electrical polarity to the first conductivity type. The heavily doped region of the first conductivity type is located within the body region. The source metal layer is electrically connected to the heavily doped region and the source region.

The present invention also provides a method of fabricating the trench power semiconductor device. In a preferred embodiment, the method of fabricating the trench power semiconductor device comprises at least the steps of: (a) providing a substrate; (b) forming at least two gate trenches in the substrate; Forming a first dielectric layer covering the inner side surface of the gate trench; (d) forming a first polysilicon structure in the gate trench; (e) forming at least one first trench adjacent to the two Between the gate trenches; (f) forming a second polysilicon structure of the first conductivity type in a lower portion of the first trench; (g) forming a first conductivity type body region between the gate trenches In the substrate, the first trench extends downward to below the body region, and the second polysilicon structure is located below the body region and spaced apart from the body region by a predetermined distance; (h) forming a source of the second conductivity type The pole region is on an upper portion of the body region; (i) forming an interlayer dielectric layer covering the first polysilicon structure, and defining a source contact window at the corresponding first trench using the interlayer dielectric layer; j) forming a heavily doped region of the first conductivity type in the body region; and (k) filling a source metal layer in the source contact window to electrically dope heavily doped The source region.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

1A to 1H are views showing a first embodiment of a method of manufacturing a trench type power semiconductor device for improving a breakdown voltage according to the present invention. In the figure, an n-type trench power semiconductor device will be described as an example. However, the invention is not limited thereto. The technique of the present invention can of course also be applied to p-type power semiconductor elements.

As shown in FIG. 1A, first, an n-type epitaxial layer 110 is formed on an n-type substrate 100 to form a substrate on which a trench type power semiconductor device is formed. Subsequently, at least two gate trenches 120 are formed in the epitaxial layer 110. Next, as shown in FIG. 1B, along the surface of the epitaxial layer 110, a first dielectric layer 130 is formed to cover the inner surface of the gate trench 120. Then, a first polysilicon structure 140 is formed in the gate trench 120 as the gate polysilicon structure of the trench power semiconductor device of the present embodiment.

Then, as shown in FIG. 1C, a p-type body region 150 is formed in the epitaxial layer 110 by ion implantation to surround each of the gate trenches 120. Next, an n-type source region 160 is formed on an upper portion of the body region 150 by ion implantation. This source region 160 is adjacent to the gate trench 120. Subsequently, as shown in FIG. 1D, a pattern layer 165 is formed on the epitaxial layer 110. The pattern layer 165 defines a first trench in the epitaxial layer 110 between the adjacent two gate trenches 120. . Then, as shown in FIG. 1E, a p-type heavily doped region 180 is formed under the source region 160 by ion implantation through the opening of the pattern layer 165. The p-type heavily doped region 180 will have a range slightly greater than the opening width.

Next, as shown in FIG. 1F, the first trench 170 is formed by etching in the epitaxial layer 110 by using the pattern layer 165 as an etch mask. The first trench 170 extends through the body region 150 and divides the source region 160 and the p-type heavily doped region 180 into two portions, respectively. Subsequently, a p-type lightly doped second polysilicon structure 172 is formed over the lower portion of the first trench 170. The upper surface of the second polysilicon structure 172 is spaced from the body region 150 by a predetermined distance to prevent the second polysilicon structure 172 from being connected to the body region 150.

Subsequently, as shown in FIG. 1G, a dielectric structure 174 is formed in the first trench 170. The dielectric structure 174 is located above the second polysilicon structure 172 and its location extends downwardly from the body region 150 below the body region 150. Next, as shown in FIG. 1H, a source metal layer 190 is formed over the pattern layer 165 and filled in the first trench 170 to connect the heavily doped region 180 and the source region 160. The pre-exposed pattern layer 165 separates the source metal layer 190 from the first polysilicon structure 140 as an inter-layer dielectric layer.

In this embodiment, a p-type floating doped region is formed under the body region 150 through the fabrication of the p-type second polysilicon structure 172 to relieve the electric field distribution between the bottom and the drain of the gate trench 120, thereby facilitating To improve the breakdown voltage. Based on this, the embodiment can increase the implantation depth of the p-type heavily doped region 180, and even allow the p-type heavily doped region 180 to extend down to the bottom surface of the body region 150, without fear that the structure causes the breakdown voltage to be too low. The problem arises.

Fig. 2 is a view showing a second embodiment of the manufacturing method of the trench type power semiconductor device for improving the breakdown voltage of the present invention. The main difference between this embodiment and the first embodiment of the present invention is the manner in which the p-type heavily doped region 180 is fabricated. In the present embodiment, the p-type heavily doped region 180 is not formed under the source region 160 by ion implantation, but a p-type heavily doped polysilicon structure 276 is first formed over the dielectric structure 274, and then applied. The thermal diffusion step forms a p-type heavily doped region 180 on the side of the p-type heavily doped polysilicon structure 276.

3A and 3B are views showing a third embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage. The main difference between this embodiment and the first embodiment of the present invention is that the present embodiment does not form the dielectric structure 174 over the second polysilicon structure 172, but forms the n-type third polysilicon structure 175. Inside a trench 170. 3A is a manufacturing step of receiving the FIG. 1F, and as shown in the drawing, after forming the second polysilicon structure 172 at a lower portion of the first trench 170, an n-type third polysilicon structure is formed. 175 is over the second polysilicon structure 172 and extends at least upwardly to the body region 150. Subsequently, as shown in FIG. 3B, a source metal layer 190 is formed over the pattern layer 165 and filled into the first trench 170 to connect the heavily doped region 180 with the source region 160. With the structure of the trench power semiconductor device of the present embodiment, a Schottky diode is formed on the interface between the source metal layer 190 and the n-type third polysilicon structure 175, and Helps improve the switching speed of power semiconductor components.

Fig. 3C is a view showing a fourth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage. The main difference between this embodiment and the first embodiment of the present invention is that the dielectric structure 174 is not formed over the second polysilicon structure 172, but a metal plug is formed in the first trench 170. . This metal plug is located above the second polysilicon structure 172 and extends at least upwardly to the body region 150. As shown in the figures, in a preferred embodiment, a source metal layer 190' can be formed directly into the first trench 170 to form the metal plug. Similar to the third embodiment of the present invention, with respect to the structure of the trench type power semiconductor device of the present embodiment, the interface of the n-type epitaxial layer 110 under the source metal layer 190' and the p-type body region 150 is provided. The Schottky diode is also formed, which helps to improve the switching speed of the power semiconductor components.

4A to 4C are a fifth embodiment of a method of manufacturing a trench type power semiconductor device with improved breakdown voltage according to the present invention. Figure 4A is a diagram of the process of undertaking Figure 1D. After the first trench 170 and the p-type second polysilicon structure 172 are formed, the pattern layer 165 overlying the epitaxial layer 110 is removed. Then, a dielectric layer 375 is deposited on the epitaxial layer 110 while filling the first trench 170.

Next, as shown in FIG. 4B, an opening is formed in the dielectric layer 375 to define the source contact window 377 by photolithography. The opening is aligned with the first trench 170 and has a width greater than the opening width of the first trench 170. It should be noted that this etching step simultaneously removes excess dielectric material in the first trench 170 to form the dielectric structure 374. Next, as shown in FIG. 4C, the dielectric layer 375 overlying the first polysilicon structure 140 is used as a mask, and the bottom surface of the deep source contact window 377 is pushed down in an etched manner. Then, a p-type heavily doped region 380 is formed by ion implantation at the bottom of the source contact window 377. The p-type heavily doped regions 380 are on either side of the dielectric structure 374, and the bottom of the p-type heavily doped regions 380 extends down to the bottom surface of the body region 150. The subsequent steps of this embodiment are substantially the same in the foregoing embodiments, and are not described herein.

5A and 5B are views showing a sixth embodiment of the method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention. The step of FIG. 5A is substantially the same as the step of the first trench 170. However, the p-type heavily doped region 480 of the embodiment is formed on both sides of the first trench 170 after the first trench 170 is completed. . As shown in FIG. 5A, after forming the dielectric structure 174, the pattern layer 465 overlying the first polysilicon structure 140 is etched by an isotropic etching technique to enlarge the opening width of the pattern layer 465. This enlarged opening serves as the source contact window 477. Then, as shown in Fig. 5B, the etched pattern layer 465' is used as a mask to push down the bottom surface of the deep source contact window 477. Next, a p-type heavily doped region 480 is formed on the bottom surface of the source contact window 477 by ion implantation.

Fig. 6 is a seventh embodiment of a method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention. After the opening width of the pattern layer 465 is expanded in an etching manner, the heavily doped region 480 is formed in the bottom of the source contact window by ion implantation. As shown in FIG. 6, the embodiment is as shown in FIG. The pattern layer 165 and the dielectric structure 174 are used as a mask, and the p-type heavily doped region 580 is formed directly on both sides of the first trench 170 by oblique ion implantation.

7A and 7B are diagrams showing an eighth embodiment of a method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention. After the position of the first trench 170 is defined by the pattern layer 465, the opening width of the pattern layer 465 is expanded by etching to form a source contact window, as shown in FIGS. 7A and 7B. As shown in the present embodiment, a spacer layer structure 667 is formed on the sidewall of the opening of the pattern layer 665 to define the first trench 170. After the fabrication of the first trench 170 is completed, the present embodiment directly strips the spacer layer structure 667 covering the sidewall of the opening of the pattern layer 665, and defines the position of the source contact window 677 by the opening of the pattern layer 665.

8A and 8E are diagrams showing a ninth embodiment of a method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention. Compared with the manufacturing method of the foregoing embodiments, the gate trench 120 is completed first, and the first trench 170 is formed between the adjacent two gate trenches 120. This embodiment is completed. After the fabrication of a trench, a gate trench is formed on both sides.

As shown in FIG. 8A, first, a first trench 770 is formed in the epitaxial layer 110. Subsequently, a second polysilicon structure 772 is formed over the lower portion of the first trench 770. Next, as shown in FIG. 8B, a dielectric pattern layer 765 is entirely deposited. The dielectric pattern layer 765 fills the first trench 770 and defines a gate trench 720 on each side of the first trench 770. Subsequently, the epitaxial layer 110 is etched through the dielectric pattern layer 765 to form the gate trench 720.

Next, as shown in FIG. 8C, the excess dielectric material is removed by etching leaving the dielectric structure 774 located within the first trench 770. Then, as shown in FIG. 8D, the first dielectric layer 730 and the first polysilicon structure 740 are sequentially formed in the gate trench 720. Next, the p-type body 750 and the n-type source region 760 are sequentially formed between the adjacent trenches 720, 770 by ion implantation.

Subsequently, as shown in FIG. 8E, an interlayer dielectric layer 775 is formed on the epitaxial layer 110, and an opening alignment alignment trench 770 is formed in the interlayer dielectric layer 775 to define a source contact. Window 777. The width of the opening is greater than the opening width of the first trench 770. Then, the epitaxial layer 110 is etched through the opening of the interlayer dielectric layer 775 to form a source contact window 777 over the dielectric structure 774. Next, a p-type doping is implanted at the bottom of the source contact window 777 by ion implantation to form a p-type heavily doped region 780 on both sides of the dielectric structure 774.

In some of the foregoing embodiments, the p-type heavily doped region extends down to the bottom surface of the body region 150 to enhance the dynamic characteristics of the trench power semiconductor device. However, the invention is not limited thereto. The p-type heavily doped region also extends further below the body region 150 or a distance above the bottom surface of the body region 150, depending on actual requirements. In a preferred embodiment, the bottom surface of the p-type heavily doped region needs to be above the lower edge of the dielectric structure 174 to maintain an appropriate breakdown voltage value.

Next, in the foregoing embodiments of the present invention, the lower portion of the first trench 170 is formed with a second polysilicon structure. However, the invention is not limited thereto. In a preferred embodiment, the present invention can also omit fabrication of the second polysilicon structure while fabricating a dielectric structure directly within the first trench 170. The dielectric structure that protrudes downward from the bottom surface of the body region also contributes to improving the electric field distribution between the gate trench and the drain to increase the breakdown voltage.

9A to 9E are diagrams showing a tenth embodiment of a method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention. In the foregoing embodiments, the first trench 170 and the gate trench 120 are respectively formed in the epitaxial layer 110 by using different etching steps. In this embodiment, the gate is formed by the same etching step. The pole trench 820a and the first trench 820b. Also, in the present embodiment, the gate trench 820a has substantially the same depth as the first trench 820b.

As shown in FIG. 9A, first, the gate trench 820a and the first trench 820b are formed in the epitaxial layer 110 by photolithography. Next, as shown in FIG. 9B, a first dielectric layer 830 is formed to cover the inner side surfaces of the respective trenches 820a, 820b. Then, a first polysilicon structure 840a, 840b is formed in each of the trenches 820a, 820b. Then, as shown in FIG. 9C, the p-type body region 150 is sequentially formed in the epitaxial layer 110 and the n-type source region 160 above the body region 150 by ion implantation. Subsequently, a photoresist pattern layer 865 is formed to cover the first polysilicon structure 840a located in the gate trench 820a, and the first polysilicon structure 840b located in the first trench 820b is removed through an etching step. Then, a dielectric structure 835 is filled in the first trench 820b.

Next, as shown in FIG. 9D, after the photoresist pattern layer 865 is removed, an interlayer dielectric layer 875 is formed to cover the first polysilicon structure 840a located in the gate trench 820a. An opening is then formed in the interlayer dielectric layer 875 by photolithography to define the extent of the source contact window 877. The opening is substantially aligned with the first trench 820b and has a width greater than the opening width of the first trench 820b. Then, the epitaxial layer 110 is etched through the opening of the interlayer dielectric layer 875 to form a source contact window 877. Next, as shown in FIG. 9E, a heavily doped region 880 is formed at the bottom of the source contact window 877 by ion implantation. Then, a conductive structure 890 is filled in the source contact window 877 to complete the manufacturing process.

In this embodiment, only one dielectric structure 835 is formed in the first trench 820b, and there is no second polysilicon structure as in the foregoing embodiments. The presence of this dielectric structure 835 also helps to improve the electric field distribution to increase the breakdown voltage. Next, as shown in FIG. 9F, this embodiment can also fabricate an additional second polysilicon structure 872 under the dielectric structure 835. However, a dielectric structure 835 is required between the second polysilicon structure and the body region 150 to be spaced apart.

10A, 10B, and 10C are three other different embodiments of the method of fabricating the p-type heavily doped region 880 of Figure 9E. As shown in FIG. 10A, in this embodiment, a p-type heavily doped polysilicon structure 876 is formed before the bottom of the source contact window 877, and then a p-type heavily doped region 880 is formed by a thermal diffusion process to form a p-type heavily doped. The heteropolycrystalline structure is around 876. As shown in FIG. 10B, in this embodiment, the bottom surface of the source contact window is pushed down to the side of the dielectric structure 835. That is, the dielectric structure 835 protrudes upward from the bottom surface of the source contact window. Subsequently, a p-type heavily doped region 880 is formed by ion implantation into the body region 150 on both sides of the dielectric structure 835. It should be noted that since the source contact window 877 of the embodiment is deep into the body region 150, the implantation depth of the ion implantation step does not need to be too deep, so that the heavily doped region 880 extends downward to The bottom surface of the body region 150. As shown in FIG. 10C, the source contact window 877 of the present embodiment is deep below the body region 150, and the bottom of the source contact window 877 exposes the n-type epitaxial layer 110 under the body region 150. The p-type heavily doped region 880' is formed on both sides of the source contact window 877 in an oblique ion implantation manner. It is noted that since the dielectric structure 835 protrudes from the bottom surface of the source contact window 877, the dielectric structure 835 can prevent the oblique ion implantation step from implanting the p-type dopant into the bottom of the source contact window 877. Thereby, a Schottky diode structure can be formed on the bottom surface of the source contact window 877 through the subsequent source metal deposition step to increase the switching speed of the power semiconductor device. Secondly, in this embodiment, in addition to the oblique ion implantation step, a forward ion implantation step may be additionally applied, and an n-type dopant is implanted at the bottom of the source contact window 877 to form an n-type heavily doped region 882. The source contact window 877 is below to further reduce the turn-on voltage of the Schottky diode structure.

Fig. 11 is an eleventh embodiment of a method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention. In contrast to the embodiment of FIG. 10C, this embodiment further deepens the source contact window 877 such that the side of the source contact window 877 extends below the body region 150. In addition, the present embodiment forms a p-type doping region 873 at the bottom of the source contact window 877 by ion implantation. After the subsequent source metal deposition step, the present embodiment can form a Schottky diode structure on the side of the lower portion of the source contact window 877 to increase the switching speed of the power semiconductor device. In addition, a p-type doped region (p-type polysilicon structure) 873 formed under the source contact window 877 helps to alleviate the electric field distribution to improve the breakdown voltage.

12A to 12C are a twelfth embodiment of a method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention. Different from the embodiments of FIGS. 9B and 9C, after the first polysilicon structure 840b located in the first trench 820b is selectively etched by the photoresist pattern layer 865, the photoresist pattern layer 865 is removed, such as As shown in FIG. 12A, in this embodiment, the pattern layer 865 is formed by using a general dielectric material, and after the first polysilicon structure 840b is removed, the pattern layer 865 is left, and a dielectric layer 965 is directly formed to cover the pattern layer. 865 and fills the first trench 820b.

Subsequently, as shown in FIG. 12B, unnecessary dielectric material is removed to form dielectric structure 935 within first trench 170. It should be noted that this etching step simultaneously removes the dielectric layer 965 overlying the pattern layer 865. Further, if a material having a similar etching property as the dielectric layer 965 is selected as the pattern layer 865, the etching step simultaneously removes part of the pattern layer 865 to form an appearance as shown in the drawing. Subsequently, as shown in FIG. 12C, the epitaxial layer 110 is etched through the opening of the pattern layer 865 to form a source contact window 977. The heavily doped region 980 is then formed by ion implantation at the bottom of the source contact window 977. Next, a conductive structure (not shown) is formed in the source contact window 977, and the heavily doped region 980 and the source region 160 are electrically connected to complete the manufacturing process of the embodiment.

In the foregoing various embodiments, the p-type heavily doped region is located at the bottom of the source contact window and is located substantially below the source region. However, the invention is not limited thereto. As shown in FIG. 13, the p-type heavily doped region 1080 and the source region 1060 may also be alternately arranged on the surface layer of the body region 150. As for the manufacturing method of the p-type heavily doped region 1080 and the source region 1060 in this embodiment, except for the two lithography steps, the positions of the heavily doped region and the source region are respectively defined in the surface layer of the body region 150. In addition, and separately applied to the ion implantation step; only one lithography step can be used to define the position of the heavily doped region or the source region. For example, an n-type dopant may be fully implanted on the surface layer of the body region 150, and then the range of the heavily doped region is defined by a lithography step, and a high concentration is implanted within the defined range. The p-type dopant converts the conductivity type of the implanted region from n-type to p-type. Thereby, the heavily doped region and the source region which are alternately arranged can be formed. The foregoing embodiment utilizes a lithography step to define the extent of the heavily doped region and to fully implant the n-type dopant prior to the surface layer of the body prior to the step of defining the heavily doped region. However, the invention is not limited thereto. This lithography step can also be used to define the extent of the source region, and the aforementioned full implantation step can also be implanted with a p-type dopant.

As described above, the method of fabricating the trench power semiconductor device of the present invention can self-align the first trench to the P-type heavily doped region to avoid the occurrence of alignment errors. Secondly, the second polysilicon structure and the dielectric structure formed in the lower portion of the first trench in the embodiment help to improve the electric field distribution between the gate trench and the drain. At the same time, a good balance can be achieved between the improvement of the dynamic characteristics of the trench power semiconductor device and the maintenance of the breakdown voltage by the combination of the heavily doped regions formed on both sides of the dielectric structure and extending to the bottom surface of the body.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

100. . . Substrate

110. . . Epitaxial layer

120. . . Gate trench

130. . . First dielectric layer

140. . . First polycrystalline structure

150. . . Body area

160. . . Source area

165. . . Pattern layer

180. . . Heavily doped region

170. . . First groove

172. . . Second polycrystalline structure

174. . . Dielectric structure

175. . . Polycrystalline germanium structure

190,190’. . . Conductive structure

276. . . Heavy doped polysilicon structure

274. . . Dielectric structure

375. . . Dielectric layer

377. . . Source contact window

374. . . Dielectric structure

380. . . Heavily doped region

480. . . Heavily doped region

465,465’. . . Pattern layer

580. . . Heavily doped region

665. . . Pattern layer

667. . . Spacer structure

677. . . Source contact window

770. . . First groove

772. . . Second polycrystalline structure

765. . . Dielectric pattern layer

777. . . Source contact window

720. . . Gate trench

774. . . Dielectric structure

730. . . First dielectric layer

740. . . First polycrystalline structure

750. . . Body area

760. . . Source area

775. . . Interlayer dielectric layer

780. . . Heavily doped region

820a. . . Gate trench

820b. . . First groove

830. . . First dielectric layer

840a, 840b. . . First polycrystalline structure

865. . . Photoresist pattern layer

835. . . Dielectric structure

872. . . Second polycrystalline structure

873. . . Doped region

875. . . Interlayer dielectric layer

877. . . Source contact window

880,880’. . . Heavily doped region

890. . . Conductive structure

876. . . Heavy doped polysilicon structure

965. . . Dielectric layer

977. . . Source contact window

935. . . Dielectric structure

980. . . Heavily doped region

990. . . Conductive structure

1080. . . Heavily doped region

1060. . . Source area

1A to 1H are views showing a first embodiment of a method of manufacturing a trench type power semiconductor device for improving a breakdown voltage according to the present invention.

Fig. 2 is a view showing a second embodiment of the manufacturing method of the trench type power semiconductor device for improving the breakdown voltage of the present invention.

3A and 3B are views showing a third embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

Fig. 3C is a view showing a fourth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

4A to 4C are views showing a fifth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

5A and 5B are views showing a sixth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

Fig. 6 is a view showing a seventh embodiment of the manufacturing method of the trench type power semiconductor device for improving the breakdown voltage of the present invention.

7A and 7B are views showing an eighth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

8A to 8E are views showing a ninth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

9A to 9F are diagrams showing a tenth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

Figures 10A through 10C are three other different embodiments of the method of fabricating the p-type heavily doped region of Figure 9E.

Fig. 11 is a view showing an eleventh embodiment of a method of manufacturing a trench type power semiconductor device for improving a breakdown voltage according to the present invention.

12A to 12E are views showing a twelfth embodiment of a method of manufacturing a trench type power semiconductor device for improving breakdown voltage according to the present invention.

Fig. 13 is a view showing a thirteenth embodiment of the method of manufacturing the trench type power semiconductor device of the present invention for improving the breakdown voltage.

100. . . Substrate

110. . . Epitaxial layer

130. . . First dielectric layer

140. . . First polycrystalline structure

150. . . Body area

160. . . Source area

165. . . Pattern layer

180. . . Heavily doped region

172. . . Second polycrystalline structure

174. . . Dielectric structure

190. . . Conductive structure

Claims (20)

A trench power semiconductor device for improving a breakdown voltage, comprising: a substrate; at least two gate trenches are disposed in the substrate; and a first dielectric layer covering an inner surface of the gate trench; a first polysilicon structure is disposed in the gate trenches; at least one first trench is located between the two gate trenches; and a first conductivity type body region is located in the gate trenches The first trench extends through the body region and extends below the body region; a second polysilicon structure of the first conductivity type is filled in a lower portion of the first trench, the second polysilicon The structure is located below the body region and spaced apart from the body region by a predetermined distance; a source region of the second conductivity type is located at an upper portion of the body region, and the second conductivity type and the first conductivity type are electrically The opposite is true; a heavily doped region of the first conductivity type is located in the body region; and a source metal layer is electrically connected to the heavily doped region and the source region. The trench power semiconductor device for improving the breakdown voltage according to the first aspect of the patent application, further comprising a dielectric structure filled in the first trench, the dielectric structure being located above the second polysilicon structure And extending at least upwardly to the body region. A trench type power semiconductor device for improving a breakdown voltage according to the first aspect of the invention, wherein the heavily doped region and the source region are alternately arranged in the upper portion of the body region. A trench power semiconductor device for improving a breakdown voltage according to claim 2, further comprising an interlayer dielectric layer on the first polysilicon structure, the interlayer dielectric layer corresponding to the first trench Wherein, a source contact window having a width greater than the first trench is defined, and the heavily doped region is located at the bottom of the source contact window. A trench power semiconductor device for improving a breakdown voltage according to claim 4, wherein the dielectric structure protrudes from a bottom of the source contact window, and the heavily doped region is located in the dielectric structure On both sides. A trench power semiconductor device for improving a breakdown voltage according to claim 2, wherein the heavily doped region is adjacent to the dielectric structure, and a bottom portion of the heavily doped region extends below the body region . A trench power semiconductor device for improving a breakdown voltage according to the second aspect of the patent application, further comprising a heavily doped polysilicon structure of a first conductivity type, above the dielectric structure, the first conductivity type heavily doped region Adjacent to the heavily doped polysilicon structure. The trench power semiconductor device for improving the breakdown voltage according to the first aspect of the patent application, further comprising a third polysilicon structure of the second conductivity type, filled in the first trench, the third polysilicon structure Located above the second polysilicon structure and extending at least upwardly to the body region. A trench power semiconductor device for improving a breakdown voltage according to the first aspect of the patent application, further comprising a metal plug filled in the first trench, the metal plug being located above the second polysilicon structure And extending at least upwardly to the body region. A method for fabricating a trench power semiconductor device for improving a breakdown voltage includes at least the steps of: providing a substrate; forming at least two gate trenches in the substrate; forming a first dielectric layer covering the gate An inner side surface of the trench; a first polysilicon structure is formed in the gate trenches; at least one first trench is formed between the two gate trenches; and a second conductivity type is formed a polysilicon structure is formed on a lower portion of the first trench; a body portion of the first conductivity type is formed between the gate trenches, the first trench extends downwardly below the body region, the second The polysilicon structure is located below the body region and spaced apart from the body region by a predetermined distance; forming a source region of a second conductivity type on an upper portion of the body region; forming an interlayer dielectric layer covering the first portion a polysilicon structure, and using the interlayer dielectric layer to define a source contact window at a position corresponding to the first trench; forming a heavily doped region of the first conductivity type in the body region; and filling in a source metal layer is in the source contact window to electrically connect the Doped region and the source region. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10, after the step of forming the second polysilicon structure of the first conductivity type, further comprising filling a dielectric structure Within the first trench, the dielectric structure is over the second polysilicon structure and extends at least upwardly to the body region. A method of fabricating a trench power semiconductor device for improving a breakdown voltage according to claim 10, wherein the gate trench and the first trench are formed in the substrate in the same etching step. The method for fabricating a trench power semiconductor device for improving a breakdown voltage according to claim 11, wherein the step of forming the dielectric structure comprises: forming a dielectric layer covering the interlayer dielectric layer, and filling the first a trench; and etching the dielectric layer outside the first trench and expanding the width of the source contact window. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10, wherein the step of forming the heavily doped region and the source region comprises a second ion implantation step, respectively implanting the first a dopant of a conductivity type and a dopant of the second conductivity type are in the body region, and an implantation region of the two ion implantation steps partially overlaps to form the heavily doped region and the source The regions are alternately arranged in the upper portion of the body region. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10, wherein the step of forming the heavily doped region is to implant the dopant of the first conductivity type through the source contact window In the body region, the heavily doped region is formed, and a bottom portion of the heavily doped region extends below the body region. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10, wherein the step of forming the heavily doped region comprises: forming a heavily doped polysilicon structure over the dielectric structure; and The dopant within the heavily doped polysilicon structure is thermally diffused into the body region to form the heavily doped region. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10, wherein the step of forming the first trench is later than the step of forming the source region in the upper portion of the body region And the first trench extends through the body region. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10, wherein the step of forming the first trench is earlier than the step of forming the body region, wherein the depth of the first trench is greater than The depth of the gate trench, and the step of forming the second polysilicon structure is earlier than the step of forming the first polysilicon structure. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10 of the patent application, after the step of forming the second polysilicon structure of the first conductivity type, further comprising filling in a second conductivity type A third polysilicon structure is disposed within the first trench, the third polysilicon structure being over the second polysilicon structure and extending at least upwardly to the body region. The method for manufacturing a trench power semiconductor device for improving a breakdown voltage according to claim 10, after the step of forming the second polysilicon structure of the first conductivity type, further comprising filling a metal plug in the Within the first trench, the metal plug is over the second polysilicon structure and extends at least upwardly to the body region.