TW201316517A - Metal oxide thin film transister - Google Patents

Abstract

A metal oxide thin film transistor includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer, in which at least one of the projection of the drain electrode and the projection of the source electrode on the substrate do not overlap the gate electrode.

Description

Metal oxide thin film transistor

This invention relates to a thin film transistor, and more particularly to a metal oxide thin film transistor.

With the development of optoelectronic technology and semiconductor process technology, flat panel displays have been widely used in various electronic devices. Today's flat panel displays mainly use thin film transistors to form their array substrates, and the array substrate is arranged in a matrix by a plurality of pixel units. Each pixel unit includes at least one drive film transistor and one switch film transistor. The driving thin film transistor is used to drive the light emitting elements of the pixel unit, and the image data can be stored in the respective pixel circuits by switching the turning on and off of the thin film transistors. The quality of a flat panel display depends in large part on the performance of the thin film transistor.

Figure 1 is a conventional thin film transistor structure in which the active layer 140 material of the thin film transistor 100 is amorphous. When the gate 120 is biased to be greater than or equal to the threshold voltage of the thin film transistor 100, a channel is formed in the amorphous germanium active layer 140, and the thin film transistor 100 is turned on. It should be noted that due to the low carrier concentration and carrier mobility of the amorphous germanium, the orthographic projections P1, P2 and the gate 120 of the source 150 and the drain 160 on the substrate 110 need to partially overlap. The regions G1, G2 are overlapped to form a channel. In addition, in the amorphous germanium thin film transistor 100, the carrier concentration of the amorphous germanium film and the carrier mobility are lower, resulting in a poor driving speed of the amorphous germanium thin film transistor 100, for a high quality flat panel display. Development is a serious limitation.

Therefore, in order to further develop the picture quality of the flat display, there is an urgent need to improve the above defects.

One aspect of the present disclosure is to provide a metal oxide thin film transistor comprising a gate, a gate insulating layer, a metal oxide active layer, a source, and a drain. The gate is formed on the substrate. A gate insulating layer is formed on the substrate and covers the gate. A metal oxide active layer is formed on the gate insulating layer. The source and the drain are respectively located at opposite ends of the metal oxide active layer, wherein at least one of the source and the drain has no overlap between the orthographic projection and the gate on the substrate.

In accordance with an embodiment of the present disclosure, the orthographic projection of the source on the substrate partially overlaps the gate, and the orthographic projection of the drain on the substrate does not overlap with the gate.

In accordance with an embodiment of the present disclosure, the orthographic projection of the drain on the substrate partially overlaps the gate, and the orthographic projection of the source on the substrate does not overlap with the gate.

According to an embodiment of the present disclosure, the front projections of the drain and the source on the substrate do not overlap with the gate.

In accordance with an embodiment of the present disclosure, the distance between the orthographic projection of the source on the substrate and the gate is 1 to 2.5 microns.

In accordance with an embodiment of the present disclosure, the distance between the orthographic projection of the source on the substrate and the gate is 0.5 to 1 micron.

In accordance with an embodiment of the present disclosure, the distance between the orthographic projection of the source on the substrate and the gate is 0 to 0.5 microns.

In accordance with an embodiment of the present disclosure, the distance between the orthographic projection of the drain on the substrate and the gate is 1 to 2.5 microns.

In accordance with an embodiment of the present disclosure, the distance between the orthographic projection of the drain on the substrate and the gate is 0.5 to 1 micron.

In accordance with an embodiment of the present disclosure, the distance between the orthographic projection of the drain on the substrate and the gate is 0 to 0.5 microns.

According to an embodiment of the present disclosure, the metal oxide thin film transistor further includes an insulating layer covering the metal oxide active layer, the source and the drain.

In summary, the above metal oxide thin film transistor of the present disclosure can improve the low carrier concentration and low carrier mobility of the conventional amorphous germanium thin film transistor, and improve the driving speed of the thin film transistor. On the other hand, by shortening the gate length or increasing the source and drain distances, the overlap between the orthographic projection and the gate of the source and the drain on the substrate is eliminated, so as to increase the stability of the critical voltage of the thin film transistor and reduce the 汲. The parasitic capacitance between the gates improves the capacitive coupling effect of the thin film transistor scanning line on the pixel electrode in the flat panel display, reduces the voltage variation of the pixel electrode during the thin film transistor switching, and further improves the image quality of the flat panel display.

The spirit and scope of the present disclosure will be apparent from the following description of the preferred embodiments of the present disclosure. Modifications do not depart from the spirit and scope of the disclosure.

The object of the embodiments of the present invention is to provide a metal oxide thin film transistor to improve the disadvantages of the conventional amorphous germanium thin film transistor driving speed, and at the same time avoid the metal oxide transistor whose gate is biased at a voltage After the pressure, there is a problem that the threshold voltage shift is excessive.

2 is a schematic view of a metal oxide thin film transistor 200 in accordance with an embodiment of the present disclosure. The metal oxide thin film transistor 200 may include a gate 220, a gate insulating layer 230, a metal oxide active layer 240, a source 250, a drain 260, and an insulating layer 270. The gate electrode 220 is formed on a substrate 210. The gate insulating layer 230 is formed on the substrate 210 and covers the gate 220. The metal oxide active layer 240 is formed on the gate insulating layer, and the source 250 and the drain 260 are respectively located. The opposite ends of the metal oxide active layer 240, and the insulating layer 270 covers the metal oxide active layer 240, the source 250 and the drain 260. In addition, the orthographic projections P1 and P2 of the source 250 and the drain 260 on the substrate 210 are not overlapped with the gate 220, and the pitches of the orthographic projections P1, P2 and the gate 220 are I1 and I2, respectively. The absence of overlap referred to herein and in this specification means that there are spacings I1, I2 between the orthographic projections P1, P2 and the gate 220.

In the present embodiment, the metal oxide active layer 240 includes, for example, zinc oxide (ZnO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc tin oxide. (ZTO), indium zinc tin oxide (IZTO), but not limited to this. Since the carrier mobility of the metal oxide active layer 240 is high, even if the orthographic projections P1, P2 of the source 250 and the drain 260 on the substrate 210 do not overlap with the gate 220, the metal oxide active is active. Channels can still be formed in layer 240. Since the length of the pitch I1 affects the vertical electric field strength of the gate bias applied to the metal oxide active layer 240, the length of the pitch I1 may be between 0 and 2.5 microns. When the pitch I1 is 1 to 2.5 μm, the metal oxide thin film transistor 200 has characteristics of high on current, low leakage current, and low sub-threshold swing. When the pitch I1 is 0.5 to 1 μm, the metal oxide thin film transistor 200 has a high on-current, a low leakage current, and a low sub-threshold swing characteristic, and the carrier migration of the metal oxide thin film transistor 200 is further improved. rate. When the pitch I1 is from 0 to 0.5 micrometers, the metal oxide thin film transistor 200 has a low threshold voltage in addition to high on current, low leakage current, low sub-threshold swing, and high carrier mobility. On the other hand, the pitch I2 may also be 0 to 2.5 μm, wherein the length of the pitch I2 is the same as or similar to the characteristic relationship of the metal oxide thin film transistor 200 and the length of the pitch I1 and the characteristic relationship of the metal oxide thin film transistor 200, I will not go into details here.

In the present embodiment, the longer the length of the pitch I1, the smaller the gate-source parasitic capacitance of the metal oxide thin film transistor 200. Similarly, the longer the length of I2, the smaller the gate-drain parasitic capacitance of the metal oxide thin film transistor 200.

In the thin film transistor 200, the material of the substrate 210 may be glass. The gate 220, source 250, and drain 260 materials can be metal, non-metal, conductive polymer, doped germanium, or a combination of some or all of the above materials. The material of the gate insulating layer 230 and the insulating layer 270 may be ceria, hafnium tetranitride, titania, polyimide, polyvinylphenol, polystyrene or a combination of some or all of the above materials. It should be noted that the above materials are merely examples, and the materials of the above components are not limited to this embodiment.

3 is a schematic view of a metal oxide thin film transistor 300 in accordance with another embodiment of the present disclosure. The metal oxide thin film transistor 300 may include a gate 320, a gate insulating layer 330, a metal oxide active layer 340, a source 350, a drain 360, and an insulating layer 370. The gate 320 is formed on a substrate 310. The gate insulating layer 330 is formed on the substrate 310 and covers the gate 320. The metal oxide active layer 340 is formed on the gate insulating layer 330. The source 350 and the drain 360 are respectively Located at opposite ends of the metal oxide active layer 340, and an insulating layer 370 overlying the metal oxide active layer 340, the source 350, and the drain 360. In addition, the orthographic projection of the source 350 on the substrate 310 is P1, and the orthographic projection P1 and the gate 320 have an overlap region G1. The front projection of the drain 360 on the substrate 310 is P2, and the front projection P2 has a pitch I2 with the gate 320.

In this embodiment, the pitch I2 may be from 0 to 2.5 microns in length. The relationship between the length of the pitch I2 and the characteristic of the metal oxide thin film transistor 300 is the same as or similar to that of the above embodiment, and will not be described herein.

In this embodiment, since the capacitance value of the parallel capacitance is proportional to the parallel plate area and inversely proportional to the parallel plate distance, the longer the overlap region G1 is, that is, the more overlapping regions, the more the gate-source parasitic capacitance is. Big. The longer the pitch I2 is, the smaller the gate-drain parasitic capacitance is. In other words, the present embodiment can reduce the gate-parasitic capacitance by increasing the distance between the gate 320 and the drain 360. If the metal oxide thin film transistor 300 is applied to a thin film transistor flat panel display, the capacitive coupling effect of the thin film transistor scanning line on the pixel electrode can be improved to reduce the voltage variation of the pixel voltage during the thin film transistor switching. And to improve the driving speed of the thin film transistor, on the other hand, it can also reduce the loss of switching power of the flat panel display.

4 is a schematic view of a metal oxide thin film transistor 400 in accordance with still another embodiment of the present disclosure. The metal oxide thin film transistor 400 may include a gate 420, a gate insulating layer 430, a metal oxide active layer 440, a source 450, a drain 460, and an insulating layer 470. The gate 420 is formed on a substrate 410. The gate insulating layer 430 is formed on the substrate 410 and covers the gate 420. The metal oxide active layer 440 is formed on the gate insulating layer 430. The source 450 and the drain 460 are respectively Located at opposite ends of the metal oxide active layer 440, and the insulating layer 470 covers the metal oxide active layer 440, the source 450 and the drain 460. In addition, the orthographic projection of the source 450 on the substrate 410 is P1, and the orthographic projection P1 and the gate 420 have a pitch I1. The front projection of the drain 460 on the substrate 410 is P2, and the front projection P2 and the gate 420 have an overlap region G2.

In this embodiment, the pitch I1 may be from 0 to 2.5 microns in length. The relationship between the length of the pitch I1 and the characteristic of the metal oxide thin film transistor 400 is the same as or similar to that of the above embodiment, and will not be described herein.

In the present embodiment, the longer the pitch I1 is, the smaller the gate-source parasitic capacitance is. In addition, the longer the overlap region G2 is, that is, the more regions overlap, the larger the gate-drain parasitic capacitance. Therefore, in this embodiment, the gate-source parasitic capacitance is reduced by increasing the distance between the gate 420 and the source 450. This metal oxide thin film transistor 400 can be particularly useful for improving picture flicker problems caused by gate-source parasitic capacitance in a flat panel display.

After the gate of the metal oxide transistor is pressurized by the voltage bias, the problem of excessive threshold voltage shift occurs, which in turn affects the normal switching of the metal oxide thin film transistor. Fig. 5 is a schematic diagram showing the negative bias effect of the metal oxide thin film transistor 200 of Fig. 2 compared with the metal oxide thin film transistor of a comparative example. Referring to Fig. 1, the metal oxide thin film transistor of the above comparative example has substantially the same structure as that of Fig. 1 except that the amorphous germanium active layer 140 is replaced by a metal oxide, that is, the source and the drain are The orthographic projections on the substrate overlap with the gate portion. The metal oxide thin film transistor of this comparative example has a problem that the gate voltage is excessively biased after the voltage is biased, such as the curve 510 of FIG. 5, and further affects the corresponding metal oxide thin film transistor. The normal switch. On the contrary, since the source of the metal oxide thin film transistor 200, the front projections P1, P2 of the drain electrodes 250, 260 on the substrate 210 and the gate 220 do not overlap, the vertical electric field is reduced to pressurize the metal oxide active layer 240. Degradation increases the lifetime of the metal oxide active layer 240, ensuring the stability of the threshold voltage of the metal oxide thin film transistor 200, as shown by curve 520.

FIG. 6 is a schematic diagram showing voltage-current of a metal oxide thin film transistor 200 under a negative gate bias according to an embodiment of the present disclosure. The negative gate bias voltage is 0.1 volts, and the negative gate bias time of the negative gate bias time is 0 seconds and 8700 seconds, as shown by curves 610 and 620, respectively. The negative gate bias voltage is 9.9 volts, and the negative gate bias time of the negative gate bias time is 0 seconds and 8700 seconds, as shown by curves 630 and 640, respectively. It can be seen from the close overlap of the curves 610, 620 and 630, 640 in FIG. 6 that the metal oxide thin film transistor 200 is in a stable operating state, and the negative gate bias-drain current relationship is continuously applied to the gate for a long time. After that, it remains unchanged.

FIG. 7 is a schematic diagram showing voltage-current of a metal oxide thin film transistor 200 under positive gate bias according to an embodiment of the present disclosure. The positive gate bias voltage is 0.1 volts, and the positive gate bias voltages of the positive gate bias time of 0 seconds and 8700 seconds are shown as curves 710 and 720, respectively. The positive gate bias voltage is 9.9 volts, and the positive gate bias time of the positive gate bias time is 0 seconds and 8700 seconds, as shown by curves 730 and 740, respectively. Similar to Fig. 6, similarly to the close overlap of curves 710, 720 and 730, 740 in Fig. 7, the metal oxide thin film transistor 200 is in a stable operating state, and the positive gate bias-dip current relationship is long in the gate. The time remains unchanged after the time is applied to the positive bias.

In summary, the technical features of the embodiments of the present invention can be achieved by using a metal oxide as the active layer material and maintaining an appropriate distance between the orthographic projection of the drain and/or source on the substrate and the gate. In order to improve the mobility of the thin film transistor carrier, and also ensure the stability of the thin film transistor, not only the high current output of the thin film transistor is provided, but also the driving speed is accelerated, and the picture quality of the flat display is further enhanced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

200, 300, 400. . . Metal oxide thin film transistor

210, 310, 410. . . Substrate

220, 320, 420. . . Gate

230, 330, 430. . . Gate insulation

240, 340, 440. . . Gold layer active layer

250, 350, 450. . . Source

260, 360, 460. . . Bungee

270, 370, 470. . . Insulation

P1. . . Orthographic projection of the source on the substrate

P2. . . Front projection of the bungee on the substrate

I1. . . The orthographic projection of the source on the substrate and the spacing of the gate

I2. . . The orthographic projection of the bungee on the substrate and the spacing of the gate

G1. . . The area between the orthographic projection of the source on the substrate and the gate

G2. . . The overlap between the orthographic projection of the bungee on the substrate and the gate

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

Figure 1 is a schematic representation of a conventional thin film transistor.

2 is a schematic view showing a metal oxide thin film transistor according to an embodiment of the present disclosure.

FIG. 3 is a schematic view showing a metal oxide thin film transistor according to another embodiment of the present disclosure.

4 is a schematic view showing a metal oxide thin film transistor according to still another embodiment of the present disclosure.

Fig. 5 is a schematic diagram showing the negative bias effect of the metal oxide thin film transistor of Fig. 2 compared with the metal oxide thin film transistor of a comparative example.

FIG. 6 is a schematic diagram showing voltage-current of a metal oxide thin film transistor under a negative gate bias according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram showing voltage-current of a metal oxide thin film transistor under positive gate bias according to an embodiment of the present disclosure.

200. . . Metal oxide thin film transistor

210. . . Substrate

220. . . Gate

230. . . Gate insulation

240. . . Metal oxide active layer

250. . . Source

260. . . Bungee

270. . . Insulation

P1. . . Orthographic projection of the source on the substrate

P2. . . Front projection of the bungee on the substrate

I1. . . The orthographic projection of the source on the substrate and the spacing of the gate

I2. . . The orthographic projection of the bungee on the substrate and the spacing of the gate

Claims (11)

A metal oxide thin film transistor comprising: a gate formed on a substrate; a gate insulating layer formed on the substrate and covering the gate; a metal oxide active layer formed on the gate insulating And a source and a drain are respectively located at opposite ends of the active layer of the metal oxide, wherein an orthographic projection of at least one of the source and the drain on the substrate does not overlap the gate . A metal oxide thin film transistor according to claim 1, wherein an orthographic projection of the source on the substrate partially overlaps the gate, and an orthographic projection of the drain on the substrate does not overlap the gate. The metal oxide thin film transistor according to claim 1, wherein an orthographic projection of the drain on the substrate partially overlaps the gate, and an orthographic projection of the source on the substrate does not overlap the gate. The metal oxide thin film transistor of claim 1, wherein the positive projection of the drain and the source on the substrate does not overlap the gate. A metal oxide thin film transistor according to claim 3 or 4, wherein a distance between the orthographic projection of the source on the substrate and the gate is 1 to 2.5 μm. A metal oxide thin film transistor according to claim 3 or 4, wherein a distance between the orthographic projection of the source on the substrate and the gate is 0.5 to 1 μm. A metal oxide thin film transistor according to claim 3 or 4, wherein a distance between the orthographic projection of the source on the substrate and the gate is 0 to 0.5 μm. A metal oxide thin film transistor according to claim 2 or 4, wherein a distance between the orthographic projection of the drain on the substrate and the gate is 1 to 2.5 μm. A metal oxide thin film transistor according to claim 2 or 4, wherein a distance between the orthographic projection of the drain on the substrate and the gate is 0.5 to 1 μm. A metal oxide thin film transistor according to claim 2 or 4, wherein a distance between the orthographic projection of the drain on the substrate and the gate is 0 to 0.5 μm. The metal oxide thin film transistor according to claim 1, further comprising an insulating layer covering the active layer of the metal oxide, the source and the drain.