TW201314784A - Semiconductor process - Google Patents

Abstract

A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure.

Description

Semiconductor process

This invention relates to a semiconductor process, and more particularly to a semiconductor process that employs a heat treatment process to make the sidewalls of the fin structure flatter.

As the size of semiconductor components shrinks, maintaining the performance of small-sized semiconductor components is currently the main goal of the industry. In order to improve the performance of semiconductor components, various Fin-shaped field effect transistors (FinFETs) have been developed. The fin field effect transistor component has several advantages. First, the process of the fin field effect transistor component can be integrated with the conventional logic component process, so that it has considerable process compatibility. Secondly, since the three-dimensional shape of the fin structure increases the contact area between the gate and the single crystal germanium, Therefore, the gate can control the charge of the channel region, thereby reducing the Drain Induced Barrier Lowering (DIBL) effect and the short channel effect caused by the small-sized component; The length of the gate has a larger channel width, which also increases the amount of current between the source and the drain.

In detail, a method of forming a fin structure in a fin field effect transistor device is generally performed by performing an etch lithography process to pattern a mask layer on a substrate. The patterned mask layer is then used as a hard mask to transfer the pattern to the substrate to form at least one fin structure on the substrate. However, the sidewall of the fin structure formed by the lithography process is uneven and has many defects caused by etching, resulting in a poor quality channel region and the subsequent formation of the via layer to be closely covered. Thereby reducing the electrical quality of the semiconductor structure formed thereon.

The present invention provides a semiconductor process that performs a heat treatment process (especially a heat treatment process greater than 1200 ° C) to form a molten layer on the sidewalls of the fin structure to smooth the sidewalls of the fin structure.

The present invention provides a semiconductor process comprising the steps described below. First, a substrate is provided. Next, at least one fin structure is formed on the substrate and an oxide layer is formed on the substrate other than the fin structure. Thereafter, a heat treatment process is performed to form a molten layer on the sidewalls of at least a portion of the fin structure.

The present invention provides a semiconductor process comprising the following steps. First, a piece of substrate is provided. Next, a mask layer is formed on the bulk substrate. Subsequently, the mask layer is patterned and the mask layer is a hard mask to form at least one fin structure. Further, an oxide layer is formed on the bulk substrate other than the fin structure. Thereafter, a heat treatment process of greater than 1200 ° C is performed to form a molten layer on the sidewalls of at least a portion of the fin structure.

The present invention provides a semiconductor process comprising the following steps. First, an insulating substrate is provided, comprising a germanium substrate, a bottom oxide layer on the germanium substrate and a germanium layer on the bottom oxide layer. Successively, a mask layer is formed on the enamel layer. Continuing, an etch lithography process is performed to pattern the mask layer and the mask layer as a hard mask to form at least one fin structure of the germanium layer while exposing a portion of the bottom oxide layer to the fin structure. It is covered on the insulating substrate. Thereafter, a heat treatment process of greater than 1200 ° C is performed to form a molten layer on at least a portion of the sidewalls of the fin structure.

Based on the above, the present invention provides a semiconductor process by which a heat treatment process (particularly a heat treatment process of greater than 1200 ° C) is performed to form a molten layer on the sidewalls of the fin structure. As such, the present invention can repair defects of the sidewall surface of the fin structure and recrystallize it to solve the problem of unevenness of the sidewall surface of the fin structure when the fin structure is patterned.

1 to 10 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention. As shown in Fig. 1, a substrate 110 is provided. In this embodiment, the substrate 110 is a piece-shaped substrate. Of course, the substrate 110 may comprise a germanium substrate, a germanium-containing substrate, a tri-five-layered germanium substrate (eg, GaN-on-silicon), a graphene-on-silicon substrate, or a germanium-covered insulating substrate. A semiconductor substrate. Next, a mask layer 20 is formed on the substrate 110. The mask layer 20 may include a pad oxide layer 22 and a nitride layer 24 on the pad oxide layer 22. Then, an etching and lithography process is performed to pattern the mask layer 20 and expose a portion of the substrate 110.

As shown in FIG. 2, the mask layer 20 is a hard mask, and the substrate 110 is etched to form a fin structure 120. In another embodiment, the mask layer 20 can also be patterned to expose regions of the substrate 110 that must form a fin structure. Then, an epitaxial process is performed to thereby grow a fin structure (not shown) protruding from the mask layer 20 in the region of the substrate 110. In addition, the present invention only shows a fin structure 120 on the substrate 110, but in practical applications, the number of the fin structures 120 may also be plural.

As shown in FIG. 3, for example, a shallow trench isolation technique is performed to form an oxide layer 130 on the substrate 110 other than the fin structure 120, but the invention is not limited thereto. The shallow trench isolation technique may include first selectively filling a liner layer (not shown), wherein the liner layer may be formed, for example, as an oxide layer on the sidewall of the fin structure 120 to serve as a buffer layer. Then, the shallow trench insulating material is filled on the substrate 110 other than the fin structure 120, and the filled material may include an oxide to form an oxide layer (not shown) on the substrate 110 other than the fin structure 120. Next, an annealing process P1 is performed to densify the oxide layer (not shown), wherein the process of the thermal annealing process P1 may include introducing nitrogen gas and having a process temperature of about 1050 ° C. Then, for example, an etching process or a chemical mechanical polishing process (not shown) is performed to remove a portion of the oxide layer (not shown) to form the oxide layer 130.

As shown in FIG. 4, a heat treatment process P2 is performed to form a molten layer 122 on the side wall surface S1 of the fin structure 120. As a result, the molten layer 122 is formed to repair various defects of the sidewall surface S1 of the fin structure 120 due to etching and recrystallize it to solve the sidewall of the fin structure 120 when the fin structure 120 is patterned. The surface S1 has a problem of unevenness due to a process such as etching. In other words, the heat treatment process P2 of the present invention can make the sidewall surface S1 of the fin structure 120 more flat. Therefore, the semiconductor structure formed on the subsequent process (for example, a dielectric layer is generally covered on the fin structure 120) can be uniformly formed on the fin structure 120, thereby improving the formed semiconductor. The electrical quality of the structure. In an embodiment, the heat treatment process P2 includes a laser heat treatment process, but the invention is not limited thereto, and the heat treatment process P2 for forming the sidewall surface S1 of the fin structure 120 into a molten layer 122 can be applied. this invention. In a preferred embodiment, the process temperature of the heat treatment process P2 is greater than 1200 °C. In still another preferred embodiment, when the substrate 110 is a germanium substrate, the process temperature of the heat treatment process P2 is greater than 1300 ° C, and the sidewall surface S1 of the fin structure 120 is completely converted into a molten state to form the molten layer 122.

As shown in FIG. 5, after the heat treatment process P2 is performed, the partial oxide layer 130 is removed again to form a desired insulating structure around the fin structure 120, such as shallow trench isolation (STI), and expose some of the fins. The sidewall of the structure 120, wherein the method of removing the oxide layer 130, may include performing an etching process, etc., but the invention is not limited thereto.

In addition, in another embodiment, as shown in FIG. 6, after performing the step of FIG. 3 (forming the oxide layer 130 on the substrate 110 other than the fin structure 120), for example, an etchback process may be performed. The partial oxide layer 130 is removed to form a desired insulating structure around the fin structure 120, such as shallow trench isolation (STI), and expose sidewalls of the portion of the fin structure 120. Next, as shown in FIG. 7, the heat treatment process P2 is performed so that the side wall surface S1 of the fin structure 120 forms the molten layer 122. In this way, the above-mentioned problem of solving the unevenness of the sidewall surface S1 of the fin structure 120 due to etching or the like can be achieved. However, the former (as shown in FIG. 4) performs the heat treatment process P2 at a point in time better than the latter (as shown in FIG. 7) at the time point of the heat treatment process P2 because the former is not exposed to the sidewall of the fin structure 120. (Specially not exposed to the atmosphere), the heat treatment process P2 is performed to form the molten layer 122, so that the sidewall of the fin structure 120 is not reacted by components such as oxygen in the process environment or the atmosphere, which causes contamination of the sidewall of the fin structure 120. . Of course, the latter embodiment can also be matched with the needs of the process.

Then, after performing the steps of FIG. 5 or FIG. 7 (after performing the heat treatment process P2 to form the molten layer 122 and the etch back oxide layer 130), an ion implantation process may be selectively performed as shown in FIG. For example, an anti-punch through ion implantation process is prevented between the fin structure 120 and the substrate 110. Then, the nitride layer 24 and the pad oxide layer 22 are sequentially removed. Continuing, a hydrogen-containing annealing process can be selectively performed to further round the top of the fin structure 120.

It is emphasized herein that the nitride layer 24 and the pad oxide layer 22 are sequentially removed in this embodiment, so that a three-gate tri-gate MOSFET can be formed in a subsequent process. In detail, since the fin structure 120 has three direct contact faces (including two contact sides and a contact top surface) between the subsequently formed dielectric layers, it is called a tri-gate field effect transistor (tri-gate). MOSFET). Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the above three direct contact surfaces as a channel through which the carrier flows. Double the drain drive current at the same drive voltage.

However, in another embodiment, the nitride layer 24 and the pad oxide layer 22 may be retained, and another multi-gate MOSFET having a fin structure may be formed in a subsequent process. Fin field effect transistor (Fin FET). In the fin field effect transistor, since the nitride layer 24 and the pad oxide layer 22 are retained, there are only two contact sides between the fin structure 120 and the subsequently formed dielectric layer.

As shown in FIG. 9, a dielectric layer (not shown) and an electrode layer (not shown) are sequentially formed on the substrate 110. Then, an electrode layer (not shown) and a dielectric layer (not shown) are patterned to form a gate structure 140. The gate structure 140 includes a dielectric layer 142 and an electrode layer 144. On layer 140. The dielectric layer 140 can be, for example, an oxide layer or a high-k dielectric layer. The high-k dielectric layer may further comprise a buffer layer between the fin structure 120 and the high-k dielectric layer, and the high-k dielectric layer may comprise a hafnium oxide. , HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide , La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO) ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), zirconium A group consisting of lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST). The electrode layer 144 can be a polysilicon electrode layer. Of course, other semiconductor processes that follow can be performed. For example, a lightly doped source/drain region (not shown) is selectively formed in the fin structure 120 on opposite sides of the gate structure 140; a sidewall (not shown) is formed on the gate structure 140. On the sidewalls, a heavily doped source/drain region (not shown) is formed in the fin structure 120 on opposite sides of the gate structure 140. In addition, the present invention can be applied to a general polysilicon gate process, a gate-first process, or a gate-Last process. In the case of the Gate-Last process, the polysilicon electrode layer is replaced by a metal electrode layer. Detailed process steps are well known in the art and will not be described again.

Further, the foregoing embodiments take the case where the substrate 110 is a block substrate. However, the invention can also be applied to a covered insulating substrate. As shown in FIGS. 10-11, an insulating substrate 210 is first provided, which includes a germanium substrate 212, a bottom oxide layer 214 on the germanium substrate 212, and a germanium layer 216 on the bottom oxide layer 214. Next, as shown in FIG. 11, the germanium layer 216 is patterned to form the fin structure 220, and a portion of the bottom oxide layer 214 is exposed on the germanium substrate 212 outside the fin structure 220. As such, the fin structure 220 can be formed on the germanium substrate 212 and an oxide layer (eg, the bottom oxide layer 214) can be formed on the germanium substrate 212 outside of the fin structure 220. As shown in FIG. 3, the oxide layer 130 formed by the germanium substrate 110 is only located on the substrate 110 other than the fin structure 120, and as shown in FIG. 11, in the blanket insulating substrate 210, the fin structure 220 will then be located above the bottom oxide layer 214. Furthermore, since the bottom oxide layer 214 is also formed on the substrate 110 when the fin structure 120 is formed, the heat treatment process P2 of the present invention is performed after the bottom oxide layer 214 is formed again to be in the fin structure. The sidewall of 220 forms a molten layer 222. In this way, the present invention can repair the defect of the sidewall surface S2 of the fin structure 220 and recrystallize the sidewall surface S2 to solve the patterning of the fin structure 220. The sidewall surface S2 of the fin structure 220 is uneven due to etching. The problem. In other words, the heat treatment process P2 of the present invention can make the sidewall surface S2 of the fin structure 220 more flat. Therefore, the semiconductor structure formed on the subsequent process (for example, a dielectric layer is generally covered on the fin structure 220) can be uniformly formed on the fin structure 220, thereby improving the formed semiconductor. The electrical quality of the structure. In an embodiment, the heat treatment process P2 includes a laser heat treatment process, but the invention is not limited thereto. In a preferred embodiment, the process temperature of the heat treatment process P2 is greater than 1200 °C. In still another preferred embodiment, the process temperature of the heat treatment process P2 is greater than 1300 ° C, and the sidewall surface S2 of the fin structure 220 is completely converted into a molten state to form the molten layer 222.

In summary, the present invention provides a semiconductor process by which a heat treatment process is performed to form a molten layer on the sidewalls of the fin structure. As such, the present invention can repair the defects of the sidewall surface of the fin structure and recrystallize the sidewall surface to solve the problem that the sidewall surface of the fin structure is uneven due to etching or the like when the fin structure is patterned. Specifically, the heat treatment process can be a laser heat treatment process. In a preferred embodiment, the heat treatment process has a process temperature greater than 1200 ° C, particularly greater than 1300 ° C, to completely melt the sidewall surfaces of the fin structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

20. . . Mask layer

twenty two. . . Pad oxide

twenty four. . . Nitride layer

110, 210. . . Base

120, 220. . . Fin structure

122, 222. . . Melt layer

130. . . Oxide layer

140. . . Gate structure

142. . . Dielectric layer

144. . . Electrode layer

212. . .矽 base

214. . . Bottom oxide layer

216. . . Layer

P1. . . Annealing process

P2. . . Heat treatment process

R. . . Fillet

S1, S2. . . Side wall surface

1-5 and 8-9 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

6-7 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

10-11 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

20. . . Mask layer

twenty two. . . Pad oxide

twenty four. . . Nitride layer

110. . . Base

120, 220. . . Fin structure

122. . . Melt layer

130. . . Oxide layer

P2. . . Heat treatment process

S1. . . Side wall surface

Claims (22)

A semiconductor process comprising: providing a substrate; forming at least one fin structure on the substrate and an oxide layer on the substrate other than the fin structure; and performing a heat treatment process to at least partially the fin structure The sidewalls form a molten layer. The semiconductor process of claim 1, wherein the substrate comprises a piece of substrate or a covered insulating substrate. The semiconductor process of claim 2, wherein the step of forming the fin structure on the bulk substrate comprises: forming a mask layer on the bulk substrate; and performing an etch lithography process to The mask layer is patterned and the mask layer is a hard mask to form at least one fin structure. The semiconductor process of claim 2, wherein the insulating insulating substrate comprises: a germanium substrate; a bottom oxide layer on the germanium substrate; and a germanium layer on the bottom oxide layer. The semiconductor process of claim 4, wherein the step of forming the fin structure comprises: patterning the germanium layer to form the fin structure, and exposing a portion of the bottom oxide layer, the fin structure Outside the substrate. The semiconductor process of claim 1, wherein the heat treatment process has a process temperature greater than 1200 °C. The semiconductor process of claim 6, wherein the heat treatment process has a process temperature greater than 1300 °C. The semiconductor process of claim 1, wherein the heat treatment process comprises a laser heat treatment process. The semiconductor process of claim 1, wherein after the heat treatment process, a portion of the oxide layer is removed. The semiconductor process of claim 1, wherein prior to performing the heat treatment process, removing a portion of the oxide layer and exposing a portion of the sidewall of the fin structure. The semiconductor process of claim 1, wherein after forming the oxide layer, further comprising: performing a thermal annealing process to densify the oxide layer. The semiconductor process of claim 11, wherein the thermal annealing process has a process temperature of about 1050 °C. A semiconductor process comprising: providing a piece of a substrate; forming a mask layer on the block substrate; patterning the mask layer and forming the mask layer as a hard mask to form at least one fin structure; Forming an oxide layer on the bulk substrate outside the fin structure; and performing a heat treatment process greater than 1200 ° C to form a molten layer on at least a portion of the sidewall of the fin structure. The semiconductor process of claim 13, wherein the block substrate comprises a one-piece base or a one-piece base. The semiconductor process of claim 13, wherein the process temperature of the heat treatment process is greater than 1300 °C. The semiconductor process of claim 13, wherein the heat treatment process comprises a laser heat treatment process. The semiconductor process of claim 13, wherein after performing the heat treatment process, further comprising removing a portion of the oxide layer and exposing a portion of the sidewall of the fin structure. The semiconductor process of claim 13, wherein prior to performing the heat treatment process, removing a portion of the oxide layer and exposing a portion of the sidewall of the fin structure. The semiconductor process of claim 13, wherein after forming the oxide layer, further comprising: performing a thermal annealing process to densify the oxide layer. A semiconductor process comprising: providing a germanium-insulating substrate comprising a germanium substrate, a bottom oxide layer on the germanium substrate, and a germanium layer on the bottom oxide layer; forming a mask layer on the germanium layer; Performing an etch lithography process to pattern the mask layer and use the mask layer as a hard mask to form the germanium layer to form at least one fin structure while exposing a portion of the bottom oxide layer on the fin And overlying the insulating substrate; and performing a heat treatment process greater than 1200 ° C to form a molten layer on at least a portion of the sidewalls of the fin structure. The semiconductor process of claim 20, wherein the process temperature of the heat treatment process is greater than 1300 °C. The semiconductor process of claim 20, wherein the heat treatment process comprises a laser heat treatment process.