TW201313490A - Printhead heater chip and method of fabricating the same - Google Patents

Abstract

A printhead heater chip is provided, including a substrate, a resistance layer, an interlayer dielectric (ILD), a first via plug, a second via plug, a protecting layer, and a controller element. The ILD is disposed above the substrate. Between the ILD and the substrate is the resistance layer which, along a longitudinal direction, has a first end, a second end, and a heating region in between. Formed through the ILD, the first via plug and the second via plug are respectively electrically coupled to the first end and the second end. The length of the first via plug and the second via plug are, respectively, 1 to 50 μ m. The distance between the edge of the first via plug and the heating region, and the distance between the edge of the second via plug and the heating region are both less than 5 μ m along the longitudinal direction. The controller element is electrically coupled to the second via plug.

Description

Inkjet head heating wafer and method of manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an ink jet head heating wafer and a method of manufacturing the same, and more particularly to a thermal bubble ink jet head heating wafer including a control element, and a method of fabricating the same.

Ink jet printing is a technique of transferring a digital pattern to a recording medium such as paper by pushing a fine ink droplet by an ink jet head. With the rapid development of semiconductor technology in recent years, the resolution of inkjet printers has been greatly improved, and compared with traditional dot matrix printers and laser printers, the noise is small and the price is low, thus becoming the current printing table. The mainstream of the machine. Depending on the inkjet mechanism, a general inkjet printer can be classified into a piezoelectric inkjet printer and a thermal inkjet printer. Piezoelectric inkjet head printers place piezoelectric materials in an inkjet head. When the printer is in operation, a voltage is applied to individual inkjet heads to deform the piezoelectric material to extrude the ink. Piezoelectric inkjet printers have better control of ink and better print quality. However, the price of inkjet heads is also high, so they are common in high-end business or industrial printers. . As for consumer printers, a thermal bubble type inkjet head printer is generally used, and the portion of the inkjet head wafer used to heat the ink is mainly composed of a resistor. When the printer is in operation, a current flows through the resistor to generate high heat, so that a part of the ink in the ink jet head is vaporized to form a bubble, and the residual heat from the bubble absorbing resistor continues to expand, and the ink at the nozzle is ejected to the surface of the recording medium. Since the thermal head type inkjet head printer operates, the instantaneous heating temperature of the ink jet head is extremely high (for example, an aqueous solution-based ink may be heated to nearly 300 ° C), and the repeated temperature rise and fall process may cause an unfavorable structure. The thermal effect reduces device reliability. Therefore, careful design of the structure of the inkjet head to heat the wafer, accelerate its heat dissipation, and reduce the ineffective heat (that is, the heat remaining in the device and unable to effectively heat the ink) is one of the research topics of the thermal bubble type inkjet head printer. .

The invention provides an ink jet head for heating a wafer, which can reduce the inefficient heat and increase the reliability of the device.

The invention provides a method for manufacturing an inkjet head heating wafer, which can manufacture the above-mentioned inkjet head to heat a wafer, which can simplify the process and reduce the cost.

The present invention provides an inkjet head heating wafer comprising: a substrate, an inner dielectric layer, a resistive layer, a first via plug, a second via plug, a control element, and a protective layer. The inner dielectric layer is above the substrate. The resistive layer is between the substrate and the inner dielectric layer, and the resistive layer has a first end, a second end, and a heating zone between the first end and the second end in a lengthwise direction. The first via plug is in contact with the first end through the inner dielectric layer, wherein the first via plug has a length of 1 μm to 50 μm, and the first via plug boundary and the heating region The distance in the length direction is less than 5 μm. a second via plug passes through the inner dielectric layer and is in contact with the second end, wherein the second via plug has a length of 1 μm to 50 μm, and the second via plug boundary is heated The distance of the zone in this length direction is less than 5 μm. The control element is electrically connected to the second via plug. The protective layer is located on the inner dielectric layer plug, the first via plug, the second via plug, and the resistive layer.

In an embodiment of the invention, the thickness of the inner dielectric layer on the heating zone is, for example, less than the thickness of the inner dielectric layer outside the heating zone.

In an embodiment of the invention, the inner dielectric layer has, for example, an opening that exposes a heated region of the resistive layer.

In an embodiment of the invention, the protective layer may further comprise a control element.

In an embodiment of the invention, the control element comprises a metal oxide semiconductor field effect transistor.

In an embodiment of the invention, the metal oxide semiconductor field effect transistor comprises: a gate, a gate dielectric layer, a first doped region, and a second doped region. The gate is located on the substrate. The gate dielectric layer is between the gate and the substrate. The first doped region and the second doped region are respectively located in the substrate on both sides of the gate.

In an embodiment of the invention, the first doped region is electrically connected to the second via plug.

In an embodiment of the invention, the first via plug has a length of 5 μm to 50 μm and the second via plug has a length of 5 μm to 50 μm.

The present invention provides a method of manufacturing an inkjet head heating wafer, comprising: providing a substrate, wherein an isolation structure is formed on the substrate, and the substrate includes an active region adjacent to the isolation structure. Next, a gate dielectric layer is formed over the active region. A layer of material is then formed on the substrate. Thereafter, the material layer is patterned to form a resistive layer on the isolation structure and a gate is formed on the gate dielectric layer. Wherein, the resistive layer has a first end portion, a second end portion and a heating region between the first end portion and the second end portion in a longitudinal direction. Thereafter, a first doped region and a second doped region are formed on both sides of the gate. An inner dielectric layer is then formed on the substrate. Next, a first via plug, a second via plug, and a third via plug are formed through the inner dielectric layer. The first via plug is in contact with the first end, the second via plug is in contact with the second end, and the third via plug is in contact with the first doped region. Then, a conductive layer electrically connecting the second via plug and the third via plug is formed on the inner dielectric layer. Thereafter, a protective layer is formed on the inner dielectric layer and the conductive layer.

In an embodiment of the invention, the step of forming a conductive layer includes forming a conductive layer coupled to the first via plug.

In an embodiment of the invention, after forming the first via plug, the second via plug, and the third via plug, the method further includes removing a portion of the inner dielectric layer to cause heating The thickness of the inner dielectric layer on the region is less than the thickness of the inner dielectric layer outside the heating region.

In an embodiment of the invention, after forming the first via plug, the second via plug, and the third via plug, the method further includes removing a portion of the inner dielectric layer to make the inner layer The layer dielectric layer has an opening that exposes the heated region of the resistive layer.

In an embodiment of the invention, the length of the first via plug is, for example, 1 μm to 50 μm, and the length of the second via plug is, for example, 1 μm to 50 μm.

In an embodiment of the invention, the length of the first via plug is, for example, 5 μm to 50 μm, and the length of the second via plug is, for example, 5 μm to 50 μm.

In an embodiment of the invention, the distance between the first via plug boundary and the heating region in the length direction is, for example, less than 5 μm, and the distance between the second via plug boundary and the heating region in the length direction. For example, less than 5 μm.

In an embodiment of the invention, the substrate comprises a crucible substrate.

In various embodiments of the invention, the material of the inner dielectric layer comprises phosphonium phosphate glass.

Based on the above, the heating wafer provided by the embodiment of the invention can effectively dissipate heat, and can reduce the residual heat and improve the reliability of the heating wafer. In addition, the method provided by the embodiment of the present invention can integrate the semiconductor process to manufacture the above-mentioned inkjet head heating wafer to simplify the manufacturing process of the inkjet head to heat the wafer and reduce the cost thereof.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1D are schematic cross-sectional views showing a plurality of ink jet head heating wafers according to an embodiment of the present invention.

Referring to FIG. 1A, a first inkjet head heating wafer 100 in this embodiment includes a substrate 102, an inner dielectric layer 104, a resistance layer 106, and a first via window. A via plug 108, a second via plug 110, a control element 120, and a protective layer 140. The inner dielectric layer 104 is located above the substrate 102. The material of the substrate 102 is, for example, germanium. The material of the inner dielectric layer 104 is, for example, a phosphorous-silicate glass. In other embodiments, an insulating layer (not shown) is disposed between the substrate 102 and the resistive layer 106. The resistive layer 106 is located between the substrate 102 and the inner dielectric layer 104, wherein the resistive layer 106 has a first end 106a, a second end 106b, and a first end 106a and a second end 106b in the length direction. Heating zone 106c. The material of the resistive layer 106 is, for example, doped polysilicon. In other embodiments of the invention, the material of the resistive layer 106 may also be a metal. The first via plug 108 and the second via plug 110 pass through the inner dielectric layer 104 and are in contact with the first end 106a and the second end 106b, respectively. The material of the first via plug 108 is generally a material having good thermal conductivity, such as copper, and its length L1 in the longitudinal direction is, for example, 1 μm to 50 μm, and the boundary and heating of the first via plug 108 are performed. The distance D1 of the region 106c in the longitudinal direction is less than 5 μm. The material of the second via plug 110 is generally a material having good thermal conductivity, such as copper, and its length L2 in the longitudinal direction is, for example, 1 μm to 50 μm, and the boundary and heating of the second via plug 110 are The distance D2 of the region 106c in the longitudinal direction is less than 5 μm. In addition, the resistive layer 106 is electrically connected to the conductive layer 114 through the first via plug 108 and electrically connected to the conductive layer 112 through the second via plug 110 to allow current to flow through the resistive layer 106. In a preferred embodiment, to increase the heat dissipation effect of the ink jet head heating wafer 100, the length L1 of the first via plug 108 in the length direction is 5 μm to 50 μm and the second via plug 110 is in the length. The length L2 in the direction is 5 μm to 50 μm.

Referring to FIG. 1A , the control component 120 is electrically connected to the second via plug 110 . The material of the protective layer 140 is a material such as hafnium oxide, tantalum nitride or tantalum carbide, which is located on the inner dielectric layer 104, the first via plug 108, and the second via plug 110. In an embodiment of the invention, the control element 120 is, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The MOSFET can be disposed on the substrate 102, including a gate (not shown), a gate dielectric layer (not shown), and a first doped region (not shown) and a second doped region in the substrate 102. (not shown). In an embodiment of the invention, the MOSFET structure is the same as or similar to that used in conventional ink jet head wafers, and those skilled in the art are aware of this structure and therefore will not be described herein. At this time, the MOSFET process can be integrated to simultaneously form the MOSFET and the inkjet head to heat the wafer 100. For example, the gate and the resistance layer 106 of the MOSFET are based on the same material (for example, doped polysilicon, but the doping concentration can be adjusted separately according to requirements). It can be fabricated at the same time, and the protective layer 140 can also cover the control element 120 in this situation.

In an embodiment of the present invention, depending on different process parameters, between the first via plug 108 and the second via plug 110, the inner dielectric layer 104 may have in addition to FIG. 1A. Several patterns are shown in FIGS. 1B to 1D. In FIGS. 1A and 1C, the thickness of the inner dielectric layer 104 on the heating region 106c is less than the thickness of the inner dielectric layer 104 outside the heating region 106c. In FIGS. 1A and 1C, the heating zone 106c is covered under the inner dielectric layer 104, while in FIGS. 1B and 1D, the inner dielectric layer 104 has an opening 104a exposing the heating zone 106c. It should be noted that in both cases shown in FIG. 1C and FIG. 1D, D1 and D2 are equal to zero.

When the ink jet head heats the wafer, the heat generated by the resistive layer 106 is transferred upward from the heating zone 106c to heat the ink to boil and generate bubbles. At both ends of the resistive layer 106, the residual heat is dissipated through the first via plug 108 and the second via plug 110, and the heat dissipation capability is equal to the area of contact between the first via plug 108 and the resistive layer 106. In proportion, it is also proportional to the area of contact between the second via plug 110 and the resistive layer 106. In the present embodiment, the lengths L1 and L2 of the via plugs 108 and 110 of the heater wafer 100 are 1 μm to 50 μm; preferably 5 μm to 50 μm, so that heat dissipation can be effectively performed, and the first via plug 108 is lowered. The contact resistance between the resistive layer 106 and the second via plug 110 and the resistive layer 106 prevents energy from being wasted excessively due to excessive resistance. In addition, the ineffective heat mainly remains at the edge of the heating zone 106c (for example, as shown in Fig. 1A, both sides of the heating zone 106c, and two regions of width D1 and D2). The heating wafer 100 in the embodiment of the present invention has a heating zone 106c which is in close proximity to the first via plug 108 and the second via plug 110, so that the residual heat can be effectively suppressed, that is, in the The heat generated by the resistive layer 106 is transferred to the ink either upwards or at both ends of the resistive layer 106 via the first via plug 108 and the second via plug 110, with only a small portion remaining in the resistive layer. 106. Thereby, the reliability of the heating wafer 100 can be improved.

2A-2E are schematic cross-sectional views showing a manufacturing process of an inkjet head heating wafer according to another embodiment of the invention.

First, please refer to FIG. 2A. Providing a substrate 200, a material of the substrate 200, such as germanium, on which an isolation structure 240 has been formed, such as shallow trench isolation, which is formed by, for example, forming a plurality of trenches on the substrate 200 by a pattern etching process. The groove is filled with an insulating material filled with an insulating material such as yttrium oxide. In other embodiments, the isolation structure 240 can also be a field oxide layer formed using a thermal oxidation process. The isolation structure 240 defines an active region 220 in the substrate 200. Next, a gate dielectric layer 222 is formed over the active region 220.

Then, referring to FIG. 2B, a material layer 201 is formed on the substrate 200. The material of the material layer 201 is, for example, polycrystalline germanium, and the formation method thereof is, for example, plasma-assisted chemical vapor deposition using decane as a source of germanium material.

Thereafter, referring to FIG. 2C, the material layer 201 is patterned to form a gate 224 on the gate dielectric layer 222, and a resistive layer 202 is formed on the isolation structure 240. The resistance layer 202 has a first end portion 202a, a second end portion 202b, and a heating region 202c between the first end portion 202a and the second end portion 202b in the longitudinal direction, wherein the first end portion 202a and the second end portion 202b It is a non-heating zone (ie, an area that does not directly heat the ink). Since the resistivity required for the resistive layer 202 and the gate 224 may be different under the operating conditions in which the ink jet head heats the wafer, different doping concentrations may be applied to the resistive layer 202 and the gate 224 to meet the demand. For example, the power required to heat the wafer can be calculated from the temperature required to vaporize the ink and the amount of ink in each inkjet head, and the resistance that the resistive layer 202 should have is calculated from the power required to heat the wafer. In the case where the size of the resistance layer 202 has been determined, the sheet resistance of the resistance layer 202 is regulated by, for example, ion implantation, so that the resistance layer 202 has a desired resistance value. In other embodiments of the invention, material layer 201 may also be a metal formed by methods such as physical vapor deposition. Thereafter, in the substrate 200 on both sides of the gate 224, a first doping region 226 and a second doping region 228 are formed, for example, by ion implantation, that is, a conventional MOSFET is formed on the active region 220. For example, if the substrate 200 is an n-type substrate, the first doped region 226 and the second doped region 228 may be p-doped regions doped with phosphorus.

Referring to FIG. 2D, an inner dielectric layer 204 is formed on the substrate 200. The material of the inner dielectric layer 204, such as a phosphonate glass, is formed by, for example, forming a cerium oxide by chemical vapor deposition or thermal oxidation, followed by doping with phosphorus, and then forming it by reflow. Flat surface to facilitate subsequent metal wiring process. Thereafter, the first via, the second via, and the third via through the inner dielectric layer 204 are formed by prior art techniques such as photolithography etching, sputtering, chemical vapor deposition, and chemical mechanical polishing. The window is filled with a suitable material (e.g., a thermally conductive material), such as copper, to form a first via plug 206, a second via plug 208, and a third via plug 210, respectively. The first via plug 206 is in contact with the first end 202a, the second via plug 208 is in contact with the second end 202b, and the third via plug 210 is in contact with the first doped region 226. The length L3 of the first via plug 206 in the length direction is, for example, 1 μm to 50 μm (5 μm to 50 μm in the preferred embodiment), and the length L4 of the second via plug 208 in the length direction. For example, it is 1 μm to 50 μm (preferably, 5 μm to 50 μm). The first via plug 206, the second via plug 208, and the third via plug 210 are formed by a method such as chemical vapor deposition.

Subsequently, referring to FIG. 2E , a conductive layer 212 is formed on the inner dielectric layer 204 to electrically connect the second via plug 208 to the third via plug 210 . The material of the conductive layer 212 is, for example, gold, copper, aluminum, or aluminum copper (AlCu). The material of the conductive layer 212 is, for example, aluminum. The formation method is, for example, first forming an aluminum thin film on the inner dielectric layer 204 by physical vapor deposition, and then patterning the aluminum thin film to make the second via plug 208 and The third via plugs 210 are electrically connected by a conductive layer 212. In another embodiment of the present invention, the conductive layer 212 is also electrically connected to the first via plug 206, but there is no electrical connection between the first via plug 206 and the second via plug 208. .

In other embodiments of the present invention, a portion of the inner dielectric layer 204 may be further removed to form a recess 204a recessed toward the heating region 202c (as shown in FIG. 2E, or FIGS. 1A, 1C) such that the heating region 202c The thickness of the upper inner dielectric layer 204 is smaller than the thickness of the inner dielectric layer 204 outside the heating region 202c to increase the effect of the heating region on the ink heating. At this time, the distance D3 between the boundary of the first via plug 206 and the heating region 202c in the longitudinal direction is less than 5 μm, and the distance D4 between the boundary of the second via plug 208 and the heating region 202c in the longitudinal direction is also less than 5 μm. In other embodiments of the invention, after removing a portion of the inner dielectric layer 204, it is also possible to form an opening that exposes the heated region 202c (as in FIG. 1B or FIG. 1D). In other embodiments, D3 and D4 are equal to zero (as in Figure 1C or Figure 1D).

Thereafter, a protective layer 260 is formed on the inner dielectric layer 204 and the conductive layer 212. The material of the protective layer 260 is, for example, ruthenium oxide, tantalum nitride or tantalum carbide, and a formation method thereof such as chemical vapor deposition.

In summary, embodiments of the present invention provide a method of fabricating an inkjet head heated wafer that is compatible with a typical MOSFET process and electrically interconnects the MOSFET control component with a resistive layer for heating by an interconnect process. Compared with the conventional heater-controller-manufactured process, the manufacturing method of the embodiment of the present invention can simplify the manufacturing process of the ink-jet head heating wafer and reduce the cost thereof. In addition, the heating wafer manufactured by the manufacturing method provided by the embodiment of the present invention has a sufficiently long via window plug length (between 1 μm and 50 μm; in the preferred embodiment, between 5 μm and 50 μm), so it can be effective Heat dissipation reduces the contact resistance between the via plug and the resistive layer, avoiding unnecessary energy loss due to excessive resistance. The heating wafer manufactured by the manufacturing method provided by the embodiment of the present invention further has a heating zone which is very close to the via window plug, so that the residual heat can be effectively suppressed and the reliability of the heated wafer can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Inkjet head heating wafer

102, 200. . . Base

104, 204. . . Inner dielectric layer

104a, 204a. . . Opening

106, 202. . . Resistance layer

106a, 202a. . . First end

106b, 202b. . . Second end

106c, 202c. . . Heating zone

108, 206. . . First via window plug

110, 208. . . Second layer window plug

112, 114, 212. . . Conductive layer

120. . . control element

140, 260. . . The protective layer

201. . . Material layer

210. . . Third layer window plug

220. . . Active zone

222. . . Gate dielectric layer

224. . . Gate

226. . . First doped region

228. . . Second doped region

240. . . Isolation structure

L1, L2, L3, L4. . . length

D1, D2, D3, D4. . . distance

1A-1D are schematic cross-sectional views of different types of inkjet head heating wafers according to an embodiment of the invention.

2A-2E are schematic cross-sectional views showing a manufacturing process of an inkjet head heating wafer according to an embodiment of the invention.

100. . . Inkjet head heating wafer

102. . . Base

104. . . Inner dielectric layer

106. . . Resistance layer

106a. . . First end

106b. . . Second end

106c. . . Heating zone

108. . . First via window plug

110. . . Second layer window plug

112, 114. . . Conductive layer

120. . . control element

140. . . The protective layer

L1, L2. . . length

D1, D2. . . distance

Claims (18)

An inkjet head heating wafer includes: a substrate; an inner dielectric layer on the substrate; a resistive layer between the substrate and the inner dielectric layer, wherein the resistive layer is in a length direction The upper portion has a first end portion, a second end portion and a heating region between the first end portion and the second end portion; a first via plug passes through the inner dielectric layer and Contacting the first end portion, wherein the first via plug has a length of 1 μm to 50 μm, and a distance between the first via plug boundary and the heating region in the length direction is less than 5 μm; a second via plug that passes through the inner dielectric layer and is in contact with the second end, wherein the second via plug has a length of 1 μm to 50 μm, and the second via a plug boundary and the heating zone are less than 5 μm in the length direction; a control element electrically connected to the second via plug; and a protective layer located in the inner dielectric layer, the first a via plug, the second via plug, and the resistive layer. The inkjet head heating wafer of claim 1, wherein the thickness of the inner dielectric layer on the heating zone is less than the thickness of the inner dielectric layer outside the heating zone. The inkjet head heating wafer of claim 1, wherein the inner dielectric layer has an opening exposing the heating zone of the resistive layer. The inkjet head heating wafer of claim 1, wherein the protective layer further comprises a control element. The ink jet head heating wafer of claim 1, wherein the control element comprises a metal oxide semiconductor field effect transistor. The inkjet head heater chip of claim 5, wherein the metal oxide semiconductor field effect transistor comprises: a gate on the substrate; a gate dielectric layer located at the gate and the gate Between the substrates; and a first doped region and a second doped region are respectively located in the substrate on both sides of the gate. The inkjet head heating wafer of claim 6, wherein the first doped region is electrically connected to the second via plug. The inkjet head heating wafer of claim 1, wherein the inner dielectric layer comprises phosphonium phosphate glass. The inkjet head heating wafer of claim 1, wherein the first via plug has a length of 5 μm to 50 μm and the second via plug has a length of 5 μm to 50 μm. . A method for manufacturing an inkjet head heating wafer, comprising: providing a substrate, wherein the substrate is formed with an isolation structure, and the substrate comprises an active region adjacent to the isolation structure; forming a gate dielectric on the active region An electric layer; forming a material layer on the substrate; patterning the material layer to form a resistive layer on the isolation structure, and forming a gate on the gate dielectric layer, wherein the resistive layer is a lengthwise direction having a first end portion, a second end portion, and a heating region between the first end portion and the second end portion; forming a first doped region on both sides of the gate electrode and a second doped region; forming an inner dielectric layer on the substrate; forming a first via plug, a second via plug, and a third through the inner dielectric layer a via plug, wherein the first via plug is in contact with the first end, the second via plug is in contact with the second end, the third via plug and the third Contacting a doped region; electrically connecting the second via plug and the third via on the inner dielectric layer A plug insertion conductive layer; and forming a protective layer on the dielectric layer and the inner conductive layer. The method of manufacturing an ink-jet head heating wafer according to claim 10, wherein the forming the conductive layer comprises forming the conductive layer electrically connected to the first via plug. The method of manufacturing an inkjet head heating wafer according to claim 10, wherein after forming the first via plug, the second via plug, and the third via plug And further comprising removing a portion of the inner dielectric layer such that a thickness of the inner dielectric layer on the heating region is less than a thickness of the inner dielectric layer outside the heating region. The method of manufacturing an inkjet head heating wafer according to claim 10, wherein after forming the first via plug, the second via plug, and the third via plug And further comprising removing a portion of the inner dielectric layer such that the inner dielectric layer has an opening exposing the heating region of the resistive layer. The method for manufacturing an ink jet head heating wafer according to claim 10, wherein the first via plug has a length of 1 μm to 50 μm, and the second via plug has a length of 1 Mm to 50 μm. The method for manufacturing an ink jet head heating wafer according to claim 10, wherein the first via plug has a length of 5 μm to 50 μm, and the second via plug has a length of 5 Mm to 50 μm. The method for manufacturing an inkjet head heating wafer according to claim 10, wherein a distance between the first via plug boundary and the heating region in the length direction is less than 5 μm, and the second via window The plug boundary is at a distance of less than 5 μm from the heating zone in the length direction. The method of manufacturing an ink jet head heating wafer according to claim 10, wherein the substrate comprises a crucible substrate. The method of manufacturing an ink jet head heating wafer according to claim 10, wherein the material of the inner dielectric layer comprises a phosphonate glass.