TW201310539A - Method of forming Non-planar FET - Google Patents

Abstract

A method of forming a Non-Planar FET is provided. A substrate is provided. An active region and a peripheral region are defined on the substrate. A plurality of VSTI are formed in the active region of the substrate. A part of each VSTI is removed to expose a part of sidewall of the substrate. Then, a conductor layer is formed on the substrate which is then patterned to form a planar FET gate in the peripheral region and a Non-planar FET gate in the active region simultaneously. Last, a source/drain region is formed on two sides of the Non-planar FET gate.

Description

A way to form a non-planar transistor

The present invention relates to a method of fabricating a non-planar crystal structure, and more particularly to a method of simultaneously forming a non-planar transistor and a planar transistor.

In recent years, as various consumer electronic products continue to be miniaturized, the size of semiconductor component designs has been shrinking to meet the trend of high integration, high efficiency, low power consumption, and product demand.

However, with the miniaturization of electronic products, existing planar transistors have been unable to meet the needs of products. Therefore, a non-planar fin-transistor (Fin-FET) technology has been developed, which has a three-dimensional gate channel structure, which can effectively reduce leakage of the substrate and reduce short channels. Effect and high drive current. However, since the fin-shaped transistor is a three-dimensional structure, it is more complicated than the conventional structure, and the manufacturing difficulty is also high. Generally, it is formed on a silicon-on-insulator (SOI) substrate, and is compatible with the existing germanium. The base process is somewhat difficult. Moreover, since the fin-shaped transistor is made in a special manner, it also encounters certain problems when it is integrated with the existing planar transistor.

The present invention thus provides a method of simultaneously forming a non-planar transistor and a planar transistor.

According to an embodiment, the present invention provides a way to form a non-planar transistor. A substrate is first provided with an active region and a peripheral region defined on the substrate. A plurality of ultra-shallow trench isolations are then formed in the active region of the substrate. A portion of the ultra-shallow trench isolation is then removed to expose a portion of the sidewall of the substrate. A conductive layer is formed on the active region and the peripheral region on the substrate, and covers a portion of the sidewall of the substrate. The conductive layer is patterned such that the conductive layer forms a gate of a planar transistor in the peripheral region and a gate of at least one non-planar transistor is formed in the active region. A source/drain is formed on both sides of the gate of the fin electrode.

The invention provides a method for simultaneously defining a gate of a planar transistor and a non-planar transistor by only one mask, and both have gates of the same level, and the process is simple. In addition, the present invention also integrates a method of forming an ultra-shallow trench isolation process in the active region and forming shallow trench isolation in the isolation region, and since the same mask layer is used for pattern transfer, the overall process is not affected. .

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 10 , which are schematic diagrams showing the steps of forming a non-planar transistor according to the present invention. As shown in FIG. 1, a substrate 300 is first provided. The substrate 300 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, or a silicon carbide substrate. Or a silicon-on-insulator (SOI) substrate, etc., but not limited to the above. An active area 301, an isolation area 303 surrounding one of the active areas 301, and a peripheral area 305 are defined on the substrate 300. The active region 301 is used to generate a region of a subsequent non-planar transistor, and the peripheral region 305 is, for example, a high voltage component region, such as an input/output region (input/output region), in which an operation can be subsequently formed. In a 1.8 volt or higher voltage MOS transistor, in one embodiment, these high voltage MOS transistors are planar transistors. Next, a liner layer 302 and a mask layer 304 are formed over the substrate 300. In one embodiment of the invention, the liner layer 302 is, for example, a hafnium oxide layer (SiO ₂ ), and the mask layer 304 is, for example, a nitride layer (SiN). The thickness of the mask layer 304 is 60 to 150 angstroms, preferably 100 angstroms, and the thickness of the backing layer 302 is 15 to 50 angstroms, preferably 20 angstroms. Next, a first patterned photoresist layer 306 is formed on the mask layer 304. The first patterned photoresist layer 306 may be a single layer structure or a multilayer structure. In an embodiment, the first patterned photoresist layer 306 may include an anti-reflection layer, for example. The first patterned photoresist layer 306 has a plurality of openings to expose the mask layer 304 in the isolation region 303. Next, an etching process is performed with the first patterned photoresist layer 306 as a mask to etch the mask layer 304, transfer the pattern to the mask layer 304 and the liner layer 302, and then remove the first patterned photoresist layer. 306.

As shown in FIG. 2, the substrate 300 is etched by using the mask layer 304 as a mask to form a first trench 308 in the isolation region 303 of the substrate 300. The depth of the first trench 308 is generally between 2000 and 3000 angstroms. After the first trench 308 is formed, a mask layer 304 pull back may be selectively performed such that the mask layer 304 is equidistant from the first trench 308. In an embodiment, a cleaning step can also be performed, for example, using the RCA1 solution (NH ₄ OH+H ₂ O ₂ +H ₂ O) or the RCA2 solution (HCl+H ₂ O ₂ +H ₂ O) to the first trench. The bottom or side wall of the 308 is cleaned. Alternatively, an in-situ stream growth (ISSG) is performed to form an oxide layer (not shown) at the bottom or sidewall of the first trench 308.

As shown in FIG. 3, a first insulating layer 310 is formed on the substrate 300 and filled in at least the first trench 308. In an embodiment, the first insulating layer 310 is, for example, hafnium oxide or other suitable insulating material. Then, a planarization process, such as a chemical mechanical polish (CMP), is performed such that the top surfaces of the first insulating layer 310 and the mask layer 304 are substantially flush.

As shown in FIG. 4, the mask layer 304 located in the active region 301 is patterned. For example, a second patterned photoresist layer (not shown) is formed on the substrate 300 to cover the isolation region 303, the peripheral region 305, and a portion of the active region 301, and is etched by using the second patterned photoresist layer as a mask. The process transfers the pattern to the mask layer 304 and the liner layer 302 and then removes the second patterned photoresist layer. Then another etching process is performed to form the mask layer 304 and the liner layer 302 as masks and further etched to the substrate 300, thereby forming a plurality of second trenches 314 in the substrate 300 of the active region 301. The second trenches 314 have a depth generally between 200 and 500 angstroms, are substantially parallel to each other, and are disposed in the active region 301.

Next, as shown in FIG. 5, a second insulating layer 316 is formed on the substrate 300 to fill at least the second trench 314. The material of the second insulating layer 316 and the first insulating layer 310 may be the same as, for example, cerium oxide, but may be different. Finally, a planarization process is performed such that the first insulating layer 310 located in the first trench 308 and the second insulating layer 316 located in each of the second trenches 314 and the top surface of the mask layer 304 are substantially flush. In this manner, in the active region 301, the first insulating layer 310 in the first trench 308 of the isolation region 303 can form a shallow trench isolation (STI) 311, and each of the active regions 301 The second insulating layer 316 in the second trench 314 forms a plurality of very shallow trench isolation (VSTI) 317. In addition, another embodiment of the present invention may form the shallow trench isolations 317 after forming the ultra-shallow trench isolations 317, and the shallow trench isolations 311 may be formed by the same layer of masks, which are all within the scope of the present invention.

As shown in FIG. 6, a third patterned photoresist layer 318 is formed on the substrate 300. In one embodiment, the third patterned photoresist layer 318 has an opening to expose all of the second insulating layer 316 in the active region 301. In another preferred embodiment, as shown in FIG. 6, one side wall of the opening can be slightly narrowed inwardly, staying on the top surface of the ultra-shallow trench isolation 317 on both sides of the outermost periphery, but will not stay at Two ultra shallow trenches are isolated on the mask layer 304 between the 317.

As shown in FIG. 7, an etching process is performed with the third patterned photoresist layer 318 as a mask to remove a portion of the second insulating layer 316 that is not covered by the third patterned photoresist layer 318. The depth of the etch will be lower than the top surface of the substrate 300, and at least a portion of the substrate 300 between the second trenches 314 will expose the sidewalls to form the desired fin structure 321 .

As shown in FIG. 8 , after the third patterned photoresist layer 318 , the mask layer 304 , and the liner layer 302 are removed, a dielectric layer 319 and a conductive layer 320 are sequentially formed on the substrate 300 . Dielectric layer 319 can be, for example, hafnium oxide or a high-k dielectric layer. The high-k dielectric layer can be selected, for example, from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), Aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconia (zirconium oxide, ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), antimony oxidation (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _{1) a} group consisting of _-x TiO ₃ , BST). The conductive layer 320 is, for example, a polysilicon layer or a metal layer. The dielectric layer 319 can be prepared by a chemical vapor deposition or thermal oxidation, and the dielectric layer 319 and the conductive layer 320 are filled in each of the second trenches 314 and contact the exposed top surface and the sidewalls of the substrate 300. The top surface and the sidewall of each fin structure 321 can also be accessed, thereby effectively increasing the width of the gate channel.

Finally, as shown in FIGS. 9 and 10, the conductive layer 320 is patterned. The patterned conductive layer 320 forms at least one non-planar transistor gate 324 in the active region 301 and simultaneously forms at least one planar transistor gate 322 in the peripheral region 305. In addition, in an embodiment, various suitable source/drain 323 doped regions may be formed in the fin structure 321 on both sides of each gate of the active region 301 and in the substrate 300 of the peripheral region 305. The structure of the non-planar transistor and the planar transistor is formed. After the non-planar transistor or the planar transistor is completed, many steps may be involved, such as forming a stress layer or forming a metal halide or the like, which will not be described herein. It can be understood that the foregoing fabrication method is exemplified by a fin-shaped transistor (Fin-FET) in a non-planar gate, but can be applied to other non-planar transistors without affecting the content of the present invention. Production.

It should be noted here that after the patterning process, although the thickness of the gate 324 of the non-planar transistor is greater than the thickness of the gate 322 of the planar transistor, the gate 324 of the non-planar transistor and the planar transistor The gates 322 will have the same level. This has the advantage that, in the subsequent metal gate last process, when the planarization process is performed to expose the gate 324 of the non-planar transistor and the gate 322 of the planar transistor, there is less The difference in height can be exposed at the same time.

In summary, the present invention provides a method for simultaneously defining a gate of a planar transistor and a gate having a same level of height of a non-planar transistor, requiring only one mask, and the process is simple. In addition, the present invention also integrates a method of forming an ultra-shallow trench isolation process in the active region and forming shallow trench isolation in the isolation region, and since the same mask layer is used for pattern transfer, the overall process is not affected. .

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300. . . Base

301. . . Active zone

302. . . Liner layer

303. . . quarantine area

304. . . Mask layer

305. . . Surrounding area

306. . . First patterned photoresist layer

308. . . First ditches

310. . . First insulating layer

311. . . Shallow trench isolation

314. . . Second ditches

316. . . Second insulating layer

317. . . Ultra shallow trench isolation

318. . . Third patterned photoresist layer

319. . . Dielectric layer

320. . . Conductive layer

321. . . Fin structure

322. . . Gate of planar transistor

323. . . Source/bungee

324. . . Non-planar transistor gate

1 to 10 are schematic views showing the steps of forming a non-planar transistor of the present invention.

300. . . Base

311. . . Shallow trench isolation

317. . . Ultra shallow trench isolation

319. . . Dielectric layer

321. . . Fin structure

322. . . Gate of planar transistor

323. . . Source/bungee

324. . . Non-planar transistor gate

Claims (11)

A method for forming a non-planar transistor includes: providing a substrate having an active region and a peripheral region defined thereon; forming a plurality of ultra-shallow trench isolations in the active region of the substrate; removing each of the ultra-shallow trenches a portion such that the substrate exposed by each of the ultra-shallow trench isolation spaces constitutes a plurality of fin structures; a conductive layer is formed on the active region and the peripheral region on the substrate, and each of the fin structures is covered Patterning the conductive layer such that the conductive layer forms one gate of a planar transistor in the peripheral region while simultaneously forming at least one gate of the non-planar transistor in the active region; and the non-planar electricity A source/drain is formed in the fin structure on both sides of the gate of the crystal. A method of forming a non-planar transistor according to claim 1, wherein the conductive layer comprises polycrystalline germanium or a metal. The method of forming a non-planar transistor according to claim 1, wherein the substrate further comprises an isolation region surrounding the active region. The method of forming a non-planar transistor according to claim 3 of the patent application, further comprising forming a shallow trench isolation in the isolation region. For example, in the method for forming a non-planar transistor according to item 4 of the patent application, the shallow trench is first formed to be isolated, and then the ultra-shallow trench is isolated. For example, in the method for forming a non-planar transistor according to Item 4 of the patent application, the shallow trench isolation is formed after the super shallow trench is isolated. The method for forming a non-planar transistor according to claim 4, further comprising: forming a mask layer on the substrate; patterning the mask layer to form a first patterned mask in the isolation region a layer is formed by etching the substrate with the first patterned mask layer as a mask to form a first trench in the isolation region, and filling a first insulating layer in the first trench to form the shallow trench isolation Patterning the mask layer to form a second patterned mask layer in the active region; and etching the substrate with the second patterned mask layer as a mask to form at least one in the active region a second trench, and a second insulating layer is filled in the second trench to form the ultra-shallow trench isolation. The method of forming a non-planar transistor according to claim 4, wherein the step of forming the fin structures comprises: forming a patterned mask layer on the substrate, the patterned mask layer having an opening, and One side wall of the opening is correspondingly disposed on the ultra-shallow trench isolation closest to the isolation region; and an etching process is performed by using the patterned mask layer as a mask to form the fin structures. A method of forming a non-planar transistor according to claim 4, wherein the shallow trench is isolated in the substrate to a depth of substantially 2000 angstroms to 3,000 angstroms. A method of forming a non-planar transistor according to claim 4, wherein the ultra-shallow trench is isolated in the substrate to a depth of substantially 200 to 500 angstroms. A method of forming a non-planar transistor according to claim 1, wherein the gate of the planar transistor has the same level as the gate of the non-planar transistor.