TW201301456A - Buffer sheet and COF bonding method applying the buffer sheet - Google Patents

Buffer sheet and COF bonding method applying the buffer sheet Download PDF

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TW201301456A
TW201301456A TW100122932A TW100122932A TW201301456A TW 201301456 A TW201301456 A TW 201301456A TW 100122932 A TW100122932 A TW 100122932A TW 100122932 A TW100122932 A TW 100122932A TW 201301456 A TW201301456 A TW 201301456A
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flip chip
film layer
film
thermal
layer
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TW100122932A
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TWI441293B (en
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Chu-Chun Lo
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Au Optronics Corp
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Abstract

A buffer sheet is adapted to bonding process of a chip-on-film (COF) and a substrate. The buffer sheet includes a first film layer, a thermal resistant layer and a second film layer stacked in order. The thermal expansion modulus of the thermal resistant layer is smaller than those of the first and the second film layer. Accordingly, when a heat header does not press against the COF, the most of heat from the header can be isolated by the buffer sheet. The heat of the header can be transferred to the conductive glue sandwiched between the COF and the substrate when the header presses the buffer sheet against the COF. Therefore, the temperature and thermal expansion of the COF can be accurately controlled.

Description

緩衝元件及應用此緩衝元件之覆晶軟膜接合方法Buffer element and flip chip bonding method using the same

本揭露係關於一種緩衝元件,特別是一種應用於覆晶軟膜接合之緩衝元件及其接合方法。The present disclosure relates to a cushioning member, and more particularly to a cushioning member for use in flip chip bonding and a bonding method thereof.

一般而言,將覆晶軟膜(Chip on Film)接合於液晶面板之方式多採用熱壓製程,在熱壓製程中,覆晶軟膜先被疊置於液晶面板,其後再以熱壓頭壓抵覆晶軟膜,因此,位於覆晶軟膜與液晶面板之間的膠材即會將覆晶軟膜及液晶面板膠合。此外,在前述壓抵過程中,熱壓頭通常經由緩衝材而壓抵覆晶軟膜。In general, a method of bonding a chip on film to a liquid crystal panel is generally performed by a hot pressing process. In the hot pressing process, the flip chip is first stacked on the liquid crystal panel, and then pressed by a hot head. The film is covered by the soft film. Therefore, the glue between the crystal film and the liquid crystal panel will bond the crystal film and the liquid crystal panel. Further, in the aforementioned pressing process, the thermal head is usually pressed against the flip chip by the buffer material.

在上述熱壓製程中,液晶面板的走線與覆晶軟膜的晶片外引線需完成對應的電性連接,走線與外引線通常為平行的電性接線(如金手指般),由於外引線所在的覆晶軟膜的熱膨脹係數大於走線所在的液晶面板的熱膨脹係數,因此,在熱壓前(如常溫下),外引線之間的間距通常小於走線之間的間距,當熱壓頭壓抵覆晶軟膜時,因覆晶軟膜的熱膨脹量大於液晶面板(玻璃)的熱膨脹量,故在熱膠合溫度時,外引線與走線即能對應地形成電性連接。In the above hot pressing process, the wiring of the liquid crystal panel and the outer lead of the flip chip are required to be electrically connected, and the wiring and the outer lead are usually parallel electrical wiring (like a gold finger), due to the outer lead The thermal expansion coefficient of the flip chip is higher than the thermal expansion coefficient of the liquid crystal panel where the trace is located. Therefore, before hot pressing (such as normal temperature), the spacing between the outer leads is usually smaller than the spacing between the traces, when the thermal head When the flip chip is pressed against the soft film, since the amount of thermal expansion of the flip chip is larger than the amount of thermal expansion of the liquid crystal panel (glass), the outer lead and the trace can be electrically connected correspondingly at the thermal bonding temperature.

雖然在上述之覆晶軟膜的熱壓製程能達到對應電性連接之目的,但是在實作時,覆晶軟膜之溫度並不易控制,當溫度未落在預定範圍時,覆晶軟膜之熱膨脹量將不足或過大,致電性連接不良或錯誤。此外,在實際製程中,前述緩衝材係配置於熱壓頭與覆晶軟膜之間,致覆晶軟膜之溫度將更不易控制,更易形成不良之電性連接。Although the hot pressing process of the above-mentioned flip chip soft film can achieve the purpose of corresponding electrical connection, in practice, the temperature of the flip chip soft film is not easy to control, and when the temperature does not fall within a predetermined range, the thermal expansion amount of the flip chip soft film Will be insufficient or too large, poorly connected or wrong. In addition, in the actual process, the buffer material is disposed between the thermal head and the flip chip, and the temperature of the crystal film is more difficult to control, and it is easier to form a poor electrical connection.

鑒於以上,本揭露提出緩衝元件及應用此緩衝元件之覆晶軟膜接合方法,適於將覆晶軟膜接合於基板。In view of the above, the present disclosure proposes a buffer element and a flip chip bonding method using the buffer element, which is suitable for bonding a flip chip to a substrate.

依據一實施例,緩衝元件包含依序疊置的第一膜層、熱阻層及第二膜層。熱阻層之熱傳導係數小於0.13 W/m-k。第一膜層之熱傳導係數為0.4 W/m-k。第二膜層之熱傳導係數大於該第一膜層之熱傳導係數。According to an embodiment, the buffer element comprises a first film layer, a thermal resistance layer and a second film layer which are sequentially stacked. The thermal resistance layer has a thermal conductivity of less than 0.13 W/m-k. The first film has a heat transfer coefficient of 0.4 W/m-k. The thermal conductivity of the second film layer is greater than the thermal conductivity of the first film layer.

依據一實施例,第二膜層包含導熱粉,且熱傳導係數為0.3 W/m-k。前述熱阻層之厚度介於0.06毫米至0.1毫米之間。第一膜層之厚度為0.05毫米,第二膜層之厚度為0.1毫米。熱阻層之熱傳導係數小於第二膜層之熱傳導係數。According to an embodiment, the second film layer comprises a thermally conductive powder and has a heat transfer coefficient of 0.3 W/m-k. The thickness of the aforementioned thermal resistance layer is between 0.06 mm and 0.1 mm. The first film layer has a thickness of 0.05 mm and the second film layer has a thickness of 0.1 mm. The thermal conductivity of the thermal resistance layer is smaller than the thermal conductivity of the second coating.

依據一實施例,應用緩衝元件之覆晶軟膜接合方法包含以熱壓頭抵壓緩衝元件於一疊置有一覆晶軟膜之基板上,覆晶軟膜與基板間具有導電膠材,而熱壓頭之溫度為380℃;以及持續抵壓該基板一預定時間後,退回該熱壓頭。According to an embodiment, a flip chip bonding method using a buffer element includes pressing a buffer element with a thermal head on a substrate on which a flip chip is laminated, and a conductive adhesive material is interposed between the flip chip and the substrate, and the thermal head is The temperature is 380 ° C; and after the substrate is continuously pressed for a predetermined time, the thermal head is returned.

藉由上述緩衝元件之結構,在熱壓頭尚未壓下(或是未接觸到緩衝元件),緩衝元件可以將熱壓頭之熱量隔離,而不致預熱覆晶軟膜,當熱壓頭抵壓緩衝元件於覆晶軟膜時,熱量可以迅速地傳導至導電膠材,而待熱壓頭退回後,熱量亦被緩衝元件隔離於熱壓頭周圍,而不致於持續對覆晶軟膜加熱,因而,能更有效地控制覆晶軟膜的接合溫度,並提高電性連接的良率。By the structure of the above buffer element, the buffer element can isolate the heat of the thermal head without pressing the thermal head (or the buffer element is not contacted), without preheating the flip chip, when the hot head is pressed When the buffer element is on the flip chip, the heat can be quickly transferred to the conductive paste, and after the hot head is retracted, the heat is also separated by the buffer element around the hot head without continuously heating the flip chip. It can more effectively control the bonding temperature of the flip chip and improve the yield of electrical connection.

以上有關於本揭露的內容說明,與以下的實施方式係用以示範與解釋本揭露的精神與原理,並且提供本揭露的專利申請範圍更進一步的解釋。有關本揭露的特徵、實作與功效,茲配合圖式作較佳實施例詳細說明如下。The above description of the disclosure is intended to be illustrative of the spirit and principles of the disclosure, and to provide further explanation of the scope of the disclosure. The features, implementations, and effects of the present disclosure are described in detail below with reference to the preferred embodiments.

以下在實施方式中詳細敘述本揭露之詳細特徵以及優點,其內容足以使任何熟習相關技藝者了解本揭露之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本揭露相關之目的及優點。The detailed features and advantages of the present disclosure are described in detail in the following detailed description of the embodiments of the present disclosure, which are The objects and advantages associated with the present disclosure can be readily understood by those skilled in the art.

首先,請參考「第1圖」,其為根據本揭露一實施例之緩衝元件之結構示意圖。緩衝元件(Buffer Sheet) 10適於一覆晶軟膜(Chip on Film)製程。請搭配「第2A圖」閱覽之。從「第2A圖」可以看見緩衝元件10係捲繞於覆晶軟膜製程中的滾筒52a,52b,滾筒52a,52b各別配置於熱壓頭(Head) 30兩側的卡匣(Buffer Sheet Cassette)50a,50b內。此熱壓頭30亦可稱為本壓頭。First, please refer to "FIG. 1", which is a schematic structural diagram of a buffer element according to an embodiment of the present disclosure. The Buffer Sheet 10 is suitable for a chip on film process. Please read it with "Figure 2A". It can be seen from "Fig. 2A" that the cushioning member 10 is wound around the rollers 52a, 52b in the flip chip process, and the rollers 52a, 52b are respectively disposed on the sides of the heat head 30 (Buffer Sheet Cassette). ) 50a, 50b. This thermal head 30 can also be referred to as the present pressure head.

覆晶軟膜22配置於一基板20上,基板20可以是液晶面板或其他欲與覆晶軟膜22接合之基板。覆晶軟膜22上具有一晶片24,於覆晶軟膜22及基板之間,具有導電膠材,導電膠材可以是但不限於異方性導電膠(ACF,Anisotropic Conductive Film)及各種熱固化型膠材。當覆晶軟膜22接合於基板20後,晶片24的外引線即對應地電性連接於基板20上的走線,關於此接合過程,容後詳述。The flip chip 22 is disposed on a substrate 20, which may be a liquid crystal panel or other substrate to be bonded to the flip chip 22. The flip chip 22 has a wafer 24 on the between the flip chip 22 and the substrate, and has a conductive adhesive. The conductive adhesive can be, but not limited to, an anisotropic conductive adhesive (ACF) and various heat curing types. Glue. After the flip chip 22 is bonded to the substrate 20, the outer leads of the wafer 24 are electrically connected to the traces on the substrate 20, and the bonding process will be described in detail later.

緩衝元件10包含第一膜層12、熱阻層14及第二膜層16。熱阻層14包含第一表面140及第二表面142。熱阻層14之熱傳導係數小於或等於0.13 W/m-k。熱阻層14可為玻纖層,熱阻層14之材質可以是但不限於玻纖布及任何具有高熱阻之材料,此處之高熱阻材料可以是熱傳導係數小於0.13 W/m-k之任何材料,此玻纖布的熱傳導係數約為0.13 W/m-k。熱阻層14之厚度可介於0.06毫米(mm)至0.1毫米之間。The buffer element 10 includes a first film layer 12, a thermal resistance layer 14, and a second film layer 16. The thermal resistance layer 14 includes a first surface 140 and a second surface 142. The thermal resistance layer 14 has a thermal conductivity of less than or equal to 0.13 W/m-k. The thermal resistance layer 14 may be a glass fiber layer. The material of the thermal resistance layer 14 may be, but not limited to, a fiberglass cloth and any material having high thermal resistance. The high thermal resistance material herein may be any material having a thermal conductivity of less than 0.13 W/mk. The fiberglass cloth has a heat transfer coefficient of about 0.13 W/mk. The thickness of the thermal resistance layer 14 may range from 0.06 millimeters (mm) to 0.1 millimeters.

第一膜層12配置於第一表面140,且第一膜層12之熱傳導係數為0.4 W/m-k。第一膜層12可以是矽材層。第一膜層12可以為無摻雜導熱粉之矽膜,此矽膜的熱傳導係數約為0.4 W/m-k。第一膜層12之厚度可介於0.01毫米至0.05毫米之間。The first film layer 12 is disposed on the first surface 140, and the first film layer 12 has a heat transfer coefficient of 0.4 W/m-k. The first film layer 12 can be a coffin layer. The first film layer 12 may be a tantalum film of an undoped thermally conductive powder having a heat transfer coefficient of about 0.4 W/m-k. The thickness of the first film layer 12 can be between 0.01 mm and 0.05 mm.

第二膜層16配置於第二表面142,且第二膜層16之熱傳導係數大於第一膜層12之熱傳導係數。第二膜層16可以是矽材層。此第二膜層16可以是但不限於矽膜,此矽膜亦可添加了導熱粉。此添加了導熱粉之矽膜的熱傳導係數約為0.3 W/m-k。導熱粉可採用混合、摻雜或塗佈方式結合於矽膜。第二膜層16之厚度可介於0.06毫米至0.1毫米之間。熱阻層14之熱傳導係數小於第二膜層16之熱傳導係數。The second film layer 16 is disposed on the second surface 142, and the heat transfer coefficient of the second film layer 16 is greater than the heat transfer coefficient of the first film layer 12. The second film layer 16 can be a coffin layer. The second film layer 16 may be, but not limited to, a ruthenium film, and the ruthenium film may also be added with a heat conductive powder. The tantalum film to which the thermal conductive powder is added has a heat transfer coefficient of about 0.3 W/m-k. The thermal conductive powder may be bonded to the ruthenium film by mixing, doping or coating. The thickness of the second film layer 16 can be between 0.06 mm and 0.1 mm. The thermal conductivity of the thermal resistance layer 14 is smaller than the thermal conductivity of the second film layer 16.

在第二膜層16相對於第二表面之另一面160(朝向覆晶軟膜22的面上)具有離形結構。此離形結構可以是多點圖樣的凸點或凹點,或在此表面160上具有離形材質,以在製程中,易於使緩衝元件10與覆晶軟膜22(異方性導電膠)脫離。The second film layer 16 has a release structure with respect to the other surface 160 of the second surface (the surface facing the flip chip 22). The release structure may be a bump or a pit of a multi-point pattern, or have a release material on the surface 160 to facilitate the separation of the buffer element 10 from the flip chip 22 (isotropic conductive paste) during the process. .

接著,請搭配「第2A圖」、「第2B圖」及「第2C圖」閱覽之。其為本揭露一實施例之應用緩衝元件之覆晶軟膜接合作業示意圖。Next, please read it with "2A", "2B" and "2C". It is a schematic diagram of a flip chip bonding process using a buffer element according to an embodiment of the present disclosure.

「第2A圖」中,覆晶軟膜22係已於前一製程中(預壓製程)預壓於基板20上之後方才移至「第2A圖」之製程(亦可稱為本壓製程),從圖中可以看見,緩衝元件10二端係捲繞於滾筒52a,52b並橫跨於熱壓頭30與覆晶軟膜22之間,其中,緩衝元件10之第一膜層12係朝向熱壓頭30。在此狀態時,由於熱阻層14及第一膜層12之熱傳導係數均小於第二膜層16之熱傳導係數,故熱壓頭30之熱量將被相當程度地隔離於緩衝元件10之上方(即熱壓頭30處),使熱量不致被熱傳導或熱對流至覆晶軟膜22處,並維持覆晶軟膜22、導電膠材及基板20在預定溫度內,此預定溫度係低於導電膠材之熔接溫度。In the "Fig. 2A", the flip chip 22 is pre-pressed on the substrate 20 in the previous process (pre-pressing process) before moving to the "Fig. 2A" process (also referred to as the press process). As can be seen from the figure, the two ends of the cushioning member 10 are wound around the rollers 52a, 52b and span between the thermal head 30 and the flip chip 22, wherein the first film layer 12 of the cushioning member 10 is oriented toward hot pressing. Head 30. In this state, since the thermal conductivity of the thermal resistance layer 14 and the first film layer 12 are both smaller than the thermal conductivity of the second film layer 16, the heat of the thermal head 30 will be relatively separated from the buffer element 10 ( That is, the thermal head 30 is located so that the heat is not thermally or thermally convected to the flip chip 22, and the flip chip 22, the conductive paste and the substrate 20 are maintained at a predetermined temperature, which is lower than the conductive paste. The welding temperature.

接著,在「第2B圖」中,熱壓頭30已朝覆晶軟膜22移動並將緩衝元件10抵壓於覆晶軟膜22上方,此時,由於熱壓頭30已抵壓於緩衝元件10及覆晶軟膜22,因此,熱壓頭30之熱量即熱傳導至覆晶軟膜22、導電膠材及基板20,故導電膠材即會在預定時間內即達到熔接溫度並將覆晶軟膜22與基板20接合。此預定時間可視緩衝元件10之結構而變化,例如,當熱阻層14之厚度愈厚、熱阻層14之導熱係數愈低、或第一膜層12之導熱係數愈低,則預定時間的則愈長,意即,此預定時間可視緩衝元件10之設計而變化。Next, in "Fig. 2B", the thermal head 30 has moved toward the flip chip 22 and the cushioning member 10 is pressed against the flip chip 22, at which time, since the thermal head 30 has pressed against the cushioning member 10 And the flip chip 22, therefore, the heat of the thermal head 30 is thermally transferred to the flip chip 22, the conductive paste and the substrate 20, so the conductive paste will reach the fusion temperature within a predetermined time and the flip chip 22 and The substrate 20 is joined. This predetermined time may vary depending on the structure of the buffer element 10. For example, when the thickness of the thermal resistance layer 14 is thicker, the thermal conductivity of the thermal resistance layer 14 is lower, or the thermal conductivity of the first film layer 12 is lower, the predetermined time is The longer, that is, the predetermined time varies depending on the design of the buffer element 10.

其次,待導電膠材達到熔接溫度後,熱壓頭30即可朝遠離覆晶軟膜22之方向移動(即朝「第2B圖」之上方移動),移動後,即形成如「第2C圖」所示,在此圖式中,即完成覆晶軟膜22接合於基板20之作業,其後,即可將接合好之基板20移出,再移入新的一片基板20,並再進行覆晶軟膜22接合製程。Next, after the conductive adhesive material reaches the fusion temperature, the thermal head 30 can move away from the flip chip 22 (ie, move upwards to the "Fig. 2B"), and after moving, the image is formed as "2C". As shown, in this figure, the bonding of the flip chip 22 to the substrate 20 is completed, after which the bonded substrate 20 can be removed, moved into a new one of the substrates 20, and the flip chip 22 is further processed. Bonding process.

再者,關於接合時的預定溫度及前述預定時間對接合效果之影響,請續參閱「第3A圖」、「第3B圖」、「第3C圖」及「第3D圖」,其為覆晶軟膜接合結果之結構示意圖。該些圖式係為「第2A圖」底視圖,即從「第2A圖」下方朝上向之視角所繪製之示意圖。In addition, regarding the influence of the predetermined temperature at the time of joining and the predetermined time on the bonding effect, please refer to "3A", "3B", "3C" and "3D", which are flip chips. Schematic diagram of the results of the soft film bonding. These figures are the bottom view of "Phase 2A", which is a schematic diagram drawn from the perspective of "2A" below.

在「第2A圖」之狀態下,晶片24的外引線(亦可稱為外引腳)23a,23b及基板20的走線21a,21b的相對位置即如圖所示,其中,外引線即可為覆晶軟膜22上的導電佈線,用以將晶片24的接腳外引。而基板20若為液晶面板時,基板20的走線21a,21b可為透明導膜(ITO,indium tin oxide)。在此「第2A圖」時,外引線23a,23b與走線21a,21b之間的導電膠材因未達熔接溫度,故外引線23a,23b與走線21a,21b之間尚未完成接合,且相鄰外引線23a,23b的間距(pitch)小於走線21a,21b的間距(pitch)。In the state of "FIG. 2A", the relative positions of the outer leads (also referred to as outer leads) 23a, 23b of the wafer 24 and the traces 21a, 21b of the substrate 20 are as shown in the figure, wherein the outer leads are It may be a conductive wiring on the flip chip 22 for guiding the pins of the wafer 24. When the substrate 20 is a liquid crystal panel, the traces 21a and 21b of the substrate 20 may be an indium tin oxide (ITO). In the "Fig. 2A", the conductive adhesive between the outer leads 23a, 23b and the traces 21a, 21b is not yet soldered, so that the outer leads 23a, 23b and the traces 21a, 21b are not yet joined. And the pitch of the adjacent outer leads 23a, 23b is smaller than the pitch of the traces 21a, 21b.

當前述預定溫度或預定時間不適當時,外引線23a,23b與走線21a,21b之間的接合即可能不適當,意即,若預定溫度過低或預定時間太短,則外引線23a,23b所在之覆晶軟膜20則可能會受熱不夠,致覆晶軟膜20之膨脹量未達預期,使外引線23a,23b之間距仍小於走線21a,21b之間距,但導電膠材已產生接合,故產生如「第3B圖」所示的接合狀態。從「第3B圖」中可以看出,外引線23a,23b正好位於走線21a,21b的間隙上,致使外引線23a,23b將相鄰的走線21a,21b形成電性連接,而短路。When the predetermined temperature or the predetermined time is not appropriate, the joint between the outer leads 23a, 23b and the traces 21a, 21b may be inappropriate, that is, if the predetermined temperature is too low or the predetermined time is too short, the outer leads 23a, 23b The flip chip 20 may be insufficiently heated, and the expansion amount of the flip chip 20 is not as expected, so that the distance between the outer leads 23a, 23b is still smaller than the distance between the traces 21a, 21b, but the conductive paste has been joined. Therefore, the joined state as shown in "Fig. 3B" is generated. As can be seen from "Fig. 3B", the outer leads 23a, 23b are located just above the gaps of the traces 21a, 21b, so that the outer leads 23a, 23b electrically connect the adjacent traces 21a, 21b and are short-circuited.

其次,若預定溫度及預定時間適當時,外引線23a,23b正好以一對一對應的方式與走線21a,21b電性連接,如「第3C圖」所示,完成將晶片24的接腳電性連接至基板20之目的。Next, if the predetermined temperature and the predetermined time are appropriate, the outer leads 23a, 23b are electrically connected to the traces 21a, 21b in a one-to-one correspondence, as shown in "3C", the pins of the wafer 24 are completed. The purpose of electrically connecting to the substrate 20.

再者,當預定溫度過高或預定時間過長,則覆晶軟膜20的膨脹量超過預期,並使得外引線23a,23b的間距大於走線21a,21b的間距,即如「第3D圖」所示,此時,外引線23a,23b與走線21a,21b間的接合可能即不適當,雖然在「第3D圖」中的接合仍屬於一對一對應方式接合,但接合後的間隙變小,除提高了短路的可能性,兩者間接合面積亦相對較小,電性連接效果亦較差。Furthermore, when the predetermined temperature is too high or the predetermined time is too long, the amount of expansion of the flip chip 20 is more than expected, and the pitch of the outer leads 23a, 23b is larger than the pitch of the traces 21a, 21b, that is, "3D" As shown, at this time, the bonding between the outer leads 23a, 23b and the traces 21a, 21b may be inappropriate. Although the bonding in the "3D" is still in a one-to-one correspondence, the gap after the bonding is changed. Small, in addition to increasing the possibility of short circuit, the joint area between the two is relatively small, and the electrical connection effect is also poor.

關於本揭露緩衝元件10應用於覆晶軟膜22接合之效果,茲進行幾組實驗,實驗中之第一膜層之材質為矽(未摻雜導熱粉),厚度為0.05毫米;第二膜層之材質為矽並摻雜導熱粉,厚度為0..1毫米;覆晶軟膜22與基板20(本實驗採用液晶面板)間的導電膠材採用異方性導電膠,而熱阻層則採用玻纖布,厚度分別為0.06、0.08、及0.1毫米。在相同製程下,完成接合時,覆晶軟膜的膨脹量即如「第4圖」所示,分別為22、15、及10微米(um)。前述膨脹量係指覆晶軟膜22在導電膠材固化(或達熔接溫度)時在水平面上的膨脹量,此水平面指的是與緩衝元件的第二表面實質上平行的面。從「第4圖」可以得知此膨脹量在10至22微米之間。而膨脹比例則在0.3%至0.8%之間,例如在最外側之兩個外引線23a,23b間的寬度為4.2毫米(mm)時,平面上的膨脹量在12.6到33.6微米之間。當然,前述膨脹量可視設計而有所不同。Regarding the effect of the buffer element 10 applied to the bonding of the flip chip 22, several experiments are carried out. The first film in the experiment is made of ytterbium (undoped thermal powder) with a thickness of 0.05 mm; the second layer The material is 矽 and doped with thermal conductive powder, the thickness is 0..1 mm; the conductive adhesive between the flip chip 22 and the substrate 20 (the liquid crystal panel used in this experiment) adopts an anisotropic conductive adhesive, and the thermal resistance layer is adopted. The fiberglass cloth has thicknesses of 0.06, 0.08, and 0.1 mm, respectively. In the same process, when the bonding is completed, the amount of expansion of the flip chip is as shown in Fig. 4, which is 22, 15, and 10 μm, respectively. The aforementioned expansion amount refers to the amount of expansion of the flip chip 22 on the horizontal surface when the conductive paste is cured (or at the fusion temperature), and the horizontal plane refers to a surface substantially parallel to the second surface of the cushioning member. It can be seen from "Fig. 4" that the amount of expansion is between 10 and 22 microns. The expansion ratio is between 0.3% and 0.8%. For example, when the width between the outermost two outer leads 23a, 23b is 4.2 millimeters (mm), the amount of expansion in the plane is between 12.6 and 33.6 microns. Of course, the aforementioned amount of expansion may vary depending on the design.

最後,請參閱「第5圖」,其為本揭露一實施例之應用緩衝元件之覆晶軟膜接合方法流程示意圖。從圖中可以知悉應用緩衝元件10之覆晶軟膜(Chip on Film)接合方法包含:步驟S90:以熱壓頭30抵壓緩衝元件10於疊置有一覆晶軟膜22之基板20上,覆晶軟膜22與基板20間具有導電膠材,熱壓頭之溫度為380℃;以及步驟S92:持續抵壓該基板一預定時間後,退回該熱壓頭。Finally, please refer to FIG. 5 , which is a schematic flow chart of a flip chip bonding method using a buffer element according to an embodiment of the present disclosure. It can be seen from the figure that the method of bonding a chip on film using the buffer element 10 includes: step S90: pressing the buffer element 10 with the thermal head 30 on the substrate 20 on which the flip chip 22 is laminated, and flipping the crystal The flexible film 22 and the substrate 20 have a conductive adhesive material, and the temperature of the thermal head is 380 ° C; and step S92: after pressing the substrate for a predetermined time, the thermal head is returned.

其中,步驟S90中熱壓頭之溫度可以高於導電膠材之熔接溫度或上述之預定溫度,亦可以是導電膠材之固化溫度。步驟S90可以是指熱壓頭30以一預定速度先接觸到緩衝元件10後,再將緩衝元件10抵壓於基板20。此預定速度可以是一等速度,且其速度值約為1~10 mm/s。The temperature of the thermal head in step S90 may be higher than the welding temperature of the conductive rubber or the predetermined temperature, or may be the curing temperature of the conductive rubber. Step S90 may mean that the thermal head 30 first contacts the cushioning member 10 at a predetermined speed, and then presses the cushioning member 10 against the substrate 20. This predetermined speed can be a first speed and has a speed value of about 1 to 10 mm/s.

而步驟S92中的預定時間可以是熱壓頭30抵壓緩衝元件10於基板20後到導電膠材達到熔接溫度時的時間,或是熱壓頭30抵壓於緩衝元件10於基板20後到導電膠材固化時的時間。而熱壓頭30之退回則是指熱壓頭30朝遠離覆晶軟膜22的方向移動。The predetermined time in step S92 may be the time when the thermal head 30 presses the buffer member 10 on the substrate 20 until the conductive adhesive reaches the fusion temperature, or the thermal head 30 is pressed against the buffer member 10 on the substrate 20. The time when the conductive adhesive is cured. The retraction of the thermal head 30 means that the thermal head 30 moves away from the flip chip 22 .

綜上所述,在熱壓頭30尚未壓下(即「第2A圖」所示或是未接觸到緩衝元件)時,緩衝元件10可以將熱壓頭30之熱量隔離於緩衝元件10之上方,而不致預熱覆晶軟膜22,當熱壓頭30抵壓緩元件10於覆晶軟膜22時,熱量可以迅速地傳導至導電膠材,而待熱壓頭30退回後,熱量亦被緩衝元件10隔離於熱壓頭30周圍,而不致於持續對覆晶軟膜22加熱,因而能更有效地控制覆晶軟膜22的接合溫度,並提高電性連接的良率。In summary, the cushioning element 10 can isolate the heat of the thermal head 30 from above the cushioning element 10 when the thermal head 30 has not been depressed (ie, as shown in FIG. 2A or is not in contact with the cushioning member). Without preheating the flip chip 22, when the thermal head 30 abuts the resistive element 10 on the flip chip 22, heat can be quickly transferred to the conductive paste, and after the thermal head 30 is retracted, the heat is also buffered. The element 10 is isolated around the thermal head 30 without continuously heating the flip chip 22, thereby more effectively controlling the bonding temperature of the flip chip 22 and improving the yield of the electrical connection.

關於緩衝材之設計,實施者可根據熱壓頭30溫度與熱壓頭30下降速度,選擇適當材料做為熱阻層14,即適當選擇一種高熱傳導係數之材料,以滿足熱壓頭30壓於覆晶軟膜22前之時間內溫度阻隔的效果,此溫度阻隔效果亦可依據覆晶軟膜22的膨脹量進行設計。Regarding the design of the cushioning material, the implementer can select a suitable material as the thermal resistance layer 14 according to the temperature of the thermal head 30 and the falling speed of the thermal head 30, that is, appropriately selecting a material having a high heat transfer coefficient to satisfy the pressure of the hot head 30. The temperature blocking effect in the time before the flip chip 22 is formed, and the temperature blocking effect can also be designed according to the amount of expansion of the flip chip 22 .

雖然本揭露以前述的較佳實施例揭露如上,然其並非用以限定本揭露,任何熟習相像技藝者,在不脫離本揭露之精神與範圍內,當可作些許更動與潤飾,因此本揭露之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。The present disclosure is disclosed in the foregoing preferred embodiments. However, it is not intended to limit the disclosure, and the skilled person can make some changes and refinements without departing from the spirit and scope of the disclosure. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

10...緩衝元件10. . . Cushioning element

12...第一膜層12. . . First film

14...熱阻層14. . . Thermal resistance layer

140...第一表面140. . . First surface

142...第二表面142. . . Second surface

16...第二膜層16. . . Second film

160...另一面,表面160. . . The other side, the surface

20...基板20. . . Substrate

21a,21b...走線21a, 21b. . . Traces

22...覆晶軟膜twenty two. . . Cladding film

23a,23b...外引線23a, 23b. . . Outer lead

24...晶片twenty four. . . Wafer

30...熱壓頭30. . . Hot head

50a,50b...卡匣50a, 50b. . . Card

52a,52b...滾筒52a, 52b. . . roller

第1圖為根據本揭露一實施例之緩衝元件之結構示意圖。FIG. 1 is a schematic structural view of a cushioning member according to an embodiment of the present disclosure.

第2A圖、第2B圖及第2C圖為本揭露一實施例之應用緩衝元件之覆晶軟膜接合作業示意圖。2A, 2B, and 2C are schematic views of a flip chip bonding operation using a buffer element according to an embodiment of the present invention.

第3A圖、第3B圖、第3C圖及第3D圖為覆晶軟膜接合結果之結構示意圖。3A, 3B, 3C, and 3D are structural schematic views of the results of the flip-chip soft film bonding.

第4圖為覆晶軟膜結果之膨脹量比較圖。Figure 4 is a comparison of the amount of expansion of the flip chip film.

第5圖為本揭露一實施例之應用緩衝元件之覆晶軟膜接合方法流程示意圖。FIG. 5 is a schematic flow chart of a flip chip bonding method using a buffer element according to an embodiment of the present disclosure.

10...緩衝元件10. . . Cushioning element

12...第一膜層12. . . First film

14...熱阻層14. . . Thermal resistance layer

140...第一表面140. . . First surface

142...第二表面142. . . Second surface

16...第二膜層16. . . Second film

160...另一面,表面160. . . The other side, the surface

Claims (15)

一種緩衝元件,適於一覆晶軟膜製程,該緩衝元件包含:一熱阻層,具有一第一表面及一第二表面,該熱阻層之熱傳導係數小於或等於0.13 W/m-k;一第一膜層,配置於該第一表面,該第一膜層之熱傳導係數為0.4 W/m-k;以及一第二膜層,配置於該第二表面,該第二膜層之熱傳導係數大於該第一膜層之熱傳導係數。A buffer element is suitable for a flip chip process, the buffer element comprises: a thermal resistance layer having a first surface and a second surface, the thermal resistance layer having a thermal conductivity of less than or equal to 0.13 W/mk; a film layer disposed on the first surface, the first film layer having a heat transfer coefficient of 0.4 W/mk; and a second film layer disposed on the second surface, the second film layer having a heat transfer coefficient greater than the first layer The thermal conductivity of a film layer. 如請求項1所述之緩衝元件,其中該第二膜層包含導熱粉。The cushioning member of claim 1, wherein the second film layer comprises a thermally conductive powder. 如請求項1所述之緩衝元件,其中該第二膜層之熱傳導係數為0.3 W/m-k。The buffer element of claim 1, wherein the second film layer has a heat transfer coefficient of 0.3 W/m-k. 如請求項1所述之緩衝元件,其中該熱阻層之厚度介於0.06毫米(mm)至0.1毫米之間。The cushioning member of claim 1, wherein the thermal resistance layer has a thickness of between 0.06 mm (mm) and 0.1 mm. 如請求項4所述之緩衝元件,其中該第二膜層之厚度為0.1毫米。The cushioning member of claim 4, wherein the second film layer has a thickness of 0.1 mm. 如請求項5所述之緩衝元件,其中該第一膜層之厚度為0.05毫米。The cushioning member of claim 5, wherein the first film layer has a thickness of 0.05 mm. 如請求項6所述之緩衝元件,其中該熱阻層之熱傳導係數小於該第二膜層之熱傳導係數。The snubber element of claim 6, wherein the thermal resistance layer has a thermal conductivity smaller than a thermal conductivity of the second film layer. 如請求項1所述之緩衝元件,其中該第二膜層相對於該第二表面之另一面具有離形結構。The cushioning member of claim 1, wherein the second film layer has an off-structure with respect to the other side of the second surface. 如請求項1所述之緩衝元件,其中該熱阻層之材質為玻纖布,該第一膜層之材質為矽膜,該第二膜層之材質為矽膜。The cushioning component of claim 1, wherein the material of the thermal resistance layer is a fiberglass cloth, the material of the first film layer is a ruthenium film, and the material of the second film layer is a ruthenium film. 一種覆晶軟膜(Chip on Film)接合方法,包含:以一熱壓頭抵壓一緩衝元件於疊置有一覆晶軟膜之一基板上,該覆晶軟膜與該基板間具有一導電膠材,該熱壓頭之溫度為380℃;以及持續抵壓該基板一預定時間後,退回該熱壓頭。A chip-on-film bonding method comprises: pressing a buffer element with a thermal head on a substrate on which a flip chip is laminated, and the flip chip has a conductive adhesive material between the film and the substrate, The temperature of the thermal head was 380 ° C; and after the substrate was continuously pressed for a predetermined time, the hot head was returned. 如請求項10之覆晶軟膜接合方法,其中該覆晶軟膜在該導電膠材固化時與常溫時的膨脹比例在0.3%至0.8%之間。The flip chip bonding method according to claim 10, wherein the crystalline soft film has a swelling ratio between 0.3% and 0.8% at the time of curing of the conductive rubber. 如請求項10之覆晶軟膜接合方法,其中該覆晶軟膜在該導電膠材固化時在水平面上的膨脹量在10微米(um)至22微米之間。A flip chip bonding method according to claim 10, wherein the flip chip is expanded in a horizontal plane between 10 micrometers (um) and 22 micrometers when the conductive paste is cured. 如請求項10之覆晶軟膜接合方法,其中該以該熱壓頭抵壓該緩衝元件之步驟為該熱壓頭以一預定速度先接觸該緩衝元件後再將該緩衝元件抵壓於該基板。The flip chip bonding method according to claim 10, wherein the step of pressing the buffer member with the thermal head is such that the thermal head contacts the buffer member at a predetermined speed and then presses the buffer member against the substrate. . 如請求項13之覆晶軟膜接合方法,其中該預定速度為一等速度。The flip chip bonding method of claim 13, wherein the predetermined speed is a first speed. 如請求項13之覆晶軟膜接合方法,其中該等速度為1~10 mm/s。The flip chip bonding method of claim 13, wherein the speed is 1 to 10 mm/s.
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