TW201251057A - Method, process and fabrication technology for high-efficiency low-cost crystalline silicon solar cells - Google Patents

Abstract

Disclosed is a method, process, solar cell design, and fabrication technology for high-efficiency, low-cost, crystalline silicon (Si) solar cells including but not restricted to solar grade single crystal Si (c-Si), multi-crystalline Si (mc-Si), poly-Si, and micro-Si solar cells and solar modules. The RTWCG solar cell fabrication technology creates a RTWCG SiOx thin film antireflection coating (ARC) with a graded index of refraction and a selective emitter (SE). The resulting top surface of the SiOx oxide can be textured (TO) concomitant with the growth process or through an additional mild wet chemical step.

Description

201251057 41245pif VI. Description of the invention: [Related application] This application claims the method, process and manufacturing technology of the high-efficiency and low-cost crystallization solar cell according to USC §119 (e). Priority is claimed in US Patent No. 61/383,435, the entire disclosure of which is incorporated herein by reference. [Incorporated by Reference] All patents, patent applications, and publications cited herein are hereby incorporated by reference in their entirety in their entirety in their entirety in their entireties Known as current advanced technology. TECHNICAL FIELD OF THE INVENTION The present invention relates to a wet chemical growth (R〇〇m (10) 卩 (10) 比 (10) W (Wet Chemical Growth 'RTWCG) method of a Si〇x film coating that can be grown on various substrates and Process. The present invention is further directed to an RTWCG method and process suitable for growing thin films on Si substrates (for use in the fabrication of germanium-based electrons and photonic (photoelectron) devices. The invention advances the production of (4) low reflectivity single-layer antireflective coatings (SLARC) SiOx thin film oxide layer and selective emitter (selective emit s, sin) [previous technique] - Oxidation crush (SiO 2 ) forms the basis of planar technology. In Industrial Practice 4 201251057 41245pif, electrons and photon-like dielectrics are most often formed by oxidation of 900^1200t|6^^T^/(s;;; SiQ2 can also be deposited by pure vapor deposition (II) Deposition ' CVD ) technology is used at lower temperatures (2 〇 (rc_9 〇〇 on various substrates. Thermal growth and CVD growth based on the layer can be used to make the junction junction passivation diffusion, used as Wei in Si technology Edge material, dielectric material' and used as an overlay for implant-activated annealing in III-V compound semiconductor technology. For high-efficiency crystallized solar cell applications, the thin film Si〇2 layer can be used for the front surface and the county surface. The first layer of ARC in the antireflection coating 'ARC' structure. The dielectric film is grown at low temperatures due to reduced capital costs, high production, and growth using conventional high temperature growth/deposition techniques. The technical constraints associated with dielectric films are attractive for most component applications. Thin dielectric film near chamber/M·growth/deposition techniques are known in the art and are primarily used for microelectronic/photonic (optoelectronic) components. Application. These low temperature sides An example of a method is a physical vapor deposition process comprising: a non-reactive (conventional) or reactive resistance process, an inductive or electron beam evaporation process, a reactive or non-reactive north or RF magnetron process, and an ion Beam sputtering process. It is well known to use anodization to grow a dielectric layer on a semiconductor surface at room temperature. It can grow up to 200 nm thick Si〇2 layer on a Si substrate, in which the underlying layer is used. In some cases, anodization is incompatible with the metallization scheme, thereby limiting its use as an alternative to SiO2 for thermal growth or Cvd deposition. 201251057 41245pif It is known in the art to use organic metal solution deposition & The dielectric layer is coated by dipping the substrate into the organometallic solution, by spraying the organometallic solution on the substrate, or by rotating the substrate after applying a small amount of the organometallic solution to the substrate. After the metal solution, the solvent portion of the solution must be removed by heating the substrate to about 400 ° C. A large number of patents, patent applications, and published papers describe the deposition of Si on various substrates (including the surface of the crucible). 2 and near-room temperature-related processes of the SiO 2 -xFx layer. The liquid-phase deposited (LPD) Si〇2 technique was originally developed in 1950 for the surface of soda lime silicate glass. The deposition of Si〇2°LPD is based on the chemical reaction of H2SiF6 with water to form hydrofluoric acid and solid Si〇2. First, the H2SiF6 solution is saturated with Si〇2 powder (usually in solution-gel form). The glass is immersed in the solution. Previously, a reagent (such as acid scavenging) which reacts with hydrofluorosilicilic acid may be added to the solution to be oversaturated with cerium oxide. The LPD process is a competition between SiO2 deposition and money engraving. Regardless of small changes in the formulation, the total reversible chemical reaction is: H2SiF6 + 2 Η20 η 6 HF + Si02. One of the major drawbacks of the above SiO 2 LPD method is the extremely low deposition rate. It has been reported that when fluorophthalic acid SiO 2 -xFx (X is about 2%) is used, the deposition rate is 110 nm/hr. These deposition rates are still too low for practical ARC applications; for solar cell applications, it will take more than an hour to deposit an almost optimal ARC thickness of 130 nm. 6 201251057 41245pif high growth rate RTWCGSiOX thin film dielectric layer entitled "Room Temperature Wet Chemical Growth Process of SiO Based Oxides on Silicon" US Patent No. 6,080,683 and The method of making Thin Films Dielectrics Distills Using a Process for Room Temperature Wet Chemical Growth of SiO Based Oxides on a Substrate U.S. Patent No. 6,593,077 describes an RTWCG SiOx process and process on a semiconductor substrate, including: 1. providing a reaction mixture comprising a ruthenium source, a pyridine compound, and a reduced oxidizing aqueous solution, ii. providing a catalyst for promoting the reaction; The mixture is reacted with a substrate to form the oxidized layer. The high growth rate RTWCG Si(R) film disclosed in U.S. Patent No. 6,080,683 and U.S. Patent No. 6,593,077, is incorporated herein by reference to the utility of the <RTIgt; High growth rate growth of SiOx oxide on the substrate can be achieved by using the following materials: commercial grade organic and inorganic cerium source, pyridine compound (ie, N-(n-butyl) chlorate), based on 2 + Deoxygenated aqueous solution, organic or inorganic, 彳 彳 b#丨 and non-invasive additives (including NaF, K〇H, NH4F and HF (aqueous solution). In US Patent No. 6,613,697, growth solution The organic component is changed to (4). The RTWCGsi〇x film layer grows at various growth rates on various semi-conducting counties, and has a lower metal 201251057 41245pif and non-metallic impurity concentration. In addition, when combined with organic groups When the RTWCG SiOx film grown in the solution is compared, the dielectric properties of the obtained film are improved. By using the above-mentioned growth solution formulation, depending on the composition of the growth solution, the growth rate of the RTWCG Si0x on the Si surface is i nm. /min to over 100 nm/min. Anti-Reflective Coatings Prior art anti-reflective coatings (ARC) are included in solar cell designs to substantially reduce the amount of reflected light. Bare Si loses 42% 1.1 microns long Long light, 37% light with 1 micron wavelength and about 54% light with 4 micron short wavelength. Textured front surface (such as regular interval pyramid or porous tantalum (ps)) can make 〇4 micron to 1.2 micron wavelength range The average weighting of AM 15 is as low as 12%-18%. The optimum thickness of the anti-reflective coating is calculated by: 〇 for quarter-wavelength ARC made of transparent material with refractive index ηι and incident on The free space on the coating, such as e), is wavelength. The light 'produces the most λ!, and the thick material of the reflection is that the folding material has a wavelength dependence', so that the near zero is anti-hetero can be riding on the single-wave. The refractive index and thickness must be such that the reflection of light with a wavelength of 〇.6 μm is minimized because this wavelength is close to the peak power of the solar spectrum (peakp depends on the square of the multiple anti-reflective coatings. However, by appropriately adjusting the refractive index and thickness of the two layers of 201251057 41245pif, it is theoretically possible to produce two minimum values and a total reflectance as low as 3%. Smooth surface (eg MgF2, Si〇2, SiO, SiNx) The appropriate SLAR on Ti〇2 and Ta205) can reduce the AMI.5 average weighted reflection (AWR) in the wavelength range of 0.4 micron to 1·1 micron to 12%-16%. CVD deposited SiNx ARC (which is the standard for AR solar cell ARC applications) 'AMI.5 AWR is about 12%, where Wright et al. for the assumed film refractive index „ is 丨.95 and thickness d For a flat c-Si of 81 nm, the minimum AWR of the simulation is 10.4%. It is still necessary to observe the minimum SiNx SLAR AWR that can be simulated in a production environment, but even if the simulated reflectance is obtained, the 10.4% reflectance The reflection loss is still too high. The industry still needs to pass the double A low-cost method for ARC, textured fossil solar cell surfaces or both to further reduce reflectivity. However, this method is limited by the high cost of most commercial solar cell applications. For well-designed single or double layers The textured surface of arc (such as IT0/SiO2, ZnS/MgF2, Ti02/MgF2, and Ti02/Al203) has dropped to between 3% and 8% for AM1.5 AWR. A large number of studies on double layer ARC have been reported. The most stable configuration of the film thickness was found to be a design with a high refractive index U) on the substrate and a low refractive index for the environment. It is difficult to deposit a uniform ARC on the textured surface. The nano-sized features of the polycrystalline structure make it difficult to Conventional techniques deposit or grow uniform ARC. Some battery manufacturers do not use ARC due to this problem; the cost of 201251057 41245pif is a relative loss of efficiency of up to 10%, and there is a problem of surface stability. Prior Art Currently, screen printing Shi Xi solar cells use n + / p emitters, the emitter is diffused to make the sheet resistance at 40 ohm / square unit _ 6 〇 / / square unit Within the circumference, and the surface doping concentration is greater than 2xl 〇 20 / cubic centimeter. High surface doping and low sheet resistance are required to obtain an acceptable contact resistance of about 1 micro ohm square centimeter and a low junction in the space charge region. Surface shunting and recombination. However, such emitters have low open circuit voltage due to poor blue response (still emitter recombination and free carrier absorption) (high emitter surface recombination and high surface doping) And Auerrecombination) and poor short-circuit current. High-efficiency industrial development with a contact resistance of about 1. 〇xl 〇 -4 ohm-cm 2 of good screen printing contact, a sheet resistance of more than 100 ohms per square unit and a surface doping of about 1 〇 19 / cubic centimeter The main task of solar cells. To reduce manufacturing costs, industrial techniques for front contact fabrication require deep and highly doped junctions to achieve acceptable low contact resistance and to avoid penetration of metal impurities into junctions, space charges, and bulk emitter regions. Conventional = Typical emitter sheet resistance used in the printing metallization process is 5 平方 square units, ohms per square unit. Small gauges are difficult to make using diffusion 3 or solid/〇5 dopant sources and open tube furnaces to perform diffusion 4 scale manufacturing using coating or spin coating of various phosphorus-containing pastes and liquid dopant sources, followed by conveyor belt furnace diffusion . _ Emitter thin layer of battery without good quality selective emitter 201251057 41245pif The resistance is 50 ohms/square unit _8 〇 ohm/square unit, and its fill factor (train factor 'FF) is usually less than 76%. The lower the FF of the cell with the higher emitter layer resistance, the lower the metal conductivity due to the south contact resistance, the high lateral emitter resistance, and the screen printing contact. To achieve full efficiency gains from improved emitter surface passivation, the doping profile of the emitter must be designed such that it is lightly doped between the gate lines and recorded underneath. This applies in particular to conventional solar cells having screen printing grid lines, under which the substrate is heavily doped to achieve an acceptable low contact resistance. A battery having a selective emitter has a large short circuit current (洳) due to the removal of the non-inductive layer from the active emitter surface. The passivation of the emitter surface is also beneficial, so that the field dark current (current 'job) is the open circuit voltage (〇pencircuitv〇Itage, the control, the limiting factor. The improved conductivity under the gate line is reduced by the series two: south diversion The resistance' is attributed to the additional "punch-thru" of the part of the thumb metal provided by the deeper junction in the gate area. Because of the high conductivity of the stone under the grid line, it can be used. The line can separate the spreader to make the shaded area smaller. In the case of screen printing, the selective emitter is difficult to obtain especially through one-step process. The extremely important SE efficiency enhancement feature is delayed. This is because the selectively patterned emitter doping profile has previously been obtained using expensive photolithography or advanced screen printing solutions and multiple high temperature diffusion steps. Conventional SE techniques can be divided into three broad categories: a. And selectively etched without the alignment manufacturing 201251057 41245pif emitter cell; b. a selective emitter cell fabricated by self-alignment without masking or etching; c. Selective emitter cells fabricated by self-aligned self-doped Ag paste. Techniques (a) and (b) are generally time consuming and slightly more expensive. Technique (c) is important because of the diffusion of Ag in Si The rate is higher than p, which can produce high junction leakage current and south junction ideal factor. High efficiency crystallization 矽 solar cell low cost south efficiency solar cell is the key to the large-scale acceptance of photovoltaic (PV) system. New Materials and Process Steps Technology Redesigned small-area solar cells have produced multiple laboratory battery solutions that yield more than 20% battery efficiency. Two small-area laboratory-scale methods (originally from the mche market (such as solar energy) Car) use) for the emitter-purified emitter with diffused emitter with 舡l〇cally d' used PERL and jnter (jigitated back c^m^act (IBC) batteries. And other laboratory battery designs have improved the efficiency of c-Si solar cells, but so far, these batteries have not used low-cost solar _ substrate, and only a few of them make Xiao low-cost manufacturing technology Process steps (such as screen printing metallization). The goal of developing high-efficiency solar cells is to increase efficiency and fish is cost. The cost-saving focus is on the number and complexity of manufacturing process steps with set peak work and material consumption. Other important factors in the selection of winning technology include the environmental aspects and 12 201251057 41245pif standard and manufacturing engineering (such as process automation and control). SUMMARY OF THE INVENTION A room temperature wet chemical growth (RTWCG) SiOx method and process are described. Manufactured using a low-cost RTWCG to produce a SiOx layer with an anti-reflective coating ("ART"), an optional # emitter ("SE"), and optionally a surface physicochemical oxide ("TO") surface. Efficient, low-cost crystalline lithography solar cells and solar cell modules, hereinafter referred to as RTCWG SiOx/ARC/SE/ (TO) based process, design and technology. The RTWCG process of the term SiOx or SiOx dielectric layer as used herein means a room temperature (eg, l〇°C-40〇C) wet chemical growth process of 3,05^2 layers where X is 0.9 to 1.1, y is 〇.9 to 1.1, and z is 〇.〇1 to 〇_2°Si means 矽'〇 represents oxygen, and X is fluorine (F), carbon (c), nitrogen (N) or these and other metals ( For example, iron (Fe), palladium (pd), titanium (Τι) or other combinations of trace metals and non-metallic contaminants depend on the oxygen system used, the catalyst, and the non-invasive additive. The novel RTWCGSi〇x growth formulation described herein will: (i) chemically clean the surface of the cell (including the metallized surface) on the spot to prepare for the interconnection, (ϋ) to produce a gradient index Si〇x ARC , which deactivates the emitter surface and has any known single-layer ARC (SLARC) low AM1_5 average-weighted reflection 帛, (v)) while selectively reversing the unmetallized portion of the emitter surface to produce extremely efficient selectivity Emitter (> RTWCG Si〇x ARC/SE/TO process and solar cell manufacturing technology and existing solar cells such as solar cell efficiency enhancement diffusion and improved metallization technology and solar power. 13 201251057 41245pif RTWCG The method and process provide a simple n+/p or p+/n RTwcg SiOx ARC/SE solar cell design, or n+/p or p+/n RTwcg SiOx ARC/SE/TO solar cell structure design, or n+/p/p+ or p+ /n/n+ RTWCG SiOx ARC/SE/TO efficiency enhanced solar cell structure design. One of the embodiments is to provide a Si0x thin film dielectric with rapid growth of low metal and non-metallic impurity concentrations on a germanium substrate. Layer for efficient An RTWCG process for low-cost crystallization solar cell applications. Another object of one or more embodiments is to provide an RTWCG SiOx process using SiOx growth solutions including all inorganic components with or without ruthenium source. Another object of an embodiment is to provide an RTWCG SiOx process using a SiOx growth solution based on a rich, low-salt, and environmentally compatible component. Another object of one or more embodiments is to provide a use having RTWCG SiOx process for long shelf life SiOx growth solution. Another object of one or more embodiments is to provide a high growth rate RTWCG SiOx process with good SiOx film uniformity, low stress, good adhesion to the ruthenium surface. And a good consistency. Another object of one or more embodiments is to provide an RTWCG SiOx process for fabricating a Si〇x film that is exposed to humidity, temperature changes, UV light, visible light, and high-strength plasma for a long period of time. Post-stabilization. Another object of one or more embodiments is to provide an RTWCG process in which an RTWCG SiOx film is grown on an unmetallized surface. , 201251057 41245pif growth 'was bonded bare (no ARC) surface of the solar cell (comprising a metallized surface) of the spot (in-situ) cleaning.

Another object of one or more embodiments is to provide an RTWCG dual-private solution in which the sl0x growth solution is compatible with the screen printing, metallization and post-metallization of bare-battery solar cells. Another object of the embodiment, or another embodiment, is to provide an rtWcg process that allows the S10x thin film dielectric layer to grow strictly on the unmetallized surface rather than the metallized surface, thereby allowing the cell to be interconnected or Another purpose of the practical example is to provide a financial record that produces a gradient index on the surface of the emitter of the battery of the battery. 'There is a low air f amount 丨5 (also _丨5, am(5) weight reflectivity (AWR) An anti-reflective coating for visible light absorption in the domain - or another object of the various embodiments is to provide a surface in which the S10x film is cleaned by a metallized surface of the solar cell. Another purpose of the embodiments is to provide A rtwcg = 〇χ clothing process, wherein the Sl0x film causes the front side of the screen printing to be passivated based on the silver gate line and the contact contact. Another purpose of the embodiment is to provide a rtwcg "X garment" The bond film S10x is grown while the depth of the unembedded emitter is not metallized to completely remove the heavily doped domain layer to form a so-called selective emitter (SE) efficiency enhancement feature. 15 201251057 41245pif One or more Another item of an embodiment In order to provide an RTWCG SiOx process, the surface of the si〇x film grown on the smooth crucible surface is textured to form a texture (j oxide, TO) efficiency enhancement feature. One or more Another object of the embodiment is to provide all of the above-described needs and efficiency-enhanced battery design features in a single short RTWCG SiOx process step, and to form a simple but efficient n+/p or p+/n RTWCG si〇x ARC/SE/ (TO) Solar cell structure and n+/p/p^ p+/n/n+ si〇x ARC/SE/TO efficiency-enhanced cell structure for high efficiency and low cost use of solar grade c_si, mc-Si and polycrystalline substrate Crystalline solar cell. Another purpose of one or more embodiments is to provide n+/p or p+/n RTWCG SiOx ARC/SE/(TO) and n+/p/p+ and p+/n/n+ SiOx ARC/ The SE/TO solar cell structure design includes a so-called kink-and-tail net majority carrier concentration diffusion profile in the emitter, and the efficiency of the bending is shallow and the tail is steep. Possibility. Another object of one or more embodiments is to provide a high efficiency n+/p/p+ and p+/n/n+ crystallization. RTWcg SiOx/ARC/SE/TO process, cell design and technology for solar cell structures, where n+ and port+diffusion are screen-printed or spin-coated on a substrate in a single high-diffusion process step. Another object of one or more embodiments is to provide an RTWCG Si0x process for high efficiency n+/p/p+ and p+/n/n+ crystallization solar cell structures, wherein n+ and p+ diffusion are in a single high temperature diffusion process. The steps are performed without separate edge isolation process steps. 16 201251057 41245pif Another object of one or more embodiments is to provide an n+/p_si RTWCG SiOx ARC/SE/T0 solar cell structure design, method, process and technique for any flat surface crystalline germanium emitter, and for Any n+/p_Si RTWCG SiOX ARC/SE solar cell structure design, method, process and fabrication technique on a smooth or textured emitter surface, and which is compatible with, including but not limited to, all of the following crystals: semiconductor grade and Czochralski (Cz) or float zone (FZ) single crystal Si (c-Si), polycrystalline Si (mc_Si), polycrystalline germanium and string ribbon Si. Another object of one or more embodiments is to provide an n+/p-Si RTWCG SiOX ARC/SE/ΤΟ solar cell structure and technology that functions equally well with the p+/n_Si RTWCG SiOX ARC/SE/ΤΟ solar cell structure. . Another object of one or more embodiments is to provide an enhanced efficiency n+/p or p+/n RTWCG SiOx ARC/SE/ (by using an RTWCG formulation capable of removing a diffusion layer while producing a backside purification and edge separation). TO) Method of battery structure. Another object of one or more embodiments is to provide a simple and low cost RTWCG SiOx based crystalline germanium solar cell technology that removes the diffusion layer from the rear surface of the solar cell and passivates the back surface of the solar cell by using the RTWCG process. At the same time, good edge separation is produced to produce a barely efficient n+/p-Si or p+/n RTWCG SiOx ARC/SE/(TO) cell structure. Another object of one or more embodiments is to provide an RTWCG SiOX method, n+/p-Si RTWCG SiOx ARC/SE/ΤΟ and p+/n-Si 17 201251057 41245pif RTWCG SiOx ARC/SE/TO processes and techniques, It can be designed from other conventional single-sided planar crystals to other less-known Si solar cell battery structures (including but not limited to Vertical Multi-Junction (VM J), spherical battery and double-sided Other crystal 矽 solar cell designs in the range of n+pp+ or p+nn+ crystallized solar cell structure) are used in combination. Another object of one or more embodiments is to include n+/p-Si or p+/n-si RTWCG SiOx ARC/SE for cells having flat or textured emitter surfaces and for cells having flat surfaces n+/p_Si or p+/n-Si and Π+ΡΡ+ or p+nn+ RTWCG SiOX ARC/SE/TO, current technology materials and efficiency enhancement solar cell process steps, including but not limited to providing low front and back Novel technical solution for surface recombination and advanced diffusion technology for ensuring strong front and back surface fields, better screen printing paste and achieving metallization narrower, higher vertical and horizontal, more conductive, contact resistance than current technology Lower metallization process with lower annealing temperature. Another object of one or more embodiments is to provide a so-called transparent conductive coating (transparent) in which a variety of substrates are grown RTWCG SiOM (where M is a compatible metal) to form a thin film solar cell and various other potential applications. Conductive coating, TCO) method and process. Another object of one or more embodiments is to provide a process, design, and technique for manufacturing a high efficiency, low cost non-(four) solar cell having the characteristics of RTWCG Si〇M TCQ. Or - in addition to the various embodiments - the object is to provide a planar based and photonic (optoelectronic) component application that can benefit from the n+/p Si4p+/n_si 18 201251057 41245 pif RTWCGSiOxARC/SE (/TO) method, process and technique, Or benefit from the incorporation of low to medium-high dielectric constant RTWCG Si〇x thin film dielectric layers or high transparency, suitable resistivity and relatively low reflectivity 2RTWCg SiOM TCO. The above and other objects, features, and advantages of the present invention will be apparent from the description of the appended claims. [Embodiment] The present invention discloses an RTWCG SiOx method and process for RTCCG SiOx ARC/SE/TO crystallization solar cell design and manufacturing technology for high efficiency and low cost crystalline cerium (si) solar cells, the crystallization solar cell These include, but are not limited to, single crystal Si (c_Si), polycrystalline Si (mc-Si), microcrystalline Si (pc-Si), and polycrystalline germanium solar cells and solar cell modules. The RTWCG SiOx process and process are a modified version of the previously disclosed room temperature humidification student length (RTWCG) process and process (see U.S. Patent Nos. 6,080,683 and 6,593,077 and 6,613, 697, incorporated herein by reference). The technique provides a catalytic process for uniformly growing an oxide layer over 10,000 angstroms thick at room temperature (e.g., 1 Torr. The composition can be used to prepare SiOx layers in processes and applications that have heretofore been limited by cost and temperature requirements. The RTWCG SiOx ARC/SE/TO solar cell design and technology reduces manufacturing costs by reducing the number of high temperature manufacturing steps and reducing the total number of manufacturing steps by using a low cost screen printing metallization scheme. While reducing the cost of fabrication, the described technology also improves cell conversion efficiency by using a cell design structure that includes efficiency enhancement features (201251057 41245pif such as gradient index RTWCG SiOx ARC). With the ARC formation, the technique produces excellent quality SE and RTWCGSiOx texturing. RTWCGSiOx texturing improves the ARC's already low reflectivity by further increasing light trapping. 1 shows a cross-sectional view of one or more embodiments of a high efficiency, low cost RTWCG SiOx ARC/SE/TO crystalline solar cell 100. The method and process described herein relates to a novel crystalline solar RTWCG SiOx ARC/SE/TO battery design comprising: (i) a SiOx thin film dielectric layer that is sufficiently passivated to the surface of the cell and is an excellent ARC. And (iii) a flat or textured SiOx (TO) surface. The wafer or substrate μ❶ is a semiconductor material 'usually Shi Xi. The selective emitter layer 12 is disposed on the substrate 140. The selective emitter provides low contact resistance due to heavy doping at the front contact 11 and provides for front side purification of the lighter doped regions between contacts. The element also includes an ARC coating 130 disposed on a lightly doped region (deep emitter) of the selective emitter. The rear contact 150 is located behind the battery. Optionally, the battery can include a textured oxide surface 135. The texturing feature can be applied to a battery having an initial flat front surface. It can be designed via another short temperature and wet chemical step or by using ARC and ^^,^^RxwcoSi〇x RTWCGSi0xARC/SE/T0 battery design (Figure υ has very low reflectivity, excellent quality selective emitter and Back surface passivation provided by more complex PERL technology. In one or more embodiments, ARC, SE, and τ stress characteristics are produced in a single step. 曰RTWCG Si〇x ARC/SE/T0 battery designed smooth emitter Minimizing the resistance loss of the 20 201251057 41245pif current to the grid finger (the lateral flow of the grid finge〇. This is in contrast to other high efficiency battery designs (such as PERI^ batteries) that use textured emitter surfaces. For these other battery designs, Resistive losses may be the limiting factor for lower fill factor (FF) compared to low efficiency to medium efficiency 矽 battery designs with smooth emitter surface and textured Si0x ARC RTWCG Si〇x arc/se /t〇's power, not counting battery efficiency. This is attributed to significantly reduced emitter layer resistivity loss, lower contact resistance, higher shunt resistance and lower diode In addition, the KTWCG SiOx ARC/SE/T0 battery is designed to be highly reproducible, compared to the most well-known n+/p crystalline solar cells that do not contain SE or contain poor functional se. Ensures good blue response. The strong front and back surface fields and good edge separation generated by the RTWCG SiOx ARC/SE/TO battery design further improve the spectral response and reduce electrical losses throughout the AM1.5 spectrum. Figure 2 depicts one or more embodiments of a low cost, high efficiency rtwcg SiOx ARC/SE/T0 novel solar cell fabrication technique. Depending on the concentration of the RTWCG solution, the novel rtwCG SiOx process is set to be within 20 seconds to 1 minute. The pre-metallization and post-metallization of the solar cell simultaneously produces the following enhancement features: i. On-site chemical cleaning of the cell surface (including metallized surface) to prepare for interconnection; ii. Purifying the emitter surface and when flat A gradient of AM1.5 average weighted reflectance (AWR) less than 1〇% when grown on the emitter surface 201251057 41245pif SiOx ARC ; iii. By controlled etchback of unmetallized hair The extremely effective SE produced by the extreme surface. The RTWCG SiOx ARC/SE/(TO) crystallized solar cell design and technology of the present invention reduces and simplifies the number of solar cell processing steps. In addition, it uses the current technology of solar cells and solar cells. Module features such as higher conductivity contacts and alternatives to EVA sealing materials. It also benefits certain benefits of the RTWCG process itself, such as the use of bend and tail-type diffusion profiles in the launch. Since the bending and tail-type diffusion profiles have relatively deep junction depths, the possibility of shorting the front gate lines to the junctions is eliminated. This in turn allows for the use of higher conductivity contacts and lower contact resistance screen printing of the metallization solution, thereby reducing the already low contact resistance resulting from the high net surface concentration of the under-gate diffusion profile. These benefits coupled with extremely efficient SE produce a battery structure with a strong front surface field, low ideal factor, and large blue light response gain resulting in a significant increase in battery efficiency. / RTWCG SiOX ARC/SE/ΤΟ 石 夕 太阳 solar cell manufacturing technology uses a low cost process method that simplifies or removes various process steps of other high efficiency 矽 solar cell technologies known in the art. The manufacturing techniques of n//p (P, B) Si solar cells are summarized below. Cutting damage removal and cleaning prior to diffusion. Phosphorus diffusion' having a net majority-carrier concentration diffusion profile of the bend and tail shape and preferably mechanical or other type of edge masking to prevent re-diffusion of the battery edges. 22 201251057 41245pif Standard screen printing pre- and post-contact and one-step pre-contact and post-contact annealing. One or more embodiments of the environmentally friendly RTWCG SiOx ARC/SE/(TO) single process step is a low cost wet chemical process that achieves the following operations in 1 minute or less: 1) Cleaning the bare solar cell and metal 11; can perform n+/p and p+/n or edge separation of n+/p/p+ or p+/n/n+ structures for enhanced efficiency diffusion; iii. on the surface of unmetallized cells, depending on the type of substrate The growth index AM1.5 AWR is between 5% and 9% gradient index Si0xARC; IV. On-the-spot TO characteristics can further reduce AM 1.5 AWR to 3%; v. Formation compatible with a large number of low-cost manufacturing Excellent quality se; vi. The Si0x film produced by the relatively 鬲 growth rate (> 2 〇〇 nm/min) rtWCG si〇x solution can produce τ〇 characteristics with the arc/se feature. An SiOx film produced from a slower growth rate (<5 Å nm/min) RTWCGSi〇x solution may require another 忉20 second etching step in 〇 5% 2% HF (aqueous solution). Cutting damage removal and 矽 wafer cleaning before diffusion Before the components were fabricated according to Fig. 2, the surface of the ruthenium substrate was prepared 2 〇〇. Conducting a bismuth (Si) semiconductor wafer prior to forming the emitter via diffusion = surface preparation is well known in the art and is typically wafer cleaning. The surface cleaning technology used by the factory conductor industry and also suitable for the conventional solar cell manufacturing technology and especially suitable for most surface efficiency solar cell technology is generally 23 201251057 41245pif divided into four groups: front-end of line (FEOL) ), diffusion-end of line (DEOL), metallization-end of line 'MEOL', and back-end 〇f line (BEOL).

There are two basic types of wafer cleaning today: RCA type wet cleaning for the Feol and DEOL processes and solvent based cleaning for the MEL and BEOL processes. Associated with the surface cleaning of the Si surface prior to diffusion is the FEOL process. While several novel technologies such as gas phase cleaning, uv assisted cleaning, low temperature aerosol cleaning, and plasma cleaning are showing promise, the semiconductor industry still relies on wet processes for most FEOL cleaning steps. The well-known and most widely used FEOL cleaning process is the RCA cleaning process. In 1965, W. Kern developed a basic RCA program during his work for RCA (Ra(}i〇 Corporation 〇f America) _ hence the name. RCA cleaning on the surface uses two The steps, called Standard Cleaning 1 (SCI) and Standard Cleaning 2 (SC2), expose the wafer to a hot mixture of dilute aqueous hydrogen peroxide solution and ammonium hydroxide in the SC1 step to remove organic surface films and particles. The conventional SC1 step consists of a volume of Hah to 1 part by volume of NH4〇h to 5 parts by volume 40. The SC2 step is designed to remove ions using a volume of H2〇2 to 1 part by volume of HC1 to 6 parts by volume of h2〇. Heavy metal atomic contaminants. Use a diluted 1 volume HF to remove a thin layer of SiO2 before diffusion. Metallic contaminants may accumulate due to SCI. 曰Because most of the ruthenium substrates are currently Solar-grade substrates, and most of the twins 2012 20125757 41245pif circle manufacturers offer pre-cleaned Shihua wafers with thicknesses ranging from 180 μm to 250 μm, and have been proposed and improved using conventional RCAFEOL cleaning. SCI step and SC2 step Before, after and between the "Piranha" (98% H2S04 and 30% H2〇2) and HF steps. For example, IMEC shows that the standard SC2 can be replaced with 0.1 mol/min. The liter of HC1 without the use of 〇2 reduces chemical consumption and saves costs while still maintaining metal removal characteristics. One of the reasons for the continued success of improved RCA wet cleaning is ultra high purity water (UHPW). And the availability of chemicals. In addition to the increased chemical purity, the most significant trend for RCA cleaning is the use of leaner mixtures in an attempt to reduce surface thickening. Today, a handful of technology-leading companies still use traditional (5:ι:ι Nh4oh:h2o2:h2o or HCl.H2〇2.H2〇 is used for SCI and SC2, respectively, many of which are diluted at least 10 times. US Patent No. 6,613,697 describes a FEOL Si wafer cleaning process, which is a conventional RCA cleaning process. Modified form. By using "Pigaver" and HF step 'on p-type and n-type (1) and (ill) substrates before, after and between SCI step and SC2 step, generally known in the art. Growing high quality R TWCG SiOX film. The improved FE〇L cleaning formulation and process disclosed in one or more embodiments of the 'US Patent No. 6,613,697 can be used for thin (about 2 micron) or thinner substrates before diffusion. Improved RCA (MoPiranha) and modified piranhas (MoRCA) for cleaning the surface of the wafer before the emitter is formed (ie, diffused). Step 25 201251057 41245pif 1. At 50°C-60°C in MoPiranha Wash the solution [2 parts 98% H2S04: 1 part 30% H2〇2: 20 parts H20] for 3 minutes - 5 minutes; 2. Ultra-high purity water (UHPW) rinse; 3. Wash in 0.5% HF (aqueous solution) 1 minute; 4. UHPW rinse; 5. Wash in MoRCA SC-1 solution [3 parts NH4OH: 1 part H202: 25 parts H20] for 3 minutes - 5 minutes at 50 °C - 60 °C; 6. UHPW rinse 2 times; 7. Wash in 0.5% HF (aqueous solution) for 30 seconds; 8. UHPW rinse; 9. In MoRCA SC-2 solution at 50 °C-60 °C [25 parts 0.05 m / liter HC1 : 1 Wash in portions of H202] for 3 minutes to 5 minutes; 10. UHPW rinse; 11. Wash in 0.5% HF (aqueous solution) for 30 seconds; 12. UHPW rinse; 13. N2 dry. F-Fold and Tail-Type Net Most-Carrier Concentration Diffusion Profile As illustrated in Figure 2A, an emitter layer 210 is first deposited on a surface-prepared tantalum matrix 2 (10). Conventional screen printing n+/pSi and possibly more efficient ρ+/η& solar/convene suspension using simple homogeneous diffusion to form the emitter, the doping amount under metal contact and the unmetallized portion of the emitter surface Same on the same. In order to produce a low contact resistance between the emitter and the gate line, a high concentration of 26 201251057 41245 pif is required under screen printing contact. However, the agent or _ agent Mei it upper layer:: it greatly reduces the blue of the battery first Ϊ 浅 浅 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The frequent drop in the shunt resistance value is also a problem. As far as is known, battery manufacturers do not currently use the f = tail f diffusion profile known in the art because of surface donors (d_0 concentration over the line and n++ emitter) The contact resistance between the surfaces is improved, but the I diaphragm should be low and the battery efficiency is degraded. The highly doped surface layer must be spontaneously returned to the unmetallized portion of the surface. This will form the so-called selective hair = (SE) An enhancement feature that has been provided by the RTWCG application of arc/se/t〇 crystal solar cell design and technology. The discussion herein will be limited to the fabrication of high efficiency, low cost crystalline germanium solar cells as described in this disclosure. +p (PB) Si cell structure. However, it should be understood that by using the same fabrication techniques disclosed herein, a low cost p+n Si RTWCG Si〇x ARC/SE/TO crystallization solar cell can be produced. Structure ' may also produce n + /p/p+Si p+/n/n+Si RTWCG SiOx ARC/SE/TO crystalline 矽 solar cell structure. Other structures are also apparent to those of ordinary skill in the art. Bending and tail-type phosphorus diffusion profiles are attributed to the source of phosphorus The double diffusion mechanism produced by the high concentration in the sputum. In this type of diffusion, the total phosphorus incorporated into the surface of the diffusion layer is much higher than the corresponding electroactive phosphorus. However, under the bending, 27 201251057 41245pif ί The thick money is almost equal. The concentration is half the impurity solubility of the impurity alizarin in Shi Xi. For example, in (4) 〆, the wall in the stone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ By using RTWCG to apply ARc/se/ (supply efficiency J gain' according to - or a plurality of embodiments, the amount of _ can be = lower than the n-degree of the diffusion at a given diffusion temperature. Forming the fold and tail type diffusion The diffusion temperature of the distribution curve can be between 875 ft and about. The diffusion time is chosen to produce a junction of G5 micron and Q65 micrometers, where the approximate depth is approximately 0.55 micrometers for the RTWCG SiOx ARC/SE cell structure and for RTWCG &;〇χ arc/se/t〇 electrical structure, approximately the best depth It is 0.60 micron to 〇65 micron. 'When the diffusion profile has a high concentration disc source, the thin resistance of the emitter mainly depends on the size of the high concentration region. Subsequently, the bending and tail-type expansion curve can produce the same thin The emitter of the layer resistance, although its depth is equal. When the diffusion time is 87 (TC-95 (the lower limit of the TC diffusion temperature range is extended, the filament is a longer concentration of the low concentration tail relative to the erbium concentration domain and is less steeply distributed) Curves. The emitter of a particular thin layer that diffuses at lower temperatures can produce screen-printed solar cells with a higher fill factor due to a reduced Schematic shunt (Seh magnetic ytypeshunt). Diffusion of a longer duration emitter at a lower temperature produces a higher gettering efficiency, and the internal quantum efficiency is higher. However, the deeper tail of the low temperature emitter extends a less steep diffusion profile and has a weaker front surface field. This increases the absorption in the complex composite emitter, resulting in current loss due to a decrease in the rate of collection at a short wavelength. Figure 3 provides an example of the bending and tail-type net majority of the donor's depth of curvature for the RTWCGSi〇XARC/SE/T〇 single crystal 矽 solar cell design. The diffusion profile is obtained using a diffusion resistance method using a furnace setup as shown in Figure 4 or any other conventional diffusion/doping technique. Experimental devitrification was performed on a 600 micron thick (touch) sin (cz) substrate. Use an open tube (.clear_) with a diffusion temperature of _. The diffusion time was 24 minutes, followed by a 7 minute purge and a 1 minute drive. Setpoint is 8〇 (rc ' is rising at a constant rate of 8t/min, and is slower down at 3 C/min. As shown in Figure 3, it is about the secret, cubic centimeter, and bent under the emitter surface: = The rapid rate drops slowly 'but the tail is still (4), thus ensuring the formation of a relatively strong front surface field. For the sub-efficiency transfer, RTWCGSic) XARC / SE process in + / Ba Shi, Figure 3 bending and tail type diffusion distribution The small area of the curve, I also makes the battery blue response better than the bare cell improvement of the 'RTWCG SK) X ARC/SE process from the unmetallized surface of the emitter (10) about 0.2 microns (shown by line 3 (10)), In order to produce the best ^ meters ° This means that these small turn-type diffusion distributions, such as W, remove about G · 2 microns from the emitter surface of the active region, so ^ ▲ visible 'remaining surface concentration is still higher than 1G2G / cubic The centimeters are therefore too high for an efficient battery. (>2 0Γ太3 J Γ The distribution curve is more suitable for the use of rtwcg 29 with a larger (not / min) Sl0x growth rate. 201251057 4I245pif

SiOx ARC/SE/TO process. To produce an initial approximate optimum Si0x thickness of 22 奈 nano-240 nm, the process etched back from the unmetallized surface of the emitter by 0.25 microns to 微米.3 microns (shown by line 310). As can be seen in Figure 3, the remaining surface concentration in the active zone is still slightly above the optimum of 1 〇 19 / cubic centimeter. For the above diffusion profile, although the blue light response of the cell after Si〇x growth is significantly improved, the high surface concentration after etchback from the emitter active region of about 0.3 μm yields only 5 〇/square on the active region of the return-to-back family. Sheet resistance in ohms per square unit. This sheet resistance is too low for high efficiency batteries. As described in the Selective Emitter section below, rTwcg SiOx AKC/SE may have a diffusion depth (junction depth, xj) of «·5 «to 55·55 μm and the bend may be approximately from the surface. Micron to maximize Isc, Voc, and FF, and thus maximize battery efficiency. The initial surface concentration can be about 6 x 1020 /cm ^ 3 and the final surface concentration (after etchback from the undoped surface by about 0.2 microns) should be from 8 χ 1 〇 18 / cubic centimeter to 1 〇 19 / cubic centimeter. After etch back, the resulting diffusion profile of the unmetallized emitter region can have a Μ slope' which produces a strong field. For high-efficiency batteries, the sheet resistance of the emitter can be 2 ohms/square unit _25 ohms/square unit before coating, and after the formation of RTWCG Si0x ARC/SE is ohms/square unit - 120 ohms/ Square unit. Edge Separation Wafers used in the processing of crystal solar cells are usually shed, but can be used as any as is well known in the art? The type of substrate, and the junction is generally expanded into the p-type substrate. Standard n-type doping is typically carried out using commercially available sources. Other types of dopants as are well known in the art can be used. Irrespective of the source 30 201251057 41245pif, phosphorus diffuses not only to the desired and back surfaces. This is in the surface - and spreads over the edge diameter. Due to this, there is a shunting and laser cutting between the objects (4). As the edge-edge separation technology, the path of the edge of the wafer containing the plasma is separated by n' edge junction or removed from the sample stack (- the edge of the exposure. L is placed in the electric cavity to remove the metal mi test After the removal of the joint. A majority (four) quotient on the back side using the shang = piece; neutralize its role, thereby obtaining two == =, /#_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Solubility usually causes ineffective damage to the n-type layer. This produces a weak back surface field, which ultimately results in low cell efficiency. Unless the parasitic emitter diffusion around the edge of the wafer is removed, most industrial cells are likely to be as low as 6〇%. Very low fill factor. A number of different methods are known in the art for performing edge separation on a tantalum solar cell, including but not limited to, electric H-cylinder surname, conventional laser slotting, dry side, in-line wet Inline wet etching and dispensing of etching pastes. Water jet-guided lasers are an emerging new laser process that can overcome the problems of conventional lasers. Until a few years ago, The name of the plasma cylinder is engraved as the standard for the separation of the edge of the solar cell. Process, but replacing the process with an appropriate in-line process is of great concern. Batch technology creates strong damage in process flow 31 201251057 41245pif (process flow) due to stacking and de-stacking a large number of wafers. This problem makes some manufacturers Choosing a destructive process step, freshly (4) ^ Battery efficiency is reduced. The most successful purchase of edge separation and throwing, it is said to be suitable for in-line reinforcement, and does not need to contact crystal _. '·,, Lei It is generally believed that the process flow associated with the interruption of the electric cylinder is extremely advantageous. The laser and etching processes each have certain advantages and major defects known in the art. Therefore, the conventional method of f-edge separation must be Whether the commercial efficiency of the edge separation step can be further improved. ° A better red light response is obtained by enhancing the back surface field. A known method of enhancing the back surface field is to use an n+pp+_Si diffusion cell structure. After that, the wafers are arranged so that the wafer surfaces with the same dopant type face each other. Although this technology has been proven to produce good efficiency, solar cells, There are two additional steps required for spin coating and organic removal. These additional steps increase manufacturing costs and reduce process flow, making it unsuitable for use in large solar cell manufacturing. Compared to the use of screen printing aluminum surface field (aluminum back surface field) , A1-BSF) traditional n+p Si cell structure, boron diffusion n + pp + Si battery structure produces a more efficient battery. By improving the surface passivation after the solar cell, by reducing the back surface recombination and improve The near-red light and red light collection efficiency is stronger after the surface field is performed. Replacing the Π+ΡΡ+Si battery structure with the p+nn+Si battery structure can prolong the effective minority carrier main body life, thereby generating a higher open circuit voltage. In one or more embodiments, the use of an in-line process eliminates the need for edge separation process steps as well as battery stacking and de-stacking. Battery edge re-diffusion can be prevented by masking 32 201251057 41245pif battery edges during the diffusion step. Figure 4 shows an intended conveyor type diffusion device 400. The germanium wafer 410 is placed between the semiconductor grade ceramic plates 415, 420 having a low thermal conductivity. The expansion and contraction constant of the semiconductor grade ceramic plate is similar to the expansion and contraction constant of the germanium substrate. The ceramic plate is mounted to the side wall of the lower diffusion chamber 430 and is secured in place by the upper stainless steel member 440. The pair of hot stainless steels used in the apparatus should be semiconductor grade stainless steel with less out-diffusion of impurities. Clean tantalum substrates are generally hydrophobic, causing problems well known in the art. A non-uniform diffusion source layer can be produced by spraying an aqueous diffusion source such as dilute phosphoric acid and dilute boric acid on a clean tantalum substrate at or near room temperature. In one or more embodiments, the above problem can be prevented by spraying the leap seconds for _5 seconds at a temperature of 175 ° C to 20 (at a temperature of TC of 20 Torr to 50 Torr above atmospheric pressure. The uniform increase in the internal temperature and the uniform rate of decrease can be carried out in a nitrogen atmosphere. As described above, the diffusion source is applied at the beginning of the rapid temperature of 5 ° ° C / min to i ° ° c / min. The source layer, however, after the diffusion of the diffusion and removal of the diffused glass, contamination is observed, especially on the doped surface. The contamination problem is added to the continuous flow by increasing the oxygen flow from 2 minutes to 2 minutes before reaching the diffusion temperature. The nitrogen flow is overcome. Then, the oxygen flow is stopped after the first i minutes_2 minutes after the temperature of the temperature should not fall ==〇C/min. 绫, the mechanical smear diffusion source enables it to cover the battery ^, It also prevents any crossover from the opposite surface. Zinc by 佶Η This simple line of inner-age compartment is also recorded by the moon diffusion technique* (its towel diffusion source is at a constant temperature uniform speed 33 201251057 41245pif (5( M〇〇°C/min) deposition at the beginning), which can be on the opposite sides of the germanium wafer A good quality n+ diffusion layer and a p+ diffusion layer are obtained. Furthermore, according to the present invention, any unsuitable cross-doping of the cell edge that may occur despite the presence of a mechanical mask can be performed during the RTWCG SiOX ARC/SE (TO) process. The meal is engraved. Because this method does not require an edge separation process step, it correspondingly reduces the processing cost' while increasing the RTWCG si〇x ARC/SE/(TO) cell efficiency. By using the above diffusion procedure, RTWCG n+/p/p+ The solar cell efficiency of Si or p+/n/n+ Si crystals is increased by the following reasons: the formation of a strong back surface field, a lower density of the recombination center on the back surface, and a significant decrease in the front contact and back contact resistance. Metallization and post-metallization require some much lower annealing temperatures. The reduced annealing temperature reduces manufacturing costs by reducing the energy consumption of the processing steps. In addition, the shunt resistance (Rsh resistance) of the excellent quality RTWCG SE features Will increase so that the front gate line and junction are less likely to be shorted. The advantages of liquid diffusion sources are known in the art. Hazardous chemical dopants (such as oxygen) Phosphorus (n+ doped), phosphine (n+ doped), boron trichloride (protective doping), boron tribromide (p+ doped) and diborane (p+ doped) can be replaced by safe dilution Phosphoric acid (n+ doped) and boric acid (p+ doped). It is recommended to use a liquid diffusion source as an example of a diffusing agent that generates p+/n/n+ Si diffusion in the line. It is also recommended to physically mask: ^ 4). It is understood by those of ordinary skill in the art that (iv) the source can be replaced by any other type of diffusion source (such as solid, gas, screen printing diffusion source, spin-on diffusion source). Similarly, = 34 201251057 41245pif Any other edge masking scheme, followed by any derivative process using the RTWCGSi〇xARc/sE/ (TO) process, removes unwanted diffusion from the edges of the η+/ρ &, & or p+/n/n+ Si solar cell structure Impurities do not depart from the teachings of the present invention and are still encompassed by the present invention. Screen printing pre-contact and post-contact and one-step front contact and rear contact annealing. Subsequently, as shown in Fig. 2B, the metallized contact 23 〇 and the front gate line 22 涂覆 are applied to the component. The Spectrolab was exposed to the ground-dream solar cell contact by screen printing metallization in the late 1970s. Although this method has indeed been tested by the time of residence, the contact resulting from this type of metallization has serious limitations. In order for the shop to have sufficient __resistance, the emitter surface must have a high impurity concentration. Since the front weave is silver = large (10) micrometers, the aspect ratio is relatively poor. It has a relatively low ^ conductivity' and finally produces a sharp peak along the (five) plane of the inscription metal = fire under the entire back surface of the cell. Although the fines obtained by screen printing metallization are flawed, they are highly cost competitive and highly adaptable for high volume manufacturing. To date, there are no other technologies available to compete in terms of cost or adjustability. The paste used in the eight-screen printing metallization consists of small metal over- and low-spot glass composites (glass frit) and organic binders and dissolved n+/p material pool structure, f-pass # contains silver (^ )powder. In order to reduce the contact resistance, a phosphorus-containing compound which increases the doping concentration of the front contact may be added to the paste. For areas that are behind the surface paste, 35 201251057 41245pif is usually used to dope the underlying p-type region with A1. Immediately after each side of the screen printing, the paste was dried by heating at a temperature of 350 C-400C. The contact is then typically fired in a belt furnace at up to 900 ° C, which is above the Ag_Si eutectic temperature of 835 ° C. It is well known in the art that the contact resistance of the gate-to-n+-Si emitter based on Ag may be highly sensitive to firing conditions. The paste used for postcontact screen printing consists primarily of silver and a small percentage of aluminum. The conditions of postcontact roasting are also critical to ensure that the back junction is neutral. Melting the temperature gradient region can be an important issue when doping the A1 paste component to form a "back surface field." Infrared lamps are typically used instead of standard furnace heating elements for firing. Novel metallization technologies with high yield potential and improved metal coverage, fingerresistance, contact resistance and material cost are being developed. Prior to the display of potential benefits, the contact and post-contact metallization process technology is: nano ink, metal aerosol spray, metal powder laser sintering, contact heterojunction and electroplating. Finally, plasma vap〇r deposited (PVD) TiN, TiW and TaN produce copper barrier layers and are potential alternatives to silver and aluminum metallization. The use of a thicker and heavier doped region under the front gate line provides greater latitude for the metal contact firing step. It makes it possible to use a screen printing metal formulation that penetrates deeper and more electrically. Back-silver and growth SiOx layer After pre-screen printing metallization and post-screen printing metallization, as illustrated in Figure 2C, the RTWCG solution grows the RTWCGSiOx film 250 on the unmetallized surface of the cell without the need for additional surface preparation. The method can be used to prepare a SiOx layer that performs multiple functions with 36 201251057 41245pif. In one or more embodiments, the SiOx layer is formed using a controlled etch back doped yttrium surface layer and a grown SiOx layer. Because of the consumption of Shi Xi, there is control of "etch back" in Shi Xi wafer. At the same time, the surface reaction produces Si〇x on the surface. Total SiOx growth is the balance of two competing reactions in the growth solution system. The SiOx thickness as used herein refers to the final SiOx thickness of the layer. The Si〇x growth rate refers to the total thickness produced in one time unit (usually 1 minute). Growing a given SiOx thickness typically requires the use of a larger thickness of the initial ruthenium substrate, so the total SiOx layer grown is smaller than the Si button. For example, when forming a 100 nm SiOx layer, 15 Å of nano Si is consumed. In one or more embodiments, the layer can be grown rapidly '~-I/, % to form an anti-reflective coating. The layer provides better anti-reflection due to the compositional gradient of the layers. Compared to SiNxARC on textured polycrystalline wafers, the RTWC on the polished wafer (J ARC can have the same or lower inverse. In one or more embodiments, the refractive index of the layer changes gradient, _ The refractive index of the outer surface is close to that of the outer surface (the refractive index is about (7), and the refractive index toward the inner layer of the layer is increased, and the refractive index of the stone (nearly 3.4) is closer to the interface of the si (five) substrate. In one embodiment, the SiOx growth process produces a purified layer that reduces the surface reactivity of the sapphire. In other embodiments, the SiOx process adsorbs J on the sap layer (respectively and reduces impurities. In detail, the doping in the paper layer The miscellaneous miscellaneous shells can be directly related to the purity of the chemicals used in the (four) layer of towels. When using high-altitude polar materials and providing high-turning ships and yue. ° Temple 37 201251057 41245pif in one or In various embodiments, the etchback layer is used to accurately thin the emitter layer 'eg, only one portion of the emitter layer is etched back. For example, etch back and s 丨〇χ growth may remove the remaining _ after diffusion process ( p) non-inductive layer (dead 1 beat). The solution only reacts with hydrazine Thus, the gate can be used as a mask before firing, and the process produces a self-aligned selective emitter. In other embodiments, the SiOx layer is grown to a sufficient thickness to remove all emitters. This process produces passivation In other embodiments, the RTWCG process can produce a textured oxide (το) layer by etching the surface of the Si〇x layer to texture the Si〇xARC. The S i〇x layer is textured rather than textured. It has certain advantages. The T〇sί〇χ layer exhibits a reduction in surface recombination velocity and a degree of enthalpy before the surface passivation due to the smaller surface damage and reduced surface area of the crucible. During the growth step, the growth rate condition (eg, &gt Textured oxide surface can be formed at 2 nanometers per minute. The texturing process can also be performed using a weak acid wet process step after growing si〇x. Si〇x thickness for texturing It is about 0.2 micron to 0.22 micron (rather than the standard si 〇 x ARC/SE 13 13 micron), which may require a slightly longer growth time (about 3 sec - 6 sec seconds) and make the etchback depth 0.2 micron increased to about 微米3 microns The net surface ρ concentration is made lower, approaching the "blue cell". In one or more embodiments, 'the Si0x layer is grown on the doped semiconductor surface. In one or more embodiments' at n+ or n++ A SiOx layer is grown on the Si surface. In one or more embodiments, the Si〇x layer is grown on the p+4p++ & layer. In one or more embodiments, the substrate is immersed in an RTWCG SiOx liquid 38 201251057 41245 pif solution. The immersion technique not only grows the SiOx film on the unmetallized portion of the emitter, but also grows the Si〇x film on the edge of the cell and on the unmetallized surface. This method was used to perform most of the experimental studies performed to generate RTWCG SiOx ARC/SE/(; TO). Other RTWCG techniques have been successfully used to deliver the RTWCG solution to the substrate. The spray technique uses a specially designed atomizer to deliver a thin film of RTWCG solution on the surface of the tantalum cell. In the floating (f]oating technique, the front side of the solar cell is placed on the surface of the RTWCG solution; the surface tension of the liquid solution is such that the battery does not sink. The dispensing technique spreads the RTWCG solution from above along parallel to the gate line. Due to the aqueous composition of the solution, the meniscus is formed, which is strong enough to prevent the solution from flowing out of the battery. The RTWCG solution is delivered using mechanical component technology and components such as brushes or rollers. Some mechanical components require the viscosity of the solution to increase via the addition of cellulose or any other non-contaminating gel. After the RTWCG SiOx is formed, the battery is rinsed with water and then blown dry with nitrogen or dry air. Although the purity of water is important for other battery processing steps, it is not particularly important for RTWCG film processing. Experimentally, there was no significant difference in the performance of RTWCG cells flushed with ultra-high purity water (approximately 18 megohm-cm) and RTWCG cells flushed with simple lower purity reverse osmosis water. In one or more embodiments, the SiOx film is grown using a modified RTWCG solution. Certain components, such as a helium source, can be removed to form a simplified solution that can be used to make high efficiency, low cost, stone solar cells. These RTWCG SiOx solutions have a high growth rate' and produce a good quality SiOx film for use as an anti-reflective coating (ARC) with an extremely low AM 1 5 39 201251057 41245 pif average weighted reflection. The formation of 'the novel RTWCG SiOx solution with ARC produces a number of other important features that are known to increase the efficiency of photovoltaic cells. This simplifies a number of expensive manufacturing steps from the novel RTWCG SiOx solution, which simultaneously produces all of the enhanced features in a single process step. The RTWCG SiOx method and process described herein is a room temperature wet chemical process which rapidly grows a thin dielectric film based on oxidized SiOx on a ruthenium substrate by catalysis. The growth rate of the RTWCG Si〇x solution for solar cell applications is about 500 nm/min. The growth solution can be formulated to grow an ARC film thickness of about 150 nm in about 18 seconds. For integration into existing manufacturing schedules, SiOx growth time can be adjusted from 25 seconds to 1 minute, for 10'\¥00 3丨0乂8 11 (: fine battery design, which can be converted to 14 nanometers per minute to Growth rate of 150 nm/min. For RTWCG siC) x ARC/SE/TO battery design, growth rates ranged from 220 nm/min to 24 N/min. The growth rate value can be determined experimentally by measuring the time required to grow an oxide of a suitable thickness. For ultrafast Si〇x growth rate dissolution, the thickness of the SiOx film grown on the heavily doped n+矽 substrate or p+矽 substrate can be as high as 500 nm in the first minute, and normalized for longer growth times. The SiOx growth rate is steadily reduced. As the SiOx film grows deeper, the oxygen required to continue the reaction must migrate through the increased SiOx thickness to the Si0x/Si interface. As the reaction progresses/rows, the growth rate becomes smaller and smaller. Therefore, the growth rate of the Rttwcg SiOx film is not constant as the growth time of si〇x. This is actually advantageous in terms of excellent uniformity of the film and greater control over the thickness of the SiOx. 201251057 41245pif If the substrate is cleaned, the Si〇x film is extremely uniform. Figure 5 shows a SEM ® of a 4 Å nanometer thick rtwcg SiOx film grown on an 8 Å semiconductor grade c-Si substrate with a mirror-like surface. The thickness of the Si〇x film of the above RTWCG SiOx film is about 5%·5% as measured by an ellipsometer. AFM revealed an average surface roughness (average resistance to roughness, ASR) as low as 〇1 nm. For a clean solar grade flat 矽 substrate, the film thickness deviation is less than 1 〇 / 。. For example, thickness measurements were performed on each of the six solar grade 5 忖 Cz Si substrates at an independent test facility using an ellipsometer. The SiOx thickness on the substrate is in the range of 68 nm to 110 nm. The 5-point thickness measurement on each substrate showed a high deviation from the mean difference of 1.0% in the optimum Si〇x film to 1.03%. As shown in Figure 6(a) showing the Nomarski micrograph (χΐ, 100) of the Si〇x film grown on the surface of the n+c_Si covered by the pyramid, the Si0x film grown on the clean germanium substrate is shown. Has good consistency. The graphs acquired by Norma Microscopy show no contrast difference between the faces of the pyramid structure. From this, it can be inferred that the RTWCGSi〇X film growth proceeds in the case where the crystallographic position is upward without any significant preferential growth. In fact, even when various crystal sites existing on the porous tantalum substrate are grown upward (Fig. 6(b)), the SiOx film is quite uniform and uniform in shape. The good consistency of the RTWCG si〇x film makes it ideal for texturing solar cell surfaces. Device-quality RTWCG SiOx film by making

The growth solution formulation disclosed herein is grown. SiOx臈 can be grown on the following materials: S 201251057 41245pif i. Various crystalline stone substrate (such as c_Si and mc_Si); ϋ·amorphous chopped substrate; m. semiconductor substrate, including but not limited to Ιπ ν compound Semiconductors (such as GaAs) and I-II-VI semiconductors. Unless otherwise specified, RTWCG Si〇x films grown in relatively low growth rate solution formulations of less than 1 nanometer per minute are uniform and consistent in shape. The car father's RTWCG SiOx growth solution was selected via a screen printing process comprising the following steps. I. Select the components of the SiOx growth solution. Π Select SiOx growth control. III. Composition and chemical SiOx composition and pollution control. IV. Test RTWCG SiOx solution for a large number of crystalline germanium solar cells of various sizes. ν·Test RTWCG SiOx solution for various metallization schemes. VI. Test the compatibility of RTWCG SiOx solution with photoresist. VII. Test the homogeneity and consistency of RTWCG SiOx using the following techniques: i. High resolution Nomas-based microscopy; ii. Scanning Electron Microscopy >SEM; iii. Transmission electron microscopy Transmission Electron Microscopy » TEM; iv. Atomic Force Microscopy (42 201251057 41245pif AFM). VIII. The chemical composition of RTwcG SiOx and the atomic concentration of each component of SiOx film were tested using the following techniques: i. Energy-Dispersive X-ray analysis (ED ΑΧ); ii. X-ray photoelectron spectroscopy (X- Ray Photoelectron Spectroscopy ' XPS) study and depth profile; iii. Auger Electron Spectroscopy (AES) depth profile; iv·Secondary Ion Mass Spectroscopy (SIMS) depth profile; ν·全Total reflection X-Ray Fluorescence (TXRF) depth profile; vi. Fourier Transform Infrared (FTTR) depth profile; IX. Vapor Phase Decomposition (VPD) SiOx Membrane surface. X. SiOx thickness is measured by using the following techniques: i. ellipsometer; Dektak profilometer; iii. SEM image of the side of the SiOx film. XI. The optical properties of the RTWCG SiOx film (including the refractive index and extinction coefficient as a function of wavelength) were tested using the following techniques: i. High-resolution ellipsometer; 43 201251057 41245pif ϋ·With UV/Vis spectrophotometry Reflectance curve of wavelength change; iii· SEM cross-section of Si〇x film. ΧΠ Use the current technology iv/cv Keithley plotter to obtain the ι γ curve and CV curve of the applied ink change with _ 〇〇 〇〇 to +100 volts, and extract relevant electrical data, including : i. leakage current; ii. breakdown voltage; iii. electrostatic dielectric constant; lv. A1 (Au) / grown state (as-grown) rTwcg SiOx/Si/Au fabricated on various SiOx coated substrates -Ti-Ag small gate area MOS capacitors are exposed to various environments (including but not limited to dry heat, high intensity near UV radiation and high intensity plasma) before and after the mobile charge density on the m〇S capacitor v. Dark and illuminating j_v characteristics and isc, Voc, FF, Pmax, Rs and Rsh on the following materials: i. Small area and large area single crystal (c_Si) RTWCGSiOxARC/SE solar cells; more than small area and large area Crystallized (mc-Si) RTWCG SiOx ARC/SE/ (TO) solar cells; iii. conventional n+/p Si homojunction solar cells with screen printing contacts; iv. specific battery design, including (but not limited to) ): a) all rear contact batteries 44 201251057 41245pif b ) spherical solar cells c) vertical Junction (vertical multi-junction, VMJ) cell. XIII. Performance data for the same battery after bare cell and RTWCG SiOx ARC/SE/ (TO) process. XIV. RTWCG SiOx ARC/SE/ (TO) Performance data for solar cells exposed to various environments. XV, internal and external quantum efficiency curves. Most solar cells used for testing are conventional n+/p (P, B) Si screen printing metallized cells having a flat or textured emitter surface. The battery is obtained from each battery manufacturer. Covers other configurations of the substrate.

Most of the atomic concentrations of the components of the Sl0x film are obtained by XPS; the atomic concentrations of the other thicker SiOx films are obtained by AES. Unless otherwise specified, the depth of the XPS and AES depth profile of the Si0x film is referenced to the Ta2〇5 frequency. The ellipsometer data of the selected sample and the Dektak pmfile of the etched features show that the actual thickness of the SiOX crucible is up to 2 times the thickness of the abscissa corresponding to which or the depth profile of the aes. Due to the large amount of experimental data required, the RTWCG SiOx solution is better.

p+ test substrate. I-result and RTWCG, reflectivity and self-emissivity on the cell or Si substrate, using photolithography with mirror-to-positive photoresist 45 201251057 41245pif mask for narrow micron-scale lines and larger millimeter-level Coverage area. The larger, non-resistive region acts as a visible light guide to grow the SiOx film in a narrower line. It can be used for decatometry. There is a relationship between the color of the film and its thickness in the art. The sample was extracted from the growth solution after the correct thickness of Si〇 and 〇 was observed on a large area of the non-resistance substrate, rinsed with water, dried and hindered. The difference between the De Carter distribution curve 2 P white before and after removal by the SiOx film & the thickness of the ten-nose SiOx film and the sound of the emitter button. In one or more embodiments, the room temperature wet chemical growth solution comprises a fluoride solution and a reduced oxidation system comprising one or more elements capable of promoting oxidation of the surface of the crucible. The solution provides a balance between etching (removing the tantalum layer) and oxide growth (depositing the SiOx layer).藉 Through a comprehensive experimental study, it is known that the RTWCGSiOx growth solution may contain a combination of a large amount of metal ions Me+n/Me+(n+m), where n to 4, and m is 1 to 4. These metal ions include, but are not limited to, such as

Ti, Co, V, Cr, Fe, Ni, Cu, Y, Sr, Ce, Ba, Zr, Nb,

Metal ions of Ru, Rh, Pb, Ag, La, W, and Pd. Other rtwcg SiOx gluten solution formulations produce good results' and include A, %, Be, Bi,

Various inorganic metal oxides of Mg, Ce, Hf, Ta, Ti, and Zr, and various non-metal oxides of i and Br. Various metal vapors and metal fluorides including, but not limited to, Bi, Ti, Co, V, Ce, A, and Mg are also used as components of the RTWCG SiOx growth solution to have relatively good results. The inorganic metal oxide containing the above ions is dissolved together with other components in the aqueous fluoride acid solution to grow the solution and the ruthenium substrate 46 201251057 41245pif

A reductive oxidation (oxygen) reaction occurs between them. In a preferred growth solution, there is a suitable ratio between the Si〇X thickness and the amount of the unmetallized surface of the accompanying (four) solar cell. The combination of one or more of the metal ions or non-metal ions listed in the above paragraphs produces an acid-based Si〇x growth solution. The growth rate of various solutions ranges from a few nanometers per minute to as high as 500 nanometers per minute. The various classes of metal and non-metal ions act to provide a reduced oxidation (oxygen) aqueous component and, optionally, can be added to the growth. A catalyst (such as H2TiF6, Pd(〇2C3F3)2, TiCl4, and (NH4)2TiF6) and the like are promoted in the solution to promote the growth of the Si〇-based film.

The modified RTCWG solution is described herein; however, a room temperature Wet Chemical Growth Process of SiO such as SiO based oxide can also be used.

US Patent No. 6,080,683 and "Method of Making Thin Films Dielectrics Using a Method for Wet Chemical Growth of Si〇 Based Oxides on a Substrate at Room Temperature" Process for Room Temperature Wet Chemical Growth of SiO Based Oxides on a Substrate, US Patent No. 6,593,077. The RTWCG dielectric film is composed of Si-Ο-χ, wherein Si is Shi Xi, Ο is oxygen, and X may be nitrogen, carbon, fluorine or hydrogen. To a much smaller extent, the membrane is also composed of a micro Si-Ο-Μ, in which ruthenium is a metal ion. The XPS depth analysis of the preferred SiOx film shows that most of the trace metals are oxidized or bonded to Si, N and other non-metallic trace impurities. By analyzing ion-etched Si, Ti, SiC, 47 201251057 41245pif BN, Ti〇2, thermal Si〇2 and various other metal standards to accurately determine the binding energy in the deconvoluted peak ( The sensitivity factor of the atomic percentage of the SiOx component in the deconvoluted peak). Additives may be included in the RTWCG solution in one or more embodiments to provide a conductive layer. Various RTWCG growth solutions composed of metal nitrides such as Bi, Ti, Co, Cu, Se, and Ce are produced with high si-〇-M (for example, Si-O-Cu, Si-O-Bi, Si-0-). Se) film of concentration. Metal chlorides and fluorides selected from the group consisting of chlorides and fluorides of Bi, Ti, Co, V, Ce, A, and Mg may also be included to promote the formation of a conductive layer. These films are electrically conductive, transparent in the visible portion of the solar spectrum and have a relatively low AWR of about 10%. The Si-ruthenium-iridium film can be used as a higher quality, lower cost alternative to transparent conductive oxide (TCO) known in the art. RTWCG TCOs are used in a variety of electronic and optoelectronic (photonic) applications, including in the manufacture of high efficiency, low cost thin film solar cells. Without being limited by any mode of operation or theory, the KTCWG solution containing these compounds exhibits a process that is capable of performing electroless plating similar to the formation of metals in the SiOx layer. In one or more embodiments, the RTCWG solution contains a fluoride source. Exemplary fluoride sources include H2SiF6, NH4F, HF, H2TiF6, BaF, BF4, and other metals and non-metal fluorides. The RTCWG solution may also contain one or more acids' which may also be a fluoride source. Exemplary acids include H2SiF6, HCl, HF, HNO3, and HzSO4. Non-invasive additives may include (but not limited to 2012, 2012, 51,051,245, pif) NHJ, HF, HCn, strontium, HN〇3, Xenon 2, and cerium oxide sources (such as colloidal cerium oxide, Si 〇 2 and other soluble metals) Citrate). According to the present invention, these additives can be used, inter alia, to adjust the chemical composition, adjust the growth, pH of the solution, the concentration of metal and non-metallic impurities in the film for 5 weeks, change the growth rate of the RTWCG SiOx film, and adjust the metal to the surname. The rate at which the emitter surface is turned. Specially formulated RTWCG SiOx solutions for high efficiency, low cost crystalline solar cell applications are described herein. The development of these novel RTWCG solutions is not only a low-cost, environmentally friendly formulation, but also a formulation that can perform an increased number of tasks. After bending and tail-type emitter diffusion, conventional screen printing metallization produces front contact and back contact. The RTWCG process allows the use of screen printing paste, which provides lower contact resistance and is more conductive prior to gate contact. Finally, the single-step RTWCG SiOx growth solution is simultaneously operated as follows: i. On-site cleaning contains a metallized cell surface; il may produce good quality edge separation; 产生 produces low reflectivity SiOx ARC; iv·passivates the cell surface, including before Ag based Contact and contact after A1; v. Produce a good quality selective emitter (SE); and vi· produce a textured SiOx (TO) surface. Together with the inherent formation of a strong front surface field, the above-mentioned RTWCG SiOx ARC/SE/(TO) characteristics contribute to a significant increase in the efficiency of the solar cell. Compared to other high efficiency battery designs known in the art, RTWCG SiOx 49 201251057 41245pif ARC/SE/(TO) technology greatly reduces manufacturing costs by removing certain processing steps, including some thermal steps that require energy. Pay special attention to the various types of rTWCG SiOx growth solutions described herein.

Development of Me/Me oxygenation systems, oxidation catalysts and non-invasive components. The non-invasive component minimizes the metal impurity concentration of SiOx and produces a low reflectivity transparent SiOx film that is sufficiently passivated to the surface of the crucible. The unmetallized surface etch back of the spontaneous emitter of the solution is required to be suitable for thickness without compromising the integrity of the battery metallization. As described herein, the preferred RTWCG Si0x growth solution utilizes an oxygen system, an aqueous homogeneous oxidation catalyst, and a non-invasive inorganic additive. The XPS BE analysis of each peak shows that traces of unoxidized metal are only present on the surface. About 100% of the impurities found in the bulk region form a stable compound with nitrogen, helium or oxygen. This observation is applicable to RTWCG SiOx films grown on Si and all other substrates studied, such as GaAs and Group IV, Group III-V, other semiconductor substrates of the Ι-ΙΙ·νΐ family. In order to produce the preferred RTWCG §i〇x growth bath formulation for the Shixi solar cell application, the RTWCG SiOx growth solution formulation contains various metal ions Me+n/Me+ (4), of which ^^4, and the melon is 1 To 4. Has successfully succeeded in increasing the rate of limulus dissolution and/or reducing the extent of metal concentrations in oxides - some or none of the metal or non-metal ions include (but are not limited to)

Ti, c〇'V'o'Ni, Sr, Cu, Ce, Y, Zr, Nb, RuRh,

Fe, Ba, Pb, IM, ϊ, Br, A1, Sb, Be, calendar, Hf, Ta, w,

La, Ir, Os, As, Sn, Ag, and Mg. The function of various metal ions is as a component of oxygen, for example, K3Fe(CN)6 forms a Fe2+/Fe3+ oxygen system. 50 201251057 41245pif Other metal ions act as a homogeneous oxidation catalyst component that increases the growth rate of the RTWCG shirt film.

Non-invasive additives include, but are not limited to, NaF, k〇h, NaF and NH4F and HF, Ηα, H2S〇4, H2o and H2o2. These additives can adjust the growth rate, reduce the light and electrical losses caused by metals and non-metals (d), and adjust the rate of the unmetallized emitter surface. However, after all the organic components of the SiOx growth solution were replaced with inorganic components, a significant improvement in SiOx quality occurred. In one or more embodiments, the RTWCGSi〇x growth formulation that produces high quality RTWCG Si〇x ARC/SE/(TO) features is substantially free of Shi Xi. "Substantially free"; ^ source means that there is no large amount of Shi Xi, the original β sheep D in the RT c w G solution, there is no thought to add Shi Xiyuan, and the solution does not contain Shi Xi components. The trace f 3 i does not impair the quality of the RTCWG solution, as it is understood that the micro 1 impurity can be difficult to remove without affecting the function of the solution. The trace amount of the finger is less than 1% by weight or less than 0.1% by weight. In some embodiments, 矽 exists in parts per million. These preferred formulations not only reduce cost, but also maintain an ideal balance between film thickness, growth rate, and etchback. The elements of the genus, and especially the transition metal elements, have a plurality of oxidation states such that they generally participate in the oxygen-reactive reaction. The two oxygens important for the RTWCG SiOx growth process and the unmetallized surface trace of the emitter also react to atomic transfer, such as oxidative addition/counter elimination and f-sub-transfer reactions. The basic oxygen also reacts as a "self-exchange" reaction involving a degenerate reaction between the oxidizing species and the reducing biomass. A relatively large number of 51 201251057 41245pif organic compounds (such as gasified N_(n-butyl)*) and inorganics (such as K3Fe(CN)6) produce electronic exchange, such as! Electron exchange between ^2+ and Fe3+ ions. Many combinations of inorganic or non-metal oxides, inorganic or non-metal chlorides, and inorganic or non-metal fluorides have been found and are used to produce RTWCGSiOx long solutions. The following paragraphs contain highly streamlined experimental subjects that have developed a better simplified RTWCG growth solution from the sub-optimal complexes found in previous RTWCG technology towels. The novel rtWCG growth solution introduces less metal components into the film, has a higher growth rate and is more suitable for mass production of low cost and high efficiency RTWCG si〇x ARC/SE/TO(R) solar cells. Figure 7 shows the XPS depth profile of a prior art SiOX film grown on a (l〇〇)p_si substrate. The growth solution consists of 3 parts by volume of 34% H2SiF6 saturated with cerium oxide, 2 parts by volume, 1 part by volume of 5% N-(n-butyl)pyridinium chloride and 2 volumes of 5% K3Fe(CN)6 (water). The growth solution is not very practical for producing Si〇x ARC in a manufacturing environment due to a growth time of about 2 minutes. The depth distribution curves of Si and germanium atoms are quite constant, so that the ami 5 AWR value is only slightly lower. Optimized cVD deposits are different from ARc film. After removing all organic components, the quality of the film is improved. The depth distribution curve of AEs in Figure 8 is formulated by inorganic growth solution composed of the following materials within 3 minutes. Depth distribution curve of 11〇μm thick Si〇x film grown on p-Si substrate: 5 parts by volume 34% H2SiF6 (aqueous solution), ! parts by volume 6〇% 52 201251057 41245pif H2TiF6 (aqueous solution) and 1 part by volume 5 % K3Fe(CN)6 (aqueous solution) σ Since the Fe concentration is relatively low, the SiOx film has good electrical and dielectric properties for solar cell applications. It is fully compatible with solar cell front contact and post contact metallization. One of the initial RTWCG solution formulations. However, The total reflectance of the light is only slightly lower than the slow growth rate S i 〇X solution formulation (Fig. 7) The unmetallized portion of the n+-Si emitter surface is not etched back enough to form a good quality selective emitter. As shown, the metal content of the RTWCG si〇x film can be further reduced by growth in other preferred growth solution formulations or by increasing the short-step process in dilute HF (aqueous solution). A preferred solution for growing a low metal RTWCG Si〇x film consists of 1 part by volume to 5 parts by volume of 34% H2SiF6 (aqueous solution), 1 part by volume to 4 parts by volume of 60% H2TiF6 (by), 1 part by volume to 4 10% by volume K3Fe(CN)6(*(4)) and} parts by volume to 5 parts by volume of 2〇g of Co(OH)2 dissolved in 1 liter of water. The optical properties of the obtained film are improved by cobalt. The XPS surface of the grown SiOx film for this preferred solution formulation is shown in (a). Only a trace amount of Fe is found by the high efficiency xps system. The low (5.4%) average reflectance of this SiOx film is shown in Figure 9 (J). The gradient index of the film shown is explained. The surface of the grown film was found using an ellipsometer. The refractive index is about 1.4. This value is in good agreement with the atomic chemical composition of the surface of the film, 31.5% of which is Shi Xi '62% is oxygen' and 5 6% is carbon. A small amount of nitrogen, fluorine, iron and other metals and The total non-metallic impurities account for 9% of the surface composition of the film. As is apparent from Fig. 9(b), the surface of the film is rich in tons. The surface of the film becomes SiOx/Si interface, and the composition of SiOx becomes gradually richer. Si〇x film 53 201251057 41245pif has a graded index of refraction which increases with depth from about 14 at the surface to about 3.5 at the SiOx/Si interface. This gradient index explains the low reflectivity of the film. The TXRT depth profile of the RTWCG SiOx film shows that the maximum concentration of metal impurities is at or near the surface of the film, possibly due to absorption from the growth solution. After growing the RTWCG film, after the water rinse, most of the surface metal contaminants can be removed by mild HF (aqueous solution). The XPS depth profile shows the atomic concentration of the main component of the SiOx film. Growth in a solution of the following composition: 3 parts by volume of H2SiF0 saturated with sulfur dioxide, 2 parts by volume of 60% and 2 parts by volume of 10 〇/〇K3Fe(CN)6 (aqueous solution). The obtained RTWCG Si〇x film was rinsed with water. After 113⁄4•, in the dilute hydrofluoric acid solution (1 part by volume of HF (concentrated solution) to 64 volumes, H2〇), the first name is engraved for 15 seconds. Finally, the sample is rinsed with DI water and dried with nitrogen. Low content of metal impurities. The atomic concentration dropped from about 1.3% to less than 1% of the instrument's detection limit, and similarly, the Ding from about 1% fell below the detection limit of the instrument. As an added benefit, mild The meal produces a textured SiOx film surface which reduces the AM 1.5 AWR from an initial value of 4.9% to 3.08%.

In one or more embodiments, the RTWCG solution is composed of 2 parts by volume of j^TiF6, 2 parts by volume of colloidal silica dioxide supersaturated with SiO2, and 1 part by volume of 1% by weight of K3Fe(CN)6 (aqueous solution). ). The smooth RTWCG SiOx film grown on a smooth n+/p c_si wafer has an extremely low AM1 5 AWR 4.78%. Referring to Figure 1, the solution produced a film similar to the film of Figure 10 (Si/Tens is gradually increasing with depth). The refractive index increases with depth from the surface of 135 to the surface of the SiQx/Si interface. It has been shown that the surface carbon of the film greatly enhances the chemical stability of the film and has no significant effect on the gradient index. It has been found that up to 1% of the relatively large surface metal impurities/density of the grown SiOx film is largely introduced by the commercial grade HjiF6 tantalum component, which is widely used on trees and other substrates at near room temperature (4) Iiid phase deposition (LPD) Si〇2 film. Attempts have been made to replace traditional HjiF6 source components with other & components. Figure 12 shows the xps depth profile of an RTWCG SiOx film grown using a growth solution consisting of 5 parts by volume of 70% NH4SiF6 (water), 2 parts by volume of 6% H2TiF6 (aqueous solution), 2 parts by volume of 10% K3Fe (CN) 6 (water record) and 3 body grams C. Pottery 2 is made in the 丨 升 · H-system

The grown film on the n+-Si substrate has Ti and R atomic concentrations below the xps detection limit. The 140 nm thick film has an AM1.5 AWR of 5.14% in the 400 nm to 1200 nm spectrum. Removed from the RTWCG SiOx growth solution formulation; the g source component increases the SiOx growth rate and has sufficient etch back depth to form an excellent quality selective emitter that maintains the integrity of the pre- and post-screening contact, and The metal impurity concentration of the obtained SiOx film is lowered. The following are two examples of larger quantities of test formulations. Figure 13 shows the XPS depth profile of a low metal impurity RTWCG SiOx film grown on a n+c_;si substrate using a solution of the following materials: 2 parts by volume 60% H2TiF6 (aqueous solution), 2 parts by volume 5% K3Fe(CN)6 (water) and 3 parts by volume. The above RTWCG solutions were tested for different component concentrations on a large number of n+p C-Si and mc_si small area tantalum solar cells. The high quality RTWCG Si〇x ArC/se battery structure obtained by 55 201251057 41245pif obtained good results. The amount of metal impurities contained in the growing sad SiOx film is reduced by the longer post-growth water rinse time. The atomic concentrations of Fe and Ti metal impurities are less than 0.1% and Si-Me or Me-Ο bonds are formed, as found by the XPS binding energy of oxygen, bismuth, titanium and iron peaks. The thickness of the etched back unmetallized emitter surface during RTWCG SiOx growth depends on the solution concentration, which can be varied to produce a good quality selective emitter while growing at an optimum thickness of 2 〇 x 8 ft. (film. For example Lu, the specific formulation consists of a relatively high concentration of ruthenium and K3Fe(CN) 6. The time to grow a 14 Å thick Si〇x ARC film on the smooth n+/p c-Si emitter surface is about 50 seconds. The solution produced a film with an AM1 5 AWR of 6.45/〇 and a depth of 〇18_〇 microns from the unmetallized emitter surface. Figure 14 shows the following on the n+c-Si substrate The xps depth profile of the components of the low-metal impurity RTWCGsi〇x film grown by a preferred growth solution (hereinafter referred to as ντ solution): 丨 volume parts to 3 parts by volume 6 〇〇 / 〇 HJiF6 (water) and 1 part by volume Up to 3 parts by volume of i gram _5 gram v 〇 dissolved in i liter (10) mascara) solution... The solution meets all the necessary requirements for open quality 5 RTWCG Si〇x ARC/SE and provides the highest efficiency gain - It is completely compatible with the metallization of the front and back surfaces. The concentration of metal miscellaneous f on the surface is lower than the instrument detection limit of the high resolution SOPS system of NASA Glerm. ° Further re-push by growth solutions such as those used in Figures 13 and 14. Mixed with 56 201251057 41245pif smooth growth of 120 nm - 150 nm thick Si〇x film. Its growth state AM1.5 AWR value 5% to 9% is reduced by another T〇 formation step. Smooth SiOx film for Visible radiation is highly transparent, especially towards the lower wavelength limit of the 4 〇〇 nano-1200 nm AM 1.5 solar spectrum. At the lower wavelength limit, all other standard monolayers (especially multilayer ARC) have the highest absorption. The example shows even for 240 nm. The absorption of visible light by thick SiOx films is also less than 丨%. To a large extent, the most expensive component of VT and related growth solutions is the 60% Hz TiFw aqueous solution> component. In addition, chemical batches have been observed. There are quality problems, especially if they are obtained from different suppliers. For economic and quality control reasons, this component is produced in the laboratory. 1〇% 5〇%hf per liter (aqueous solution) dissolves from 10g to 275g Ren Quantity of industrial grade Ti〇2 anatase. Add 2g to 50g V2〇5 directly to it, or first dissolve 2g to 5〇g of V2〇5 in 1〇% to 3〇% HC1 (aqueous solution) And a mixture of V2〇5/HCl (aqueous solution) and HzTOVHF (aqueous solution) is produced. Ultra-high purity water 'semiconductor grade HF and semiconductor grade Ηα are used. ^ SiOx growth solution containing a higher concentration of V+ ion component is gradually added The same growth rate produces a SiOx film. Table 1 shows the length of time necessary to simultaneously produce the RTWCG SiOx ARC/SE/TO cell structure on the n+_Si substrate. Depending on the amount of Ti 〇 2 source added to the constant amount of V 2 〇 5 component, the SiOx thickness of 13 〇 not 150 nm (see Table 1) needs to be no more than ^ seconds to about 15 seconds. In this experiment and in a number of other similar experiments, the si〇x thickness was estimated from the pre-established color code eGde) and/or by the Dekater distribution curve using the photoresist masked surface. 57 201251057 41245pif Ti02 concentration V2〇5 concentration 373 grams Ti02/liter 52 grams V2〇5/liter 298 grams Ti02/liter 52 grams V2〇5/liter 224 grams Ti02/liter 52 grams V,0 J well 149 Gram Ti02 / liter 52 grams V2 〇 5 / liter 75 grams Ti02 / liter 52 grams V2 〇 5 / liter

15 seconds Second ~ < 1 second < 1 second Table 1. Time required for growth of the metallic blue RTWCGSiOx film by several growth solutions. The concentration of the V2〇5 component was kept constant (52 g/L), while the concentration of the Ti02 anatase component varied. Since the difference in growth time between the leading part of the battery and the lagging part of the battery is small, controlling the ultra-high growth rate in Table 1 in an industrial environment is extremely challenging. In one or more embodiments, the solution should be adjusted to grow the ARC/SE/TO structure for at least 2 sec and optimally 25 seconds to minutes. Figure 15 shows the xps depth profile of the main components of the low impurity RTWCG SiOx film grown on the heavily doped phosphorus n+c_Si substrate. = Produce the company's ultra-low-cost growth solution (4) as follows: (4) Composition: ι volume to 3 parts by volume 1 〇 coupon / gong τ · η, Λ 0 / very see / soar Tl 〇 2 sharp Qin mine dissolved in 15% to medium solution and i parts by volume to = 2 = solution in muscle HC1 (_). The time required for this solution is 13 〇 ^ nanometer thick RTWCGSl 〇 X film is 20 seconds - 30 higher growth rate solution (such as Figure 15 growth rate slit is more cut, even faster than the lower cause, faster growth The solution produces a surface refractive index, which is the same as that of the film at the interface of 58 201251057 41245pif /Si. The orientation of the Si〇x/Si junction is the same as f 2 t The oxygen atom concentration decreases with the depth of Si〇X. Although the reflectivity of this Ertian 3 Si SlOx film is higher than that of the Si〇x film in Figure 1但, its 鸠1.5 AWR is still much lower than 1〇%. These second-rich Si〇x films are more transparent in the visible spectrum and much more transparent than multilayer ARC compared to any other single layer of the current technology. Producing a high quality 150W thick RTWCGSiOx film The growth rate low-cost solution is prepared by dissolving a mono-metal oxide, a metal chloride or a metal vapor component in various concentrations of HF aqueous solution. The transition metal halogen oxide described herein is a preferred metal. Oxide component. SiOx growth rate increases with the concentration of metal oxide components Increased, and at a higher degree, increases as the concentration of HF used increases. The pentoxide bismuth solution dissolved in HF (aqueous solution) is a growth solution produced by dissolving the metal oxide component in yeah. The length of time required to grow 13 〇 nanometer to 15 = = RTWCG on the heavily doped 夕 夕 substrate is the curve dissolved in the 50% HF_ regulatory amount. The growth rate of Si0x is greater than the concentration of V2 〇 5 And to a lesser extent, depending on the dilution of the HF aqueous solution. Different amounts of v2〇5 solution are dissolved in different y (aqueous) concentrations. On similar heavily doped n+_si substrates, different growth solutions are used. G0 nanometer thick film was applied. The time required to form strontium was measured' and the results were shown in Table 2. As can be seen, the growth time of a constant amount of solution of gradually increasing desertification was only less than $. The solution of V2〇5 dissolved in the same concentration of HF t is also significantly reduced by the growth time of 59 201251057 41245pif. The concentration of ▽2〇5 is less than 7.5g ν9Ος/gong and HF, and the Si produces a sharp atomic concentration of 0.1% of Si0x film.诸=表2中生^容=二容: Producing metal hunger The atomic concentration is gradually increased by 'exceeding by growing 14G nanometer thick Si0x film within 1G seconds. The quality control problem with the growth rate solution is preferably less than 7.5g v2〇5/liter HF (aqueous solution) ), and preferably 1 ^ '10% to 30%. / Exhibition 1 horse per liter HF V2 〇 5 gram 10% HF (aqueous solution) 20% HF (aqueous solution) 3〇% HF~ (aqueous solution) 40% HF (Secondary bubble, 〇 public see V2 〇 5 / liter HP 185 seconds 180 seconds 180 seconds πη ίΊ '~ 3.0 grams V2 〇 5 / liter hf 54 seconds 51 seconds 45 seconds 44 ΰ '~~ 12 $>1' 4.5 Gram V2 〇s / liter HF 23 seconds 22 seconds 26 seconds 6.0 grams V2 〇 5 / liters hf 16 seconds 14 seconds ~ ~ 133⁄4 ~ 7.5 grams V205 / liters hf 16 seconds 11 seconds 11 seconds 8 hours L, 9.0 grams V205 / public And HF 10.5 gram V2 〇 5 / 5: fFHF 16 seconds ~ 16 seconds 8 seconds ~ ~ 7 ^ ~ ~ 8 seconds Ο 5 seconds [4 seconds 12.0 grams V205 / liter HF 12 seconds 5 seconds 5 # ~ ~ Table 2. Use The time required for the growth of the metal blue rtwcG SiOx film with different amounts of the catalyst V2〇5 dissolved in different concentrated HF (aqueous solution). Figure Π (a) shows the xps depth profile of the main components of the low-metal impurity RTWCG SiOx film grown from a V2O5/50% HF (aqueous) growth solution. In about 30 seconds, about 140 nm thick is grown on the n+ c-Si substrate. 201251057 41245 pif Membrane As seen, this rapidly growing Si〇x film is rich in yttrium and has a gradient 矽 and oxygen depth profile. The vanadium peak is shown at background level in Figure 17(b) and is therefore below the 1% instrument detection limit of the xps system. As is well known in the art, XPS, AES, and other surface analysis techniques cannot speculate elements (such as hydrogen) having a low atomic sequence. However, SIMS can be successfully used to determine the amount of hydrogen and other impurities present in the RTWCG SiOx film. Figure 18 shows the SIMS atomic concentration depth profile of major non-metallic impurities found in a rapidly growing Si-rich SiOx film grown in a solution similar to the solution used in Figure 16. The membrane has a relatively high carbon atom concentration, a relatively low hydrogen atom concentration, and even a lower gas and nitrogen atom concentration. The carbon atom concentration of the RTWCG SiOx film (Fig. 18) is significantly higher than the atomic concentration of the low temperature SiOx deposition known in the art. For example, the carbon atom concentration ratio of the RJWCG SiOx film is "at the atomic layer deposition (ADL)" which is known in the art as "the ultra-low temperature Si〇2 using the amine-based mash*" at a temperature of 250 °C. Deposition (Extra Low-temperature

Si〇2 Deposition Using Aminosilanes) (I. Suzuki et al.) has a carbon atom concentration as high as two orders of magnitude. However, the atomic concentrations of hydrogen and nitrogen in the RTWCG SiOx and SiO 2 ADL films are almost identical. Since RTWCG SiOx is a room temperature process, the atomic concentration of hydrogen gradually decreases with depth toward the SiOx/Si interface. This indicates that the hydrogen passivation known in the art is minimal' at the SiOx/Si interface and is clearly not present in the core body. However, the ι_ν feature 201251057 41245pif of the small-area MOS device described herein does not heat the substrate at a relatively low temperature of about 2〇〇t: after the growth of the RTWCG SiOx, and some of the hydrogen in the Si〇x film makes the Si0x/Si5 The surface is fully passivated. Heating the SiOx film at higher temperatures can even passivate some of the defects in the ruthenium body. Experiments conducted on a large number of small-area solar cells show the cost and electrical and dielectric properties of RTWCG enriched in other Si〇x films (such as the films in Figures 15 and 17) in ultra-low cost, high growth rate RTWCG growth solutions. Provide a good compromise between features. It is superior to the formation of a good quality RTWa} Si〇x ARC/S E/T0 crystalline germanium solar cell structure on a lower cost solar grade c-Si, mc-Si or polycrystalline germanium substrate. Although the resulting film has a slightly higher reflectance, the SiOx film grown from these solutions has a low metal concentration and is compatible with the metallization present on the battery. Similar to other rTWcg SiOx growth baths, excellent quality SE and TO efficiency enhancement features are produced simultaneously. In addition to the Fe, Ti, V and Co ions, there are various other Me+n/Me+(n+m) ions in the RTWCG SiOx solution for solar cell applications, where η is 0 to 4 and m is 1 To 4. Specific examples include, but are not limited to, metal ions such as Ti, Co, V, Cr, Fe, Ni, Cu, Y, Sr, Ce, Ba, Zr, Nb, Ru, Rh, and Pd. However, some of these ions only weakly catalyze the growth of SiOx, making it impractical for a large number of 1% battery fabrication. For example, the fastest Nb:HF growth solution formulation consumed a rTwcg Si〇x ARC film of the necessary thickness for 40 minutes. A compound containing a metal group (for example, K3Fe(CN)6, V205, Ti〇2 anatase, Co(OH)2, etc.) is dissolved in an acidic solution to produce a film which promotes SiOx-based film growth while producing excellent quality. Sex emitter 62 201251057 41245pif = ^ formulation. Preferred solutions contain various concentrations of Ηρ(_, and may have a combination of other acids such as Hcl, H2S〇4, and HN〇3. The components are used for (10) the emitter, while other acids may be dissolved. Some of the metal ion components that are not easily/solved in HF t are required. The Group IV Sn4+ and pb4+ ions dissolved in HF (tree) are relatively y RTWCGSi0x catalysts. In a preferred embodiment of the present invention, The Pb-based RTWCG SiOX growth solution was prepared by dissolving 3 g of _7·5 g of pb〇2 per metric metric metric solution. As with all pots, the solution was dissolved, as shown in Figure 19, catalyzed by Si〇x solution. Concentration. i + Growth of a very uniform metal (130 nm] 50 nm thick on a heavily doped (four) ruthenium substrate in 80 seconds. The Si〇x layer of low-cost qing (7) (10) growth solution can be obtained by i liter 50 % HF (aqueous solution) is dissolved in 45 psi Pb 〇2. The obtained film contains only traces (if any) of pb atoms and has good electronic/optical properties. It can be obtained by _ _5 〇 % HF (water immersion concentration) To adjust the thickness of the emitter etched back by the solution = raw good quality selective emitter. There are a variety of co-catalysts, which can Increasing the growth rate without significantly increasing the metal of the alloy. Examples are compounds based on Ti, Co, V and Fe. 丨 ' contains several oxidizing ions (including but not limited to Μη〇4·&& 〇 2 ^ HF aqueous solution can also be used as a homogenization of RTWCG Si〇x film growth to develop the most effective and lowest cost and environmentally friendly RTWcg raw liquid, which has successfully used non-metallic catalysts in n+/p c_Si and mc_si tables: 63 201251057 417.5pif growth of SlOx. Acidic aqueous solution containing VII gas and ion-filling can be used in RTWCGSiOx growth solution.> RTyCG SiOx growth solution is prepared by dissolving pentoxide (12 〇5) in various / HF ( Prepared in water-soluble phantom. The solution can grow the desired SiOx ARC thickness in no more than 5 sec. These growth solutions and standard crystal n+/p

Si Tai battery shovel screen printing metallization compatible. The resulting good quality Si〇x film has a low reflectivity, sufficiently passivates the surface of the emitter, and produces a good quality selective emitter. All of the Wei-containing compounds that can be used by us are dissolved: the Si〇x film is grown when the HF-based acidic solution is used, and the moth-containing compound includes, but is not limited to, iodic acid (HI〇3), potassium iodide (KI). If the battery is completely immersed for more than 1 minute, the screen printing A1 paste, sintering temperature and time can be used, and the I2〇^hf growth solution can react with Al-based screen printing to degrade it. If the solar cell with A1 contact is completely immersed in the growth phase of the base (4), a high growth rate formulation must be tested. Of course, other methods than complete immersion can be used to avoid unsuitable reactions with post-A1 contact. The battery can float on the growth solution with the emitter facing down, or the film of the growth solution can be applied only to the emitter surface. In one experiment, RTWCG Si〇x growth solution containing different amounts of l2〇5 dissolved in different concentrations of HF (aqueous solution) was formulated. The concentration of LQs was in the range of 0.3 g/L-2 g/L, and HF ( The ww concentration is in the range of 10 〇 / -50%. It has been determined that the growth rate on the surface of the heavily doped n + 矽 is mainly the concentration of the listener (10), and to a lesser extent depends on the concentration of HF used. 2 gram LOW liters 5 〇% HF (aqueous solution) concentration in 64 201251057 41245pif in about 15 seconds produces 130 nm to 丨 杳 杳 I Ο /1 八 44 · irw not water thick metal blue oxide. 0.3

SiOx thickness. • Degrees within 5 minutes of growth of the same composition of the growth solution components of the burdock 1205 and KI, there is a relatively large number of two: f dew 'except m 〇 3, good quality RTWCG Si0x material f can be used to produce modified K film For solar cells and other should be SU4, PI3, P2l4, Til4, Vl3, col2, bribe 2, Asi3, _, Qing, 13⁄4, Qing and call. According to the present invention, various combinations of one or more of the euchemical containing materials in HF will push or co-catalyze the siox film and produce Rtwcg Si〇x arc/se/ on the surface of H+-S! or P+-Sl. The efficiency enhancement characteristics of the t〇 cell structure have also been demonstrated to increase the RTWCG® quality grown on non- & substrates when added to several SiOx growth solutions described herein. For example, 'If A% is Adding to the VT RTWCG growth solution in Figure 14, the passivation ability of the RTWCG Ga-As-Ο thin film dielectric layer grown on the p_GaAs and n GaAs substrates is significantly improved. Compared with the conventional crystalline solar cell design, The efficiency gain obtained from the RTWCG Si〇x ARC/SE/T0 cell structure is attributed to significantly lower light, resistance and composite damage. The reflectivity and absorption of the RTWCG SiOx film is very low. SiOx film has good passivation. , producing a highly efficient selective emitter (SE)' and inherently lower resistive losses due to the smooth se/textured SiOx concept. The environmentally friendly rjWCG SiOx method and process design as described herein is designed to be 65 201251057 41245pif can be used Screen printing metal Manufacturing low-cost, high-efficiency, crystalline solar cells. The RTWCG SiOx ARC/SE/TO process is simple and controllable, and can be operated in less than 1 minute: i. cleaning the tantalum and metallized surface on the spot; ii. Refractive index SiOx anti-reflective coating (ARC) with an AM1.5 average weighted reflectance (AWR) of 5%-9% on a fabricated n+p Si substrate, and optimized for RTWCG SiOxARC/TO cells The structural AM 1.5 AWR is 3°/. to 5%; iii. SiOx makes the dangling bond at the SiOx/emitter interface extremely sufficiently passivated; iv. Produces good edge separation if using the shadow diffusion described herein, V Using a standard screen printing metallization layer as a mask to etch back only the active area of the emitter, thereby producing an excellent quality SE that is compatible with large scale, low cost manufacturing; and vi. producing optionally textured SiOx The above and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments of the present invention. Example 1 - Ultra low cost RTWCG SiOX solution. Use dilution on the spot The material produces an ultra-low cost RTWCG Si〇x aqueous solution formulation which not only significantly reduces the cost of HAiF6, HJiF6 and other solution components, but also optimizes the quality control of the manufacturer. 66 201251057 41245pif a preferred embodiment of the invention In one example, the rtwcg Si〇x growth solution formulation does not require any other Shishi source present in the Xiji source, such as HjiF6 or a prior art rtwCG SiOx growth solution formulation. The solution can be diluted to a desired concentration of 1% to 40% using ACS grade or higher HFouw and ultra high purity water. You can also use ACS or better grade Ηα (* material) and dilute to the desired concentration. The RTWCG SiOx growth solution also contains a non-invasive aqueous component 'additional oligo (mother 1 liter HF (material 1 gram ι gram) single preferred catalyst or a combination of preferred catalysts. Preferred catalyst has ACS grade Or better grades, and examples include, but are not limited to: bismuth titanium (anatase), vanadium pentoxide, iodine pentoxide, potassium ferricyanide, dioxins, and optionally oxidized drills or Cerium oxide. Two samples were cut from the same FZ c-Si η+/ρ diffusion wafer. One sample was completely immersed in an ultra low cost high growth rate vanadium-based Si〇x growth solution for 10 seconds' and the second sample was dipped. The human ultra-low cost and high growth rate is based on the hunger SiOx growth solution for 40 seconds. After removing the obtained Si〇x film by buffered HF (concentrated solution) etching solution, the net majority carrier concentration depth distribution of the remaining emitter is obtained. The curved sample of this experiment was made according to the book, and the test was performed by Socon Laboratories (s〇lec (10) Laboratories, Inc.). The distribution curve of the majority carrier concentration was obtained by the distributed resistance analysis method. Thin layer The value is obtained by four-pin measurement. As can be seen in Table 3, after 1 〇 Si〇x growth time, the sheet resistance of the emitter is increased from its initial 43 ohm/square unit to about ιΐ4 = square unit. And after 40 seconds of Si0x growth time, the emission resistance is significantly higher, about 695 ohms/square unit. 曰67 201251057 41245pif RTWCG SiOx growth time (seconds) 0 10 20 30 40 an average 4PP layer resistance (ohm/square unit 43.2 114.4 260 406.8 695 Table 3. Average four-point probe sheet resistance of n+/p c-Si samples in Figure 20 over several SiOx growth times. Example 2 - Surface cleaning and screen printing metallization Compatibility All small-area, high-efficiency batteries are manufactured in clean room facilities' but most current state-of-the-art solar cell manufacturing is carried out in non-clean room environments. Non-clean room environments are not good for introducing impurities into the cell surface. The effect of the battery affects the efficiency of the battery. The RTWCG SiOx ARC/SE process, which is the final manufacturing step, regains the efficiency lost due to the non-clean room environment by cleaning the active surface and the screen front grid. In addition, as in the following examples It can be seen that on-site cleaning reduces the efficiency dispersion between the same batch and the batch. Figure 21 (a) shows a Nomsky diagram of a c_si solar cell with a pyramidal textured front surface, the front surface It has a higher peak-to-valley aspect ratio of 25 microns. As can be seen in Figure 21 (b), the RTWCGSiOx process is fully compatible with screen printing metallization. Due to the high aspect ratio of the textured surface (see Figure 21 (c)), portions of the grid lines are suspended between the pyramids and cannot contact the bottom of the valley. The mechanical and electrical integrity of the precontact was examined on a small area of large coated RTWCG SiOx and large area c_si, cast mc-Si and polycrystalline 矽n+/p solar cells. It has been found that the preferred RTWCG SiOx process does not adversely affect screen printing contact. For example, the series resistance of almost all cells (series 68 201251057 41245 pif resistance 'Rs) is reduced by up to 40% after RTWCg SiOx coating. Lower Rs contributes to significant fill factor (FF) and improved efficiency. An increase in Pmax of more than 1% after RTWCG growth cannot be explained by only a reduction in optical loss or an increase in the intrinsic blue light response. One explanation is that the RTWCG growth solution cleans the surface of the cell on the spot immediately before growing SiOx. This is particularly advantageous for batteries having poor surface conditions due to various contaminants that reduce the open circuit voltage (v〇c) and the short circuit current (Isc). In addition, some metallization-related conditions known to reduce the fill factor (FF) can be mitigated by contact with the cleaning crucible. It is well known in the art that during the calcination step, silver based oxides are based on Ag-based screen printing prior to contact and conventional bus-based bars after Ag. Contamination reduces the conductivity of the busbar and increases the contact resistance between the busbar and the interconnect material. As can be seen in Figure 21(b), the RTWCG sap liquid does not cover the metallization layer with SiOx and actually cleans the oxide contamination, as shown by the oxidized RTWCG pre-metallization layer in Figure 21 (a) and Figure 21 ( b) The clean silver is confirmed by the metallization layer after growth. Long-term durability tests were performed on batteries that were barely coated and coated with SiOx from large industrial c_si and mc_Si cells cut in the same industry. These batteries are kept in the laboratory for up to 11 miles. The test demonstrates that SiOx grows after exposure to aging based on Ag and maintains its silver color, integrity and availability. The calcined Ag metallized surface becomes oxidized and more difficult to weld after exposure to the same laboratory environment for an equal length of time. The preferred short RTWCG SiOx ARC/SE/(TO) process steps are compatible with conventional A1-based screen printing contacts. Some RTWcg si〇x growth solutions 69 201251057 41245pif liquid components (such as Ηθ〇4) can make the contact thickness of A1 slightly thinner or make its color change from light gray to dark gray, and should be avoided. When the battery is completely immersed in the growth solution, a small amount of A1 is contacted and dissolved. It has been shown that the composition and quality of SiOx 不会 are not so dissolved in A1 and wheat is turned on, even if the solution is repeatedly used. The presence of A1 in the RTWCG film grown in the re-used growth solution cannot be detected by XPS or AES analysis. The small area of the solar cell completely immersed in the re-used growth solution is as effective as the immersion in the fresh solution. Almost all RTWCG SiOx growth solution formulations exhibit full chemical passivation of the A1-based screen printing contact, which is clearly demonstrated by some long-term durability tests (including the long-term tests described above) in which small area cells are stored in chemical experiments. About U years in the room environment. After a few years, it can be seen that the contact of A1 of some bare cells degenerates into a powdery appearance. The A1 postcontact of the coated Si〇x battery maintains its chemical, mechanical and electrical integrity.

EXAMPLES 3-RTWCG SiOx ARC Solar cells are mostly determined by their reflectivity and are therefore determined by their ability to retain, rather than reflect, solar energy back to the outside world. Many solar cell manufacturers still use titanium dioxide (TiOx) as a single layer antireflection coating (SLARC), which is usually sprayed onto a battery and then baked to remove the solvent. The main drawback of the relatively low cost Ti〇x ARC is its relatively large (about 15%) AMI.5 AWR. In addition, the TiOx film covers the front surface metallization layer and thus needs to be removed from the front busbar so that the cells can be interconnected into wires during manufacture of the solar cell module.

Nitroxide (SiNx) ARC is the preferred method because its AM丨5 AWR 201251057 41245pif is about 12%. SiNx is relatively high by chemical vapor deposition (CVD) or plasma enhanced CVD (PECVD). Deposition in air or vacuum at low temperatures. SiNx deposition is quite expensive for manufacturing, maintenance, and especially capital equipment. However, in contrast to Ti〇2 ARC, the screen front metallization paste can be fired through the SiNx film, thereby removing another relatively low throughput process step, i.e., removing the film from the front busbar surface. To further reduce the relatively high reflectivity of single layer ARC (SLARC) films, surface texturing and double layer ARC (d〇uble layer ARC 'DLARC) or triple layer ARC (triple layer ARC, TLARC) can be used. . Due to its relatively high cost, DLARC or TLARC has not been used in industry. Since SiNx ARC is becoming the industry standard for c_Si solar cells, it is instructive to compare the optical and electrical properties of CVD SiNx and RTWCG SiOx films. Figure 22 is a reflectance curve obtained by an independent laboratory for its optimal siNxARC and two unoptimized RTWCG SiOx ARCs. For the optimized SiNx film, the AM1.5 AWR in the 400 nm-1200 nm wavelength range is 12.1%, and for two unoptimized si〇x films, the AMI is in the 400 nm-1200 nm wavelength range. 5 AWR is 8.3% and 8.5% ° The large reflectance of the CVD SiNx film is mainly due to the significant reflectance improvement of the blue region of the visible spectrum. The AM 15 mean weighted reflectance (AWR) values provided herein are known from the art from R Hulstrom, R. Bird, and C. Riordan. "Spectral solar irradiance data sets for selected terrestrial conditions", 乂71 201251057 41245pif 縻云龙(5b/arCWA〇, Vol. 15(4), pp. 365-391 , 1985 AM1.5 Spectral Irradiance Data (for 〗, 〇〇〇 / / 平方 平方 normalized calculation. Usually 'the AM1.5 AWR of the unoptimized Si〇x ARC produced by the RTWCG process In the range of 6°/〇-9%, it is lower than the AM1.5 AWR of any other SLARC film on the surface of the smooth stone. For example, Figure 23 shows the n+/p Si bend and tail type diffusion structure (such as Figure 3) "The group of RTWCG Si〇x reflectance curves of the grown SiOx film. The "PR4-y" notation indicates the plane RTWCGSiOxARC grown on the n+_p4吋 polished single crystal germanium (c_si) wafer, Where "y" is the Si〇x growth time (in seconds). Table 4 shows the same use as in Figure 12. The growth of the solution on four different substrate groups, RTWCG Si〇X2 AM1 5 awr as a function of growth time. The first column contains the data of the group of Si〇x films in Figure 23. AWR number of 帛二财The SiQx group is grown on the tSin+/P diffusion structure coated with the pyramid. The data of the Si〇x film grown on the cast mc_Si mc-Si (band) n+/p structure are respectively in the third block. It can be seen from Table 4 that the coating of the n+/p(10)Si diffusion structure of the coated pyramid is 32.68%, and the n+/p-diffusion structure with a smooth surface=, AWR* 33.63%. The growth is suitable for thickness (7 〇 and (10) seconds

After Si〇x ARC/SE, the surface with a smooth surface is actually lower than the surface of the coated pyramid. Because the resistive losses of the ", 4 emitters are lower than the physico-chemical emitters, the pyramids 72 201251057 41245pif The higher resistive losses of the physicochemical emitters are especially related to the high lateral resistance, so the texture is used to texture the surface (such as Figure 21(4) is suitable for RTWCG SiOx ARC/SE process RTWCG SiOx growth time (seconds) c-Si smooth surface (see Figure 20) c-Si coated pyramid surface (see Figure 18) mc-Si (casting) wafer mc -Si (strip) wafer

Table 4. AM 1·5 average weighted reflectance (AWR) of the RTWCG SiOx film grown on crystalline n+/p c_si, cast mc_Si, and polycrystalline germanium wafers in the wavelength range of 400 nm to 1200 nm with SiOx growth time Variety. The ribbon mc-Si substrate has the highest SiOx growth rate, which produces a SiOx film with a minimum AWR of 6.35%. For reasons not fully understood, the SiOx growth rate on the cast n+/p mc-Si diffusion wafer is lower, which explains the higher AMI.5 AWR for this particular diffusion wafer group. An ami.5 AWR of less than 1% was obtained after a relatively long SiOx growth time of 100 seconds (Table 4). Subsequent experiments were carried out using a higher growth rate si〇x solution formulation on phase 73 201251057 41245pif with a cast mc-Si diffusion substrate. A suitable Si〇x film thickness was obtained in 45 seconds and produced a much lower AMI.5 AWR 6.32%. As shown herein, certain RTWCG formulations having a high Si〇x growth rate of up to 500 nm/min grow the textured ARC SiOx film in less than one minute while producing excellent quality SE and surface passivation. The resulting cell has a low AMI.5 AWR and produces all RTWCG SiOx ARC/SE/TO enhancement features in a single wet chemical process step. The lowest AM15 AWR value was obtained for SiOx films grown in a high growth rate RTWCG solution with a textured refractive index on the textured SiOx surface. The reflectance curve of the textured RTWCG SiOx film grown on a smooth n+/p c_Si substrate is shown in FIG. After si〇x growth, τ〇_ι was immersed in 1% HF (aq) for 15 seconds and an AM1.5 AWR value of 3.09% was produced. The AM1.5 AWR is about 4.5% of the SiOx film TO-2 and TO-3 are grown films. The AWR values for these low cost films are as low or lower than the AWR values of the three layer ARCs known in the art that are too costly to limit. Example 4 - RTWCG SiOx Film Transparency To reduce the useful light absorption of the ARC film, it must be as transparent as possible in the wavelength range of 300 nm to 1200 nm. Compared to rTWCg si〇x ARC, conventional SLARC has a large absorption of visible light, especially in the blue portion of the spectrum. Although generally not explained, light absorption is particularly pronounced in the case of thicker layers. The term "transparent layer" refers to a layer having a sufficiently low extinction coefficient value (k). For example, if k is less than 0.10 in the visible light region of the available AM1.5 spectrum, the layer is substantially not at a thickness of about four-quarters of the wavelength of visible light. 201251057 41245pif absorption visible H-light coefficient (1) is equivalent to low The absorption (4) (for example, less than 〇) corresponds to less than 1% of α) because α = 4 π k / λ. If k is high = (U 'Jt is the case of money Si 〇 2, the film is highly absorbing light, so that the film having the y y is not suitable for the solar cell ARC. ^ Figure 25 (a) shows the current technology The refractive index and extinction coefficient of a transparent RTWCGSiOx thick film (about 2 〇 8 nm) grown using a high growth rate solution (such as in Fig. 14). The extinction coefficient in the wavelength range of 働 nanometer nanometer is lower than 0·02, The film is made suitable for the car = thick film necessary to produce a textured surface. The rich cut Si〇x off matte growth, such as the growth solution in Figure 15 on the Mi substrate, is slightly higher, slightly below (10) 4 ( See Figure 25(b)). These RTWCGARCs are exactly as good as competitive ARC (such as optimized SiNx SLAR (k > 0.06), TiOx SLAR (k>G.G8) or known double Layer and three-layer ARC (k>Q)). Because the RTWCG Si〇x film is highly transparent and its reflectivity decreases with thickness, the small change in the thickness of SlX is too critical compared to the conventional ARC*. The thickness of the gamma film is determined by the depth of the reverberation pole during the growth process. Example 5 RTWCG Selective Emitter Industry Appropriate Choice Lin has been very entangled, but has not yet obtained a cost-effective method to achieve this efficiency increase. Good optical performance is important, but the preferred RTWc G si 〇χ growth process also produces a highly cost-effective good quality selective emitter ( SE) For screen printing contacts with reasonable low contact resistance, it is necessary to use re-diffusion and impurity. This is a large number of surface defects and reduces battery efficiency. 75 201251057 41245pif However, for RTWCG which only etches back the surface of the unmetallized emitter Process, this is not a problem. The emitter region under the contact grid remains undisturbed and re-diffused. In other words, the gate metal acts as a mask for the unmetallized surface of the etched emitter. Because the RTWCGSiOX film is extremely fast (<1 Minutes of growth, so no damage to the grid. The contact resistance is about 1.0X1CT4 ohm-cm ^ 2 and the sheet resistance is higher than 100 ohm / square unit and the surface doping amount is about lxl 〇 i9 / cubic centimeter Printing contact is a key requirement for the manufacture of effective solar cells. The use of thicker, heavier emitters makes the latitude during the metallization step much greater It makes it possible to use a more transparent and conductive front gate metallization material, which reduces the resistance loss and improves the yield. The amount of doping under the contact metallization layer before screen printing produces less than 1.0x1 〇_3 ohm-square. Acceptable low contact resistance and small density junction shunt path. However, this type of emitter has a low open circuit voltage due to poor blue response and poor short circuit current. To simulate the cell front gate line, smooth n+/ A narrow photoresist line is created on the p c_Si bend and the tail-type diffused emitter surface (such as in Figure 3). Since the RTWCG growth solution does not react with the photoresist, the si〇x film grows only on the bare portion of the emitter. The surface profile measurement in Figure 26 was obtained after removal of the photoresist and SiOx film, and it exhibited the depth of the emitter etched back by the growth solution. In a preferred embodiment of one or more embodiments, to obtain a well-designed, mother-fold and tail-type diffusion profile, for a RTWCG SiOx ARC/SE cell structure, the growth solution should have an etched emitter of 〇2 μm, For the RTWCG SiOx ARC/SE/TO battery structure, the etch back should be slightly larger than 〇25 76 201251057 41245pif micron. The optimum bend and tail type diffusion profile of the present invention has a bend at about G.1 fresh under the emitter surface (see Figure 3). (4) Folding means the so-called "non-inductive layer" or an area with a large defect density. Since the rtwcg growth solution removes 0.2 (four) or more than 〇 2 μm of the emitter unmetallized surface, the sensitized layer is etched back on the active region rather than from the front contact. Since SE is formed while SiOx ARC is growing. This novel singularity has been produced in a large number of manufacturing single-units and polycrystalline solar cells from various solar cell manufacturers. In the following simple display, the excellent quality RTWcx} se is currently RTWCG Si〇x ARC The /SE/T0 technology has a single 'one biggest reason for the efficiency gain of the conventional battery technology of the current technology SE compared to the absence of se or effective. The RTWCG SiOx growth solution returns to the heavily damaged emitter layer to a depth depending on the formulation used and the length of growth time. In one or more of the preferred embodiments of the embodiment, the above preferred growth solution (4) is formulated to grow 130-220 nm thick S1 X XC and back to 2 Q microns · Q 25 microns of unmetallized emitter. The initial junction depth of the approximate optimal bend and tail-type phosphorus diffusion is about 〇·55 μm 'bend at the depth of OW m, and the net majority carrier concentration on the surface is 5xl 〇 2Q/cm ^ 3 to 8xl 〇 2 〇/cubic centimeters. Health

Long-dissolved, _ emitter line surface after _ unmetallized surface inversion of 8x10 / cubic centimeter to lxl 〇 i9 / cubic centimeter, which can ensure a good blue light 仍 while still producing a fill factor greater than 0.78. S Figure 27 shows two n+p c_si and one thin film polysilicon diffusion structure. 77 201251057 41245pif Thin layer resistance curve as a function of RTWCG Si〇X growth time. The re-diffused C-Si smooth emitter structure has an initial sheet resistance of about 12 ohms per square unit, similar to the bend and tail type diffusion of Figure 3, and a depth of about 107 microns. As can be inferred from the low initial sheet resistance, this diffusion structure has a depth that is thicker than the most joint junction depth and has an extremely deep bend of 0.2 microns. After 1 second of RTWCG SiOx growth time, the remaining sheet resistance is still about 4 〇 / square unit. The internal and external quantum efficiency curves of small-area cells fabricated on these diffusion structures before and after the formation of RTWCG SiOx ARC/SE are prepared. As shown herein, although the blue response after growth is increased as much as it corresponds to an ISC increase of up to 52% and a Pmax increase of 54%, the blue light response is far from optimal. After a 60 second SiOx growth time, the sheet resistance of the c-Si structure of the deep junction coated pyramid increased from about 26 ohms per square unit to about 85. . Euro/square unit' and increased to about ^ ohms per square unit after 7 seconds of growth time. This is in sharp agreement with the increased blue-light response of the average Pmax of the small batch large cell fabricated using the same n+/p diffusion structure. Fig. 27 shows that the rate of increase in sheet resistance of the polycrystalline 矽n+/ρ diffusion structure is faster than that of the Si battery. 6 〇 && 〇χ growth time, the sheet resistance from about 2 〇 / / square unit of the initial value before growth reached about 157 square units. The accelerated sheet resistance improvement and observable with respect to the Cz cji or cast mc_Si substrate can be observed for the polycrystalline substrate.臈” Polycrystalline 矽n+/p cell structure accelerates Si0x growth rate. 1. For the same growth time, the faster growth rate will return to the unmetallized emitter in a larger process, resulting in a larger sheet resistance. Value of the 78 201251057 41245pif battery structure. There is a positive correlation between the concentration of oxygen in the crystallization wafer and the growth rate of the RTWCG Si〇X film; the larger the oxygen content, the greater the growth rate. As shown in this article, the significant increase in battery power of the RTWCGSiOXARC/SE process is largely due to the increased Blu-ray response. It is worth mentioning that all c-Si, cast mc-Si and polycrystalline large-area solar cells for the incremental optimization of RTWCGSiOxARC and SE are manufactured batteries with different emitter depths. Some are too deep, some have shallow. However, these batteries are not optimal for the RTWCG SiOX ARC/SE battery structure, not to mention the enhanced efficiency RTWCG SiOX ARC/SE/TO battery structure. Except for a limited number of c_Si cells (ie, Figure 3) fabricated on an optimized diffusion structure, as described in more detail in the following sections, large-area cells do not contain intentionally designed bend and tail-type emitter diffusion profiles. curve. Nonetheless, based on the manufacturer's AM1.5 IV data, the RTWCGSiOXARC/SE cell structure produced on a small batch (12) CZ c-Si 6吋 fabricated cell has an average Pmax increase of 56% and an average AM1 of 15.6%. 5 efficiency, of which the highest AM 1.5 efficiency is 16.4%. Based on the manufacturer's AM1.5 I-V data, nine 6-inch "thin film" polysilicon 矽n+/p fabricated solar cells have an average Pmax increase of 47.7% after the RTWCG SiOx ARC/SE cell structure is produced. This represents an absolute gain estimate of 9.4% compared to conventional batteries using SiNxARC, as calculated from data in the art, which shows that for small area cells, the maximum Pmax (efficiency) increases after coating SiNx. 39% and up to 35% for manufacturing batteries. The deep-emitter battery Pmax is compared to the use of any 79 201251057 41245pif

The unbalanced large increase in pmax of other ARCs and conventional batteries that do not yet have SE is due to the significant increase in the blue response of the RTWCG SiOX ARC/SE battery structure. This can be clearly demonstrated by the external quantum efficiency curve performed on the battery as shown in the subsequent section. Even for batteries that do not have optimal bend and tail diffusion, but have a sufficiently thick emitter and an initial net majority donor concentration that is sufficiently high at the emitter surface, SE is in RTWCG SiOX ARC/SE/ (TO) cell structure The effect is also significantly higher than other SE schemes known in the art. In a preferred embodiment of one or more embodiments, the efficiency enhanced RTWCG SiOX ARC/SE/(TO) cell structure requires an initial sheet resistance of 20 ohms per square unit _ 25 ohms per square unit. After Si0x is grown, the sheet resistance of the emitter must be 11 〇/square unit _丨2〇 ohm/square unit. When the sheet resistance is 120 ohms/square unit to 15 ohms/square unit, the FF gradually decreases and when the sheet resistance exceeds 150 ohms/square unit, the ρρ accelerates down. Example 6 • Textured rTwCG SiOx Film Surface texture of the emitter is commonly used in conventional n+/p crystallization solar cell designs to reduce optical loss by reducing reflection from light exiting the surface. Surface texturing, which is primarily used for c-Si solar cells, is obtained by chemical-side wafers prior to diffusion. For example, a surface covered by a "random pyramid" is produced along the (ιη) plane preferential side of the (100) stone substrate. Experience has shown that this pyramid can have a peak height of 25 microns (see Figure 21(e)) that can be broken during diffusion to remove the diffusion during the break. The screen printing process can then generate a shunt path control' shunt path that greatly reduces shunt resistance and shunt voltage, all of which can significantly reduce battery efficiency. At 201251057 41245pif, despite the known mechanical difficulties known in the art and the known difficulties of fabricating good quality textured mc-Si substrates, most laboratory and battery manufacturers still use some form of textured emitter surface. Although the AWR of a battery with a textured emitter can be significantly lower in some cases, the negative effect is an increase in lateral emitter resistance loss, thereby reducing the fill factor. To the best of our knowledge, the concept of using a textured emulsion (TO) deposited on the surface of a smooth emitter (at least for crystallized solar cells) was first proposed by NREL in 1994. If well designed, this method can significantly reduce the resistive losses associated with larger effective sheet resistivities and can significantly reduce the likelihood of such mechanical failures. For example, NR £L's Gee et al. used CVD to deposit an optimized textured Zn〇 coating and reported that the AM1.5 AWR of the encapsulated c-Si wafer was as low as 6%. It also shows that the encapsulated battery has an absolute improvement of up to 0.5% compared to the encapsulated SLAR planar battery. . The monthly force that textures the surface of the RTWCG SiOX film to produce a so-called τ 〇 characteristic is the last efficiency enhancement element of the RTWCG SiOx ARC/SE/TO cell structure design disclosed herein. It is known that the textured emitter surface undergoes a voltage drop due to the lateral flow of current to the gate fingers, thereby reducing the conversion efficiency. Smoothing the emitter surface and texturing Si〇x ensures a significant reduction in the sheet resistance of the emitter, thereby increasing the efficiency of the crystallization solar cell. The optimized RTWCG TO film further enhances the proven efficiency gain of the RTWCG Si〇x arc/se solar cell structure. RTWCG si〇x臈 grown in low growth rate formulations has a smooth surface topography. These smooth SiOx films can be textured by another short wet process step of continuous flow to 15 81 201251057 41245 pif seconds to form T〇 Si〇x features. The resulting pyramidal features on the SiOx surface (preferably grown on a smooth emitter) will recapture the light that will be reflected off the cell without the adverse effects of the previously textured emitter surface. The effectiveness of this τ 〇 feature as shown in the following example becomes increasingly important as the angle of incidence of light is removed from perpendicular to the cell surface. Figure 28 shows the AFM surface topography of the RTWCQ Si〇x film grown on a solar grade c_Si substrate before and after 15 seconds of 1% HF ((iv) liquid) etching. The thicker si〇X film of about 0.25 μm has a further reduction of the film. The reflectance in the upper limit of the visible spectrum thus produces a textured characteristic of the efficiency gain. As shown, the lowest AM1.5 AWR 3.09 recorded to date exists on the smooth n+c-Si emitter surface and subsequently dip On a 15 second SiOx film in i% HF (water (iv)). The high SiOx growth rate solution produces a textured Si〇x film surface as part of a single RTWCG SiOx ARC/SE/TO process step. As can be seen in Figure 24, these The SiOx film has an extremely low AMI.5 AWR value of about 4.5%. Since the pyramidal feature is about 120 nm high, the RTWCG Si〇x ARC/SE/TO process step should produce a film thickness of not less than 22 Å. In order to achieve this film thickness, the active emitter should return a nominal value of 0 25 μm to 0.3 μm, and the Si Ming Ting fold and tail type diffusion profile must produce a junction depth of not less than 〇 6 μm. Example 7 - for solar cells and others The preliminary identification test of the applied RTWCG Si〇x film has tested several RTWC The shelf life of the G solution formulation. The maximum shelf life test is about 8 years for an early solution formulation. For 82 201251057 41245pif this ongoing shelf life test 'periodically saves 1 lifetime during the time range The VT solution (such as in Figure 14) in a sealed nalgene container was used to grow the Si〇x film over more than 100 large area c_Si, mc-Sim, and polycrystalline n+/p solar cells. To date, there has been no significant change in the quality of the resulting RTWCGSiOxARC/SE cell structure or the resulting solar cell performance. Small area n+/p solar cells have also been used to test the shelf life of recent RTWCG growth solution formulations. Most novel formulations are shown again. There is no significant change in the structure or performance of the RTWCG battery. Initial identification tests for high growth rate RTWCGSiOx films (including but not limited to the tests below) indicate that these Si0x films are not only potentially useful for solar cell applications, but also for a large number of other Electron (microelectronics) and optoelectronic (photonic) applications. Since a relatively large amount of A1 (Au) / growth hybrid RTWCG SiOx film / Si / Au: Ti MOS The electrical and dielectric properties of the RTWCG SiOx film were extracted (the front gate area was approximately 〇·〇 49 cm 2 ). IV and CV characteristics were obtained on the fabricated MOS capacitor before and after various stress conditions, which were used to determine: (丨) resistivity of SiOx film, (ii) leakage current, (iii) dielectric constant, and (iv) breakdown voltage. Figure 29 (a) shows the i-v characteristics of an A1/growth RTWCG SiOx/Si/Ti-Au MOS capacitor with a SiOX film thickness of 11 Å. The I-V characteristic at (1) a bias voltage of 110 volts to (+) 110 volts and a bias voltage of (-) 3 volts to (+) 3 volts shows that the mobile ion density in the SiOx film is extremely small. Another evidence is the good C-V curve obtained on the same MOS capacitor in Figure 29(b). The I-V characteristics of the film not only meet the standards for solar cell applications, but also meet a number of other more demanding standards for electronic and optoelectronic (photonic) 83 201251057 41245 pif component applications. In a series of experiments, A1/growth SiOx/p-Si/Au:TiMOS capacitors were produced using the preferred RTWCGSiOx growth solution formulations described herein. The I-V and C-V characteristics were obtained before and after the voltage stress of up to 1 hour at a fixed bias of (-) 100 volts or (+) 100 volts. Time-dependent leakage currents and breakdown voltages fail to exhibit any significant change in voltage stress. The current leakage current density of the RTWCG SiOx film of the prior art is about 25 N/cm 2 at a positive electric field of 8 megavolts/cm, and is low at a positive electric field and a negative electric field applied at 〇3 volts/cm. Leakage current at 0.8 N/cm2. The current technical RTWCG SiOx film has a resistivity of about 4 x 1 〇 14 ohm-cm. The data is no less than the known data for spin coating and CVD SiNx films deposited in the art at temperatures below 500 °C. These results show that the RTWCG SiOx thin film dielectric layer is suitable for high efficiency 矽 solar cells and passivation/anti-reflective coatings for microelectronics and photonic applications. Figure 30 shows initially at 1〇〇. The i v characteristics of the A1/growth RTWcg SiOx (about 1 Å nanometer thick) film/p_Si Au:Ti M〇s capacitor were measured by heating under the arm for 1 hour and then heating at 200 ° for 1 hour. The leakage current is reduced by the heat treatment to dry the surface of the grown state si x x film. The lv data display obtained from a large number of c-Si and mc-Si batteries can be removed by drying at about 12 Gt:T for 5 minutes to remove the humidity of the SiOx county. In the relevant experimental towel, it was found that the battery was stored at room temperature for two days until the day (depending on the thickness of the SiOx film), and the relative percentage of the increase was the same as that of the battery treated at 12 (TC for 5 minutes). 84 201251057 41245pif points = five A1/growth RTWCG SiOx films/p-Si/AuTi MOS capacitors, heat treated in air at 200 ° C, 30 (TC, 450. (and 60) at elevated temperature of TC A small area of n+/p c_Si and five small areas of n+/p mc-Si RTWCG SiOx ARC/SE solar cells for 1 hour. As can be seen in Figure 18, the relatively high hydrogen atom concentration on the SiOx surface decreases with depth. Based on experimental data. , as low as 2 〇〇, its temperature can transfer hydrogen to the Si〇x/Si interface and passivate the interface. Heat treatment at 200 ° C under a positive bias and a negative bias of 0.3 MV / cm. After an hour, it can be observed that the leakage current drops from about 5x10 11 amps/cm 2 to as low as 2 xi 〇 12 amps/cm 2 . 5 for this reduction is due in part to the hydrogen passivation of the si 〇 x / si interface. After further heating for a period of i hours at a temperature in the range of 200 ° C to 450 ° C, the leakage current of the MOS capacitor is small. The rate is gradually reduced. At 600 ° C, the leakage current of all MOS capacitors is slightly increased. And the Pmax of all c-Si and mc-Si solar cells is slightly reduced due to the small decrease of Voc and FF. These findings are likely to be The SiOx film from the metal gate through the MOS capacitor and the Ag of the solar cell diffuse from the front gate line to generate some small short circuit paths. However, it is worth mentioning that the above c_Si and mc-Si small area test cells are self-comparison The fabricated RT solar cell with the best RTWCg SiOx ARC/SE (TO) junction is cut. According to the invention, the emitter of the RTWCG SiOx ARC/SE cell design should be 〇·55 μm thick and RTWCG SiOx ARC/ The SE/ΤΟ battery is designed to be approximately 0.65 microns thick. Figure 31 shows A1/Life 85 201251057 stored at near room temperature before and after exposure to relatively high intensity (approximately 5 watts/cm 2 ) near UV radiation for six hours. 41245pif long-state RTWCG SiOx/Si/Au: IV characteristics of Ti M〇S capacitor. The SiOx thickness in this example is about 140 nm, which is close to the optimum thickness for ARC. For example, in small area c-Si and mc-Si battery was exposed to near UV radiation for up to 6 days and The data obtained from the battery obtained later confirmed that the above UV stress conditions did not increase the leakage current. In one of the experiments, '12 small-area c-Si cells and 12 mc-Si small-area cells were stored under the above UV exposure 4 day. Surprisingly, Isc, V〇c, FF, Pmax and Rs are substantially unchanged or slightly increased. During the Ι-ν test, the temperature of the battery was maintained at about 25 °C by the small area I-V system, which was calibrated using the NREL standard battery before all Ι-V data for this and all other stress testing experiments were obtained. Studying Plasma Induced Using Existing High Density Tantalum Plasma (1〇5 to 1〇6,; μ3 Electron Volt) System Obtaining Field IV Characteristics at (-) 200 V to (+) 200 V Applied Voltage Destruction of the SiOx film. The plasma induced damage was evaluated for the I_V curve group after the SiOx film was exposed to the plasma environment several times. Growing on the front side of the 2吋Si wafer is 1% big! ^ 50 nm thin SiOx film with atomic concentration. A good quality Au-Ti ohmic contact is applied to the back surface. Figure 32 shows two ι_ν curves for the above SiOx coated 2 吋 P-Si wafer after 5 minutes of plasma exposure. The plasma density is 2 x l 〇 i 〇 5 / cm ^ 3 , the electron temperature is 1.7 eV, the plasma potential is 9.8 volts and the neutral gas (Xe) residual pressure is 6 χΐ〇 - 5 Torr. The IV curve clearly indicates the presence of positively moving ions, but the two curves indicate a very small hysteresis indicating that the s丨〇X / si interface trapped by the plasma has a very low density—the sample is exposed to 86 after the next 15 minutes of electrical exposure 86 201251057 41245pif The IV curve again shows an approximately consistent curve. This shows that even after the combined 20 minutes of plasma exposure, the SiOx/Si interface trap generated by the plasma of very small density is produced, but the concentration of metal impurities in the SiOx film is relatively large. The leakage current through the SiOx film depends on the plasma density and the neutral (Ar) gas pressure. When a (+) 70 volt bias voltage is applied, the Ar pressure for 2 〇 〇 -5 Torr ') 3⁄4 leakage current is 1.6 mA' and for a 〇 _ 4 Torr α γ Li, the leakage current is 2.7 mA. . A (-) 200 volt bias was applied to the SiOx film having the worst case profile (Fe impurity atom concentration of about 3%). Initially, the leakage current was 57 microamperes and was 60 microamps after 1 minute exposure. The SiOx film had an initial leakage current of up to 7 mA after applying a (+) 1 〇〇 (Ar pressure 77 μTorr) bias to the sample, but dropped to about 6 mA after 1 minute. The SiOx film was exposed to high-strength plasma for 25 minutes because it was suspected that there was a change in the top layer of Si〇x. However, XPS/SEM analysis did not show any change in the surface of the siQX. The conductivity (σ) can be estimated by the following equation.

ά 2 V where / is 9 leakage current, voltage, is the diameter of the sample and t is the film thickness. See above for a set of specific measurements with 1 = 6 mA, V = 1 〇〇, d = 5 cm and 1 = 5 〇 nanometer. Using the above equation, the film is applied with σ = 1.5 χ 1 〇 η / ohm - cm, which corresponds to a relatively low film resistivity of about 6 < 1 〇 1 () ohm centimeters. This relatively high conductivity is the worst case profile for & contamination, but its health is no less than the public value of f ^Ti〇x arc film 87 201251057 41245pif and other so-called room temperature spin-on film dielectric layers. Battery number

Damp heat test (Dff): 80 ° C, relative humidity is about R solution Description

Isc(安)

Voc (volts) bare A8-3 MA-1 after coating SiOx 96 ^ φί 139.62 199^62 199.98 '20329 204.93ϋ 501 5Ϊ2

513 •5lT 513 '51*3' 71.22 69.8Ϊ' 68.69 68'.3δ' 67.9 67.64 0.4652 FF(%) Rs(Europe)

0.3888 03933 0.3909 ^3999 α39Ϊ3 Naked A8-5 H-1 After coating SiOx·ϋϋ·150.85 217.82 216.11 219^07 500 5Ϊ〇" 512 •5ΪΓ 70.83 67.ΪΪ' 68.27 '68.21' 0.4369 '03887 03835 2:9 :4:4:9: 8 : 5 ; 7 : 6 ; 5 : 00—8 ·7: 4· : 4· : 2 : 3 : 5 3 PC 149.70.70:7171:7153. 144 土轻 24〇Vj&gt ;B^i bare 217.15ϋ 511 '5Ϊ2 68.47 68.08' 0.3791 0;3753 0.3833 A8-14

B After coating SiOx 96^Β^ΐ' 175.14 25153 251.88 "25Ϊ2" 255.09 25Ϊ53 500 '5ΪΪ' 512 512 512 5ΪΓ 70.98 64.'29" 64.97 66.'84' 66.25 65.'71" 0.3884 0.4156 α4Ϊ29 0.3552 "0'3548 0372Ϊ 8:1:1:9/5:6:9:8:6:21 6 ; 6 ; 4 : 8 1 : 3 : 2 : 9 : 5 : 1 1·4:·3; ·°ί·5^ί-··3*··7*-·5*··4-· 4; 5τ-·6Γ-·6Γ-'6· 2τ-3· -* 3T-'6r;6r ;5· 7-7-7-7-7 6.-8-8-8-8,-8- 49 Table 5_ Small-area coated RTWCG SiOx mc-Si sun from the same large-area manufacturing battery The wet heat durability test of the battery. Table 5 contains IV data for three small area mc-Si solar cells before and after complete immersion in three different RTWCG SiOx growth formulations. It is shown after the formation of the RTWCG SiOX ARC/SE mc-Si electrical structure and after exposure to a hot and humid environment (80 ° C, relative humidity of about 100%) for up to 24 hours after Isc, Voc, FF, Rs and Pmax The change that has taken place. 88 201251057 41245pif The increase in Isc, Voc and Pmax less than the expected value is caused by a bare cell having a thickness that is thinner than the optimum emitter. A battery with a thicker emitter will fully utilize the SE produced during RTWCG SiOx growth. This example shows that even if the remaining emitter is extremely thin, the battery will not degrade during the DH test. The next example contains I-V data for a fabricated cell before and after coating SiOx. Although the cell is not optimal for RTWCG SiOx ARC/SE cell design, it has a thicker emitter. Example 8 n+/p (P,B) RTWCG SiOx ARC/SE c-Si, converted mc-Si and polycrystalline germanium solar cell performance RTWCG SiOx ARC/SE/TO low cost crystallization solar cell technology is suitable for all crystallization Shixi substrate, such as Chai and floating zone single crystal (c-Si), cast polycrystalline (mc_si) and ribbon polycrystalline germanium (polycrystalline germanium) substrates. The RTWCG SiOx process is well suited for existing fabrication methods (such as screen printing metallization) and only the diffusion step requires modification. In addition, it reduces the number and complexity of standard processing steps. Optimization of the butyl growth solution considers a large number of RTWCG Si〇x variables, such as solution formulation, growth rate, and etchback of the unmetallized emitter. Structures that must be considered include the depth of the joint, the distribution of the diffusion (four), and the f-depth of the bend and the distribution curve of the house and type. Optimized and metallized phase RTWCG SiOx growth solution must be able to pass the dog! Do the following in minutes: ° i. Clean the surface of the bare cell on the spot; ii. Produce low reflectivity and high transmittance & (^ film; iii. Produce good quality selective emitter at the same time; 89 201251057 41245pif iv. Textured film surface. This thorough study can be done using a large number of manufactured C-Si and cast and ribbon-like diffusion structures and bare solar cells. Diffusion η+/ with a bend-to-tail diffusion profile ρ structure only produces a small number of small-area solar cells, RTWCG SiOx ARC/SE / (TO) process requirements. Table 6 contains 12 uncoated 6 p-inch manufacturing c-Si solar cell manufacturer IV data and the same battery IV data after coating SiOx. The emitter of the cell is extremely thick and textured by a pyramid rather than a smooth surface. The textured emitter surface makes it impossible to obtain a precise net majority carrier concentration profile or diffusion profile shape' Therefore, the joint depth is estimated to be greater than 〇6 μm. The average gain of the Isc is moderate, about 40%, and the average Voc gain is surprisingly low at only 5 millivolts. However, due to the substantial increase of about 12%, Therefore, the average Pmax gain is significant at 56%. Based on the manufacturer's data, the maximum absolute AM1.5 efficiency of the batch is calculated to be 16.4%, and the batch average is about 15.6%. This average efficiency clearly shows RTWCg.

The feasibility of SiOx cell design and technology, especially since the cell is fabricated on a shredded substrate, has a large aspect ratio pyramidal textured emitter surface and the diffusion profile is far from optimal for high efficiency RTWCG SiOX ARC/SE cell designs. Suitable for RTWCG SiOx growth solutions to maintain cell metallization integrity and produce efficiency enhancement features that will partially reduce reflectivity, passivate the surface, and favor good quality selective emitters. However, any given small batch battery (up to 30 cells per batch) contains any number of cells in the range of 2 to 5 with a maximum pmax (efficiency) gain after coating si〇x. In 201251057 41245pif, the Pmax of the No. 2 battery and the No. 7 battery of Table 6 were 85.4% and 97.7%, respectively. This is explained by the ability of the SiOx growth solution to clean the surface of the cell and remove some of the deleterious surface conditions prior to the growth of SiOX. This benefit is not present in the conventional ARC coating technique known in the art. The Pmax dispersion of many manufactured c_Si, mc_si and polycrystalline solar cell batches is small. Figure 33 shows that the Pmax dispersion of the cell of Figure 6 is significantly reduced after being fully immersed in the RTWCG SiOx ARC/SE growth solution. The 1-V data shown in Table 7 was from a small area n+/p c_Si solar cell cut from a 6 吋 cell of the same coated pyramid, which was completely immersed in the RTWCG SiOx growth solution formulation of Figure 12. After growth, the battery was immersed in 1% HF (aqueous solution) to produce a textured tSi〇x surface. Since the emitter is very shallow and the junction depth is estimated to be 0.45 μm to 0.5 μm, it is expected that FF will be etched back after Si0x growth. The emitter is reduced. Although the resulting emitter of about 25 microns thick corresponds to an emitter sheet resistance greater than 12 ohms per square unit, the series resistance (rs) of the battery unexpectedly decreases by an average of about 23%. The 〇 gain (see Table 7) is the main reason for the average increase of 51.58% in the shape of .111. The relatively small Voc increase (up to 13 mV) and the residual emitter sheet resistance is higher than 12 〇 ohm/square unit. The other relevant IV data collected by the coated battery are consistent. Although the Isc can be gradually increased as the sheet resistance increases, the Voc and FF gradually decrease. The test battery A5-1 and the test battery A5-7 are not included in the average gain because respectively The immersion time of 3 sec and 15 sec. does not produce a film similar to the thickness of the remaining batteries. However, it should be noted that as the Rs of the battery A5-7 drops by 15.7%, the relatively long immersion time 91 201251057 41245pif does not seem to Will adversely affect the screen The integrity of the brush contact. Another interesting observation is that Voc, Isc, and FF only slightly change with the immersion time in the range of 50 seconds to 70 seconds; small RTWCG SiOx process time changes do not greatly affect the battery performance. Depth is important for maximizing RTWCG SiOx ARC/SE/(TO) pmax (efficiency). Table 8 shows the Pmax gain of two small-area c_Si solar cells coated with SiOx. The fabricated n+/p c_Si large-area cell is fabricated for a deeper emitter of about 0. 65 microns. The growth solution formulation and post-growth treatment are the same as in Table 6. Battery 20-2 has the best v〇c and Pmax gains. , 30 mV and 109% respectively. The relatively large Pmax gain is contributed by the FF which is raised by the relatively large Rs drop. The relatively large v〇c increase indicates that the surface passivation of Si〇x is good, but it is immersed in the growth solution. After the leap second, the remaining sheet resistance is too low, about 50 ohms/square unit. The average VGe of the solid small area battery cut from two large-area solar cells is increased to 17 2 millivolts. Solar cells 'on average, Pmax is increased by 6 7 91%, which is within 1% of the jump, but the average gain is relatively low, only 41 · 35% 〇 with smooth emitter and material and tail · scattered distribution secret (such as

The maximum voc of the ηΛΓ square male *n+/pc-Sit pool batch is increased to m. This is expected to increase moderately because RTWCG Si0x ARC/SE VIII >, ,,. After formation, the net majority surface concentration is greater than (4) 19/cm ^ 3 0 ^ cloth S 〇 X so that the efficiency of small batch (10) batteries (including 3 92 201251057 41245pif, pool in Table 10) is increased by an average of 5449% (am 〇 condition). The average is 40.79%. In comparison, the efficiency gain of a fabricated battery using & Νχ coating is no more than 35%, even under the positive effect on the battery body that occurs during CVD siNx deposition. The absolute efficiency improvement of the three-phase compared to the SiNx-coated battery on this small-volume-manufactured battery is about 14 〇/〇, although the RTWCGSiOx process is a surface process that does not passivate the body. Based on extensive testing of RTWCG SiOx cells, the use of an approximately optimal RTWCG SiOx ARC/SE/(TO) cell structure results in a much larger absolute efficiency gain than a battery using an optimized but SE-free SiNx ARC film. Table 9 shows the I-V data for small batches of large-area low-efficiency n+/p polycrystalline germanium-produced solar cells measured by solar cell manufacturers before and after coating si〇x. It should be noted that the average Pmax gain obtained by RTWCG SiOx ARC/SE formation is about 48%. In comparison, as far as we know, the Pmax average gain generated by the SiNx coating on the molded battery is less than 35%, which includes the hydrogen body passivation initiative. Experimental studies have shown that the SiOx ARC/SE efficiency enhancement feature is more suitable for low efficiency polysilicon fabricated cells compared to higher efficiency c-Si cells. Table 10 shows the I-V data of three of the small batch fabrication type polycrystalline Si solar cells before and after they were completely immersed in the SiOx growth solution. The battery is tested at NASA's Glenn Research Center (NASA GRC) under standard AMO conditions; therefore, the standard AMI.5 efficiency value should be approximately 20% higher. As shown in one of these batteries, the main parameter that promotes the increase in the ΑΜ0 efficiency Pmax (97.5%) after coating SiOx is that the ISC is increased by 89.5%. This large increase in Isc can not be solved by a simple reduction in optical loss. 93 201251057 41245pif can not be explained by simple surface passivation because the maximum increase of v〇c is only 16_2 mV. Interpretation must be a combination of optical presence, surface passivation, and some other factors. Battery Description i Isc Voc FF Pmax Bare 1 Pool 1 5.81 安 593 _4 volt 68.20% 2_35 watts RTWCG SiOx coated battery after 55 seconds 1.97 An 599.0 volts 74.90% 3_58 watt gain 37.18% 0.94% 9.82% 52.34% bare battery 2 (*) 5.71 amp 585.9 volt 59.60% 1.99 watt RTWCG SiOx coated battery after 60 seconds 2 (*) 8.18 amp 597.0 volt 75.60% 3·69 watt gain 43.26% 1.89% 26.85% 85.43% bare cell 3 5.87 amp 585.9 volts 68.60% 2.36 watts RTWCG SiOx coated battery after 60 seconds 3.29 amps 596.0 volts 73.30% 3.62 watts gain 41.23% 1.72% 6.85% 53.39% bare cells 4 5·83 amps 592.8 volts 69.80% 2_41 watts RTWCG SiOx coating 60 seconds After the battery 4 8.23 An 595.0 volts 75.50% 3.70 X gain 41.17% 0.37% 8.17% 53.53% bare battery 5 5.86 amp 596.0 volts 70.90% 2.48 watts RTWCG SiOx coated battery after 60 seconds 5 8_15 An 598.0 volts 74.00% 3.61 watts Gain 39.08% 0.34% 4.37% 45.56% bare cell 6 5.89 amp 588.0 volt 65.60% 2.70 watt RTWCG SiOx coated 65 seconds after battery 6 8.26 amp 592.0 volt 74.20% 3.81 watt gain 40.24% 0.68% 13.11% 41.11% bare battery 7 (*) 5.74 An 589.2 volts 53.00% 1.79 watts RTWCG SiOx coated battery after 65 seconds 7 (*) 8.15 An 595.0 volt 72.90% 3.54 watt gain 41.99% 0.98% 37.55% 97.77% bare battery 8 5.88 amp 588.3 volt 60.10% 2.08 watt RTWCG SiOx coated battery after 70 seconds 8 8.11 An 593.0 volts 72.80% 3.50 watt gain 37.93% 0.80% 21.13% 68.27% bare battery 9 5.86 amp 590.5 volts 67.80% 2.35 watts RTWCG SiOx coated battery after 60 seconds 9 8.21 amp 591_0 volts " 73.30% 3.55 watt gain 40.10% 0.08% ~8.11% 51.06% 94 201251057 41245pif Battery Description Isc Voc FF Pmax Naked Battery 10 5.91 Ann 587.3 Volt 68.40% 2.37 Watt RTWCG SiOx coated battery after 60 seconds 10 8.27 Am 590.0 V 72.50% 3.53 W Gain 39.93% 0.46% 5.99% 48.95% bare battery 11 5.87 amp 593.2 volts 69.90% 2.44 watts RTWCG SiOx coated battery after 60 seconds 11.17 amp 597.0 volts 73.10% 3.56 watt gain 39.18% 0.64% 4.58% 45.90% bare cell 12 5.88 amp 593.3 Volt 70.20% 2.45 watts RTWCG SiOx coated battery after 60 seconds 12 8_24 amp 596.0 volts 74.10% 3.64 watt gain 40.14% 0.46% 5.56% 48.57% average of all bare cells 5.84 amps 590.3 volts 66.01% 2.31 watts Average of all batteries coated with RTWCG SiOx 8.19 amps 594.9 volts 73.85% 3.61 watts average gain 40.11% 0.78% 11.88% 56.03% Table 6. Surfaces of shredded wafers and coated pyramids before and after RTWCG SiOx coating AM1.5 IV data for an n+/p c-Si solar cell (such as in Figure 20). 95 201251057 41245pif Battery description Reaction time [seconds] Isc bare cell (A) Isc RTWCG SiOx coating (A) Voc bare cell [volt] Voc RTWCG SiOx coating (volt) FF bare cell [%) FF RTWCG SiOx coating ( %) Rs bare cell [Europe] Rs RTWCG SiOx coating (Europe) Pmax bare cell (Watt) Pmax RTWCG SiOx coating (Watt) A5-2 50 280.31 438.29 581.0 592.0 73.8 70.1 0.25 0.19 120.18 182.05 Gain 56.36% 1.89% - 4.95% -22.36% 51.48% A5-3 50 262.89 398.84 579.0 592.0 70.9 71.1 0.28 0.20 107.91 168.19 Gain 51.71% 2.25% 0.28% -29.00% 55.86% A5-4 55 262.71 400.85 583.0 593.0 72.4 71.2 0.27 0.20 110.92 169.16 Gain 52.58% 1.72% -1.77% -26.38% 52.51% A5-5 55 331.66 514.03 577.0 590.0 69.6 68.0 0.21 0.17 133.28 206.31 Gain 54.99% 2.25% -2.28% -18.91% 54.80% A5-6 60 412.68 625.86 581.0 593.0 70.4 68.1 0.18 0.15 168.82 252.73 Gain 51.66% 2.07% -3.17% -17.49% 49.70% A5-8 60 271.7 400.57 579.0 586.0 66.8 65.6 0.27 0.22 105.03 153.98 Gain 47.43% 1.21% -1.80% -19.42% 46.60 % A5-9*** 60 216.41 332.85 581.0 591.0 68.5 68.2 0.31 0.24 86.00 134.20 Gain 53.81% 1.72% -0.38% -22.17% 56.04% A5-10 65 263.51 408.20 588.0 596.0 73.7 71.7 0.24 0.19 114.23 174.20 Gain 54.91% 1.36% -2.82% -21.21% 52.49% A5-11 65 228.97 351.41 586.0 595.0 73,4 71.4 0.28 0.22 98.51 149.20 Gain 53.47% 1.54% -2.71% -21.94% 51.45% A5-12 65 241.23 365.82 587.0 596.0 73.5 71.9 0.27 0.20 104.07 156.67 Gain 51.65% 1.53% -2.19% -22.95% 50.54% A5-13*** 70 218.45 334.30 589.0 597.0 73.9 72.0 0.30 0.22 95.01 143.75 Gain 53.03% 1.36% -2.45% -25.79% 51.30% A5-14 60 272.01 409.17 590.0 596.0 74.9 72.8 0.23 0.19 120.21 177.39 Gain 50.42% 1.02% •2.84% -20.20% 47.57% A5-1* 30 263.51 408.20 588.0 596.0 73.7 71.7 0.24 0.19 114.23 174.20 Gain 54.91% 1.36% -2.82% -21.21% 52.49% A5 -7** 150 312.02 456.06 577.0 583.0 66.4 64.2 0.24 0.20 119.52 170.53 Gain 46.16% 1.04% -3.37% -15.79% 42.67% Average 271.9 415.0 583.4 593.1 71.8 70.2 0.26 0.20 113.7 172.3 Average gain 52.65% 1.66% -2.28% -22.61% 51.58% Average deviation 34.9 55.5 3.8 2.4 2.2 1.8 0.03 0.02 14.7 21.8 Table 7. From the emitter surface with a shallow emitter, an estimated junction depth of about 0.45 μm and a coated pyramid IV data of a small area n+/p c-Si solar cell cut by the same 6-inch battery. 96 201251057 41245pif Battery Number Description Isc (milliampere) Voc (millivolts) FF (%) Rs (Europe) Pmax (milliwatts) 18-8 Naked 222.2 569 50.71 0.408 64.1 Fully immersed for 30 seconds 317.4 589 61.1 0.268 114.2 Increased 42.8% 3.5% 20.5% -34.3% 78.2% 20-2 Bare 81.85 550 39.36 1.58 17.73 Fully immersed for 60 seconds 114.4 580 55.85 0.69 37.07 Increased 39.8% 5.5% 41.9% -56.3% 109.1% Table 8. Before and after RTWCGSiOx coating, The AM1.5 IV data of the n+/p c-Si solar cells (such as in Figure 21) using the shredded wafer and the surface of the pyramid was applied. After the wafer is coated with SiOX, Voc Isc Pmax FF Voc Isc Pmax FF 1 516 4.01 1.41 68.2 525 5.93 2.08 66.8 2 517 3.98 1.38 66.9 521 5.83 2.04 67.0 3 514 3.99 1.34 65.0 520 5.96 2.02 65.2 4 516 3.95 1.40 68.8 522 5.78 2.07 68.5 5 514 4.02 1.41 68.1 525 5.71 2.06 68.7 6 514 4.00 1.38 67.2 517 5.67 1.98 67.5 7 513 3.95 1.35 66.6 526 5.76 2.08 68.9 8 516 4.06 1.38 65.9 523 5.76 2.02 67.2 9 518 4.03 1.39 66.6 520 5.63 2.03 69.3 Average 515 4.00 1.38 67.0 522 5.78 2.04 67.7 Increase % 1.33% 44.57% 47.71% 0.93% Table 9 · AM1.5 IV data on large-area n+/p polycrystalline silicon fabricated solar cells before and after RTWCG SiOx coating. 97 201251057 41245pif Battery Number Description Isc (A) Voc (millivolts) FF (%) Eff (%) P-33 Naked 1.72 498 56.3 3.25 yuan all into 65 seconds 2.71 510.8 54.3 5.07 4s. Ancient 57.6% 2.6% - 3.6% 56.0% P-37 bare 1.69 500.5 57.9 3.3 Complete immersion 60 seconds 2.74 516.7 60.5 5.78 Lifting 62.1% 3.2% 4.5% 75.2% P-45 bare 1.53 505.3 62 3.23 Full immersion 65 seconds 2.9 517.8 62.9 6.38 Lifting 89.5% 2.5% 1.5% 97.5% Table 10. AMO 25°c IV data for selected low efficiency polycrystalline germanium fabricated solar cells before and after coating SiOx. Recently, a large number of 18 large-area (about 243.5 square centimeters) cast mc_Sin+/p solar cells were manufactured by Equity Solar, Inc. The IW data of the RTWCG SiOx growth and subsequent I-V data were measured by a dedicated independent laboratory. On average, Lu 1.5 has an efficiency of about 14.14%.

Voc is 603.5 millivolts' FF of 78.9% and the average JSC is about 29.7 milliamps per square centimeter. It should be noted that after coating SiOx, the FF of the three cells is about 82% or greater than 82%, i.e., 81.95%, 82.22%, and 83.56%. The 83.56〇/〇 FF value is close to the ideal theoretical limit of 85%-86% for batteries operating in low injection conditions. To the best of our knowledge, this FF value is the highest ff reported for large area screen printed metallized mc-Si solar cells, and the highest FF reported for any large area crystalline germanium solar cell. The above RTWCG SiOx film uses two ultra-low cost rtwcg

The SiOx solution formulation (such as in Example 1) was grown. 140 nm _i5 〇 98 98 201251057 41245 pif The growth time of the thick S1 X film is about 3 G seconds, and the unmetallized surface of the emitter is about 0.20 μm. Unfortunately, the film grows on less than 85% of the emitter surface. It was found that the n+ emitter was accidentally removed from the active battery area estimated to be (10) in the electric-edge edge. Stealing growth solutions cannot grow on the lesser part of the cell. Si〇x is attributed to the different growth rates of Si〇x in heavily doped and lightly doped counties. It is shown that if the above-mentioned emitter portion is not unintentionally removed, the average AM1 5 efficiency of the above-mentioned unoptimized cast me_Si solar cell will be higher than 16.2%. '

It should be noted that for the above mc_Si batch, the average shunt resistance (Rsh) value becomes more than twice after coating si〇x. The average series resistance (Rs) of the 11 cells using the first growth solution decreased by about 30/〇' after coating Si〇x, i.e., from 7.75 microohms to 5 41 microohms. The average Rs of the remaining seven cells using the second SiOx growth solution decreased to about 6.5 ohms from 6 micro ohms. The high FF values obtained on these RTWCG Si〇x ARC/SE cells are consistent with a large Rsh increase and a large Rs reduction. A thick hair emitter battery may have an Rsh increase of up to 500% due to the removal of certain short circuit paths from the bare cell. RS reduction of up to 60°/〇 occurs in almost all deep junction cells' but is difficult to fully explain because of the relatively large etchback (〇2〇micron) thickness during RTWCG si〇x ARC/SE cell structure formation The surface of the emitter is unmetallized and etched back to an unmetallized emitter surface of up to 0.30 microns thickness during formation of the RTWCG SiOx ARC/SE/TO cell structure. The total performance gain provided by the low-cost SiOx ARC/SE/(TO) process to solar grade C-Si, mc-Si 99 201251057 41245pif and other crystalline germanium solar cells is indeed greater than that of any other known current state of the art ARC/ The total performance gain obtained by the SE scheme. However, the advantages of using RTWCG SiOx processing are not limited to the cell level; it has the following capabilities: i. Controls the refractive index of the upper portion of the SiOx film (see Figure 25 (a), Figure 25 (8)); ii. Produces a gradient index (see figure) 9 to Fig. 15); iii. Texturing the upper portion of the SiOx film (see Fig. 28). The RTWCGSiOx process produces an SiOx film (Figure 24) with an average weighted reflectance (AWR) of 3% AM1.5, which is well suited for producing a good glass-EVA-SiOx-Si structure. Figure 34 shows the external and internal quantum efficiency and reflectance curves for a large area 6" fabricated mc-Si solar cell before and after the RJWCG SiOx ARC/SE process and after standard EVA packaged into a micromodule. The internal and external quantum efficiency curves clearly show that approximately 61% of the blue response gain at 500 nm results in a significant gain in battery performance after SiOx growth. However, this is by no means the maximum possible blue light response gain available for an approximately optimal RTWCG SiOx ARC/SE/(TO) battery. This example was chosen because it clearly demonstrates the AM1.5 AWR reduction of the RTWCG SiOx coated battery. Before packaging, the AM1.5AWR of the battery is 23.1%. After packaging, it drops to ΐ6·7%β. Please note that these reflectance curves include the reflectivity of the grid and busbar. Although the battery efficiency of a solar cell coated with RTWCG SiOx is important, the battery efficiency is a factor that makes any novel battery manufacturing technology truly meaningful. The following is based on a large number of n+ / p § 丨 battery collection 100 201251057 41245pif ^ comparison number, approximate the best RTWCGSi 〇 x ARC / SE / (T 〇) c_Si 2 〇〇 m battery expected performance. The calculated value of the performance assumes that the JL ancient 1 and mC-Si solar-grade substrates have smooth emitters, and the second and second-like · good · fold and tail-shaped diffusion profiles, the net surface of the emitter surface, the body concentration is 6xlo2 . /cubic centimeters 18xlo20/cubic centimeter, and 3 is about G1 micron below the surface of the emitter. The accuracy should be 0 5 micro = 55 microns. The growth solution etches back from the unmetallized emitter surface 0.2 + The remaining active emitter surface concentration should be 8x1q18/cm ^ 3 to 1 ίο /cm ^ 3 , and the remaining sheet resistance should be no ohm / square unit to 120 ^ / square unit . Under these conditions, low-cost RTWCG SiOx will produce a low-reflectivity ARC layer with excellent transparency and excellent quality and a v〇c increase of 30 mV to 50 mV. Comparative data show that for RTWCG SiOx ARC/SE c-Si electricity = expected average V〇e should be higher than 64 〇 millivolts, average Tse should be higher than 37 mA / cm ^ 2, FF is about 80% and AM 1.5 The efficiency calculation is about 18.9%. For a near-optimal RTWC (} Si〇x ARC/SE good quality solar grade n+/p C-Si cell structure, the expected average performance is: v〇c is about 650 mV, Isc is about 38 mA/ In square centimeters, FF is about 82 〇/0 and the average efficiency of AM1.5 is about 2〇25%. For good quality solar grade mc_Sl substrates, the average structure of RTWCG SiOx ARC/SE mc-Si cells coated with SiOx should be generated. : Voc of about 625 millivolts, current density of more than 34.5 milliamps per square centimeter, FF of about 8〇%, and AM1.5 average efficiency of more than 1725%. For the best quality RTWCG SiOxARC/SE good quality mc-Si The cell structure, the expected average performance is: v 〇e is about 635 101 201251057 41245 pif millivolts, Jsc is about 36 mA / cm ^ 2, and FF is about 0.815, which will increase the average efficiency of AM 1.5 to about 18.6 〇 / 〇 It is estimated that by using an approximately optimal RTWCG SiOx ARC/SE/TO cell structure, a good quality solar grade substrate, a better quality front and back surface screen printing metallization paste and an optimized front gate design, n+/p c-Si 'average AM 1.5 efficiency should be higher than 21%, and for casting mc-Si solar cells 'flat AM 1.5 efficiency should be higher than 19%. By using examples and 1〇

Example n: n+/p/p+ or p+/n/n+ RTWCG SiOx ARC/SE/TO Shixi solar cell structure replaces n+/p RTWCG SiOx ARC/SE/TO cell structure in the above example 'According to c_Si solar cell The average efficiency of AM1.5 available is about 22.5%, and the average efficiency of AM1.5 for cast mc-Si solar cells is slightly over 2 〇〇/0. Example 9 - VMJSi concentrating cell coated with RTWCGSiOX If a dielectric layer, such as an ARC film, is to be deposited or grown directly on the Si surface, the dielectric layer is required to sufficiently passivate the surface. This is problematic for most of the deposition techniques known in the art for ARC, DLARC or TLARC anti-reflective coatings known in the art. The KTWCG SiOX thin film dielectric layer chemically grows at room temperature and produces an amorphous layer with a well-defined short-range order. These chemically stable SiOx coatings provide sufficient passivation of the Si surface and the RTWCG SiOx process does not require post-growth annealing. The chemical stability and surface passivation of the si〇x film depends on the composition of the film and, in terms of expansion, depends on the composition of the growth solution. The current state of the art Si0x film (see Figures 9 through 15) has passivation characteristics superior to the previous Si〇x 102 201251057 41245 pif film (see Figures 7 and 8) due to the small metal impurity concentration and gradient index. Due to the low ISC value, in the case of other concentrating cell designs, the operability of the concentration level is limited, and the vertical multi-junction (VMJ) Si solar cell (U.S. Patent No. 4,332,973, U.S. Patent No. 4,409,422, and U.S. No. 4,516,314) shows the prospect of being used as a high-intensity concentrating solar cell. The biggest cause of efficiency loss in the Si VMJ cell structure is that the illumination = face, back surface, and two unmetallized edge surfaces are highly composite surfaces, which have exposed joints that are difficult to passivate by any conventional method. Conventional ARCs (such as thermal Si〇2) having known good purification characteristics can be used for these batteries due to temperature limitations. b Photovoltaics (Photo Volt, Inc.) provided some early vertical multi-junction (VMJ) & solar cells [9] to SPECMAT, Inc., on which the RTWCG process can be used. The SiOx coating was grown simultaneously on all unmetallized surfaces. After cleaning and surnamed “PV4-14-X” battery, Photo Volt, Inc. measured the performance on both sides of the Si VMJ battery in Table 11. Efficacy is then measured after growing a relatively low growth rate SiOx coating (such as in Figure 5). Prior to testing, the only post-growth treatment accepted by the battery was DI water rinse and nitrogen dry. 103 201251057 41245pif Residual and cleaned Si〇x growth gain Voc (volts) 8.786 9.883 12.5% front side Isc (milliampere) 0.17 0.34 100.0% FF 53.7% 60.7% 13 2% Pmax (milliwatts) 0.779 2.022 159.6% Voc ( Volts 8.699 9.672 11.2% Backside Isc (mA) 0.15 0.30 100.0% FF 51.4% 59.3% 15 5% Pmax (milliwatts) 0.672 1.741 159.1% Table 11. Bare VMJ Si concentrating battery (PV4-14-X) and A solar strength effect parameter of the rjwCG Si-OC-Ν VMJ Si concentrating battery (PV4-14-X) was coated. Photovoltaic companies perform initial engraving and surface cleaning of bare cell surfaces and measurement of performance parameters. It should be noted that the Voc value and the FF value of the VMJ battery after RTWCG SiOx coating were significantly & These values, and especially the sharp increase in is, after coating, cannot be explained simply by the reduction in loss of light form. It clearly shows that surface passivation plays a major role in Pmax up to three times that of bare cells. Example 10 - Enhanced Efficiency n+/p or p+/n Crystallization rTWcg Si〇x ARC/SE/ (TO) 矽 Solar Cell Manufacturing Technology. During the formation of the junction of the I1+/P (P, B) cell structure, phosphorus diffuses not only into the desired front wafer surface but also into the edge and backside surfaces. In industrial practice, the removal of the back joint is usually not attempted after removal of the ph〇sph〇rus Siiica glass (PSG), and in some cases edge separation is not performed. A1 contact after calcination reduces this technical effect, but the success achieved is usually only limited to produce a weak back surface field and low red light 104 201251057 41245 pif response. Based on the experimental data, the RTWCG solution formulation can form a Si0x passivation film in a single step, in addition to the PSG. It can be used in a variety of electronic/microelectronic applications because SiOx growth begins only for solar cell applications when the solution is in contact with a clean tantalum surface, which is used on the back side of the cell because the front side requires the front gate to act as a mask to form a selective emitter. In the standard n+/pRTWCGSiOxARC/SE/(TO) crystalline germanium solar cell fabrication techniques described herein, the PSG is removed and the standard screen printing contacts are deposited and fired. Finally, the RTWCG growth solution was applied to a bare cell to grow a thin Si〇x film on all unmetallized surfaces while etching back a diffusion layer of a certain thickness from these surfaces. This produces excellent ARC and SE on the front side of the battery and removes some of the junctions from the edges. Unfortunately, the n+ diffusion layer under contact with A1 is still intact', which may result in weak back surface fields and high recombination. In one embodiment of one or more embodiments, after removal of the PSG, the back side is floated on the RTWCG solution, or the solution is only delivered to the back side via any other suitable method. Regardless of the delivery system, the RTWCG solution cannot react with the front side because the formation of good quality SE depends on the presence of the front gate line that acts as a mask. Thus, the RTWCG solution reacts with the subsequent wafer edge and removes most of the n+ junction from these surfaces while growing a passivated SiOx film layer on the surface. After deposition and post-baking contact and post-contact, the front side of the cell is floated on the RTWCG solution or the RTWCG solution is applied to the front side of the cell via any other method to produce si〇x ARC and SE, and further reduction is still present at the edge of the cell. Any junction. The post-metal 105 201251057 41245 pif layer sintering time and temperature must be selected such that all of the A1 film regions pass through the back side SiOx passivation layer, resulting in good ohmic contact and a strong back surface field. It is known in the art that a single step HF based solution does not completely remove the PSG. Battery manufacturers can use a two- or three-step wet chemical process to obtain a clean stone surface. For the above-mentioned standard dream solar cell fabrication based on RTWCG SiOx, it is not a critical issue that some PSG remain on the front surface because the surface is cleaned by the RTWCG solution on-site with the SiOx ARC passivation layer and SE formation. However, the back side of the cell requires a pSG-free surface under the A1 metallization layer, and the thin film RTWCGSi〇x layer, which preferably contains a p-type dopant, achieves post-surface passivation, thereby forming a thin p+ layer during contact sintering. In a preferred embodiment of one or more embodiments, a boron-containing & 〇χ: passivation film can be produced on the back side of the cell using a slightly modified RTWCG formulation. An embodiment of one or more embodiments uses from 5 parts by volume to 1 part by volume of the RT volume fraction to 5 parts by volume of a boron saturated aqueous solution in the fast RTWCG formulation described herein. The boron source can include, but is not limited to, ACs or H3B〇4, B2〇3, and BI3 of better purity. In a preferred embodiment, 〇·5 gram-2 gram B2〇3 or BI3 is dissolved directly in any of the fast growing solutions in 1 liter of Example i. Example 10-1. In one embodiment, a small dot of a boron-containing metallization layer is produced on the back surface. The rapidly growing RTWCG Si0x:B solution was then coated to grow a rotten SiOx:B purified film on the back surface. With film growth, the RTwcg Si〇X:B solution removes any remaining PSG from the back surface and wafer edge and 106 201251057 41245pif most n+ junctions. The front gate line is then deposited, and the front gate line is sintered together with the back surface point at a high temperature (800 ° C - 920 ° C), thereby producing good ohmic contact with the underlying surface and forming on the unmetallized surface Light p+ junction. Subsequently, such as in Example 1, the front side of the battery was floated down on the fast RTWCG solution. This produces an AR coating, a SiOx passivation film, and a good quality SE on the unmetallized portion of the front side of the cell. Finally, an A1 post contact and an Ag based bus are produced on the entire back side, and are at about 4 Torr. Sintered at low temperatures. _ Example 10-2. In a second example, the RTWCG SiOx:B purification layer was grown using the above solution formulation after standard PSG removal. In this single step, the solution simultaneously cleans any remaining PSG, etches back the n+ diffusion layer from the entire back surface and edges and grows a Si〇x:B passivation layer. A Me: B point is then deposited on the back side and a grid based on Ag is deposited on the front side. Subsequently, the battery was subjected to temperature sintering (800 〇 920. 〇:) to produce an ohmic contact while a shallow p+ layer was formed on the surface after the battery was covered with the SiOx:B film. Subsequently, a RTWCGSiOxARC/SE passivation layer is produced on the front side of the cell, which further contributes to edge separation. Finally, the entire back side was printed with an A1 screen, the bus bar was deposited and sintered at a low (about 400 ° C) temperature. Anyone with general knowledge in the field of solar cell manufacturing should be aware that the above description of the enhancement efficiency n+/p rTWCG SiOx ARC/SE/(TO) crystallographic solar cell structure can be contacted with appropriate modifications and using any η In the case of doped SiOx film (ie SiOx:P), it is used to fabricate enhanced efficiency p+/n RTWCG SiOx ARC/SE/(TO) crystalline germanium solar cell 107 201251057 41245pif structure. The above-mentioned n+/p or p+/n RTWCG SiOx ARC/SE/(TO) crystallization solar cell structure efficiency enhancement is attributed to the removal of the diffusion layer from the front and back surfaces of the solar cell using the RTWCG process, passivating the front surface of the solar cell and The back surface creates a strong front surface field and increases the strength of the back surface field while producing good edge separation. Example 11 - Em+ and backside purified n+pp+ or p+nn+ c-Si, mc-Si or polycrystalline 矽RTWCG SiOx ARC/SE/ΤΟ double-sided solar cell RTWCG SiOx ARC/SE/ (TO) process is available in principle Most high efficiency solar cell designs of the current technology that typically use expensive high life floating zone (FZ) c-Si substrates. However, the inherent economic efficiency enhancement of the RTWCG SiOx ARC/SE/ ( TO ) technology produces relatively high efficiency on lower solar grade CzC-C-Si substrates, lower mc_si substrates or ribbon polycrystalline germanium substrates. The crystal is double-sided 矽 solar cells. The cross-sectional view in Figure 2 is a good example of a high efficiency, low cost RTwcg double sided solar cell. The simple high efficiency low cost double-sided n+pp+ or P+HH+ C-Si or mc-Si RTWCG SiOx ARC/SE/(TO) solar cell manufacturing technical steps include: i. Any dilute etchant process, such as this article M〇piranha and MoRCA, which maintain a smooth wafer surface while removing surface cut damage from lightly doped p-type or n-type c-Si mc-Si wafers; ii. preferably used in belt furnaces The dilute liquid diffusion source and the protection edge are free from the diffusion process of n++ and P++, and the Π+ + ΡΡ + + or P + + nn++ diffusion structure is generated by simultaneously forming n++ and P + + heavy hetero layers on both sides of the wafer; Iii. Removal of diffusion glass with dilute HF (aqueous solution enzymatic solution; 108 201251057 41245pif iv. Screen printing front and rear grid lines using screen printing pastes of the prior art; V. in belt furnaces in the art It is known to produce a low-contact resistance temperature and time to co-fire the pre-fired metallization layer and the post-metallization layer; vi. Simultaneous growth of the RTWCG SiOx film on both sides of the diffusion wafer, thereby producing a low reflectivity ARC 'while returning money n++ And the unmetallized portion of the p++ re-diffusion layer of a particular thickness and etching away the non-metallurgy present on the edge of the wafer The diffusion layer' thus eliminates the need for a conventional edge separation process step; vii. SiOx surface texturing 'which is produced as a by-product of the fast Si〇x growth solution in step vi or in a separate step using a dilute HF solution. RTWCG SiOx ARC/SE/TO n++pp++ or p++nn++ double-sided solar cell design can achieve large absolute power gain at a cost comparable to conventional single-sided solar cell designs. The reasons are: i. The diffusion temperature and the shorter diffusion time produce a strong front surface field and a back surface field; ii. Smoothing the front surface and overlapping the back surface in principle produces an ideal factor that is more consistent than the battery design using the textured emitter surface; iii. The surface concentration under the metallization layer is high enough to ensure low contact resistance; iv. The deeper emitter prevents the metallization layer from shorting to the junction during the firing step; v. The smooth emitter surface has a textured si〇x ARC battery design The gate occlusion loss is minimized by separating the gate lines farther because of the large lateral resistance work generated by the textured emitter surface not counted by the conventional power source 2012 201251057 41245pif pool. There is no loss;

Vi. Lightly doped front unmetallized surface and unmetallized surface and good surface passivation to minimize composite loss; vii. RTWCG SiOx/ARC/TO film can reduce AM1.5 AWR from 35% to as low as 3%; Viii. Visible spectral absorption in SiOx films is significantly less than conventional arc, especially when compared to low transparency double or triple ARC designs. As is well known in the art, good passivation of the p+ Si surface is one of the major problems to be solved in the design of p+/n Si solar cells and n++pp++ or P++HH++ double-sided solar cells using rotten diffusion hair emitters. The reason for this is that several passivation experiments have shown that the SiNx thin passivation layer not only does not passivate the p+矽 surface and the n+ stone surface, but on the highly P-doped germanium surface, SiNx even exhibits weak depassivation properties. On the other hand, RTWCGSi〇x exhibits good passivation characteristics on both the p+矽 surface and the n+矽 surface. Example 12 - emitter and back side RTWCG SiOx passivated and partially post-surface metallized Π+ΡΡ+ or p+nn+ c_Si, mc_Si or polycrystalline sand RTWrn SiOx ARC/SE/TO solar cells. The so-called emitter passivation backside local (PERL) diffusion cell design is well known in the art. It produces a battery with a record high efficiency (close to 25% under the standard AM 1.5 spectrum). To passivate the emitters of these high efficiency pERL cells, a film of thermal Si〇2 is used to reduce carrier recombination on the surface. The surface of the cell is then locally diffused only at the metal contact to minimize recombination of the back side while maintaining good electrical contact. 110 201251057 41245pif It is well known in the art to use a diffused surface to enhance the back surface field (BSF). As a standard procedure, the n+pp+ diffusion structure uses doping of germanium to form an n+ emitter layer' and uses doping to form bsf. This approach provides advantages over conventional n+/p cell structures by creating potentially more efficient cells on thinner wafers with less curvature. RTWCG SiOx ARC/SE/TO technology produces emitter and back side

SiOx passivated n+pp+ or p+nn+ C-Si or mc_Si solar cell structures (see Figure 36). By using deep junction bend and tail diffusion profiles and standard screen printing and doped contact metallization layers, it produces the following efficiency enhancement features: (i) low reflection in the useful AM丨.5 spectrum Rate and absorption, (ii) front and back surface passivation and (iii) strong front surface field and back surface field. A method of minimizing the recombination of the back side of the battery while producing good post contact is within the scope of one or more embodiments. In this scheme, the layer and the metal layer are separated using Si〇x except for the presence of a small layer of the layer after the absence of SiOx. The concentration of the surface dopant at these points of the heavily doped P+ (n+) diffusion layer is about two orders of magnitude higher than the layer covering the SiOx. For each of the battery structures shown in Figure 35, the front gate line must be screen printed on the n+ (or p+) diffusion layer of Example 11. Subsequently, light lithography can be used to define a small dot area on the back surface. The RTWCG SiOx film can then be grown simultaneously on the surface of the un-metallized front surface, and after the photoresist. Between Si〇x, from the unmetallized front surface of each emitter and the non-resistance back surface: a specific thickness. After removing the photoresist from the back surface, the screen printing will produce a rear-to-back contact with only the heavily doped regions originally masked by the photoresist. Remaining 111 201251057 41245pif The post-crushed surface will have a lower trim concentration, good purity and will be insulated from the metallization layer by the SiOx film. Alternatively, a small dot of the metallization layer is produced after the front gate line is printed and the back surface is screen printed. After co-baking the metallization layer and the post-metallization layer, the RTWCG SiOx film is simultaneously grown on the unmetallized front surface and the unmetallized surface. Finally, the entire region is metallized at the point of SiOx oxide and previous screen printing and fired at a low (<500 ° C) temperature. Since the metallization layer is not covered by the SiOx film, the full area back contact metallization layer forms a good ohmic contact with the point of previous metallization on the surface of the re-diffused p++ (n++) Si. The remainder of the Si surface is separated from the full area back contact metallization layer by a well-passivated textured (TO) SiOx film. When a high-efficiency crystallized solar cell is fabricated on a gradually thinned wafer, the cell becomes more transparent to the red portion of the spectrum, resulting in lower efficiency. Using a textured back surface metallization layer (as described in Figure 36), the path of the reflected light is extended to increase the red light response of the cell. Example 13· Low Cost Enhanced Efficiency A-Si Thin Film Solar Cell Low Cost RTWCGSiOM Transparent Conductive Coating. Transparent conductive oxides (T C Ο ) are well known in the art and play a major role in a-S i and other thin film solar cells. Other applications include flat panel displays and many other electronic (photonic) applications. The conventional TCO film contains In203:Sn (ITO), Sn02:F (FTO), Sn02:Sb (ΑΤΟ), and a conductive polymer. For low cost and high efficiency a-Si solar cells and other electronic and optoelectronic applications, conventional TCO films are not fully compatible for the following reasons: i. relatively high deposition temperatures; 112 201251057 41245pif ii. relatively low transparency; • relatively high reflectivity; iv. high defect density at the TCO/a-Si interface; V. relatively high contact resistance with the underlying a-Si layer; vi. relatively high cost. Various metal nitrides, including but not limited to nitrides based on Bi, Ti, Co, and Cu, produce si〇x having a higher Si-Ο-Μ content when used as a component of the RTWCG solution as described herein. membrane. Some si-0-Μ films (such as Si-0-Cu and Si-O-Bi) were produced and the measurement results showed that they were electrically conductive. Preliminary results demonstrate low-cost, high growth rate RTWCG Si〇M films (wherein, including but not limited to, metal components) provide a good alternative to current state-of-the-art TCO films for thin film solar cells and Various other applications. The main advantages of RTWCG SiOM over current TCO films are: i. room temperature process makes it possible to use temperature sensitive substrates; ii. si〇 due to improved lattice matching with the underlying a-Si layer ]y[Excellent a-Si surface passivation; iii. SiOM TCO is more transparent in the visible spectrum, transparency is higher than 95%; iv. SiOM gradient index and better index matching with the lower a_Si layer yields less than 10 % AM 1.5 AWR ; v. The conductivity of the SiOM film can be adjusted for specific applications, as evidenced by several Si〇Cu and SiOBi SiOM films grown on a c-Si germanium substrate in no more than 1 minute. The resistivity of the film is adjusted in the range of 1 > 1 〇 -3 ohm _ cm 113 201251057 41245pif to lxio · 1 ohm - cm; vi. Because the surface of the RTWCG SiOM can be easily textured, it is easy to achieve light capture; Environmental factors (such as UV radiation, temperature changes) Humidity is more stable; viii. The manufacturing system of SiMO TCO is simple and low cost. The cross section of the a-Si RTWCG SiOM TCO/ARC/SE battery structure is designed using n/i/p standard, with the exception of: ι.η + sacrificial front layer is preferred to make the preferred plastic/screen printing front gate metallization layer /n+/n/i/p/A1/plastic low-cost a_si battery with minimum contact resistance before silver or copper; Wherein the n+ layer is only in contact with the screen printing front grid, and is partially etched back from the surface of the battery before the metallization to form a good quality SE; in. together with SE, other inherent efficiency enhancement features are higher transparency, Low reflectivity, improved collection efficiency, and possibly higher fill factor improvement 'will significantly improve the efficiency of RTWCG SiOM a-Si thin film solar cells; iv. compared to standards from the same basic design category known in the art a -Si battery, high environmental stability. Example 14. RTWCG SiOx on GaAs substrate To a large extent 'research work focused on the characterization of Si0x film grown on Si substrate and the resulting film. However, RTWCG process is also used in Non-amplifier substrates (including GaAs, GaP, AlGaAs, and Various thin film dielectric coatings are produced on CuInSe2 film. 114 201251057 41245pif For example, in a number of chemical systems, a very uniform RTWCG coating is grown on n-type and p-type QaAs substrates. To demonstrate these growths on GaAs substrates. The possibility of coatings, this article provides preliminary room temperature photoluminescence intensity (PLI) for multiple samples in several n-GaAs-like ασ obtained by NASA GRC. )data. The PLI data of the uncoated substrate was compared with the pu data of the same substrate after the growth of the RTWCG coating; the peak intensity of the pl spectrum is shown in FIG. The coating was grown in five different chemical systems designed for the RTWCG SiOx film on Shixia. To achieve consistency, the growth time between 2 minutes and 4 minutes was adjusted to grow similar (about 1 nanometer) oxide thickness on each of the five samples. The data for the two coatings 115-99-2 and 116-99-5 shows a significant increase in PLI compared to the uncoated surface. These experimental data show that room temperature oxides can grow without destroying the GaAs surface. The ιΐ5_99_2 and 116-99-5 coatings show promising purification of the electronic surface of the GaAs surface. The two coatings are suitable for a wide variety of applications, including passivation/first layer ARC of space solar cells, and many other electronic and microelectronic applications, such as gate oxides of GaAs-based integrated CMOS components. As described above, the dielectric coating of RTWCG on GaAs has not been studied intensively as the RTWCG SiOx film on the ruthenium substrate. Preliminary research mainly uses old 2-inch GaAs substrates and some small-area GaAs solar cells. In addition, the RTWCG chemical system formulation based on the Ga_As_〇 thin film dielectric layer on GaAs (see Fig. 36) is the same formulation for growing RTwc(} SiOx film on the Shixi substrate. However, in recent years, it has been found Various GaAs 115 201251057 41245pif specific additives 'including (but not limited to) various precursors and ruthenium precursors, S2 〇 3 As2 〇 5, AsCl 3 and Ga 2 〇 3. These prior art growth solutions for RTWCG on GaAs Increasing the uniformity, growth rate and adhesion of the obtained film. It should be noted that when the addition of yttrium based on As is used, not only the growth rate of the Ga-As-O oxide containing As is increased to as high as 120 nm/min. Moreover, the thermal stability of the film is significantly improved. When the GaAs sample of the RTWCG oxide is heated to 5 〇〇〇c, no observable change in thickness occurs. λ In a preferred embodiment of one or more embodiments For solar cell applications, a low-cost growth solution consists of 2 g to 5 g of Asl3 dissolved in HF (aqueous solution). Within 1 minute, a highly uniform film can be grown, and the pot has good n+-GaAs passivation capability, such as Small area The 42 mV Voc increase of the n+/p GaAs homojunction cell indicates that the cell also produces an increase in Pmax of up to 62.5 °/〇 after coating. The following references are incorporated herein by reference in their entirety: Han Xiangmin (Sang M. Han) and Eray S. Aydil, "Reason f0I·i〇wer dielectric constant of fluorinated SiO 2 films" Journal of Applied Physics, Vol. 83, No. 4, February 15, 1998, pp. 2172-2178. CF Yeh, SSin (SSLin) and T_Y _Hong (TY

Hong), "The low temperature addition of liquid-deposited SiO2-xFx as a gate insulator

Low-Temperature Processed MOSFET's with Liquid Phase Deposited Si〇2-x Fx as Gate Insulator), IEEE 116 201251057 41245pif IEEE Electron Device Letters, 16 (7), 316 (1995) Huang Qianxi (Chien -Jung Huang), Quality Optimization of Liquid Phase Deposition Si02 Films on Silicon, Jpn. J. Appl. Phys_, 41 (2002) ) 4622-4625 page Faur et al., "Room Temperature Wet Chemical Growth Process of SiO-Based Oxides on Silicon", US Patent No. 6,080,683, July 2000. Faur et al., "Method of Making Thin Film Dielectrics Using a Process for Room Temperature Wet Chemical Growth of SiO on a Substrate at Room Temperature Wet Chemical Growth of SiO Based Oxide Processes" Based on Oxides on a Substrate), U.S. Patent No. 6,593,077, July 15, 2003. Faur et al., "Low metallic Impurity SiO Thin Film Dielectrics on Semiconductor Substrates Using a Room Temperature using a room temperature wet chemical growth process, a low metal impurity SiO thin film dielectric layer obtained on a semiconductor substrate. Wet Chemical Growth Process, Method and Applications Thereof), U.S. Patent No. 6,613,697, September 2003. EYWang, FTS Yu, VL Sims, E_W. EW Brandhorst and JD Broder, "Anti-solar battery resistance 117 Optimum Design of Anti-reflection coating for silicon solar cells, Conference Record, 10th IEEE Photovoltaic Specialists Conference, 1973, 168 -171 pages. Daniel N. Wright, Erik S. Marstein and Arve Holt, double-layer anti-reflective coating for Shi Xi solar cells (Double Layer Anti-Reflective Coatings for Silicon Solar Cells), 0-7803-8707-4/05/$20.00 ◎2005 IEEE, pp. 1237-1240. D. Bauhaus, A. Moussi, A. Chikouche, JM Ruiz, "Anti-Reflective Coating Systems for Optoelectronic Components" Design and simulation of antireflection coating systems for optoelectronic devices: Application to silicon solar cells, Solar Energy Materials and Solar Cells, 52, 1998, pp. 79- 93 pages. M. Cid, N. Stem, C. Brunetti, AF Beloto, CAS Ramos "Improvements in anti-reflection coatings for high efficiency silicon solar cells", Surface and Coatings Technology, 106, 1998, p. 117 -120 pages. BS Richards, single material Ti02 double layer anti-118 201251057 41245pif reflective coating "Single-material Ti〇2 double-layer antireflection coatings", solar energy materials and solar cells (Solar Energy Materials & Solar Cells), 79, 2003, pp. 369-390. BS Richards, SF Roland (8. Rowlands only), CB Β·Honsberg, JE Cotter, Ti02 DLAR coating for planar tantalum solar cells (Ti02 DLAR coatings for planar silicon solar cells, Progress in Photovoltaics: Research and Applications, Vol. 11, No. 1, pp. 27-32, published online: December 16, 2002. Shui-Yang Lien, Dong-Sing Wuu, Wen-Chang Yeh and Jun-Chin Liu, three-layer anti-solar technology for solar cells using sol-gel technology Reflective coating (Si〇2/Si〇2~Ti02/Ti〇2) (Tri-layer antireflection coatings (Si02/Si02 Ti02/Ti〇2) for silicon solar cells using a sol-gel technique ), solar materials and the sun Solar Energy Materials and Solar Cells, Vol. 90, No. 16, October 16, 2006, pp. 2710-2719. K丄.Jiao, W_A. Anderson, SiO2/Ti02 double-layer anti-reflection for metal/insulator/n-Si/p-Si solar cells deposited at room temperature Si02/Ti02 double-layer antireflective coating deposited at room temperature for metal/insulator/n-Si/p-Si solar cells, Solar Cells 22, pp. 229-236 (1987). 119 201251057 41245pif DJ Aiken, High performance anti-reflection coatings for broadband multi-junction solar cells, solar bar soap material and sun Solar Energy Materials & Solar Cells 64, pp. 393-404 (2000). M. Kuo et al., Optics Letters 33 (21), 2527 (2008). M. LIPlASKI, S. KLUSKA, H. CZTERNASTEK, P. Zeba (P. ΖΙξΒΑ), for solar cells Graded SiOxNy layers as antireflection coatings for solar cells application, Materials Science-Poland, 24 (4), pp. 1009-1016, 2006. Mason, N., 2009, "High efficiency crystalline silicon PV cell manufacture: status and prospects", PVSAT-5, Glyndwr, Wales. Mai, L. (Mai, L.) et al., 2006, "New emitter design and metal contact for screen printed solar cell front surfaces", 4th IEEE World Conf. on Photovoltaic Energy Conversion, Hawaii, USA (USA). Tajuno, B. (Tjahjono, B.) et al., 2008, "High efficiency solar cell structures through the use of laser doping" by using laser 120 201251057 41245pif 23rd EUPVSEC (23rd EUPVSEC), Valencia, Spain. Hirshman, W., 2008, "Banking on selective research", Photon International, 3rd edition, p. 91. Booker, F., et al., 2008, "Two-step diffusion step selective emitter: comparing two diffusion step selective emitters: comparison of mask opening By laser or etching paste), 23rd EUPVSEC (23rd EUPVSEC), Valencia (Spain). Ν·B. Mason, T. Μ· Bruton and MA. Balbuena, European PV-PV technology to energy solution (PV in Europe-From PV Technology to Energy Solutions), Rome, Italy (2002) 227. WP Mulligan, DH Rose, MJ Cudzinovic, etc., Proceedings of the 19th European Photovoltaic Solar Energy Conference , Paris, France (2004) 387. M. Tanaka, S. Okamoto, S. Tsuge, et al., Proceedings of the 3rd World Conference on Photovoltaic 121 201251057 41245pif

Energy Conversion), Osaka (Osaka), Japan (2003) 955. U.S. Patent Nos. 4,332,973 and 4,409,422 and 4,516,314. Maria Faur, Mircea Faur, SG Bailey, DJ J. Flood, DJ Brinker, Η.Μ. HM Faur, SA Alterovitz, DR Wheeler and DL Boyd, "Room for anti-reflective coatings for Si-based solar cells Room Temperature Wet Chemical Growth of Passivating/Antireflection Coatings for Si-Based Solar Cells, Proceedings at the 2nd World Conference and Exhibition on Photovoltaic Energy Conversion ) , 2000, Vienna, Austria, p. 1574. B丄Sater, "Recent Results on High Intensity Silicon VMJ Cell", Proc. at the American Solar Energy Conference, Minnesota (Minnesota), July 15, July 20, 1995. J. Libal et al., n-type polycrystalline silicon solar cells, BBr3 diffusion and passivation of p+ diffused silicon surfaces, 20th EU-PVSEC (20th 122 201251057 41245pif EU_PVSEC), Barcelona, 2005, pp. 793-796. In the course of reviewing the present invention, it will be appreciated by those skilled in the art that modifications and equivalent substitutions may be made without departing from the spirit of the invention. Therefore, the present invention is not intended to be limited to the embodiments disclosed herein, but only by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of a KTWCG Si〇x ARC/SE/T〇 crystal solar cell design developed by Specmat, Inc. Figure 2 depicts the rTwcg SiOx ARC/SE/TO fabrication steps. Figure 3 is a plot of the net majority donor concentration depth profile for the bend and tail of the RTwcG SiOX ARC/SE/TO single crystal tantalum solar cell design. Figure 4 is an intended belt-type diffusion device that shields the edge of the substrate and simultaneously produces a good quality n+ diffusion layer and diffusion layer on the opposite side of the Shihua wafer. Figure 5 is a SEM image of a uniform 4 Å nanometer RTWCG Si〇x film grown on a semiconductor grade c-Si substrate. Figure 6 (a) is a Nomsky micrograph (XI, 100) of a Si〇x film grown on the surface of a pyramid-covered n+ c_Si. Figure 6 (b) is a Norma micrograph (XI, 100) of a Si〇x film grown on a porous tantalum substrate. Figure 7 is an XPS depth profile 123 201251057 41245pif curve for a prior art RTWCG SiOx film. Figure 8 shows the modified AES depth profile of the SiOx film after removal of all organic components. Figure 9 (a) shows an XPS surface study of an as-grown SiOx film with only traces of metallic impurities. Figure 9 (b) is the XPS depth profile of the film in Figure 9 (a). The oxygen concentration gradually decreases with depth, while the strontium concentration gradually increases with depth. Figure 1 shows the XPS depth profile of the RTWCG SiOx film. After the short temperature and the etch step, the Fe and Ti impurity levels of the sample fall below the detection limit of the instrument. Figure 11 is an XPS depth profile of the main components of the RTWCG SiOx film grown using the RTWCG SiOx solution formulation consisting of 2 parts by volume of H2TiF6 (aqueous solution), 2 parts by volume of gelatinous dioxide supersaturated with cerium oxide.矽 and 1 part by volume of 10% K3Fe(CN)6 (aqueous solution) 〇 Figure 12 is an xps 5 woody distribution curve of the main component of the low-metal impurity RTWCG SiOx film grown using the RTWCG solution formulation consisting of the following materials. 70% by volume NH^SiFy water soluble "〇, 2 parts by volume 60% H2TiF6 (aqueous solution) λ 2 parts by volume 10% K3Fe(CN)6 (aqueous solution) and 3 parts by volume by dissolving 10 g of Co(OH)2 in 1 liter of a solution prepared in 10% HCl (water solution). Figure 13 is an xps depth profile of the main components of a 400 nm thick low metal impurity RTWCG SiOx film grown on an n+ c-Si substrate using the following materials: 2 parts by volume 60% H2TiF6 (aqueous solution), 2 parts by volume 5 % K3Fe(CN)6 (aqueous solution) 3 parts by volume H20. 124 201251057 41245pif Figure 14 is an XPS depth profile of the main components of a low metal impurity RTWCG si〇x film grown on an n+ c-Si substrate using an RTWCG solution formulation consisting of: i parts by volume - 3 parts by volume 6〇% 1^6 (water) and 1 part by volume _3 parts by volume M gram v2 〇 5 / liter 1 〇 % HC1 (aqueous solution) 〇 Figure 15 is the use of ultra-low cost rtwcq solution formulation composed of the following substances XPS depth profile of the main component of the low-metal impurity RTWCG SiOx film grown on the n+ C-Si substrate: 丨 'volume ι 〇 克 〇 Ti〇 2 anatase dissolved in 2 〇〇 / 0 HF (aqueous solution > The solution in solution and 1 part by volume of 3.5 gram % 〇5 are dissolved in a solution of 〇 〇 Η α (aqueous solution). Figure 16 shows the growth metal of RTWCG growth solution in different concentrations of V 2 〇 5 dissolved in 50% HF (aqueous solution). Blue 13 〇 nano _15 〇 nanometer thickness & 〇 图 〇 膜 膜 膜 膜 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The xps depth profile of the component. Figure 17 (b) shows the RTWCG grown in a growth solution such as Figure 16. The v 2p peak of the SiOx film. Figure 18 is found in the RTWCG Si〇x film grown in a growth solution prepared by dissolving 1.7 g of νζ〇5 per liter of 〇5Η%Η]ρ(^_^) in 30 seconds. The SIMS diffusion profile of the main non-metallic impurities. Figure 19 shows the time required to grow a 130 nm-150 nm thick RTWCG SiOx film on a heavily doped disc substrate and dissolved in 5 % HF (aqueous solution). Curve of the normalized amount of Pb 〇 2 in the middle. 125 201251057 41245pif Figure 20 shows the net majority carrier concentration depth profile of the emitter belonging to the sample cut from the same n+/pFZc-Si wafer, which is shown in 1〇 second

SiOx growth time and active response after 4 seconds of growth time. The distribution curve was obtained by a diffusion resistance analysis method after removing the obtained RTWCG Si0x film. Figure 21 (a) is a typical Nomsky diagram of a solar cell coated with a pyramid before RTWCGSi0x, and Figure 21 (b) is a typical Nomsky diagram of a c-Si solar cell coated with a pyramid after RTWCGSi〇x, 21 (c) is a typical DeCarter surface profile of the bare n+/p c_Si structure coated with the pyramid in Figure 21 (a). Figure 22 shows the reflectance curves of the better S1Nx ARC and the two unoptimized RTWCG SiOx ARC obtained by the Independent Solar Cell Research and Development Laboratory. Figure 23 is a group of n+/p diffused c_Si structures coated with RTWCG SiOX (as in Figure 3) along with long-term (seconds) curve of SiOXs. Figure 24 is flat in the fast growing RTWCG Si〇x solution. The group of textured & reflectance curves grown on the n+/p c-Si substrate of the emitter. Figure 25 (a) shows the refractive index of the high growth rate of Si*x film (such as 13) in low metal impurities. And the curve of the extinction coefficient and the wavelength. Figure 25 (b) is the curve of the refractive index and the extinction coefficient wavelength of the film enriched with Shi Xi. Figure 26 shows the emitter from the unmetallized period during the growth of RTWCG 126 201251057 41245pif emitter Dekater distribution curve of thickness. Diffusion (pB/s has two C_Si and a mc_Si disc expansion of the emitter, 1, ·, the thin layer resistivity film with the growth time of si〇xFig. 28 AFM surface topography before (left) and after (right) for 5 seconds in RTWCG SiOx (aqueous solution) grown on a solar, grade c_Si substrate. A f 29 (aD is A1/growth RTWCG SiOX/Si/Ti -Au M0S Capacitor is typically [V characteristic at (-) 110 volts to +11 偏压 bias voltage [Fig. = a) (ii) is A1/growth The typical RTWCG Si〇x/si/Ti Au m〇s electric grid is grown in a typical nano-thick film at a bias voltage of 3 volts to +3 volts in a solution such as that in Figure 13. Features, 110 Figure 29 (b) is a c_v curve of the MOS capacitor of Figure 29 (a). Figure 30 is a heat treatment in air at 100 Torr for an hour, followed by heat treatment at 2 ° C for 1 hour and After that, the A1/growth bear si〇x /p-Si/Au: Ti MOS capacitor (Si0x thickness: about 1 〇〇 ^ m, front gate area: 0_049 cm ^ 2) IV characteristics. Figure 31 is exposed to high Strength (approx. 5 watts / cm ^ 2 ) IV characteristics of A1/RTWCg SiOx/Si/Au:Ti MOS capacitors stored at room temperature before and after six hours of exposure to uv. Si〇x thickness: approx. 12〇 Fig. 32 (a) and Fig. 32 (b) are high-density tantalum plasma at 2xl〇5/cubic centimeter, electron temperature of 1.7 eV, plasma potential of 98 volts and 6χ1〇_5 Torr. After 20 minutes in the residual pressure of the gas (Xe), the IV curve of the 2吋P-Si wafer of 127 201251057 41245pif thick SiOx was coated. The IV curve was obtained after 20 minutes of plasma exposure: (a)-100 Volt up to +100 ; (B) +100 volts to -100 volts pmax is 0 in the FIG. 33 6 n + / p c-Si solar cells in the table before and after growth RTWCG SiOx deviation. Figure 34 shows the external and internal quantum efficiency and reflectance curves of large-area (6”) fabricated mc-Si solar cells before and after RTWCG SiOx ARC/SE and the SiOx-coated cells in standard EVA packaged into micromodules. Reflectance curve after. Figure 35 is a cross-sectional view of the design of a rectangular W-Cy SiOx ARC/SE/TO n++pp++ or p++nn++ double-sided C-Si, mc-Si or polycrystalline silicon cell. Figure 36 shows the RTWCG SiOx ARC. /SE/TO n++pp++ or p++nn++ Cross-sectional views of c-si'mc-si or polycrystalline tantalum solar cell designs for front and back passivation and partial back contact. Figure 37 shows several n-GaAs samples at RTWCG Relative photoluminescence intensity data before and after Ga-As-Ο. [Main component symbol description] 100: Solar cell 110: Front contact 120: Selective emitter layer 130: ARC Coating 135: Textured oxide surface 140 : Wafer / Substrate / Substrate 128 201251057 41245pif 150 : Post Contact 200 : Cut Substrate Surface / Cut Substrate 210 : Emitter Layer 220 : Front Gate Wire 230 : Metallized Contact 250 : RTWCG SiOx Film 300 : Line 310 : Line 400 : Conveyor-type diffusion device 410 : 矽 wafer 415 : semiconductor-grade ceramic plate 420 : Semiconductor grade ceramic plate 430 : Lower diffusion chamber 440 : Upper stainless steel member 129

Claims (1)

201251057 41245pif VII. Patent Application Range: Growth Based on Oxide L A composition for a wet chemical layer on a substrate at room temperature, including an acidic aqueous solution of each fluoride; and an inorganic substance containing one or more of the following elements Reduction Oxidation System: Yuanqing Y'Zr^Nb>Ru.Rh.Fe, Ba^b ''Ni'S-Cu^Ce Be, Bl, Hf, Ta, W, selected from Ti, Co, v, and c-vector groups La, Ir, 〇s and, Sn 'Ag and Mg; the composition of Danjia is substantially free of bismuth. 2. A composition for a wet layer at room temperature on a substrate, comprising: an acidic aqueous solution of an oxygen-containing fluoride; and an inorganic reducing oxidation system mSb, Be, CHf] W containing - or a plurality of elements (4) , La, Ag, Ir, 0s, As, Sl^Mg. 3. The article for use in the layer of wet chemically grown wad-wet on the substrate as claimed in claim 2, wherein the constituent shirt comprises a sputum source. 4. The composition of the oxide-based layer for wet chemical growth at room temperature on a substrate as described in U.S. Patent No. 3, wherein the source of the towel is made of colloidal oxidized slag saturated with Si〇2, Selected from the group consisting of H2SiF6 and metal Wei salt. 5. The composition for chemically growing an oxide-based layer at room temperature on substrate 130 201251057 41245pif as described in paragraphs 1 to 4 of the patent scope, the source of which is I^SiF6, NHJ 'HF Selected from the group consisting of postal, BaF, BF4, trace and other metal and non-metallic fluorides. - 6. The composition for chemically growing an oxide-based layer on a substrate to a temperature and humidity according to the above-mentioned items of the invention, further comprising an element of the inorganic reducing oxidation system and promoting the A catalyst that reduces oxygen and also reacts with oxygen. Special Wei (four) 6-ton secrets on the 撼 室温 室温 室温 学生 学生 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏 魏The composition for chemically growing an oxide-based layer according to Item 7, wherein the group f is prepared by dissolving one or more compounds containing an element of the reducing oxidation system in a fluorine-containing water. Produced in an acidic component. The composition of the invention described in Section 8 of the patent, which is recorded on the substrate at room temperature, wherein the compound consists of a group consisting of 2〇5 and Pb〇2. The composition of the oxide-based layer on the substrate as described in claim 8 is wherein the compound consists of 2 5, 205, Pb 〇 2, C () 3〇4, Nb〇, Nb〇2, Nb2〇5, e^〇4, and Fe2〇3 are selected from the group consisting of u !*!_' as stated in items 1 to 10 of the scope of the patent application. A composition for growing an oxide-based layer in a base-to-wet chemical, further comprising 131 201251057 41245pif Co(〇H)2, 12. The composition for wet chemically growing an oxide-based layer on a substrate at room temperature, wherein the aqueous solution comprises KTiF6 or HF, and the reducing oxidation system comprises (4), wherein the composition does not contain a unit Or the composition of the oxide-based layer for chemically growing the room temperature on the substrate, as described in claim 1, the aqueous solution package, HJiF6 or HF' The reduced oxidation system comprises % 〇5, wherein the composition is free of organic components or lanthanum. The utility model is used in the base water, chemistry as described in the first or second item of the patent. A composition for growing an oxide-based layer, wherein the aqueous solution comprises HF, and the reduced oxidation system comprises pb〇2. 柘i i5: Tian Ru Shen ° month patent | & circumference 1 or 2 The phase composition for use in the base water, the chemical student, and the subtractive material, wherein the water is included, and the reducing oxidation system comprises 1205. a composition comprising a layer of HF sputum at room temperature, wherein the aqueous solution package And the reduced oxidation system comprises a composition for coating a layer of an oxide in the base compound according to items 1 to 16 of the crucible, and further comprising a base formed on the gold plate; After the oxygen cutting plate, the composition is used in the base temperature and humidity: the composition for the oxide-based layer on the substrate, as described in Item 17, wherein the metallization 132 201251057 41245pif compound is A metal nitride, a metal vapor, and a metal vapor. 19. The composition for growing an oxide-based layer on a substrate upper chamber according to claim 18, wherein the metal nitrogen = by, ^ . The family of nitrides of ..., ... is selected from the ' and the metal chloride and the metal fluoride are selected from the group based on the group. 1, U and called chloride and fluoride group 2f · A method for preparing a doped semiconductor layer, comprising: providing a semiconducting plate with a doped layer; and engraving the student long solution 'to simultaneously money and growth Balanced to "the method of preparing the anti-reflective coating on the doped semiconductor layer, the semiconductor substrate with the doped layer; and the etching of the doped layer by the B- Temple: temperature and humidity chemical growth The solution 'haves the same layer as the ladder growth oxide layer, the oxidation rate, wherein the refractive layer within the equilibrium range of engraving and growth is selected. The oxygen is provided for the preselected characteristics, which is used in the substrate item and the 21st The method of the present invention comprises the acidity of the fluoride, the group based on the composition of the constituent elements of the layer of the oxidized stone, and the inorganic reducing oxidation system containing one or more of the following selected elements: Ti, 133 201251057 41245pif c〇, v, Cr, Ni, Sr, Cu, Ce, Y, Zr, NbRu, RhFe, Ba, Pb, Pd, I, Br, δι, qu, ^ Price A^Sb, Be, Bi, Hf , Ta, W, La, Ir, Os, As, Sn, Ag, and Mg. 23. As in the method of (4) patent scopes 2Q to 22, in the preparation of the oxide layer, all of the soot layers on the real f are consumed. 24. See paragraph 2 of the patent application. To the method of item 22, wherein a portion of the thickness of the doped layer is consumed in the preparation of the oxide layer. 25. The method of claim 4, wherein the alternating layer is on a single side of the substrate. 26. The method of claim 24, wherein the hybrid layer is on both sides of the substrate. 2. The method of claim 25, wherein the doped layer is on a side edge of the substrate. 28. The method of claim 2, wherein the f comprises, prior to exposing the _ room temperature wet liquor residue, a portion of the doped layer. ^ 29. The method of claim 2, wherein the photoresist or metallization layer. 30. The method of claim 2, wherein the property is characterized by surface texture, refractive index, oxide thickness, extinction coefficient, rubbing layer consumption, interstitial constant, rate, and chemical composition In the Syrian group, the method described in the second to fourth aspects of the patent application, 134 201251057 41245pif wherein the surface of the doped layer after exposure is relative to the doped layer at the beginning A few ship's concentration is reduced, and the four-layer thin layer resistance of the _ layer is increased. The method of claim 2, wherein the substrate comprises ruthenium and the oxide layer comprises Si 〇 x. The method of claim 32, wherein the layer having a composition has a composition gradient of a small oxide composition on the side of the oxide layer at the surface of the oxide layer. 34. The method of claim 32, wherein the layer forms a passivation layer. The method of claim 32, wherein the dopant of the oxide layer is reduced relative to the doped layer after exposure to the room temperature wet chemical growth solution. The method of claim 33, wherein the surface comprises at least 5% oxygen at the surface of the layer and substantially no oxygen at the telluride conductor interface. 37. The method of claim 2, wherein the method further comprises exposing the substrate to a room temperature humidified student solution comprising a metal additive, wherein the conductive oxide film is grown. The method of claim 37, wherein the metal additive comprises a metal nitrogen selected from the group consisting of Bi, Ti, c, Cu, & a metal chloride and a metal fluoride selected from the group consisting of chlorides and fluorides based on Bi, Ti, C〇, V, Ce, Ab La and ]vig. 39. The method of claim 37, wherein the additive comprises a butterfly source selected from the group consisting of H3B〇4, B2〇3, BI3 or a group. 40. A method of processing an electronic component, comprising: providing a substrate having an emitter layer; and at least exposing the emitter layer to a room temperature wet chemical growth solution to simultaneously etch the emitter layer and from the The emitter layer grows a SiOx layer, wherein at least a portion of the emitter layer is removed. 41. The method of processing an electronic component of claim 40, wherein the emitter layer is on a front surface of the component. 42. The method of processing an electronic component as claimed in claim 40, wherein the emitter layer is on a rear surface of the component. The method of processing an electronic component according to claim 40, wherein the emitter layer substantially surrounds the substrate. 44. The processed electronic component of claim 44, wherein the emission interface is separated from a side edge of the substrate. ι 45. If the processing electronic component described in the first paragraph of the patent application, the eighth is from the front or the back of the component, the layer is removed. 46. > The force oral electronic component described in the section wherein the towel portion removes the emitter to provide the SiOx layer on the thinned hair. 47. The force described in claim 46. 136. The method of processing an electronic component according to claim 46, wherein the SiOx layer is located on the incident surface of the component and is used as an anti-reflective coating. The method of processing an electronic component according to claim 46, further comprising: exposing the emitter layer to the surface of the device A mask is applied to the emitter layer before the room temperature wet chemical growth solution. The method of processing an electronic component according to claim 49, wherein the mask is a metallized contact or a resist. 51. If the scope of patent application is the fourth item The method of processing electronic components is used to achieve - or more of the following: generating a selective emitter, producing an anti-reflective coating, producing a passivation film, producing a textured anti-reflective coating, removing the emitter, and producing Transparent conductive oxide, oxide-based film, sacrificial layer, thinner emitter, cleaned electronic component surface, = bismuth silicate glass coating, and passivated vertical multi-junction 矽 unmetallized surface. a method of processing a substrate having an emitter layer, comprising: m providing a wire plate, wherein the % substrate has substantially a substrate A face is exposed to the emitter layer to grow the SiOx layer to simultaneously remove the emitter layer and self-defect to obtain an element having a complete emitter face, a 137 201251057 4I24ipif junction separation layer and a purification face. 53. A method of processing a substrate having an emitter layer as described in claim 52, by floating or suspending the substrate in the room temperature wet chemical growth solution solution. 54. A method of processing a substrate having an emitter layer as described in claim 52, wherein any residual slag cullet on the emitter is also removed. 55. A method of processing a substrate having an emitter layer, comprising: providing a substrate having an emitter layer; exposing the emitter layer to a room temperature wet chemical growth solution in a single step to simultaneously etch the At least a portion of the emitter layer and a SiOx layer grown from the emitter layer to obtain an element having a complete emitter face with an anti-reflective or reflective layer disposed thereon. 56. A method of processing a substrate having an emitter layer, comprising: providing a substrate having an emitter layer; exposing the emitter layer to a room temperature wet chemical growth solution in a single step to simultaneously etch the At least a portion of the emitter layer and a Si0x layer are grown from the emitter layer to obtain an element having a complete emitter face with a purification layer disposed thereon. 57. The method of applying the tool of the emitter layer, the method of the substrate of the emitter layer, wherein the (4) and the growth conditions are selected to provide a textured oxide surface, as claimed in the scope of claims 2 to 10. 58. A method of processing a substrate having an emitter crucible as described in claim 56, wherein the growth rate is greater than 2 nanometers per minute. 138. The method of claim 20, wherein the etching and growth conditions are selected to provide a smooth oxide surface. 60. A method of processing a substrate having an emitter layer as described in claim 59, wherein the growth rate is from about 50 nm/min to 2 Å nm/min. 61. A method of processing a substrate having an emitter layer as described in claims 20 to 60 wherein the substrate is selected from the group consisting of: single crystal germanium, polycrystalline germanium, polycrystalline germanium, micro Crystalline and amorphous germanium, ribbons of any crystalline configuration, III-V, I-III_VI and n-VI compound semiconductors, GaAs, CuInSe2 and CdTe, carbon substrates, graphite substrates, carbon fibers and nanocarbons tube. 62. A method of processing a substrate having an emitter layer as described in claim 61, wherein the doped layer is any wafer structure comprising a smooth, textured or porous tantalum surface. 63. A method of processing a substrate having an emitter layer as described in claim 32, wherein the Si〇x layer is produced on the germanium substrate, the substrate comprising a diffusion profile, wherein The dopant concentration of the substrate is increased up to a certain depth and then decreased with depth to a concentration below the surface dopant concentration. 64. A method of processing a substrate having an emitter layer as described in claim 63, wherein the diffusion profile provides a junction depth of from 5 micrometers to 0.65 micrometers and a surface concentration of 5 χ 1 〇 20 per cubic centimeter To 8xl 〇 2G / cubic centimeter and sheet resistance is 25 ohm / square unit to 25 ohm / flat 139 201251057 square unit of the emitter. 65. A method of processing a solar cell, comprising: using a composition for wet chemically growing an oxide-based layer on a substrate at room temperature as described in any one of claims 1 to 20. Coating a solar cell comprising a front contact and a rear contact on the doped layer to etch back the doped layer from the unmetallized surface to form a ruthenium oxide-based resistance on the unmetallized surface of the solar cell A reflective coating, a selective emitter and a junction removed from the edge. 66. A method of processing a solar cell, comprising: coating a composition for wet chemically growing an oxide-based layer on a substrate at any temperature as described in any one of claims 1 to 20. a substrate having a doped layer coated with residual bismuth glass, wherein residual bismuth glass is removed, and the composition reacts with the back and side edges of the substrate wafer to remove from the surface a majority of the doped layer, and a passivation film layer is grown on the back and side edges of the germanium substrate; thereafter, pre-contact and post-contact are deposited on the front and back sides of the substrate and baked; and finally, The front side of the substrate reacts with the composition to produce an anti-reflective coating and a selective emitter, and further reduces any junctions still present on the edges of the substrate. 67. A method of processing a solar cell, comprising: coating a composition for wet chemically growing an oxide-based layer on a substrate at any temperature as described in any one of claims 1 to 2 Covering a germanium substrate having a doped layer coated with residual bismuth glass to grow a ruin-containing passivation film on the surface of the non-gold 140 201251057 HIZHDpiI genus, and removing any remaining from the surface of the substrate and the edge of the substrate The spheroidal acid glass and most of the doped layer; thereafter, the front gate line is deposited, and at 800. (: to 920. Sintering with the back surface point at a high temperature in the range of 〇; thereafter, the front side is used for wet chemistry at room temperature on the substrate as described in any one of the above claims A method of growing a composition of the oxide-based layer to produce an anti-reflective coating, a passivation layer, and a selective emitter. The method of processing a solar cell according to claim 67, wherein the metal The method is formed after the composition is applied to the back surface. 69. A method of manufacturing a double-sided solar cell, comprising: providing a lightly doped initial p-type or n-type single crystal germanium or polycrystalline germanium a wafer, forming a n++ heavily doped layer and a ρ++ heavily doped layer on either side of the wafer; removing residual oxide glass, printing the gate line and the front gate line, and firing, Exposing the substrate to a composition for wet chemically growing an oxide-based layer on a substrate at room temperature as described in any one of claims 1 to 18 to react with the front side and the back side To produce an anti-reflective coating and a selective emitter' while etching An undesired diffusion layer present on the edge of the substrate. 141 201251057 - ri 7 〇. A method of manufacturing a solar cell, comprising: having a doped layer, a front gate line, and using photolithography to generate behind The ruthenium substrate of the small dot region is exposed to a composition for wet chemically growing an oxide-based layer on a substrate at any temperature according to any one of claims 1 to 2 to Simultaneously growing a yttria-based film on the front surface and the non-resistive surface and etch back the unmetallized surface and the non-resistive rear surface; μ removing the photoresist; and forming the doped layer The point regions are in direct contact after contact. 71. A system for creating diffusion on a crucible substrate comprising placing a lower chamber to a wall above the wall to create a diffusion chamber, the diffusion chamber substantially containing a heating element, an upper mask and a lower mask sandwiched on an edge portion of the substrate and possibly positioned between the upper chamber wall or the lower chamber wall or the upper chamber to the wall and the lower chamber wall For spraying and expanding 72. The system for generating diffusion on a germanium substrate according to claim 7 of the patent application, wherein the cut wafer is placed between two semiconductor grade ceramics to protect the edge of the substrate from being recorded. Disperse, and the source starts to deposit at a rapid temperature (耽/min·(10)·c/min) to form a good quality η+diffusion layer and ρ on both opposite faces of the Shihua wafer. + diffusion layer. 142