TW201250019A - Electronic component manufacturing method including step of embedding metal film - Google Patents
Electronic component manufacturing method including step of embedding metal film Download PDFInfo
- Publication number
- TW201250019A TW201250019A TW100122221A TW100122221A TW201250019A TW 201250019 A TW201250019 A TW 201250019A TW 100122221 A TW100122221 A TW 100122221A TW 100122221 A TW100122221 A TW 100122221A TW 201250019 A TW201250019 A TW 201250019A
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- TW
- Taiwan
- Prior art keywords
- target
- film
- barrier layer
- layer
- electrode
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 75
- 239000002184 metal Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims abstract description 142
- 238000004544 sputter deposition Methods 0.000 claims abstract description 49
- 238000000151 deposition Methods 0.000 claims abstract description 27
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000007246 mechanism Effects 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 42
- 238000002844 melting Methods 0.000 claims description 29
- 230000008018 melting Effects 0.000 claims description 28
- 239000010936 titanium Substances 0.000 claims description 22
- 238000012546 transfer Methods 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010408 film Substances 0.000 description 230
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 94
- 239000002356 single layer Substances 0.000 description 93
- 239000000758 substrate Substances 0.000 description 75
- 238000012545 processing Methods 0.000 description 65
- 239000010410 layer Substances 0.000 description 37
- 230000015572 biosynthetic process Effects 0.000 description 28
- 239000007789 gas Substances 0.000 description 25
- 239000002245 particle Substances 0.000 description 22
- 230000008021 deposition Effects 0.000 description 19
- 239000004065 semiconductor Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 15
- 150000004767 nitrides Chemical class 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 14
- 238000010438 heat treatment Methods 0.000 description 12
- 239000011800 void material Substances 0.000 description 12
- 230000006870 function Effects 0.000 description 10
- 238000002441 X-ray diffraction Methods 0.000 description 9
- 238000001816 cooling Methods 0.000 description 9
- 238000005259 measurement Methods 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 230000005012 migration Effects 0.000 description 7
- 238000013508 migration Methods 0.000 description 7
- 230000003746 surface roughness Effects 0.000 description 6
- 239000010409 thin film Substances 0.000 description 6
- 239000011261 inert gas Substances 0.000 description 5
- 229910001092 metal group alloy Inorganic materials 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000011835 investigation Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910001868 water Inorganic materials 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 238000004630 atomic force microscopy Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 241000894007 species Species 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- -1 Ar) Substances 0.000 description 1
- 241001674044 Blattodea Species 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- UYVZCGGFTICJMW-UHFFFAOYSA-N [Ir].[Au] Chemical compound [Ir].[Au] UYVZCGGFTICJMW-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/0641—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
201250019 六、發明說明 【發明所屬之技術領域】 本發明相關於包括嵌入金屬膜之步驟的電子元件製造 方法。 【先前技術】 習知地，半導體積體電路已使用先閘極法，其係在已 將閘極絕緣膜及閘極電極形成在晶圓表面上之後藉由蝕刻 實施處理之方法。最近，MOSFET的閘極絕緣膜隨著元件 的小型化而變得更薄，且當將Si 02膜用於閘極絕緣膜 時，穿隧電流對係最近要求値之2nm或更小的膜厚度產 生，且閘極漏電流增加。因此，最近已硏究以具有高於 Si02膜的介電係數之相對介電係數的高介電係數材料取代 閘極絕緣膜。藉由此方法，甚至在使絕緣膜的實際厚度更 大時，可使Si02-轉變膜厚度（EOT:等效氧化物厚度）更 小。然而，在具有 22nm或更小之閘極長度的最近 MOSFET中’需要將EOT更行縮減。爲滿足此要求，必 需藉由使用高介電係數材料增加絕緣膜的實際厚度，以減 少閘極漏電流。然而，在先閘極法中，源極/汲極形成步 驟係在閘極形成之後實施，且因此閘極絕緣膜及閘極電極 受加熱’而由於該加熱在絕緣膜及金屬膜之間導致熱擴 散，並引發遷移率退化及操作電壓（Vt)偏移發生的問題。 因此，爲解決此等問題，已針對預先形成源極/汲 極’且最後形成閘極絕緣膜及閘極電極的後閘極法實行積 -5- 201250019 極硏發。在此方法中，因爲閘極部係最後形成的，5 加至閘極部的加熱溫度較低，且或許可能抑制已係另 法中之問題的遷移率退化及操作電壓（Vt)偏移。後 的主題係將各種類型的金屣薄膜沈積在具有22nm 的開口及2 2nm或更大之深度的形狀中（在下文中，择 槽），以及將分別沈積在溝槽的側壁及底部上之材和 厚度控制成可取値。另外，因爲堆疊各種類型的途 膜，也需要抑制金屬薄膜之間的相互擴散。 在後閘極法中，形成各種類型金屬薄膜的 CVD(化學氣相沈積）法、原子層吸收/沈積法、# ：§ 法。因爲孕育時間存在於形成處理中，CVD法+醇 可控制性、表面均勻度、以及可重複性上有問題。頂 吸收/沈積法具有優秀的膜厚度可控制性，但在# f 時，成長時間變長，且因爲使用昂貴的來源氣體 本問題。使用來源氣體之化學反應的此等方法各_ 在溝槽底部上，也在側壁上均勻地形成膜，但另一 當使沈積膜厚度更大時，該溝槽變爲具有較窄開口 解決此等問題的方法，已揭示藉由具有優秀膜厚度 性、表面均勻度、以及可重複性的濺鍍法形成各種 金屬薄膜材料的方法。 曰本未審查專利申請案公告（PCT申請案f謂 2004-5 06090號揭示藉由在1托或更高的高壓實 而可如同CVD法在溝槽部的側壁上也形成膜4設 此方法中’濺鍍離子對晶圓表面的指向性係藉^在 Γ使施 £;閘極 3極法 艺更小 I爲溝 的膜 :屬薄 丨包括 :濺鍍 !厚度 (子層 5厚膜 !生成 『不僅 ί面， 作爲 ί控制 ΐ型之 案）第 ί濺鍍 ί。在 ί壓下 201250019 的濺鍍而受抑制，且因此也可能將膜形成在溝槽部的側壁 上。日本專利序號第3 1 93 8 75號揭示在已形成堆疊Ti及 TiN的障壁下層之後，藉由濺鍍法形成用於加速A1膜遷 移的種-A1層，並導致A1在高溫下遷移以嵌入的技術及 設備。此方法顯示可能在藉由堆疊Ti及TiN之障壁下層 抑制A1擴散的同時將A1嵌入該溝槽。 如上文所述，在最近的在極精細型樣上的膜形成中， 堆疊各種類型的金屬薄膜，且因此導致溝槽開口直徑降 低。因此，必需使用甚至在堆疊各種類型的金屬薄膜時可 儘可能地抑制開口直徑降低的金屬薄膜形成技術。另外， 藉由A1擴散，A1嵌入清楚地使使用在閘極電極部中之金 屬膜的特徵退化，且因此需要抑制A1擴散的極薄膜障壁 層形成技術。 然而，上述各技術具有下列問題。 揭示於日本未審查專利申請案公告（PCT申請案的譯 案）第2004-506090號中之在1托或更高之高壓下濺鍍的 方法可將膜形成在溝槽側壁上，但具有當使溝槽開口小於 22nm或更小時，溝槽開口變得更窄的問題。另外，揭示 於日本專利序號第3193875號中的A1嵌入方法具有需要 形成用於抑制A1擴散之堆疊Ti及TiN的厚障壁膜之問 題。再者，因爲將用於加速A1遷移的種-A1層另外形成 在堆疊Ti及TiN的障壁膜上，有溝槽開口窄化的問題。 【發明內容】 -7- 201250019 本發明的目的係提供電子元件製造方法，包括將金屬 膜（例如，A1)嵌入凹部（例如，溝槽）中的步驟，該方法可 抑制形成在基材上之凹部的開口縮減，並可形成能抑制待 嵌入金屬擴散的障壁膜》 由於爲解決上述問題的熱切硏究，本發明人已發現藉 由使用本發明的沈積設備可將極薄TiN單層障壁膜形成在 形成於基材上的凹部（例如，溝槽部）中，且甚至可不使用 種-A1層而另外在TiN單層膜上實施A1嵌入，並已到達 本發明的完成。 本發明的第一實施樣態係電子元件製造方法，包含： 在將尖磁場形成在靶材表面上的同時，藉由濺鍍法將 包括氮化鈦的單障壁層沈積在形成於待處理物件上之凹部 中的第一步驟；以及在容許低熔點金屬層流動的溫度條件 下，將該低熔點金屬層直接塡補在該單障壁層上的第二步 驟。 在此種組態中，可能不降低開口直徑，或甚至在具有 2 2 nm或更小之開口直徑的精細溝槽中，藉由抑制開口直 徑的降低，而將A1嵌入。 本發明之第二實施樣態係電子元件製造方法，包含： 濺鍍·機構，包括與高頻電源連接並能載置靶材的靶材電 極，以及組態成當將該靶材載置在該靶材電極上時，將尖 磁場形成在該靶材之表面上的磁鐵單元；以及控制單元， 控制該濺鍍機構，其中當將包含鈦或氮化鈦之靶材設置在 該靶材電極上並將障壁層形成在形成於待處理物件上的凹 -8 ~ 201250019 部中時，將該控制單元組態成控制該濺鑛機構，使得將包 含氮化鈦之單障壁層形成在該凹部中。 本發明之第三實施樣態係電子元件製造方法，包含： 第一濺鍍設備，包括：第一濺鍍機構，具有與第一高頻電 源連接並能載置靶材的第一靶材電極，以及組態成當將該 靶材載置在該第一靶材電極上時，將尖磁場形成在該靶材 之表面上的第一磁鐵單元；以及第一控制單元，組態成控 制該第一濺鍍機構，使得當將包含鈦或氮化鈦之靶材設置 在該第一靶材電極上並將障壁層形成在形成於待處理物件 上的凹部中時，將包含氮化鈦之單障壁層形成在該凹部 中；以及第二濺鍍設備，包括：第二濺鍍機構，具有與第 二高頻電源連接並能載置靶材的第二靶材電極，以及組態 成當將該靶材載置在該第二靶材電極上時，將尖磁場形成 在該靶材之表面上的第二磁鐵單元；以及第二控制單元， 組態成控制該第二濺鍍機構，當將包含該低熔點金屬的靶 材設置在該第二靶材電極上並將該低熔點金屬嵌入在形成 該單障壁層的該凹部中時，將低熔點金屬層直接形成在該 單障壁層上並在容許該低熔點金屬層流動的溫度條件下將 該低熔點金屬嵌入在該凹部中。 本發明的第四實施樣態係電子元件，包含：構件，包 括凹部；電極層，形成在該凹部內；低熔點金屬層，嵌入 在該凹部內；以及障壁層，形成在該低熔點金屬層及該電 極層之間並包括氮化鈦，該障壁層具有（220)定向。 根據本發明，藉由將極薄TiN單層障壁膜形成在形成 -9 - 201250019 於基材上的凹部（例如，溝槽）內，並將低熔點金屬（例 如，A1)嵌在該TiN單層障壁膜上，例如，在導致TiN單 層障壁膜具有抑制該低熔點金屬擴散入上層之可取障壁性 質的同時，可能不降低開口直徑，或甚至在具有22nm或 更小之開口直徑的精細凹部中，藉由抑制開口直徑的降 低，而嵌入該低熔點金屬（例如，A1)。因此，當將包括嵌 入金屬膜之步驟的本發明之電子元件製造方法又施用至佈 線步驟的製造方法時，可能不降低開口直徑，或藉由抑制 在具有22nm或更小之開口直徑的精細凹部中之開口直徑 的降低，而嵌入A1。 【實施方式】 在下文中，將根據該等圖式詳細地解釋本發明的實施 例。 由於爲解決上述問題的熱切硏究，本發明人已發現包 括藉由形成極薄TiN單層障壁膜並將A1嵌在TiN單層障 壁膜上，使用可抑制溝槽開口縮減並抑制A1擴散的障壁 膜而將A1嵌入溝槽部中之步驟的電子元件製造方法。 圖1顯示根據本發明之實施例的設備之輪廓，其使用 在將作爲障壁層之氮化鈦膜形成在形成於基材上的凹部 (例如’溝槽）內的第一步驟中，以及將作爲低熔點金屬層 之A1膜形成在形成於凹部內之氮化鈦膜上，以將A1嵌入 凹部中的第二步驟中。 根據本發明之货施例的半導體製造設備1 00包括具有 -10- 201250019 上電極401及下電極301的室201，如圖1所示。室201 的功能如同真空處理容器並具有連接至連同自動壓力控制 機制（APC)431用於將室201內側排空之排放埠205的真 空排放泵410。上電極401經由匹配箱101連接有上電極 高頻電源102及DC電源103。另外，下電極301經由匹 配箱304連接有下電極高頻電源305。 室201具有近似圓柱的形狀並包括具有近似碟狀形狀 的上壁（頂壁）202、具有近似圓柱形狀的側壁203、以及具 有近似碟狀形狀的底壁204。將用於量測壓力的壓力指示 器430(例如，隔膜壓力計）設置在室201內的側壁203周 圍。將壓力指示器43 0電性連接至組態成能依據由壓力指 示器430量測的壓力値自動地控制室201內之壓力的自動 壓力控制機制4 3 1。 上電極401具有上壁202、磁鐵機制405、靶材電極 (第一電極）402、絕緣器404、以及屏蔽403。將磁鐵機制 40 5設置在上壁2 02下方，並將靶材電極4 02設置在磁鐵 機制405下方。另外，絕緣器404將靶材電極402與室 201的側壁絕緣，並也將靶材電極402保持在室201內。 再者，將屏蔽4 03設置在絕緣器4 04下方。此處，靶材電 極402經由匹配箱101連接有上電極高頻電源102及DC 電源1 03。靶材電極402的主部位係由非磁性材料製造， 諸如Al、SUS、以及Cu。將膜形成在基材3 06上所需之 材料靶材構件（未顯示在圖式中）可設置在靶材電極402的 降壓側（基材側）上。另外，將管線配置形成在上電極40 1 -11 - 201250019 及靶材電極402中，且上電極401及靶材電極402可藉由 在此管線配置中流動的冷卻水冷卻。 磁鐵機制4〇5具有磁鐵支撐板407、由磁鐵支撐板 407支撐的複數個磁鐵片406、以及設置在複數個磁鐵片 406之周長最外側上的磁場調整磁性體408。此處，將磁 鐵機制40’5組態成藉由未顯示於圖式中的旋轉機制將材料 靶材的中心軸使用爲旋轉軸而可旋轉。將複數個磁鐵片 406設置成在靶材402上方彼此相鄰，以配置成與靶材電 極402的表面平行。相鄰磁鐵片406形成用於控制電漿的 封閉點-尖磁場41 1。將磁場調整磁性體408延伸成與位 於靶材電極402側上之外圓周側上的磁鐵片406部分地重 疊。藉由此種組態，可能抑制（控制）在靶材電極402及屏 蔽403間之間隙中的磁場強度。 下電極301具有台保持器3 02、冷卻/加熱機制412、 底壁204、以及第二電極絕緣器303。台保持器302係用 於載置基材3 06的單元，並於其中設有冷卻/加熱機制 4 1 2。可藉由冷卻/加熱機制4 1 2將基材的溫度（基材溫度） 控制至預定溫度。第二電極絕緣器303係用於支撐台保持 器3 02及室201之底壁2 04而使彼等彼此絕緣的單元。另 外，台保持器302經由匹配箱304連接有下電極高頻電源 305。此處，台保持器3 02設有未顯示於圖式中之具有單 極電極的靜電吸收單元，且此單極電極連接有DC電源 (未顯示於圖式中）。另外，台保持器3 02設有未顯示於圖 示中之用於控制基材3 06的溫度之供應氣體至基材3 06的 -12- 201250019 背側之複數個氣體（例如，惰性氣體，諸如Ar)注入埠，以 及用於量測基材溫度之基材溫度量測單元。 在室201內側，設置用於將處理氣體，諸如氬，供應 至室201中的複數個氣體導入埠409。 參考圖2，將詳細地解釋磁鐵機制405的形狀。圖2 係從靶材電極402側觀看時，磁鐵機制405的平面圖。如 圖2所示，環狀形狀的磁場調整磁性體408及設置在磁場 調整磁性體40 8之內圓周區域中的磁鐵片4 06係藉由碟狀 磁鐵支撐體407支撐並設置於其。此處，在圖2中，參考 數字403a指示屏蔽403的內直徑且許多小圓指示個別磁 鐵片406的外形。另外，各磁鐵片406具有相同形狀及相 同磁通密度。再者，字母N及S分別指示從靶材電極40 2 側觀看時，磁鐵片406的磁極。 將磁鐵片406配置在以具有彼此大致相同之間距（在 5至lOOnm的範圍中）的格型樣（在X-軸方向及γ-軸方向 上）上。以此方式將複數個磁鐵片406各者設置在多邊形 格的格點上。相鄰磁鐵片406具有彼此相反的極性。同 時，在包括沿著X-軸方向及Y-軸方向配置之任意四個磁 鐵片406的長方形中，沿著對角方向彼此相鄰之磁鐵片 4 0 6的極性彼此相同。亦即，任何四個相鄰磁鐵片4 0 6在 靶材表面上形成點-尖磁場（在下文中，稱爲PCM)411。半 導體製造設備100可用此方式形成PCM ,且因此有時稱 爲PCM濺鍍設備或PCM處理設備。 磁鐡片406的高度典型地大於2mm且其橫剖面形狀 -13- 201250019 爲長方形或圓形。磁鐵片406的直徑、高度、及材料可依 據處理應用選擇性地設定。當將高頻電力施加至半導體製 造設備1 〇〇的上電極40 1時’電漿經由電容-耦合型機制 產生。此電漿受封閉點-尖磁場41 I的動作控制。 將磁場調整磁性體408延伸成與位於靶材電極402側 上之外圓周側上的磁鐵片406部分地重疊。因此，靶材電 極402及屏蔽403間之間隙中的磁場強度可受抑制（控 制）。例如，磁場調整磁性體408可能以可控制靶材電極 4 02及屏蔽403間之磁場強度的材料製造，或以高磁透性 材料製造爲佳，諸如SUS430。磁鐵機制405可藉由調整 磁鐵片406及磁場調整磁性體408彼此重疊的區域調整磁 場。亦即，當調整磁鐵片406及磁場調整磁性體408彼此 重疊的區域時，可能跨越靶材電極402的最外側圓周供應 濺鍍靶材電極402所需之磁場，並調整靶材電極402及屏 蔽403間之間隙中的磁場強度。 回到圖1，參考數字420指示作爲控制整體半導體製 造設備1 00之控制機構的控制單元。此控制單元420具有 實施處理操作，諸如各種計算、控制、以及決定，的 CPU，以及儲存待由此 CPU執行之各種控制程式的 ROM。另外，控制單元420具有RAM、非揮發性記憶 體，諸如快閃記憶體、及SRAM，其暫時地儲存在CPU中 受處理操作的資料、及輸入资料等。將具有此種組態的控 制單元420組態成控制上電極高頻電源！ 〇2、DC電源 H)3、及下電極高頻電源3〇5，以將預定電壓分別施加至 -14 - 201250019 上電極及下電極。另外，將控制單元420組態成控制自動 壓力控制機制43 1，以在室20 1內得到預定壓力。再者， 將控制單元420組態成控制冷卻/加熱機制412，以得到基 材溫度的預定溫度。 圖3A及3B分別係低壓濺鍍及高壓濺鍍中的粒子轉 移處理，及形成在溝槽45 3中之濺鍍膜的形狀之解釋圖。 如圖3A所示，在低壓濺鍍中，由碰撞導致的濺鑛粒子散 射在濺鍍粒子到達基材之前不發生。因此，在圖3A之基 材邊緣部3 00 1及圖3A的基材中心部3002之間導致濺鍍 膜形狀的偏置狀態。 然而，當濺鍍使用圖1中之本實施例的設備而以高壓 實施時，濺鍍粒子450在濺鍍粒子450到達基材306之前 藉由與處理氣體（在本實施例中爲氬氣體）的碰撞所導致之 散射散佈在該容器內，如圖3B所示。藉由形成在基材 306周圍的護套451將藉由碰撞散射的濺鏟粒子450加 速。以此方式，將藉由上述碰撞散射並藉由護套451加速 的濺鍍粒子輸入至基材3 06上，且因此可能如圖3B之參 考數字3003及3004所指示地將具有高對稱覆蓋形狀的濺 鍍膜45 2沈積在整體基材表面上的各溝槽453中，並另外 抑制對側壁的沈積。亦即，在本實施例中，針對容許濺鍍 粒子均勻地進入基材306的整體表面，使壓力變得更高爲 佳，以藉由大氣氣體導致濺鍍粒子的碰撞發生。從靶材產 生的濺鑛粒子450藉由上述碰撞擴散，以均勻地進入基材 3 06的整體表面，但在另一方面，其能量也由於該碰撞而 -15- 201250019 損耗。然而，在本實施例中，藉由係用於加速離子之區域 的護套451之動作將其能量已減少的濺鍍粒子450朝向基 材306加速。因此，可能導致相似的濺鍍粒子450垂直地 進入形成在基材3 06上的各溝槽中。此處，數字454指示 基底基材。 圖4顯示後閘極形成技術的解釋圖，其使用CVD法 將各種類型的材料堆疊入分別具有32 nm及15 nm之開口 直徑的各精細溝槽開口中。初步形成的底層絕緣膜602存 在於精細溝槽結構601中。將高介電係數絕緣膜603形成 在底層絕緣膜602上。另外，形成用於控制操作電壓的金 屬氮化物膜A 604、金屬氮化物膜B 605、金屬氮化物膜 C 606、以及金屬膜607，並形成用於嵌入的堆疊障壁膜 608及種-A1膜609。當藉由CVD法形成此等各種類型的 材料時，在膜不僅均勻地形成在溝槽部的底表面上，也均 勻地形成在側壁上時，隨著使沈積膜厚度更大，溝槽開口 變得更窄，如圖4所明顯顯示的。因此，除非使各層的厚 度更小，該開口在1 5nm的精細溝槽中封閉。因此，在障 壁底層必需具有障壁性質所需之更大厚度的情形中，不可 能形成具有夠大厚度的膜。201250019 VI. Description of the Invention [Technical Field] The present invention relates to an electronic component manufacturing method including a step of embedding a metal film. [Prior Art] Conventionally, a semiconductor gate circuit has used a gate first method in which a gate insulating film and a gate electrode have been formed on a wafer surface by etching. Recently, the gate insulating film of the MOSFET has become thinner as the element is miniaturized, and when the Si 02 film is used for the gate insulating film, the tunneling current has recently required a film thickness of 2 nm or less. Generated, and the gate leakage current increases. Therefore, it has recently been studied to replace the gate insulating film with a high dielectric constant material having a relative dielectric constant higher than the dielectric constant of the SiO 2 film. By this method, the SiO 2 -transition film thickness (EOT: equivalent oxide thickness) can be made smaller even when the actual thickness of the insulating film is made larger. However, in recent MOSFETs having a gate length of 22 nm or less, the EOT needs to be further reduced. To meet this requirement, it is necessary to increase the actual thickness of the insulating film by using a high dielectric constant material to reduce the gate leakage current. However, in the first gate method, the source/drain formation step is performed after the gate is formed, and thus the gate insulating film and the gate electrode are heated' and the heating is caused between the insulating film and the metal film. Thermal diffusion and cause problems with mobility degradation and operating voltage (Vt) shift. Therefore, in order to solve such problems, the back-gate method in which the source/drain electrodes are formed in advance and the gate insulating film and the gate electrode are finally formed has been subjected to the product -5 - 201250019. In this method, since the gate portion is finally formed, the heating temperature applied to the gate portion is low, and it is possible to suppress the mobility degradation and the operating voltage (Vt) shift which have been the problem in the other method. The latter theme is to deposit various types of gold-iridium films in a shape having an opening of 22 nm and a depth of 22 nm or more (hereinafter, groove selection), and materials to be deposited on the sidewalls and the bottom of the trench, respectively. And thickness control is desirable. In addition, since various types of films are stacked, it is also necessary to suppress interdiffusion between the metal thin films. In the back gate method, a CVD (Chemical Vapor Deposition) method, an atomic layer absorption/deposition method, and a #: § method for forming various types of metal thin films. Since the incubation time is present in the formation process, there are problems in CVD method + alcohol controllability, surface uniformity, and repeatability. The top absorption/deposition method has excellent film thickness controllability, but at #f, the growth time becomes longer, and this problem is caused by the use of an expensive source gas. These methods of chemical reaction using the source gas each form a film uniformly on the bottom of the trench and also on the sidewall, but when the thickness of the deposited film is made larger, the trench becomes a narrower opening to solve this problem. As a method of the problem, a method of forming various metal thin film materials by a sputtering method having excellent film thickness, surface uniformity, and reproducibility has been disclosed. The unexamined patent application publication (PCT Application No. 2004-5 06090 discloses that a film 4 can also be formed on the sidewall of the groove portion as in the CVD method by a high voltage of 1 Torr or higher. In the method, the directivity of the sputter ion on the surface of the wafer is used to make the film; the gate 3 pole is smaller and the method is smaller. The film is thin: including sputtering: thickness (sublayer 5 thick) Membrane! Generated "not only ί, as the case of ί control type" ί 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Patent No. 3 1 93 8 75 discloses that after the underlayer of the barrier Ti and TiN has been formed, the species-A1 layer for accelerating the migration of the A1 film is formed by sputtering, and the A1 migrates at a high temperature to be embedded. Techniques and equipment. This method shows that A1 may be embedded in the trench while suppressing A1 diffusion by stacking underlying barrier layers of Ti and TiN. As described above, in recent film formation on very fine patterns, stacking Various types of metal films, and thus the diameter of the opening of the trench is reduced. Therefore, it must It is possible to use a metal thin film formation technique which suppresses a decrease in opening diameter as much as possible even when stacking various types of metal thin films. Further, by A1 diffusion, A1 embedding clearly degrades the characteristics of the metal film used in the gate electrode portion, Therefore, there is a need for a technique for forming a thin film barrier layer which inhibits the diffusion of A1. However, each of the above-mentioned techniques has the following problems. It is disclosed in Japanese Unexamined Patent Application Publication No. 2004-506090 Or higher sputtering method under high pressure can form the film on the sidewall of the trench, but has a problem that the trench opening becomes narrower when the trench opening is less than 22 nm or less. Further, it is disclosed in Japanese Patent No. The A1 embedding method in No. 3193875 has a problem of forming a thick barrier film for stacking Ti and TiN for suppressing A1 diffusion. Furthermore, since the species-A1 layer for accelerating A1 migration is additionally formed on the stacked Ti and TiN. On the barrier film, there is a problem that the opening of the trench is narrowed. [Abstract] -7-201250019 The object of the present invention is to provide a method for manufacturing an electronic component, including a metal film. For example, A1) a step of embedding in a recess (for example, a groove) which suppresses the reduction of the opening of the concave portion formed on the substrate, and forms a barrier film capable of suppressing diffusion of the metal to be embedded, because the above problem is solved. The inventors have found that an extremely thin TiN single-layer barrier film can be formed in a recess (for example, a groove portion) formed on a substrate by using the deposition apparatus of the present invention, and even without using a species - The A1 layer is additionally subjected to A1 embedding on the TiN single layer film, and has reached the completion of the present invention. The first embodiment of the present invention is an electronic component manufacturing method comprising: forming a sharp magnetic field on a surface of a target while a first step of depositing a single barrier layer comprising titanium nitride in a recess formed on the object to be processed by sputtering; and a low melting point metal layer at a temperature permitting flow of the low melting metal layer The second step of directly filling the single barrier layer. In such a configuration, the opening diameter may not be lowered, or even in a fine groove having an opening diameter of 22 nm or less, A1 may be embedded by suppressing a decrease in the diameter of the opening. A second embodiment of the present invention is an electronic component manufacturing method comprising: a sputtering mechanism including a target electrode connected to a high frequency power source and capable of mounting a target, and configured to mount the target when a magnet unit that forms a sharp magnetic field on the surface of the target electrode; and a control unit that controls the sputtering mechanism, wherein a target including titanium or titanium nitride is disposed on the target electrode When the barrier layer is formed in the recess -8 ~ 201250019 formed on the object to be processed, the control unit is configured to control the sputtering mechanism such that a single barrier layer containing titanium nitride is formed in the recess in. A third embodiment of the present invention is a method of manufacturing an electronic component, comprising: a first sputtering apparatus, comprising: a first sputtering mechanism having a first target electrode connected to the first high frequency power source and capable of mounting the target And a first magnet unit configured to form a pointed magnetic field on a surface of the target when the target is placed on the first target electrode; and a first control unit configured to control the a first sputtering mechanism such that when a target comprising titanium or titanium nitride is disposed on the first target electrode and a barrier layer is formed in a recess formed on the object to be processed, titanium nitride is included a single barrier layer is formed in the recess; and a second sputtering apparatus comprising: a second sputtering mechanism having a second target electrode coupled to the second high frequency power source and capable of mounting the target, and configured to be a second magnet unit that forms a pointed magnetic field on the surface of the target when the target is placed on the second target electrode; and a second control unit configured to control the second sputtering mechanism, When a target containing the low melting point metal is disposed in the second When the target electrode is embedded in the recess forming the single barrier layer, the low melting point metal layer is directly formed on the single barrier layer and at a temperature permitting the flow of the low melting metal layer The low melting point metal is embedded in the recess. A fourth embodiment of the present invention is an electronic component comprising: a member including a recess; an electrode layer formed in the recess; a low melting metal layer embedded in the recess; and a barrier layer formed on the low melting metal layer And between the electrode layers and including titanium nitride, the barrier layer having a (220) orientation. According to the present invention, a very thin TiN single-layer barrier film is formed in a recess (for example, a trench) on which a -9 - 201250019 is formed on a substrate, and a low melting point metal (for example, A1) is embedded in the TiN single On the barrier film, for example, while causing the TiN single-layer barrier film to have a barrier property that inhibits diffusion of the low-melting metal into the upper layer, the opening diameter may not be lowered, or even in a fine recess having an opening diameter of 22 nm or less The low melting point metal (for example, A1) is embedded by suppressing a decrease in the opening diameter. Therefore, when the electronic component manufacturing method of the present invention including the step of embedding the metal film is applied to the manufacturing method of the wiring step, the opening diameter may not be lowered, or by suppressing the fine recess in the opening diameter of 22 nm or less The diameter of the opening is lowered while the A1 is embedded. [Embodiment] Hereinafter, embodiments of the present invention will be explained in detail based on the drawings. In order to solve the above problems, the present inventors have found that by forming an extremely thin TiN single-layer barrier film and embedding A1 on a TiN single-layer barrier film, the use can suppress the reduction of the opening of the trench and suppress the diffusion of A1. A method of manufacturing an electronic component in which a barrier film is used to embed A1 in a groove portion. 1 shows an outline of an apparatus according to an embodiment of the present invention, which is used in a first step of forming a titanium nitride film as a barrier layer in a recess (for example, a 'groove) formed on a substrate, and An A1 film as a low-melting-point metal layer is formed on the titanium nitride film formed in the concave portion to embed A1 in the second step in the concave portion. The semiconductor manufacturing apparatus 100 according to the embodiment of the present invention includes a chamber 201 having an upper electrode 401 and a lower electrode 301 of -10-201250019, as shown in Fig. 1. The chamber 201 functions as a vacuum processing vessel and has a vacuum discharge pump 410 connected to a discharge port 205 for evacuating the inside of the chamber 201 together with an automatic pressure control mechanism (APC) 431. The upper electrode 401 is connected to the upper electrode high frequency power source 102 and the DC power source 103 via the matching box 101. Further, the lower electrode 301 is connected to the lower electrode high-frequency power source 305 via the matching box 304. The chamber 201 has an approximately cylindrical shape and includes an upper wall (top wall) 202 having an approximately disk shape, a side wall 203 having an approximately cylindrical shape, and a bottom wall 204 having an approximately disk shape. A pressure indicator 430 (e.g., a diaphragm pressure gauge) for measuring pressure is disposed around the side wall 203 in the chamber 201. The pressure indicator 43 0 is electrically coupled to an automatic pressure control mechanism 43 that is configured to automatically control the pressure within the chamber 201 based on the pressure measured by the pressure indicator 430. The upper electrode 401 has an upper wall 202, a magnet mechanism 405, a target electrode (first electrode) 402, an insulator 404, and a shield 403. The magnet mechanism 40 5 is placed below the upper wall 222 and the target electrode 420 is placed below the magnet mechanism 405. In addition, the insulator 404 insulates the target electrode 402 from the sidewalls of the chamber 201 and also holds the target electrode 402 within the chamber 201. Furthermore, the shield 403 is placed under the insulator 04. Here, the target electrode 402 is connected to the upper electrode high frequency power source 102 and the DC power source 103 via the matching box 101. The main portion of the target electrode 402 is made of a non-magnetic material such as Al, SUS, and Cu. A material target member (not shown in the drawings) required to form a film on the substrate 306 may be disposed on the pressure reducing side (substrate side) of the target electrode 402. Further, a pipeline configuration is formed in the upper electrodes 40 1 -11 - 201250019 and the target electrode 402, and the upper electrode 401 and the target electrode 402 can be cooled by the cooling water flowing in the pipeline configuration. The magnet mechanism 4〇5 has a magnet supporting plate 407, a plurality of magnet pieces 406 supported by the magnet supporting plate 407, and a magnetic field adjusting magnetic body 408 disposed on the outermost side of the circumference of the plurality of magnet pieces 406. Here, the magnet mechanism 40'5 is configured to be rotatable by using the central axis of the material target as a rotation axis by a rotation mechanism not shown in the drawings. A plurality of magnet pieces 406 are disposed adjacent to each other above the target 402 to be disposed in parallel with the surface of the target electrode 402. Adjacent magnet pieces 406 form a closed point-tip magnetic field 41 1 for controlling the plasma. The magnetic field adjusting magnetic body 408 is extended to partially overlap the magnet piece 406 on the outer circumferential side on the side of the target electrode 402. With this configuration, it is possible to suppress (control) the magnetic field strength in the gap between the target electrode 402 and the shield 403. The lower electrode 301 has a stage holder 302, a cooling/heating mechanism 412, a bottom wall 204, and a second electrode insulator 303. The stage holder 302 is used for a unit on which the substrate 306 is placed, and a cooling/heating mechanism 4 1 2 is provided therein. The temperature of the substrate (substrate temperature) can be controlled to a predetermined temperature by a cooling/heating mechanism 4 1 2 . The second electrode insulator 303 is a unit for supporting the table holder 302 and the bottom wall 204 of the chamber 201 to insulate them from each other. Further, the stage holder 302 is connected to the lower electrode high frequency power source 305 via the matching box 304. Here, the stage holder 302 is provided with an electrostatic absorption unit having a monopolar electrode not shown in the drawing, and this monopolar electrode is connected to a DC power source (not shown in the drawings). In addition, the stage holder 312 is provided with a plurality of gases (for example, an inert gas, not shown in the drawing for controlling the temperature of the substrate 306 to the back side of the substrate 306-201250019. A substrate such as Ar), and a substrate temperature measuring unit for measuring the temperature of the substrate. Inside the chamber 201, a plurality of gases for supplying a process gas, such as argon, into the chamber 201 are provided to the crucible 409. Referring to Figure 2, the shape of the magnet mechanism 405 will be explained in detail. 2 is a plan view of the magnet mechanism 405 as viewed from the side of the target electrode 402. As shown in Fig. 2, the magnetic field adjusting magnetic body 408 having an annular shape and the magnet piece 106 provided in the inner circumferential region of the magnetic field adjusting magnetic body 40 8 are supported by and provided on the disk magnet supporting body 407. Here, in Fig. 2, reference numeral 403a indicates the inner diameter of the shield 403 and many small circles indicate the outer shape of the individual magnet pieces 406. Further, each of the magnet pieces 406 has the same shape and the same magnetic flux density. Further, the letters N and S indicate the magnetic poles of the magnet piece 406 when viewed from the side of the target electrode 40 2 , respectively. The magnet pieces 406 are arranged in a lattice pattern (in the X-axis direction and the γ-axis direction) having substantially the same distance (in the range of 5 to 100 nm) from each other. In this way, a plurality of magnet pieces 406 are placed on the grid points of the polygon grid. Adjacent magnet pieces 406 have opposite polarities to each other. Meanwhile, in the rectangle including any four of the magnet pieces 406 arranged along the X-axis direction and the Y-axis direction, the polarities of the magnet pieces 406 adjacent to each other in the diagonal direction are identical to each other. That is, any four adjacent magnet pieces 406 form a point-point magnetic field (hereinafter, referred to as PCM) 411 on the surface of the target. The semiconductor manufacturing apparatus 100 can form a PCM in this manner, and thus is sometimes referred to as a PCM sputtering apparatus or a PCM processing apparatus. The height of the magnetic gusset 406 is typically greater than 2 mm and its cross-sectional shape -13 - 201250019 is rectangular or circular. The diameter, height, and material of the magnet piece 406 can be selectively set depending on the processing application. When high frequency power is applied to the upper electrode 40 1 of the semiconductor manufacturing apparatus 1 'the plasma is generated via a capacitance-coupling type mechanism. This plasma is controlled by the action of the closed point-tip magnetic field 41 I. The magnetic field adjusting magnetic body 408 is extended to partially overlap the magnet piece 406 on the outer circumferential side on the side of the target electrode 402. Therefore, the strength of the magnetic field in the gap between the target electrode 402 and the shield 403 can be suppressed (controlled). For example, the magnetic field modulating magnetic body 408 may be made of a material that can control the magnetic field strength between the target electrode 422 and the shield 403, or preferably made of a high magnetic permeability material such as SUS430. The magnet mechanism 405 adjusts the magnetic field by adjusting the area where the magnet piece 406 and the magnetic field adjustment magnetic body 408 overlap each other. That is, when the region where the magnet piece 406 and the magnetic field adjusting magnetic body 408 overlap each other, the magnetic field required to sputter the target electrode 402 may be supplied across the outermost circumference of the target electrode 402, and the target electrode 402 and the shield may be adjusted. The strength of the magnetic field in the gap between 403. Returning to Fig. 1, reference numeral 420 indicates a control unit as a control mechanism for controlling the overall semiconductor manufacturing apparatus 100. This control unit 420 has a CPU that performs processing operations such as various calculations, controls, and decisions, and a ROM that stores various control programs to be executed by the CPU. In addition, the control unit 420 has a RAM, a non-volatile memory such as a flash memory, and an SRAM, which temporarily stores data processed by the CPU, input data, and the like. The control unit 420 having such a configuration is configured to control the upper electrode high frequency power supply! 〇2, DC power supply H)3, and lower electrode high-frequency power supply 3〇5, to apply a predetermined voltage to the upper electrode and the lower electrode of -14 - 201250019. Additionally, control unit 420 is configured to control automatic pressure control mechanism 43 1 to obtain a predetermined pressure within chamber 20 1 . Again, control unit 420 is configured to control cooling/heating mechanism 412 to obtain a predetermined temperature of the substrate temperature. 3A and 3B are explanatory views of particle transfer processing in low-pressure sputtering and high-pressure sputtering, and a shape of a sputtering film formed in the trench 45, respectively. As shown in Fig. 3A, in low-pressure sputtering, splashing of the splashed particles caused by the collision does not occur until the sputtered particles reach the substrate. Therefore, a bias state of the shape of the sputter film is caused between the edge portion 3 00 1 of the substrate of Fig. 3A and the center portion 3002 of the substrate of Fig. 3A. However, when sputtering is performed at a high pressure using the apparatus of the present embodiment of FIG. 1, the sputtered particles 450 are treated with a process gas (argon gas in this embodiment) before the sputtered particles 450 reach the substrate 306. The scattering caused by the collision is scattered in the container as shown in Fig. 3B. The shovel particles 450 by collision scattering are accelerated by a sheath 451 formed around the substrate 306. In this manner, sputter particles that are scattered by the above-described collision and accelerated by the sheath 451 are input onto the substrate 306, and thus may have a high symmetrical coverage shape as indicated by reference numerals 3003 and 3004 of FIG. 3B. The sputter film 45 2 is deposited in each of the trenches 453 on the surface of the monolith substrate and additionally inhibits deposition of the sidewalls. That is, in the present embodiment, it is preferable to allow the sputtering particles to uniformly enter the entire surface of the substrate 306 to make the pressure higher, so that collision of the sputtering particles by the atmospheric gas occurs. The splash particles 450 generated from the target are diffused by the above collision to uniformly enter the entire surface of the substrate 306, but on the other hand, the energy is also lost due to the collision -15 - 201250019. However, in the present embodiment, the sputtered particles 450 whose energy has been reduced are accelerated toward the substrate 306 by the action of the sheath 451 for accelerating the region of the ions. Therefore, it is possible to cause similar sputter particles 450 to vertically enter the respective grooves formed on the substrate 306. Here, numeral 454 indicates the base substrate. Fig. 4 shows an explanatory diagram of a post gate forming technique in which various types of materials are stacked into respective fine trench openings having opening diameters of 32 nm and 15 nm, respectively, using a CVD method. The preliminary formed underlying insulating film 602 is present in the fine trench structure 601. A high dielectric constant insulating film 603 is formed on the underlying insulating film 602. In addition, a metal nitride film A 604, a metal nitride film B 605, a metal nitride film C 606, and a metal film 607 for controlling an operation voltage are formed, and a stacked barrier film 608 and a seed-A1 film for embedding are formed. 609. When these various types of materials are formed by the CVD method, when the film is formed not only uniformly on the bottom surface of the groove portion but also uniformly formed on the side wall, the groove opening is made larger as the thickness of the deposited film is made larger. It becomes narrower, as shown clearly in Figure 4. Therefore, unless the thickness of each layer is made smaller, the opening is closed in a fine groove of 15 nm. Therefore, in the case where the barrier underlayer must have a larger thickness required for the barrier property, it is impossible to form a film having a sufficiently large thickness.
同時，圖5顯示後閘極形成技術的解釋圖，其使用本 實施例之圖1所示的PCM濺鍍設備1〇〇堆疊各種類型的 材料。初步形成的底層絕緣膜6 02存在於精細溝槽結構 6〇1中。將高介電係數絕緣膜603形成在底層絕緣膜602 上。另外，形成用於控制操作電Μ的金屬氮化物膜A -16- 201250019 701、金屬氮化物膜B 702、金屬氮化物膜C 703、以及金 屬膜704，並形成用於嵌入的單層障壁膜705。在根據本 實施例的設備中，將護套形成在作爲基材保持部之台保持 器302(亦即，將基材306置於台保持部302上）的周圍， 且因此可抑制濺鍍膜在溝槽之側壁上形成。因此，如圖5 所示，相較於圖4所示之使用習知CVD法的情形，可能 將各種類型的材料形成在溝槽內而抑制溝槽開口的窄化。 因此，可能將膜形成在15nm的精細型樣中，甚至使用與 3 2nm溝槽之厚度相同的厚度。因此，甚至在將溝槽尺寸 更加小型化時，可能形成膜而不改變各種類型材料的最佳 膜厚度。亦即，也可針對具有窄寬度的溝槽，甚至在將該 層形成爲具有較大厚度時，抑制溝槽開口的窄化。另外， 根據本實施例的障壁膜使用單層膜，且因此可降低堆疊結 構的層數。 圖6顯示根據本實施例的半導體製造設備500，其使 用在包括將金屬膜嵌入凹部中之步驟的電子元件製造方法 中。半導體製造設備5 00包括分別用於第一步驟及第二步 驟的處理之形成氮化鈦膜的室501及實施將A1嵌入溝槽 中的室502，以及附接之金屬膜形成室503、504、以及 505，以沈積各種類型的金屬材料。另外，半導體製造設 備500包含轉移室506，其包括能將基材轉移至室50丨至 505之各設備而不將基材曝露於大氣中的真空轉移單元、 以及用於將基材從大氣轉移至真空中的晶圓承載室507。 須注意各室501、502、503、504、以及505係根據本實 -17- 201250019 施例之顯示於圖1中的PCM濺鍍設備（半導體製造設備 1〇〇)。藉由使用本半導體製造設備5 00，可能連續地實施 處理而不將基材曝露於大氣中，且因此可能抑制雜質至介 面的吸收，諸如水、碳、及氧。因此，可能將基材轉移至 次一步驟而不改變由各設備形成之膜的性質。 此處’半導體製造設備500包含控制器（未顯示於圖 式中），該控制器包括算術處理單元，諸如CPU，並根據 預定程式藉由輸出指令訊號至各處理設備501至507，實 行用於待處理基材的預定處理。須注意各處理設備501至 5 07包括控制單元，諸如PLC(可程式化控制器）（未顯示於 圖式中：須注意各處理設備501至505中的控制單元係解 釋於圖1中的控制單元420)，並依據從控制器輸出的指 令訊號控制諸如質量流控制器及排放栗的單元。因此，在 對應室中，將圖1中的控制單元420組態成根據從上述控 制器接收之各種類型的指令訊號，控制上電極高頻電源 1 02、DC電源103、低電極高頻電源305、冷卻/加熱機制 4 1 2、及自動壓力控制機制43 1等。 圖7A及7B分別顯示將金屬膜嵌入溝槽中之方法的 習知流程及本實施例之流程。在習知A1嵌入方法中’在 障壁膜形成步驟810中，將用於抑制A1擴散之堆疊Ti及 TiN的堆疊障壁膜形成在溝槽中。隨後，在種-A1層形成 步驟811中，將用於加速A1遷移的種-A1層形成在上述 堆疊障壁膜上。之後，在A1嵌入步驟812中’在高溫環 境下將A1形成在堆餿障壁層上，以待嵌入溝槽中。 -18- 201250019 然而’根據本實施例的A1嵌入方法甚至可藉由將單 層障壁膜形成步驟815實施爲第一步驟，並直接在該單層 障壁膜上將A1嵌入形成步驟816實施爲第二步驟而不使 用種-A1 ’得到完美的嵌入特徵。Meanwhile, Fig. 5 shows an explanatory diagram of a technique of forming a rear gate which stacks various types of materials using the PCM sputtering apparatus 1 shown in Fig. 1 of the present embodiment. The preliminary formed underlying insulating film 902 is present in the fine trench structure 〇1. A high dielectric constant insulating film 603 is formed on the underlying insulating film 602. In addition, a metal nitride film A-16-201250019 701, a metal nitride film B 702, a metal nitride film C 703, and a metal film 704 for controlling the operation of the electric field are formed, and a single-layer barrier film for embedding is formed. 705. In the apparatus according to the present embodiment, the sheath is formed around the table holder 302 as the substrate holding portion (that is, the substrate 306 is placed on the stage holding portion 302), and thus the sputtering film can be suppressed Formed on the sidewall of the trench. Therefore, as shown in Fig. 5, it is possible to form various types of materials in the grooves and suppress the narrowing of the groove openings as compared with the case of the conventional CVD method shown in Fig. 4. Therefore, it is possible to form the film in a fine pattern of 15 nm, even using the same thickness as the thickness of the 32 nm trench. Therefore, even when the groove size is further miniaturized, it is possible to form a film without changing the optimum film thickness of various types of materials. That is, it is also possible to suppress the narrowing of the groove opening even for the groove having a narrow width even when the layer is formed to have a large thickness. In addition, the barrier film according to the present embodiment uses a single layer film, and thus the number of layers of the stacked structure can be lowered. Fig. 6 shows a semiconductor manufacturing apparatus 500 according to the present embodiment, which is used in an electronic component manufacturing method including a step of embedding a metal film in a recess. The semiconductor manufacturing apparatus 500 includes a chamber 501 for forming a titanium nitride film and a chamber 502 for embedding A1 in the trench, and the attached metal film forming chambers 503, 504 for the processing of the first step and the second step, respectively. And 505 to deposit various types of metal materials. In addition, the semiconductor manufacturing apparatus 500 includes a transfer chamber 506 including a vacuum transfer unit capable of transferring the substrate to the respective chambers 50 to 505 without exposing the substrate to the atmosphere, and for transferring the substrate from the atmosphere. To the wafer carrier chamber 507 in vacuum. It is to be noted that each of the chambers 501, 502, 503, 504, and 505 is a PCM sputtering apparatus (semiconductor manufacturing apparatus 1) shown in Fig. 1 according to the embodiment of the present invention -17-201250019. By using the present semiconductor manufacturing apparatus 500, it is possible to continuously carry out the treatment without exposing the substrate to the atmosphere, and thus it is possible to suppress the absorption of impurities to the interface such as water, carbon, and oxygen. Therefore, it is possible to transfer the substrate to the next step without changing the properties of the film formed by each device. Here, the semiconductor manufacturing apparatus 500 includes a controller (not shown in the drawings) including an arithmetic processing unit such as a CPU, and is executed by outputting an instruction signal to each of the processing devices 501 to 507 according to a predetermined program. The predetermined treatment of the substrate to be treated. It should be noted that each processing device 501 to 507 includes a control unit, such as a PLC (programmable controller) (not shown in the drawings: it should be noted that the control units in each of the processing devices 501 to 505 are explained in the control of FIG. Unit 420) controls the units such as the mass flow controller and the discharge pump in accordance with the command signal output from the controller. Therefore, in the corresponding room, the control unit 420 of FIG. 1 is configured to control the upper electrode high frequency power source 102, the DC power source 103, and the low electrode high frequency power source 305 according to various types of command signals received from the controller. , cooling / heating mechanism 4 1 2, and automatic pressure control mechanism 43 1 and so on. 7A and 7B respectively show a conventional flow of a method of embedding a metal film in a groove and a flow of this embodiment. In the conventional A1 embedding method, in the barrier film forming step 810, a stacked barrier film for stacking Ti and TiN for suppressing Al diffusion is formed in the trench. Subsequently, in the seed-A1 layer forming step 811, a seed-A1 layer for accelerating the A1 migration is formed on the above-described stacked barrier film. Thereafter, in the A1 embedding step 812, A1 is formed on the stack barrier layer in a high temperature environment to be embedded in the trench. -18-201250019 However, the A1 embedding method according to the present embodiment can be implemented as the first step even by the single-layer barrier film forming step 815 as the first step, and directly embedding the A1 in the single-layer barrier film. Two steps without using the species -A1 'get the perfect embedding feature.
TiN單層障壁膜在第一步驟815中的沈積係在室501 中實施。將Ti金屬靶材使用爲該靶材並將該Ti靶材載置 在室501中的靶材電極4〇2上。各參數設定爲以下情況。 亦即，室501的控制單元420控制冷卻/加熱機制412 ’以 將基材溫度設定在30 °C。另外，室501的控制單元420 控制室501的上電極高頻電源1〇2及DC電源103，以將 Ti靶材的 RF功率及DC電壓分別設定在l5〇〇W及 43 0V。再者，將Ar使用爲該惰性氣體、將Ar的供應量 設定爲 7〇Secm、將係反應氣體之氮的供應量設定爲 3〇Sccm、將Ar氣體及氮氣體從室501的氣體導入埠409 導入、藉由室501的自動壓力控制機制431將該室內的壓 力設定爲10帕，然後實施膜形成。另外，爲控制膜形成 形狀，室501的控制單元420控制室501的低電極高頻電 源305，以將係基材電極之低電極301的RF功率設定爲 5 0W，然後實施膜形成。 再者，實施用於與單障壁層材料比較之Ti單層障壁 膜的沈積。在Ti單層障壁膜的沈積中，將基材溫度設定 爲30°C、將Ti靶材的RF功率及DC電壓分別設定爲 1 500W以及43 0V、將Ar使用爲該惰性氣體、將Ar的供 應量設定爲lOOsccm、藉由自動壓力控制機制將該室內的 19 - 201250019 壓力設定爲ίο帕，然後實施膜形成。另外，針 形狀的控制，藉由將基材電極的RF功率設定爲 施膜形成。 須注意，當在本實施例中使用含Ti之靶材 可能使用含TiN的靶材。在此情形中，可能將惰 用爲待從氣體導入埠4 09導入的氣體。 以此方式，在第一步驟中，室501的控制單 靶材的周圍產生電漿，以從該靶材產生濺鍍粒子 上電極高頻電源102，使得使用灑鍍粒子將TiN 膜形成在形成於係待處理物件之基材306上的溝 也控制自動壓力控制機制43 1以導致自動壓力 431操作，以在室501內得到預定壓力。 其次，在第二步驟816中，在容許低熔點金 溫度條件下，以低熔點金屬（此處，A1)塡充溝槽 二步驟816中的沈積係在室502中實施。將A1 載置在室5 02的靶材電極4 02上。將各參數設定 例之以下情況。亦即，室502的控制單元420 ： 加熱機制4 1 2，以將基材溫度設定在400 °C。 5 02的控制單元420控制室502的上電極高頻電 DC電源103，以將A1靶材的RF功率及DC電 定在3 000W及100V。再者，將Ar使用爲該惰 將Ar的供應量設定爲lOOsccm、從室502的氣 409導入Ar氣體、藉由室502的自動Μ力控制 將該室內的壓力設定爲1〇帕，然後苡施膜形成 對膜形成 50W而實 的同時， 性氣體使 元420在 ，並控制 單層障壁 槽內，並 控制機制 屬流動的 。Α1在第 金屬靶材 爲作爲範 控制冷卻/ 另外’室 源102及 壓分別設 性氣體、 體導入埠 機制43 1 。另外， -20- 201250019 爲增加在溝槽底部之沈積膜的厚度量，室502 420控制室502的下電極高頻電源305，以將 之下電極 301的 RF功率設定爲200W，然 成。此處，將高頻電源的頻率設定成在10及 間的頻率爲佳。針對在上述壓力下使用點-尖 密度電漿的目的，該頻率係在40及60MHz之 佳。 以此方式，在第二步驟中，室502的控制 靶材周圍產生電漿，以從靶材產生濺鍍粒子， 極高頻電源102，使得使用濺鍍粒子將A1膜 於係待處理物件之基材306上的溝槽內，並1 加熱機制4 1 2，以得到A1可流動的基材溫度。The deposition of the TiN single layer barrier film in the first step 815 is performed in chamber 501. A Ti metal target was used as the target and the Ti target was placed on the target electrode 4〇2 in the chamber 501. Each parameter is set to the following. That is, the control unit 420 of the chamber 501 controls the cooling/heating mechanism 412' to set the substrate temperature at 30 °C. Further, the control unit 420 of the chamber 501 controls the upper electrode high-frequency power source 1〇2 and the DC power source 103 of the chamber 501 to set the RF power and the DC voltage of the Ti target at 15 〇〇 W and 43 0 V, respectively. In addition, Ar is used as the inert gas, the supply amount of Ar is set to 7 〇Secm, the supply amount of nitrogen of the reaction gas is set to 3 〇Sccm, and Ar gas and nitrogen gas are introduced from the gas of the chamber 501. 409 is introduced, and the pressure in the chamber is set to 10 Pa by the automatic pressure control mechanism 431 of the chamber 501, and then film formation is performed. Further, in order to control the film formation shape, the control unit 420 of the chamber 501 controls the low-electrode high-frequency power source 305 of the chamber 501 to set the RF power of the lower electrode 301 of the substrate electrode to 50 W, and then performs film formation. Further, deposition of a Ti single-layer barrier film for comparison with a single barrier layer material was carried out. In the deposition of the Ti single-layer barrier film, the substrate temperature was set to 30 ° C, the RF power and DC voltage of the Ti target were set to 1 500 W and 43 0 V, respectively, and Ar was used as the inert gas, and Ar was used. The supply amount was set to 100 sccm, and the pressure of 19 - 201250019 in the chamber was set to ίοPa by an automatic pressure control mechanism, and then film formation was performed. Further, the control of the needle shape is formed by setting the RF power of the substrate electrode to be applied. It should be noted that when a target containing Ti is used in the present embodiment, a target containing TiN may be used. In this case, it is possible to use inert gas as the gas to be introduced from the gas into the 埠4 09. In this manner, in the first step, plasma is generated around the control single target of the chamber 501 to generate a sputter particle upper electrode high frequency power source 102 from the target, so that the TiN film is formed using the sputtered particles. The ditch on the substrate 306 of the item to be treated also controls the automatic pressure control mechanism 43 1 to cause the automatic pressure 431 to operate to achieve a predetermined pressure within the chamber 501. Next, in a second step 816, the deposition system in step 816 of the lower melting point metal (here, A1) is carried out in chamber 502 under conditions permitting a low melting point gold temperature. A1 is placed on the target electrode 420 of the chamber 502. The following cases are set for each parameter. That is, the control unit 420 of the chamber 502: heats the mechanism 4 1 2 to set the substrate temperature at 400 °C. The control unit 420 of 052 controls the upper electrode high frequency DC power source 103 of the chamber 502 to set the RF power and DC of the A1 target to 3 000 W and 100 V. Further, Ar is used to set the supply amount of the inert Ar to 100 sccm, the Ar gas is introduced from the gas 409 of the chamber 502, and the pressure in the chamber is set to 1 kPa by the automatic force control of the chamber 502, and then 苡The film formation forms 50W for the film formation, while the gas makes the element 420 and controls the single-layer barrier groove, and the control mechanism flows. Α1 in the first metal target is used as the control cooling / other 'room source 102 and pressure separately set gas, body introduction mechanism 43 1 . Further, -20-201250019, in order to increase the thickness of the deposited film at the bottom of the trench, the chamber 502 420 controls the lower electrode high-frequency power source 305 of the chamber 502 to set the RF power of the lower electrode 301 to 200 W. Here, it is preferable to set the frequency of the high-frequency power source to a frequency of 10 or more. For the purpose of using point-tip density plasma under the above pressure, the frequency is preferably 40 and 60 MHz. In this manner, in the second step, plasma is generated around the control target of the chamber 502 to produce sputtered particles from the target, the very high frequency power source 102, such that the A1 film is applied to the object to be treated using the sputtered particles. Within the trenches on substrate 306, and 1 heating mechanism 4 1 2, to obtain a substrate temperature at which A1 is flowable.
圖8A及8B係針對使用根據本實施例之ϋ 示的PCM濺鍍設備之情形，顯示確認Α1嵌入 的圖。A1嵌入特徵係藉由 SEM(掃描式電子 算。圖8A係顯示在第一步驟之Ti單層障壁 Ti單層障壁膜沈積至具有10nm之厚度，然後 驟之A1嵌入的情形之結果的圖。圖8B顯示在 TiN單層障壁膜形成中將TiN單層障壁膜： 10nm之厚度，然後實施第二步驟的A1嵌入 果。在圖8A中，至溝槽部中的A1嵌入並未 觀察到許多空洞空間（在下文中，稱爲空隙）。 在圖8B中，至溝槽部中的A1嵌入已完成，且 隙的產生。可能係因爲在Ti單層障壁膜中，T 的控制單元 係基材電極 後實施膜形 100MHz 之 磁場形成高 間的頻率更 單元420在 並控制上電 形成在形成 fe控制冷卻/ E 1及6所 特徵之結果 '顯微鏡）估 膜形成中將 實施第二步 第一步驟之 尤積至具有 之情形的結 完成，並可 另一方面， 未觀察到空 i及A1之間 -21 - 201250019 的反應在A1嵌入時發生並加速合金化以抑制A1遷移。因 此，此顯示藉由使用本實施例的TiN單層障壁膜，合金化 可在A1嵌入時受抑制並可加速A1遷移。 圖9A係顯示在第一步驟之TiN單層障壁膜形成中將 TiN單層障壁膜形成至具有lOnm之厚度，然後在曝露於 大氣中後，實施第二步驟之A1嵌入的情形之結果的圖。 圖9B係顯示在第一步驟的TiN單層障壁膜形成中將TiN 單層障壁膜形成至具有1 Onm的厚度，並在曝露於大氣中 後，在第一步驟的TiN單層障壁膜形成中將TiN單層障 壁膜再度形成至具有1 Onm的厚度，然後未曝露於大氣中 而實施第二步驟之A1嵌入的情形之結果的圖。圖9C係顯 示在第一步驟之TiN單層障壁膜形成中將TiN單層障壁 膜形成至具有l〇nm之厚度，然後實施第二步驟之A1嵌 入而未曝露於大氣中的情形之結果的圖。 在圖9A中’至溝槽部的A1嵌入尙未完成，且觀察 到空隙。在圖9B中，觀察到溝槽部具有比圖9A之嵌入 更好的嵌入，但導致空隙。在9C中，將A1完全嵌入至溝 槽部中，且未觀察到空隙產生。可能因爲將TiN膜曝露於 大氣中且在曝露於大氣中時導致來自大氣之水及碳的污 染，防止在高溫下之A1膜形成時的A1遷移。因此，當第 —步驟及第二步驟分別使用不同真空容器實施時，實施該 轉移且該處理不曝露於大氣中爲佳。 其次，圖10A至10G顯示將典型使用的磁控管濺鑛 設備（在下文中，稱爲STD)用於第一步驟及第二步驟之比 -22- 201250019 較硏究的結果。圖10A係顯示以室溫之基材溫度及10帕 的壓力，在STD設備中將TiN單層障壁膜形成爲具有 10nm的厚度作爲第一步驟’並以400 °C之基材溫度在 STD設備中將A1嵌入實施爲第二步驟的情形之結果的 圖。在此情形中，至溝槽部的A1嵌入尙未完成，且觀察 到空隙。圖10B係顯示以室溫之基材溫度及1 0帕的壓 力，在根據本實施例的處理設備（例如’作爲PCM處理設 備的半導體製造設備1〇〇)中將TiN單層障壁膜形成爲具 有10nm的厚度作爲第一步驟，並以400°C之基材溫度在 STD設備中將A1嵌入實施爲第二步驟的情形之結果的 圖。在此情形中，A1嵌入比圖10A的嵌入更成功地完 成，但在溝槽底部導致空隙。圖1 0C係顯示以室溫之基材 溫度及10帕的壓力，在根據本實施例的PCM處理設備中 將TiN單層障壁膜形成爲具有10nm的厚度作爲第一步 驟，並以400°C的基材溫度在根據本實施例之處理設備中 將A1嵌入實施爲第二步驟的情形之結果的圖。在此情形 中，相較於圖1 〇B之特徵，A1嵌入特徵改善，但觀察到 空隙產生。 圖10D係顯示以400 °C之基材溫度及1〇帕的壓力， 在根據本實施例的PCM處理設備中將TiN單層障壁膜形 成爲具有l〇nm的厚度作爲第一步驟，並以40(TC的基材 溫度在根據本實施例之處理設備中將A1嵌入實施爲第二 步驟的情形之結果的圖。在此情形中，甚至在4 0 0 °C的 TiN膜形成溫度’仍觀察到與圖丨〇c之情形相似的空隙產 -23- 201250019 生。圖10E係顯示以室溫之基材溫度及loo帕的壓力，在 根據本實施例的PCM處理設備中將TiN單層障壁膜形成 爲具有10nm的厚度作爲第一步驟，並以4001的基材溫 度在根據本實施例之處理設備中將A1嵌入實施爲第二步 驟的情形之結果的圖。在此情形中，至溝槽部的A1嵌入 完美地完成，且未觀察到空隙產生。 其次，將解釋與第一步驟中之TiN單層障壁膜有關的 硏究結果。圖11係顯示藉由AFM(原子力顯微鏡）法分析 TiN單層障壁膜的表面粗糙度（Ra)之結果的圖。如圖11 所示，當藉由使用STD處理設備在室溫及1〇帕的壓力下 沈積之TiN單層障壁膜的表面粗糙度（Ra)爲〇.479nm之同 時，藉由使用根據本實施例之PCM處理設備在室溫及10 帕的壓力下沈積之TiN單層障壁膜的表面粗糙度（Ra)爲 0.1 62ηιη，且發現平坦度較佳。另外，藉由使用根據本實 施例的PCM處理設備在400°C之基材溫度及10帕的壓力 下沈積之TiN單層障壁膜的表面粗糙度（Ra)爲〇.〇91nm， 且相較於在室溫下沈積之情形，發現平坦度改善。再者， 發現藉由使用根據本實施例的PCM處理設備在室溫之基 材溫度及100帕的壓力下沈積之TiN單層障壁膜的表面粗 糙度（Ra)爲最小之0.073 nm。通常隨著表面粗糙度越小， 金屬元素的表面遷移越好。然而，未於圖10C及圖10D 之間發現A1嵌入特徵的改善，且平坦度的影響甚小。另 外，爲降低TiN單層障壁膜的表面粗糙度，第一步驟中在 真空容器內的壓力不低於1帕且不高於2 00帕爲佳，且不 -24- 201250019 低於10帕且不高於100帕更佳。 其次’將解釋與第一步驟中的TiN單層障壁膜之晶體 定向有關的硏究結果。圖12A係顯示針對各情況藉由 XRD(X光繞射）法分析TiN單層障壁膜中的晶體定向之結 果的圖。在圖12A及12B中，「室溫STD4Pa」指示藉由 使用STD處理設備在室溫之基材溫度及4帕的壓力下將 TiN單層障壁膜形成至溝槽中之情形，且曲線ι21顯示在 此條件下形成之膜的XRD量測結果。「室溫STD 10Pa」 指示藉由使用STD處理設備在室溫之基材溫度及1〇帕的 壓力下將TiN單層障壁膜形成至溝槽中之情形，且曲線 1 22顯示在此條件下形成之膜的xrd量測結果。「室溫 PCM 4Pa」指示藉由使用根據本實施例的pCM處理設備 在室溫之基材溫度及4帕的壓力下將TiN單層障壁膜形成 至溝槽中之情形，且曲線123顯示在此條件下形成之膜的 XRD量測結果。「室溫PCM 10Pa」指示藉由使用根據本 實施例的PCM處理設備在室溫之基材溫度及1〇帕的壓力 下將TiN單層障壁膜形成至溝槽中之情形，且曲線124顯 示在此條件下形成之膜的XRD量測結果。「400°C PCM 10Pa」指示藉由使用根據本實施例的PCM處理設備在 400 °C之基材溫度及10帕的壓力下將TiN單層障壁膜形成 至溝槽中之情形，且曲線1 25顯示在此條件下形成之膜的 XRD量測結果。「室溫PCM lOOPa」指示藉由使用根據 本實施例的PCM處理設備在室溫之基材溫度及100帕的 壓力下將TiN單層障壁膜形成至溝槽中之情形，且曲線 -25- 201250019 126顯示在此條件下形成之膜的XRD量測結果。 如圖12A所示，發現藉由使用STD處理設備沈積之 TiN單層障壁膜具有比藉由使用根據本實施例的PCM處 理設備沈積之TiN單層障壁膜更弱的C(lll)、C(200)、以 及C(220)定向。將藉由C(lll)定向的尖峰強度正規化之 此C(2 2 0)定向的尖峰強度比率顯示於圖12B中。依據此 結果，藉由使用STD處理設備沈積之TiN單層障壁膜具 有約0.5至0.7的C(22 0)/C(lll)比率，其比藉由使用根據 本實施例的PCM處理設備沈積之TiN單層障壁膜的比率 更小》該等晶體定向在藉由使用根據本實施例之PCM處 理設備以室溫的基材溫度及10帕之壓力沈積TiN單層障 壁膜的情形及以40(TC之溫度及10帕的壓力沈積TiN單 層障壁膜之情形的二情形之間等同。 另外，發現當沈積係藉由使用根據本實施例之PCM 處理設備以室溫的基材溫度及100帕之壓力實施時，將 C(220)/C(lll)比率最大化。從此結果及圖10E之結果， 或許TiN單層障壁膜的較佳C(22 0)定向使A1嵌入特徵改 善。從此結論，TiN單層障壁膜的結晶度顯示0.7或更大 的C(220)/C(lll)比率爲佳。另外，爲得到TiN單層障壁 膜之較佳晶體定向的目的，第一步驟之真空容器內的壓力 不低於1帕且不高於200帕爲佳，且不低於1〇帕且不高 於100帕更佳。 另外，當TiN單層障壁膜的晶體定向甚弱時，在第二 步驟的AI嵌入中，障壁性質有時退化且A1擴散至比該障 -26- 201250019 壁層之TiN膜更低的層。因此，MOSFET特徵退化在形成 MOSFET電極時發生。 藉由使用PCM處理設備，以不低於1帕且不高於 2 00帕，且不低於10帕且不高於100帕較佳，之該室內 的壓力形成TiN單層障壁膜，本實施例可改善形成於溝槽 內之TiN單層障壁膜的C(220)晶體定向。因此，可能在 降低空隙形成的同時將A1較佳地嵌入於其中形成TiN單 層障壁膜的溝槽中，並也可能抑制已嵌入之A1至TiN單 層障壁膜之下層的擴散。 如上文所述，在本實施例中，爲改善C(220)晶體定 向，例如，重點係使用如圖1所示的PCM處理設備，並 增加該室內的壓力爲佳。亦即，如圖1 2B所示，當以相同 壓力在STD處理設備及PCM處理設備之間比較形成TiN 單層障壁膜的情形時（曲線1 2 1及曲線1 23之間的比較及 曲線122及曲線124之間的比較），發現PCM處理設備可 改善C(220)定向。另外，當在使用相同之PCM處理設備 的情形中比較改變壓力之情形時（曲線1 2 3、曲線1 2 4、以 及曲線126之間的比較），發現較高的壓力可導致C(220) 定向改善。以此方式，本實施例可藉由在TiN單層障壁膜 形成時使用PCM處理設備，並將該室的壓力也設定成較 高値（不低於1帕且不高於2 00帕，不低於1〇帕且不高於 100帕爲佳）而改善形成於溝槽內之TiN單層障壁膜的 C(220)定向。8A and 8B are diagrams showing the embedding of the confirmation Α1 for the case of using the PCM sputtering apparatus according to the present embodiment. The A1 embedding feature is shown by SEM (scanning electronic calculation. Fig. 8A shows a result of deposition of a Ti single-layer barrier Ti single-layer barrier film in the first step to a thickness of 10 nm, and then A1 embedding. Fig. 8B shows a TiN single-layer barrier film in the formation of a TiN single-layer barrier film: a thickness of 10 nm, and then an A1-embedded fruit of the second step. In Fig. 8A, many A1 embedding into the groove portion was not observed. The void space (hereinafter, referred to as a void). In Fig. 8B, the A1 embedding into the trench portion is completed, and the gap is generated. Perhaps because of the control unit cell of T in the Ti single-layer barrier film. After the electrode is implemented, the film-shaped magnetic field of 100 MHz forms a high frequency. The unit 420 is controlled and the power is formed. The result of forming the FE control cooling / E 1 and 6 results in the formation of the film. The step is particularly complicated to the completion of the junction, and on the other hand, no reaction between the empty i and A1 is observed. The reaction of -21,500,1919 occurs at the time of A1 embedding and accelerates alloying to inhibit A1 migration. Therefore, this display shows that by using the TiN single-layer barrier film of the present embodiment, alloying can be suppressed at the time of A1 embedding and acceleration of A1 migration. Fig. 9A is a view showing a result of forming a TiN single-layer barrier film to have a thickness of lOnm in the formation of a TiN single-layer barrier film in the first step, and then performing the second step of A1 embedding after being exposed to the atmosphere. . 9B is a view showing the formation of a TiN single-layer barrier film to a thickness of 1 Onm in the formation of a TiN single-layer barrier film in the first step, and in the formation of a TiN single-layer barrier film in the first step after exposure to the atmosphere. A TiN single-layer barrier film was again formed to have a thickness of 1 Onm, and then exposed to the atmosphere to perform the result of the second step of A1 embedding. 9C shows the result of forming a TiN single-layer barrier film to have a thickness of 10 nm in the TiN single-layer barrier film formation in the first step, and then performing the second step of A1 embedding without being exposed to the atmosphere. Figure. In Fig. 9A, the A1 insertion into the groove portion was not completed, and a void was observed. In Fig. 9B, it is observed that the groove portion has a better embedding than the embedding of Fig. 9A, but causes a void. In 9C, A1 was completely embedded in the groove portion, and no void generation was observed. It is possible to prevent the A1 migration at the time of formation of the A1 film at a high temperature by exposing the TiN film to the atmosphere and causing contamination of water and carbon from the atmosphere when exposed to the atmosphere. Therefore, when the first step and the second step are respectively carried out using different vacuum vessels, it is preferable to carry out the transfer and the treatment is not exposed to the atmosphere. Next, Figs. 10A to 10G show results of comparison of the typically used magnetron sputtering apparatus (hereinafter, referred to as STD) for the first step and the second step ratio -22-201250019. 10A shows that a TiN single-layer barrier film is formed to have a thickness of 10 nm as a first step in a STD apparatus at a substrate temperature of room temperature and a pressure of 10 Pa, and a substrate temperature of 400 ° C is used in the STD apparatus. The map in which the middle keeper A1 is embedded as a result of the second step. In this case, the A1 insertion enthalpy to the groove portion was not completed, and the void was observed. 10B shows that a TiN single-layer barrier film is formed in a processing apparatus according to the present embodiment (for example, 'a semiconductor manufacturing apparatus as a PCM processing apparatus 1') at a substrate temperature of room temperature and a pressure of 10 Pa. A graph having a thickness of 10 nm as a first step and embedding A1 in the STD apparatus as a result of the second step at a substrate temperature of 400 °C. In this case, the A1 embedding is completed more successfully than the embedding of Fig. 10A, but causes a void at the bottom of the trench. Fig. 10C shows that a TiN single-layer barrier film is formed to have a thickness of 10 nm as a first step and a temperature of 400 ° C in a PCM processing apparatus according to the present embodiment at a substrate temperature of room temperature and a pressure of 10 Pa. The substrate temperature is a diagram in which the result of the case where A1 is embedded as the second step in the processing apparatus according to the present embodiment. In this case, the A1 embedding feature is improved as compared with the feature of Fig. 1 〇B, but void generation is observed. 10D shows a substrate temperature of 400 ° C and a pressure of 1 kPa, in the PCM processing apparatus according to the present embodiment, a TiN single-layer barrier film is formed to have a thickness of 10 nm as a first step, and 40 (Pipe of the substrate temperature of TC in the case of embedding A1 in the processing apparatus according to the present embodiment as a result of the second step. In this case, even the TiN film formation temperature at 40 ° C is still ' A void production similar to that of Fig. c was observed. Fig. 10E shows a TiN single layer in the PCM processing apparatus according to the present embodiment at a substrate temperature of room temperature and a pressure of a loo. The barrier film is formed as a pattern having a thickness of 10 nm as a first step and embedding A1 as a second step in the processing apparatus according to the present embodiment at a substrate temperature of 4001. In this case, The A1 embedding of the groove portion is perfectly completed, and void generation is not observed. Next, the results of the investigation relating to the TiN single-layer barrier film in the first step will be explained. Fig. 11 shows the method by AFM (atomic force microscopy) Analysis of surface roughness of TiN single-layer barrier film A graph of the results of (Ra). As shown in Fig. 11, the surface roughness (Ra) of the TiN single-layer barrier film deposited by using an STD processing apparatus at room temperature and a pressure of 1 kPa is 479.479 nm. Meanwhile, the surface roughness (Ra) of the TiN single-layer barrier film deposited by using the PCM processing apparatus according to the present embodiment at room temperature and a pressure of 10 Pa was 0.162 ηηη, and it was found that the flatness was better. The surface roughness (Ra) of the TiN single-layer barrier film deposited by using the PCM processing apparatus according to the present embodiment at a substrate temperature of 400 ° C and a pressure of 10 Pa is 〇.〇91 nm, and is compared with the room. In the case of subsurface deposition, it was found that the flatness was improved. Further, the surface roughness of the TiN single-layer barrier film deposited by using the PCM processing apparatus according to the present embodiment at a substrate temperature of room temperature and a pressure of 100 Pa was found. (Ra) is the minimum 0.073 nm. Generally, as the surface roughness is smaller, the surface migration of the metal element is better. However, the improvement of the A1 embedding feature is not found between Fig. 10C and Fig. 10D, and the flatness is affected. In addition, in order to reduce the surface of the TiN single-layer barrier film Roughness, the pressure in the vacuum vessel in the first step is not less than 1 Pa and not more than 200 Pa, and not -24-201250019 is less than 10 Pa and not more than 100 Pa. The results of the investigation relating to the crystal orientation of the TiN single-layer barrier film in the first step are explained. Fig. 12A shows the result of analyzing the crystal orientation in the TiN single-layer barrier film by XRD (X-ray diffraction) method for each case. In FIGS. 12A and 12B, "room temperature STD4Pa" indicates a case where a TiN single-layer barrier film is formed into a trench at a substrate temperature of room temperature and a pressure of 4 Pa using an STD processing apparatus, and Curve ι 21 shows the XRD measurement results of the film formed under this condition. "Room Temperature STD 10Pa" indicates the formation of a TiN single-layer barrier film into the trench by using an STD processing apparatus at a substrate temperature of room temperature and a pressure of 1 kPa, and the curve 12 is shown under this condition. The xrd measurement of the formed film. "Room PCM 4Pa" indicates a case where a TiN single-layer barrier film is formed into a trench at a substrate temperature of room temperature and a pressure of 4 Pa using the pCM processing apparatus according to the present embodiment, and a curve 123 is displayed at The XRD measurement results of the film formed under these conditions. "Room PCM 10Pa" indicates a case where a TiN single-layer barrier film is formed into a trench at a substrate temperature of room temperature and a pressure of 1 kPa using the PCM processing apparatus according to the present embodiment, and a curve 124 is displayed. The XRD measurement results of the film formed under this condition. "400 ° C PCM 10 Pa" indicates a case where a TiN single-layer barrier film is formed into a trench at a substrate temperature of 400 ° C and a pressure of 10 Pa using the PCM processing apparatus according to the present embodiment, and curve 1 25 shows the XRD measurement results of the film formed under this condition. "Room PCM 100 Pa" indicates the case where a TiN single-layer barrier film is formed into the trench at a substrate temperature of room temperature and a pressure of 100 Pa using the PCM processing apparatus according to the present embodiment, and the curve - 25 - 201250019 126 shows the XRD measurement results of the film formed under this condition. As shown in FIG. 12A, it was found that the TiN single-layer barrier film deposited by using the STD processing apparatus has C (lll), C (we are weaker than the TiN single-layer barrier film deposited by using the PCM processing apparatus according to the present embodiment). 200), and C (220) orientation. The C (2 2 0) oriented peak intensity ratio normalized by the C (lll) oriented spike intensity is shown in Figure 12B. According to this result, the TiN single-layer barrier film deposited by using the STD processing apparatus has a C(22 0)/C(llll) ratio of about 0.5 to 0.7, which is deposited by using the PCM processing apparatus according to the present embodiment. The ratio of the TiN single-layer barrier film is smaller. The crystal orientation is in the case of depositing a TiN single-layer barrier film at a substrate temperature of room temperature and a pressure of 10 Pa using the PCM processing apparatus according to the present embodiment and at 40 ( The case where the temperature of TC and the pressure of 10 Pa were deposited in the case of depositing a TiN single-layer barrier film was equivalent. Further, it was found that when the deposition was performed by using the PCM processing apparatus according to the present embodiment, the substrate temperature at room temperature and 100 Pa were used. When the pressure is applied, the C(220)/C(lll) ratio is maximized. From the results and the results of Fig. 10E, perhaps the preferred C(22 0) orientation of the TiN single-layer barrier film improves the A1 embedding characteristics. The crystallinity of the TiN single-layer barrier film shows a ratio of C(220)/C(lll) of 0.7 or more. In addition, for the purpose of obtaining a preferred crystal orientation of the TiN single-layer barrier film, the vacuum of the first step The pressure inside the container is not less than 1 Pa and not more than 200 Pa, and not less than 1 Pa In addition, when the crystal orientation of the TiN single-layer barrier film is very weak, in the AI embedding of the second step, the barrier property sometimes degrades and the A1 diffuses to the barrier layer -26-201250019 The lower layer of the TiN film. Therefore, MOSFET feature degradation occurs when the MOSFET electrode is formed. By using a PCM processing device, not less than 1 Pa and not more than 200 Pa, and not less than 10 Pa and not high Preferably, the pressure in the chamber forms a TiN single-layer barrier film at 100 Pa. This embodiment can improve the C(220) crystal orientation of the TiN single-layer barrier film formed in the trench. Therefore, it is possible to reduce the formation of voids. At the same time, A1 is preferably embedded in the trench in which the TiN single-layer barrier film is formed, and it is also possible to suppress the diffusion of the layer underlying the Al to TiN single-layer barrier film. As described above, in the present embodiment, In order to improve the orientation of the C(220) crystal, for example, the focus is on using a PCM processing apparatus as shown in Fig. 1, and it is preferable to increase the pressure in the chamber. That is, as shown in Fig. 12B, when the same pressure is applied in the STD Comparison between the device and the PCM processing device to form a TiN single-layer barrier film Shape time (comparison between curve 1 2 1 and curve 1 23 and comparison between curve 122 and curve 124), it was found that the PCM processing equipment can improve the C (220) orientation. In addition, when using the same PCM processing equipment In the case where the pressure is changed in comparison (curve 1 2 3, curve 1 2 4, and comparison between curves 126), it is found that higher pressure can lead to an improvement in C (220) orientation. In this way, this embodiment can By using a PCM processing device when forming a TiN single-layer barrier film, and setting the pressure of the chamber to a higher enthalpy (not less than 1 Pa and not higher than 200 Pa, not less than 1 Pascal and not higher than 100 Pa is preferred) to improve the C (220) orientation of the TiN single-layer barrier film formed in the trench.
另外，如圖13所示，藉由STD處理設備形成的TiN -27- 201250019 單層障壁膜具有高電阻係數値。當電阻係數甚高時，與電 極膜的接觸電阻變高且MOSFET特徵的退化，諸如電力 消耗，發生。同時，發現藉由根據本實施例之PCM處理 設備以50帕及1〇〇帕之壓力形成的TiN單層障壁膜分別 具有較高電阻係數値的同時，比在較低壓力的STD處理 設備之情形中的値具有更低之値。可能係因爲當在STD 處理設備中實施高壓力膜形成時，濺鍍粒子與大氣氣體之 間的碰撞率增加，導致不充份的活化並損失晶體化及反應 所需的能量。然而，在根據本實施例的PCM處理設備 中，高密度電漿係藉由PCM形成，且甚至在濺鍍粒子及 大氣氣體之間的碰撞率增加時，仍可導致充分活化的濺鍍 粒子到達基材表面。因此，或許可能在不增加電阻値或抑 制電阻値增加的同時，形成具有較佳結晶度的TiN單層障 壁膜。 圖14A係針對當第一步驟之TiN單層障壁膜的沈積 係在STD處理設備及根據本實施例之PCM處理設備中實 施時的TiN單層障壁膜，顯示與沈積在溝槽底部之膜厚度 對沈積在溝槽上部的膜厚度之比率的壓力相依性有關之硏 究結果的圖。圖14B係針對當第一步驟之TiN單層障壁 膜的沈積係在STD處理設備及根據本實施例之PCM處理 設備中實施時的TiN單層障壁膜，顯示與沈積在溝槽側壁 部之膜厚度對沈稂在溝槽上部的膜厚度之比率的壓力相依 性有關之硏究結果的圖。從圖1 4 A證實並未發現溝槽底 部的沈積膜厚度比率（底覆蓋率）增加，甚至在S T D設備中 -28- 201250019 的壓力增加時，且溝槽底部的沈積膜厚度比率在4帕的壓 力下爲40%，而在根據本實施例之PCM處理設備中的壓 力增加至10帕或更高時顯著地增加至60 %或更高。另 外，爲增加溝槽底部的沈積膜厚度，壓力不低於帕且 不高於1〇〇帕爲佳。再者，從圖14B，溝槽側壁部的沈積 膜厚度比率（側覆蓋率）在二設備之間係等同的。從此結 果，可將圖10A至10E的結果討論如下。 圖15A及15B係用於解釋在第一步驟中將單層TiN 障壁膜802沈積入溝槽結構801中以及在第二步驟中實施 A1嵌入8 03之情形的槪要圖。具體地說，圖15A係用於 解釋在根據本實施例之PCM處理設備中沈積TiN單層障 壁膜並在STD處理設備中實施A1嵌入之情形的圖，且圖 15B係用於解釋在根據本實施例之PCM處理設備中沈積 TiN單層障壁膜並在PCM處理設備中實施A1嵌入之情形 的圖。如圖15A所示，在將STD處理設備使用在第二步 驟之A1嵌入中的情形中，形成在溝槽底部上之A1的膜厚 度可能甚小，且因此當A1從上方遷移時不能充份地實施 A1嵌入，且空隙804產生。另一方面，如圖15B所示， 當使用根據本實施例的PCM處理設備時，形成在溝槽底 部上之A1的膜厚度可能甚大且A1也可能從上方遷移，且 因此可實施完美的A1嵌入。另外，爲增加在溝槽底部上 的膜形成量之目的，第一步驟及第二步驟中之真空容器內 的壓力不低於1帕且不高於2 00帕爲佳，且不低於10帕 且不高於100帕更佳。 -29 - 201250019 <範例1 > 將參考該等圖式解釋本發明之第一範例。 圖15B係顯示如上文所述地藉由使用根據本發明的實 施例之顯示於圖1及圖6中的P CM濺鍍設備，在第一步 驟中將TiN單層障壁膜形成在溝槽結構中並在第二步驟中 將A1嵌入之處理的圖。首先，將TiN單層障壁膜8 02沈 積在溝槽結構801中，作爲第一步驟。將Ti金屬靶材使 用爲該靶材並將氬氣體及氮使用爲該濺鍍氣體。其次，在 TiN單層障壁膜802上實施A1嵌入，作爲第二步驟。將 A1金屬靶材使用爲該靶材並將氬使用爲該濺鍍氣體。 可分別在25°C至500 °C、100W至5000W、1帕至200 帕、lOsccm 至 500sccm、以及 lsccm 至 lOOsccm 範圍中 選擇性地決定基材溫度、靶材功率、濺鍍氣體壓力、Ar 氣體流動量、以及氮氣體流動量。In addition, as shown in FIG. 13, the TiN-27-201250019 single-layer barrier film formed by the STD processing apparatus has a high resistivity 値. When the resistivity is very high, the contact resistance with the electrode film becomes high and degradation of MOSFET characteristics such as power consumption occurs. Meanwhile, it was found that the TiN single-layer barrier films formed by the PCM processing apparatus according to the present embodiment at a pressure of 50 Pa and 1 Pascal respectively have a higher resistivity 値 while being compared with the STD processing apparatus at a lower pressure. The cockroaches in the situation have a lower threshold. This may be because when high pressure film formation is performed in the STD processing apparatus, the collision rate between the sputtered particles and the atmospheric gas is increased, resulting in insufficient activation and loss of energy required for crystallization and reaction. However, in the PCM processing apparatus according to the present embodiment, the high-density plasma is formed by PCM, and even when the collision rate between the sputtered particles and the atmospheric gas is increased, the sufficiently activated sputter particles can be caused to arrive. The surface of the substrate. Therefore, it is possible to form a TiN single-layer barrier film having a better crystallinity without increasing the resistance 値 or suppressing the increase in resistance 値. 14A is a TiN single-layer barrier film when the deposition of the TiN single-layer barrier film in the first step is performed in the STD processing apparatus and the PCM processing apparatus according to the present embodiment, and shows the film thickness deposited on the bottom of the trench. A graph of the results of the correlation regarding the pressure dependence of the ratio of the film thickness deposited on the upper portion of the trench. 14B is a TiN single-layer barrier film when the deposition of the TiN single-layer barrier film in the first step is performed in the STD processing apparatus and the PCM processing apparatus according to the embodiment, and is shown and deposited on the sidewall of the trench. A graph of the effect of the thickness on the pressure dependence of the ratio of the thickness of the film deposited on the upper portion of the trench. It is confirmed from Fig. 14A that the deposition film thickness ratio (bottom coverage) at the bottom of the trench is not increased, even when the pressure of the -28-201250019 is increased in the STD device, and the deposition film thickness ratio at the bottom of the trench is 4 Pa. The pressure is 40%, and is significantly increased to 60% or more when the pressure in the PCM processing apparatus according to the present embodiment is increased to 10 Pa or higher. Further, in order to increase the thickness of the deposited film at the bottom of the groove, it is preferable that the pressure is not lower than Pa and not higher than 1 Pa. Further, from Fig. 14B, the film thickness ratio (side coverage) of the groove side wall portion is equivalent between the two devices. From this result, the results of Figs. 10A to 10E can be discussed as follows. 15A and 15B are diagrams for explaining a case where a single-layer TiN barrier film 802 is deposited in the trench structure 801 in the first step and A1 is embedded in the second step. Specifically, FIG. 15A is a diagram for explaining a case where a TiN single-layer barrier film is deposited in the PCM processing apparatus according to the present embodiment and A1 embedding is performed in the STD processing apparatus, and FIG. 15B is for explaining A diagram of a case where a TiN single-layer barrier film is deposited in a PCM processing apparatus of an embodiment and A1 is embedded in a PCM processing apparatus. As shown in FIG. 15A, in the case where the STD processing apparatus is used in the A1 embedding of the second step, the film thickness of A1 formed on the bottom of the trench may be very small, and thus the A1 may not be sufficient when it migrates from above. The A1 is embedded and the void 804 is generated. On the other hand, as shown in Fig. 15B, when the PCM processing apparatus according to the present embodiment is used, the film thickness of A1 formed on the bottom of the groove may be very large and A1 may also migrate from above, and thus a perfect A1 can be implemented. Embed. In addition, for the purpose of increasing the amount of film formation on the bottom of the trench, the pressure in the vacuum vessel in the first step and the second step is preferably not less than 1 Pa and not more than 200 Pa, and not less than 10 Pa is not more than 100 Pa. -29 - 201250019 <Example 1> A first example of the present invention will be explained with reference to the drawings. Figure 15B shows a TiN single-layer barrier film formed in a trench structure in a first step by using the P CM sputtering apparatus shown in Figures 1 and 6 according to an embodiment of the present invention as described above. A diagram of the processing in which A1 is embedded in the second step. First, a TiN single-layer barrier film 822 is deposited in the trench structure 801 as a first step. A Ti metal target was used as the target, and argon gas and nitrogen were used as the sputtering gas. Next, A1 embedding is performed on the TiN single-layer barrier film 802 as a second step. An A1 metal target was used as the target and argon was used as the sputtering gas. The substrate temperature, target power, sputtering gas pressure, Ar gas can be selectively determined in the range of 25 ° C to 500 ° C, 100 W to 5000 W, 1 Pa to 200 Pa, lOsccm to 500 sccm, and lsccm to 100 sccm, respectively. The amount of flow, and the amount of nitrogen gas flow.
TiN單層障壁膜802在第一步驟中的沈積係在使用Ti 金屬靶材、將基材溫度設定爲30°C、將Ti靶材的RF功 率及DC電壓分別設定爲1 500 W及43 0V、將Ar使用爲該 惰性氣體、將Ar的供應量設定在70sccm、將係反應氣體 之氮的供應量設定在3〇SCCm、以及使用自動調整單元將 該室內的壓力設定爲10帕的條件下實施，然後實施膜形 成。另外，爲控制沈積膜之形狀的目的，藉由將基材電極 的RF功率設定爲50W而苡施沈積。在上述形成步驟中將 TiN膜形成在3nm至10nm的厚度範圍中。其次，A1 803 -30- 201250019 在第二步驟中的沈積係在將基材溫度設定爲400°C、將A1 靶材的RF功率及DC電壓分別設定爲3000W及100V、將 Ar使用爲該惰性氣體、將Ar的供應量設定爲100 seem、 並使用自動調整單元將該室內的壓力設定爲10帕的條件 下實施，然後實施膜形成。另外，爲增加沈積在溝槽底部 上之膜的厚度量之目的，膜形成係藉由將基材電極的RF 功率設定爲200W而實施。 <範例2 (施用至後閘極法的範例）> 在下文中，將參考圖式解釋本發明的第二範例。圖 16中之步驟161至步驟166的各圖式顯示係本發明之第 二範例的半導體裝置製造方法。在本範例中，針對待形成 η-型 MOSFET之第一區域的各區域以及待形成 p-型 MOSFET之第二區域的各區域，實施上述實施例中之第一 步驟的TiN單層障壁膜之沈積及第二步驟的Α1嵌入，並 形成閘極電極以分別實現合適的有效工作函數。 在圖16的步驟161中，將溝槽結構901及溝槽結構 902分別形成在待形成η-型MOSFET的第一區域及待形成 p-型MOSFET之第二區域中，並將金屬氮化物膜A 9 00分 別形成在溝槽結構901及902中。其次，在圖16的步驟 162中，藉由使用根據本發明之實施例的PCM濺鍍處理 設備，將金屬氮化物膜B 9 03及金屬合金膜904形成爲覆 蓋溝槽結構901及902的個別內側。其次，在圖16的步 驟1 6 3中，藉由使用光微影技術及蝕刻技術將在待形成 -31 - 201250019 η-型MO SFET之第一區域中組成溝槽結構901的底部 屬氮化物膜B 903及金屬合金膜904移除。在本範例 金屬氮化物膜B 903係藉由使用硫酸、過氧化氫溶液 及水之混合溶液的濕蝕刻移除，且金屬合金膜904係 Ar電漿蝕刻移除。 其次，在圖16的步驟164中，在圖6所示之可 根據本發明的實施例之濺鍍法的半導體製造設備中將 轉移至室501並將TiN單層障壁膜905形成爲覆蓋溝 構901及902的個別內側（根據本發明之實施例的第 驟）。 其次，在圖16的步驟165中，將TiN單層障壁 成在於其上之溝槽結構901及902中的基材轉移 5 02，並實施根據本發明之實施例的第二步驟之A1嵌 以將金屬膜906形成爲在溝槽結構901及902內之 之後，在圖16的步驟166中，藉由使用CMP技術實 坦化並將非必要的金屬膜906移除。 須注意，在形成以A1製造之金屬膜的步驟中， 將基材溫度設定在3 00 °C及400°C之間，金屬合金膜 至少在待形成η-型MOSFET之區域中的金屬氮化物 900中擴散，並可實現適合η-型 MOSFET的有效工 數。另一方面，在待形成Ρ-型MOSFET的區域中， 氮化物膜B 903及金厠合金膜904抑制A1的擴散， 此可能維持適合P-型MOSFET的有效工作函數。將 MOSFET之此有效工作函數的硏究結果顯示於圖1 7中 之金 中， 、以 藉由 實行 基材 槽結 一步 膜形 至室 入， A1。 施平 藉由 904 膜A 作函 金屬 且因 P-型 -32- 201250019 圖17係顯示緊接在上述之各種金屬材料的堆疊步 已完成後之該步驟中的A1嵌入形成之後及450°C的額 熱處理之後的個別有效工作函數之硏究結果的圖。此處 該估算係針對3nm及5nm的TiN單層障壁膜厚度實施 雖然已知有效工作函數在A1擴散入TiN單層障壁膜中 降低，如圖17所示，甚至在實施45(TC的加熱時，並 發現有效工作函數的顯著減少。此顯示藉由使用根據本 明之實施例的PCM處理設備形成之TiN單層障壁膜對 擴散具有良好的障壁性質。由於該已產生組件的有效工 函數、EOT、及弱電流特徵的量測，藉由使用本發明之 施例中的A1嵌入法，證實得到適合各MOSFET的有效 作函數（針對η-型MOSFET爲4.4eV或更小，且針對p-MOSFET爲4.6eV或更大），而不招致EOT的增加。 【圖式簡單說明】 圖1係根據本發明之實施例的處理設備之槪要圖。 圖2係載置在根據本發明之實施例的處理設備內之 鐵的配置圖。 圖3 A係根據本發明之實施例的低壓濺鑪粒子轉移 理以及沈積在溝槽中的濺鍍膜之形狀的解釋圖。 圖3B係根據本發明之實施例的高壓濺鑛粒子轉移 理以及沈積在溝槽中的濺鍍膜之形狀的解釋圖。 圖4係當將習知CVD法用於形成技術時，顯示後 極法中之溝槽尺寸相依性的槪要圖。 驟 外 時 未 發 A1 作 實 工 型 磁 處 處 閘 -33- 201250019 圖5係當將根據本發明之實施例的PCM濺鍍法用於 形成技術時，顯示後閘極法中之溝槽尺寸相依性的槪要 圖。 圖6係顯示根據本發明之實施例的半導體製造設備之 組態的圖。 圖7A係顯示將A1嵌入溝槽中之習知順序的流程 圖。 圖7B係顯示根據本發明的實施例之將A1嵌入溝槽中 的順序之流程圖。 圖8A及8B係顯示根據本發明之實施例的A1嵌入特 徵之單下層材料相依性的圖。 圖9A至9C係顯示大氣曝露對根據本發明之實施例 的A1嵌入特徵之影響的圖。 圖10A至10E係顯示根據本發明之實施例的A1嵌入 特徵之處理設備相依性的圖。 圖1 1係顯示根據本發明之實施例的TiN單層障壁膜 之AFM量測結果的處理設備相依性之圖。 圖12A係顯示根據本發明之實施例的TiN單層障壁 膜之XRD量測結果的處理設備相依性之圖。 圖12B係針對根據圖12A之結果的各狀況，顯示藉 由C(lll)定向的尖峰強度正規化之C(220)定向的尖峰強 度比率的圖。 圖]3係顯示在根據本發明之實施例的TiN單層障壁 膜中之電阻係數的處理設備相依性之圖。 -34- 201250019 圖ΜΑ係顯示根據本發明實施例之在溝槽底部上的 TiN單層障壁膜之沈積量的壓力相依性之圖。 圖1 4B係顯示根據本發明實施例之在溝槽側壁部上的 TiN單層障壁膜之沈積量的壓力相依性之圖。 圖15A及15B各者係顯示根據本發明之實施例的處 理設備之A1嵌入特徵的槪要圖。 圖16係顯示本發明之範例2中的半導體設備製造方 法之步驟的圖。 圖17係顯示在藉由圖16之製造方法製造的p_型 MOSFET中之有效工作函數的硏究結果之圖。 【主要元件符號說明】 100、500 :半導體製造設備 1 0 1、3 0 4 :匹配箱 102 :上電極高頻電源 1 0 3 : D C電源 121 、 122 、 123 、 124 、 125 、 126 :曲線 201 、 501 、 502 ：室 202 :上壁 2 0 3 :側壁 204 :底壁 2 0 5 :排放埠 301 :下電極 3 02 :台保持器 -35- 201250019 3 0 3 :第二電極絕緣器 305:下電極商頻電源 306 :基材 401 :上電極 402 :靶材電極 403 :屏蔽 403 a ：內直徑 404 :絕緣器 405 :磁鐵機制 406 :磁鐵片 407 :磁鐵支撐板 408 :磁場調整磁性體 409 :氣體導入埠 4 1 0 :真空排放泵 41 1 :封閉點-尖磁場 412 :冷卻/加熱機制 4 2 0 :控制單元 430 :壓力指示器 4 3 1 :自動壓力控制機制 450 :濺鍍粒子 451 :護套 452 :濺鍍膜 453 :溝槽 454 :基底蕋材 201250019 503、5 04、505 :金屬膜形成室 5 0 6 :轉移室 5 07 :晶圓承載室 601、 701、 801、 901、 902 ：溝槽結構 602、 702:底層絕緣膜 603、 703 :高介電係數絕緣膜The deposition of the TiN single-layer barrier film 802 in the first step is performed by using a Ti metal target, setting the substrate temperature to 30 ° C, and setting the RF power and DC voltage of the Ti target to 1 500 W and 43 0 V, respectively. Ar is used as the inert gas, the supply amount of Ar is set to 70 sccm, the supply amount of nitrogen in the reaction gas is set to 3 〇 SCCm, and the pressure in the chamber is set to 10 Pa using an automatic adjustment unit. It is carried out and then film formation is carried out. Further, for the purpose of controlling the shape of the deposited film, deposition was performed by setting the RF power of the substrate electrode to 50 W. The TiN film is formed in a thickness range of 3 nm to 10 nm in the above formation step. Next, A1 803 -30- 201250019 The deposition in the second step is to set the substrate temperature to 400 ° C, set the RF power and DC voltage of the A1 target to 3000 W and 100 V, respectively, and use Ar as the inertia. The gas was supplied under the condition that the supply amount of Ar was set to 100 seem, and the pressure in the chamber was set to 10 Pa using an automatic adjusting unit, and then film formation was performed. Further, for the purpose of increasing the thickness of the film deposited on the bottom of the trench, film formation is carried out by setting the RF power of the substrate electrode to 200 W. <Example 2 (Example of application to the post-gate method)> Hereinafter, a second example of the present invention will be explained with reference to the drawings. The respective drawings of steps 161 to 166 in Fig. 16 show a method of manufacturing a semiconductor device according to a second example of the present invention. In this example, the TiN single-layer barrier film of the first step in the above embodiment is implemented for each region of the first region where the n-type MOSFET is to be formed and each region of the second region where the p-type MOSFET is to be formed. The deposition and the second step of Α1 are embedded and the gate electrodes are formed to achieve a suitable effective work function, respectively. In step 161 of FIG. 16, a trench structure 901 and a trench structure 902 are respectively formed in a first region where an n-type MOSFET is to be formed and a second region where a p-type MOSFET is to be formed, and a metal nitride film is formed. A 9 00 is formed in the trench structures 901 and 902, respectively. Next, in step 162 of FIG. 16, the metal nitride film B 9 03 and the metal alloy film 904 are formed to cover the individual of the trench structures 901 and 902 by using the PCM sputtering processing apparatus according to the embodiment of the present invention. Inside. Next, in step 163 of FIG. 16, the bottom nitride of the trench structure 901 is formed in the first region where the -31 - 201250019 η-type MO SFET is to be formed by using photolithography and etching techniques. The film B 903 and the metal alloy film 904 are removed. In the present example, the metal nitride film B 903 is removed by wet etching using a mixed solution of sulfuric acid, a hydrogen peroxide solution, and water, and the metal alloy film 904 is removed by Ar plasma etching. Next, in step 164 of FIG. 16, in the semiconductor manufacturing apparatus of the sputtering method according to the embodiment of the present invention shown in FIG. 6, the process is transferred to the chamber 501 and the TiN single-layer barrier film 905 is formed to cover the trench structure. Individual inner sides of 901 and 902 (steps according to embodiments of the invention). Next, in step 165 of FIG. 16, the TiN single-layer barrier is transferred into the substrate in the trench structures 901 and 902 thereon, and the second step of the embodiment of the present invention is implemented. After the metal film 906 is formed within the trench structures 901 and 902, in step 166 of FIG. 16, the non-essential metal film 906 is removed by using a CMP technique. It should be noted that in the step of forming the metal film manufactured by A1, the substrate temperature is set between 300 ° C and 400 ° C, and the metal alloy film is at least in the region of the metal nitride to be formed in the region of the n-type MOSFET. Diffusion in 900, and can achieve an effective number of η-type MOSFET. On the other hand, in the region where the Ρ-type MOSFET is to be formed, the nitride film B 903 and the gold-sink alloy film 904 suppress the diffusion of A1, which may maintain an effective work function suitable for the P-type MOSFET. The results of the evaluation of the effective working function of the MOSFET are shown in the gold in Fig. 17 to form a film into the chamber by a substrate, A1. Shi Ping uses 904 Membrane A as the metal and P-type-32-201250019. Figure 17 shows the formation of A1 in this step immediately after the stacking step of the various metal materials described above is completed and 450 °C. A graph of the results of an individual effective work function after the amount of heat treatment. The estimation here is for the thickness of the TiN single-layer barrier film of 3 nm and 5 nm. Although the effective working function is known to decrease in the diffusion of A1 into the TiN single-layer barrier film, as shown in Fig. 17, even when 45 is applied (TC heating) And found a significant reduction in the effective work function. This shows that the TiN single-layer barrier film formed by using the PCM processing apparatus according to the embodiment of the present invention has good barrier properties for diffusion. Due to the effective work function of the generated component, EOT And the measurement of the weak current characteristic, by using the A1 embedding method in the embodiment of the present invention, it is confirmed that an effective function suitable for each MOSFET (4.4 eV or less for the n-type MOSFET and for the p-MOSFET) 4.6 eV or more, without incurring an increase in EOT. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a processing apparatus in accordance with an embodiment of the present invention. Figure 2 is placed on an embodiment in accordance with the present invention. Figure 3 is an explanatory view of the low-pressure sputtering furnace particle transfer theory and the shape of the sputter film deposited in the trench according to an embodiment of the present invention. Figure 3B is an implementation according to the present invention. Case Interpretation of the shape of the high-pressure splashing particles and the shape of the sputtered film deposited in the trenches. Figure 4 is a summary of the size dependence of the trenches in the post-pole method when the conventional CVD method is used in the forming technique. Fig. 5 is not issued as a physical type magnetic gate-33-201250019. FIG. 5 shows a groove in the rear gate method when a PCM sputtering method according to an embodiment of the present invention is used for a forming technique. Figure 6 is a diagram showing the configuration of a semiconductor manufacturing apparatus in accordance with an embodiment of the present invention. Figure 7A is a flow chart showing a conventional sequence of embedding A1 in a trench. Figure 8A and 8B are diagrams showing the dependence of a single underlying material of an A1 embedded feature in accordance with an embodiment of the present invention. Figures 9A through 9C show FIG. 10A to FIG. 10E are diagrams showing the dependence of a processing device of an A1 embedding feature according to an embodiment of the present invention. FIG. TiN of the embodiment Fig. 12A is a diagram showing the dependence of the processing apparatus on the XRD measurement results of the TiN single-layer barrier film according to an embodiment of the present invention. Fig. 12B is a diagram showing the dependence of the processing apparatus on the XRD measurement results of the TiN single-layer barrier film according to the embodiment of the present invention. The results of the results of 12A show a plot of C (220) oriented spike intensity ratio normalized by C (lll) orientation. Figure 3 shows a TiN single layer barrier in accordance with an embodiment of the present invention. A diagram of the dependence of the processing apparatus on the resistivity in the film. -34 - 201250019 The figure shows the pressure dependence of the deposition amount of the TiN single-layer barrier film on the bottom of the trench according to an embodiment of the present invention. Fig. 1B is a graph showing the pressure dependence of the deposition amount of the TiN single-layer barrier film on the side wall portion of the trench according to the embodiment of the present invention. 15A and 15B are schematic views showing an A1 embedding feature of a processing device in accordance with an embodiment of the present invention. Fig. 16 is a view showing the steps of a method of manufacturing a semiconductor device in Example 2 of the present invention. Fig. 17 is a graph showing the results of an investigation of the effective work function in the p-type MOSFET fabricated by the manufacturing method of Fig. 16. [Description of main component symbols] 100, 500: Semiconductor manufacturing equipment 1 0 1 , 3 0 4 : Matching box 102: Upper electrode high-frequency power supply 1 0 3 : DC power supply 121, 122, 123, 124, 125, 126: Curve 201 , 501 , 502 : chamber 202 : upper wall 2 0 3 : side wall 204 : bottom wall 2 0 5 : discharge 埠 301 : lower electrode 3 02 : stage holder - 35 - 201250019 3 0 3 : second electrode insulator 305: Lower electrode commercial power supply 306: substrate 401: upper electrode 402: target electrode 403: shield 403 a: inner diameter 404: insulator 405: magnet mechanism 406: magnet piece 407: magnet support plate 408: magnetic field adjustment magnetic body 409 : gas introduction 埠 4 1 0 : vacuum discharge pump 41 1 : closed point - pointed magnetic field 412 : cooling / heating mechanism 4 2 0 : control unit 430 : pressure indicator 4 3 1 : automatic pressure control mechanism 450 : sputtering particles 451 : sheath 452 : sputter film 453 : trench 454 : substrate coffin 201250019 503, 5 04, 505 : metal film forming chamber 5 0 6 : transfer chamber 5 07 : wafer carrying chamber 601, 701, 801, 901, 902 : trench structure 602, 702: underlying insulating film 603, 703: high dielectric constant insulating film
6 04、7 04、9 00 :金屬氮化物膜A 605、903 :金屬氮化物膜B6 04, 7 04, 9 00: Metal nitride film A 605, 903: metal nitride film B
606 :金屬氮化物膜C 607 、 906 :金屬膜 608:堆疊障壁膜 609 :種-A1 膜 705:單層障壁膜 8 02 :單層TiN障壁膜 803 : A1嵌入 804 :空隙 904 :金屬合金膜 905 : TiN單層障壁膜 300 1 :基材邊緣部 3 0 0 2:基材中心部 N、S :磁極 -37-606: metal nitride film C 607 , 906 : metal film 608 : stacked barrier film 609 : seed - A1 film 705 : single layer barrier film 8 02 : single layer TiN barrier film 803 : A1 embedded 804 : void 904 : metal alloy film 905 : TiN single-layer barrier film 300 1 : substrate edge portion 3 0 0 2: substrate center portion N, S: magnetic pole - 37-
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| JP3408527B2 (en) * | 2000-10-26 | 2003-05-19 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
| JP4614578B2 (en) * | 2001-06-01 | 2011-01-19 | キヤノンアネルバ株式会社 | Plasma processing equipment for sputter deposition applications |
| TW554420B (en) * | 2001-08-06 | 2003-09-21 | Anelva Corp | Surface processing device |
| JP2004162138A (en) * | 2002-11-14 | 2004-06-10 | Anelva Corp | Plasma assisted sputtering film-forming apparatus |
| US7211502B2 (en) * | 2003-03-26 | 2007-05-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| JP2007027392A (en) * | 2005-07-15 | 2007-02-01 | Denso Corp | Semiconductor device and its manufacturing method |
| US7892911B2 (en) * | 2008-01-10 | 2011-02-22 | Applied Materials, Inc. | Metal gate electrodes for replacement gate integration scheme |
| JP5166531B2 (en) * | 2008-06-24 | 2013-03-21 | キヤノンアネルバ株式会社 | Magnetic field generator and plasma processing apparatus |
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2010
- 2010-12-28 JP JP2010294009A patent/JP5649441B2/en active Active
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- 2011-06-24 TW TW100122221A patent/TWI509094B/en active
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| DE102011078243B4 (en) | 2022-07-21 |
| TWI509094B (en) | 2015-11-21 |
| KR101252126B1 (en) | 2013-04-08 |
| KR20120089989A (en) | 2012-08-16 |
| JP5649441B2 (en) | 2015-01-07 |
| DE102011078243A1 (en) | 2012-06-28 |
| JP2011153374A (en) | 2011-08-11 |
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