201248169 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種具有多功能BIOS的主機板及其測試方法 【先前技術】 [0002] 在一些主機板的測試過程中，客戶對出貨版本BIOS的特 殊要求往往會導致測試流程無法正常的進行。例如，客 戶要求燒錄有出貨版本BIOS的電腦進入客戶自主研發的 作業系統中，則測試時電腦便無法進入到測試用的作業 系統中。在這種情況下，目前工廠通常準備兩個版本的 BIOS燒錄文檔，先在主機板上離線燒錄測試版本BIOS， 在主機板測試完畢後出貨前再重新燒錄出貨版本BIOS， 或使用工具將測試版本BIOS改為出貨版本BIOS。但這幾 種方法都需要BIOS開發人員維護兩種版本的BIOS，增加 開發負擔和成本。此外，在測試流程中也需要增加程式 來修改BIOS版本，這對測試流程管控和測試時間都有一 定的負面影響。 【發明内容】 [0003] 鑒於以上内容，有必要提供一種具有多功能BIOS的主機 板，該多功能BIOS可以在主機板測試時實現測試版本 BIOS的功能，還可以在主機板出貨後實現出貨版本BIOS 的功能。 [0004] 還有必要提供一種多功能BIOS主機板的測試方法，可以 使該多功能BIOS在主機板測試時實現測試版本BIOS的功 能，在主機板出貨後實現出貨版本BIOS的功能。 100118783 表單編號 A0101 第 3 頁/共 14 頁 1002031707-0 201248169 刪-種具有多功能_的主機板，該主機板還包括Gpi〇介 面、跳線和電源，其中：所述多功能Bl〇s與所述^1〇介 面連接，包括測試版本^08的程式碼和出貨版本以⑽的 程式碼，所述多功能BI0S根據該GPI0的狀態位元選擇執 行測試版本BIOS的程式碼或出貨版本bIOS的程式碼；所 述跳線包括三個Pin腳，第一Pin腳與所述電源相連，第 二Pin腳與所述GPI0介面相連，第三pin腳接地。 [0006] —種多功能BIOS主機板的測試方法，包括以下步驟：讀 取步驟：當安裝有該主機板的電腦啟動時，所述多功能 BIOS讀取該GPI0介面的電平資訊，從而獲得該GPI0的狀 態位元；選擇步驟：多功能BIOS根據該GPI0的狀態位元 選擇執行測試版本BIOS的功能或出貨版本BIOS的功能。 [0007] 松較於習知技術，本發明具有多功能BIOS的主機板及其 測試方法，可以使該多功能BIOS在主機板測試時實現測 試版本BIOS的功能，在主機板出貨後實現出貨版本BIOS 的功能。 【實施方式】201248169 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a motherboard having a multi-function BIOS and a test method thereof [Prior Art] [0002] In the test process of some motherboards, the customer is out The special requirements of the BIOS version of the product often result in the test process not working properly. For example, if the customer requests that the computer with the shipped version of the BIOS be entered into the operating system independently developed by the customer, the computer will not be able to enter the test operating system during the test. In this case, the current factory usually prepares two versions of the BIOS burning document, first burns the test version BIOS offline on the motherboard, and then re-burns the shipping version BIOS before shipping the motherboard, or Use the tool to change the test version BIOS to the shipping version BIOS. However, all of these methods require the BIOS developer to maintain two versions of the BIOS, increasing the development burden and cost. In addition, an additional program is required to modify the BIOS version during the test process, which has a negative impact on test process control and test time. SUMMARY OF THE INVENTION [0003] In view of the above, it is necessary to provide a motherboard with a multi-function BIOS, which can implement the test version BIOS function when the motherboard is tested, and can also be implemented after the motherboard is shipped. The function of the goods version BIOS. [0004] It is also necessary to provide a test method for a multi-function BIOS motherboard, which enables the multi-function BIOS to implement the function of the test version BIOS when the motherboard is tested, and implements the function of the shipped version BIOS after the motherboard is shipped. 100118783 Form No. A0101 Page 3 of 14 1002031707-0 201248169 Delete a motherboard with multi-function _, which also includes a Gpi interface, jumpers and power supplies, where: the multi-function Bl〇s and The interface of the test version includes the code of the test version ^08 and the code of the shipment version (10), and the multi-function BI0S selects the code or shipping version of the test version BIOS according to the status bit of the GPI0. The program code of the bIOS; the jumper includes three Pin pins, the first Pin pin is connected to the power source, the second Pin pin is connected to the GPI0 interface, and the third pin pin is grounded. [0006] A multi-function BIOS motherboard testing method, comprising the following steps: a reading step: when a computer with the motherboard is started, the multi-function BIOS reads the level information of the GPI0 interface, thereby obtaining The status bit of the GPI0; selection step: the multi-function BIOS selects the function of executing the test version BIOS or the function of the shipping version BIOS according to the status bit of the GPI0. [0007] Compared with the prior art, the present invention has a multi-function BIOS motherboard and a test method thereof, which can enable the multi-function BIOS to implement the test version BIOS function when the motherboard is tested, and implement the function after the motherboard is shipped. The function of the goods version BIOS. [Embodiment]
[0008] 參閱圖1所示，係本發明具有多功能BIOS的主機板1較佳 實施方式的架構圖。該主機板1包括多功能BIOS (Basic Input Output System，基本輸入輸出系統）2、GPIO (General Purpose Input Output，通用輸入/輸出 )介面3和跳線4。 [0009] 所述多功能BIOS 2是一組固化到主機板1上的唯讀記憶體 (Read-only Memory，ROM)上的程式’它儲存著安裝 有主機板1的電腦中最重要的基本輸入輸出程式、系統設 100118783 表單編號A0101 第4頁/共14頁 1002031707-0 201248169 置資訊、開機自檢程式和系統自啟動程式等。其為該電 腦提供最底層的以及最直接的硬體設置和控制。本實施 方式中，在該多功能BIOS 2中新增一段電腦程式，該段 電腦程式可能被分成一個或多個軟體模組，用於在主機 板1進行測試時使多功能BI 〇 S 2實現測試版本B10 S的功 能，在主機板1出貨後使多功能BI0S 2實現出貨版本 B10S的功能。 [0010] ο [0011] 所述測試版本BIOS是指一般情況下，在主機板丨測試時燒 錄的BIOS。透過該測試版本Bl〇s，可以使安裝有主機板 1的電腦進入測試所需的環境，如測試用的作業系統中。 所述出貨版本BIOS是指根據客戶的特殊要求在主機板1燒 錄的BIOS。主機板1在燒錄該出貨版本BI〇s之後出貨。 透過該出貨版本BIOS，可以使安裝有主機板1的電腦進入 客戶要求的環境’如客戶自主研發的作業系統中。 [0012] ❹ 該測試版本BIOS和出貨版本BIOS的程式碼差別不大，一 般是一些啟動順序的設置參數和對一些硬體資源的使用 方式的差別，例如測試時要求BIOS中的SATA (Serial Advanced Technology Attachment ·串歹丨j 高級技術附 件）模式設置為 IDE (Integrated Drive Electronics ， 電子集成驅動器） 模式， 而出貨要求的 bios 中的 SATA模式設置為RAID (Redundant Array 〇f independent Disk， 獨立冗餘磁碟陣列） 模式。 多功能BIOS 2中包括測試版本BIOS的程式碼和出貨版本 BIOS的程式碼’其中測試版本BIOS和出貨版本的相 100118783 表單編號A0101 第5黃/共14頁 1002031707-0 [0013] 201248169 同程式碼部分可以共用。多功能Bl〇s 2中透過IF語句等 選擇語句選擇執行測試版本BIOS和出貨版本BIOS中不同 的程式碼部分。 [0014] 參閱圖2所示，係多功能bios 2的程式碼實現示意圖。在 多功能BIOS 2的程式碼中，可以先設置一個布林類型的 全域變數（Global Variable)，並設置根據該全域變數 的值選擇執行測試版本BIOS的程式碼部分，還是出貨版 本BIOS的程式碼部分。例如，當該全域變數為“TRUe” 時’可以執行測試版本BIOS程式碼部分，從而使多功能 BIOS 2實現測試版本Bi〇s的功能，當該全域變數為“ FALSE”時’可以執行出貨版本BI〇s程式碼部分，從而 使多功能BIOS 2實現出貨版本BIOS的功能》 [0015] 再參閱圖1所示，多功能BIOS 2可以透過讀取所述GP 1〇 介面3狀態位元的值來為該全域變數賦值，從而選擇實現 測試版本BIOS的功能，還是實現出貨版本BI〇s的功能。 [0016] GPI0介面3可以位於主機板丨的南橋晶片組。GpI〇介面3 透過電阻6與跳線4連接，該跳線4包括3個Pin腳，分別為 Pin腳 100、Pin腳2〇〇和pin腳3〇〇，其中pil^1〇〇接有 電源5，Pin腳2〇〇連接GPI0介面3，pin腳3〇〇則接地。 在Pin腳200與GPI0介面3之間還連接有電阻6，該電阻6 用於防止GPI0介面3在上電過程中燒毁。在其他實施方式 中’ GPI0介面3與pin腳2〇〇之間的電阻6也可以不要。 當透過跳帽使Pin腳1〇〇和pin腳2〇〇短路時，Gpi〇介面3 將由於連接電源5而為高電平，當透過跳帽使pin腳和 100118783 表單編號Α0101 第6頁/共14頁 1002031707-0 [0017] 201248169 [0018] Ο ❹ [0019]Referring to FIG. 1, there is shown an architectural diagram of a preferred embodiment of a motherboard 1 having a multi-function BIOS. The motherboard 1 includes a multi-function BIOS (Basic Input Output System) 2, a GPIO (General Purpose Input Output) interface 3, and a jumper 4. [0009] The multi-function BIOS 2 is a set of programs that are hardened to a read-only memory (ROM) on the motherboard 1 and stores the most important basics of the computer on which the motherboard 1 is mounted. Input and output program, system setting 100118783 Form No. A0101 Page 4 / Total 14 pages 1002031707-0 201248169 Information, power-on self-test program and system self-starting program. It provides the lowest level and most straightforward hardware setup and control for the computer. In this embodiment, a computer program is added to the multi-function BIOS 2, and the computer program may be divided into one or more software modules for implementing the multi-function BI 〇S 2 when the motherboard 1 is tested. The function of the test version B10 S enables the multi-function BI0S 2 to implement the function of the shipping version B10S after the motherboard 1 is shipped. [0011] The test version BIOS refers to a BIOS that is normally burned during a motherboard test. Through the test version Blss, the computer with the motherboard 1 installed can enter the environment required for testing, such as the test operating system. The shipping version BIOS refers to a BIOS that is burned on the motherboard 1 according to the special requirements of the customer. The motherboard 1 is shipped after burning the shipping version BI〇s. With this shipped version of the BIOS, the computer on which the motherboard 1 is installed can be brought into the environment requested by the customer, such as the operating system developed by the customer. [0012] ❹ The test version BIOS and the shipped version of the BIOS code are not much different, generally some boot order setting parameters and the difference in the use of some hardware resources, such as testing the BIOS in the SATA (Serial Advanced Technology Attachment · Serial j Advanced Technology Accessories) mode is set to IDE (Integrated Drive Electronics) mode, and the SATA mode in the bios required for shipment is set to RAID (Redundant Array 〇f independent Disk, independent redundancy) Remaining disk array) mode. Multi-function BIOS 2 includes the code of the test version BIOS and the code of the shipping version BIOS. The test version BIOS and the shipping version of the phase 100118783 Form No. A0101 5th Yellow / Total 14 Page 1002031707-0 [0013] 201248169 The code part can be shared. Multi-function Bl〇s 2 selects the different code parts in the test version BIOS and the shipped version BIOS through the IF statement and other selection statements. [0014] Referring to FIG. 2, it is a schematic diagram of the implementation of the code of the multifunctional bios 2. In the code of the multi-function BIOS 2, you can first set a global variable of the Boolean type (Global Variable), and set the code part of the test version BIOS to be executed according to the value of the global variable, or the program of the BIOS version. Code part. For example, when the global variable is "TRUe", the test version of the BIOS code portion can be executed, so that the multifunctional BIOS 2 implements the function of the test version Bi〇s, and when the global variable is "FALSE", the shipment can be performed. Version BI〇s code part, so that the multi-function BIOS 2 implements the function of the shipping version BIOS. [0015] Referring again to FIG. 1, the multi-function BIOS 2 can read the GP 1 interface 3 status bit. The value of the value is assigned to the global variable, so that the function of implementing the test version BIOS is selected, or the function of the shipping version BI〇s is implemented. [0016] The GPI0 interface 3 can be located in the south bridge chipset of the motherboard. The GpI interface 3 is connected to the jumper 4 through the resistor 6. The jumper 4 includes three Pin pins, which are a Pin 100, a Pin 2, and a Pin 3, wherein the pil^1 is connected to a power supply. 5, Pin 2 is connected to GPI0 interface 3, pin 3 is grounded. A resistor 6 is also connected between the pin 200 and the GPI0 interface 3, and the resistor 6 is used to prevent the GPI0 interface 3 from being burned during power-on. In other embodiments, the resistance 6 between the GPI0 interface 3 and the pin 2 〇〇 may not be required. When the Pin pin 1〇〇 and the pin pin 2〇〇 are short-circuited through the jump cap, the Gpi〇 interface 3 will be high due to the connection of the power source 5, and when the jump pin is used to make the pin pin and the 100118783 form number Α 0101, page 6 / A total of 14 pages 1002031707-0 [0017] 201248169 [0018] Ο ❹ [0019]
Pin腳300短路時，GPIO介面3將由於接地而為低電平。 多功能BIOS 2透過讀取GPI0介面3所處的電平資訊，可 以獲知GPI0介面3的狀態位元’該電平資訊為高電平或低 電平之一。例如，GPI0介面3的狀態位元為1表示GPI〇介 面3處於高電平，GP10介面3的狀態位元為0表示gp 1〇介 面3處於低電平。 多功能BIOS 2可設置GP10介面3的兩種狀態位元分別與 測試版本BIOS的功能和出貨版本BIOS的功能的對應關係 。例如，當多功能BIOS 2讀取到GPI0介面3的狀態位元 為1時’將選擇執行測試版本BI 〇S程式碼部分。當多功妒 BIOS 2 β貴取到GPI0介面3的狀態位元為〇時’將選擇執行 出貨版本BIOS程式碼部分。因此當需要對主機板1進行測 試時’可透過跳帽使pin_1〇Q和piri腳2〇〇短路，使 GPI0介面3的狀態位元為i，多功*BI〇s 2選擇執行測試 版本BI〇S程式碼部分，從而實現測試版本BIOS的功能。 當對主機板1測試完畢需要出貨時，可透過跳帽使pin腳 200和Pin腳300短路，Gpi〇介面3的狀態位元為〇，多功 能BIOS 2選擇執行出貨版本BI〇s程式碼部分從而實現 出貨版本BIOS的功能。 參閱圖3所不’係本發明多功能BIGS主機板的測試方法較 佳實施方式的流程圖。 先在多功能BIOS 2中設置GPI()介面3的兩種狀態位元分 別與測試版本BIOS的功能和出貨版本BI〇s的功能的對應 關係。 100118783 表單編號A0101 第7頁/共14頁 1002031707-0 [0020] 201248169 [0021] [0022] [0023] [0024] [0025] [0026] [0027] [0028] 步驟SOI，在GPIO介面3與Pin腳200連接，pin腳loo與 電源5連接，Pin腳300接地後’當安裝有主機板1的電腦 啟動時，多功能BIOS 2讀取GPI0介面3的電平資訊，從 而獲得GPI0介面3的狀態位元。當Pin腳1〇〇和Pin腳200 短路時，GP10介面3由於連接電源5而為高電平，此時 GPI0介面3的狀態位元為第一數值（如1)。當Pin腳2〇〇 和Pin腳300短路時，GPI0介面3由於接地而為低電平， 此時GPI0介面3的狀態位元為第二數值（如〇)。 步驟S02 ’多功能bios 2根據該GPI0介面3的狀態位元選 擇實現測試版本BIOS的功能或出貨版本BIOS的功能。 綜上所述’本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅爲本發明之較佳實施例，本發 明之範圍並不以上述實施例爲限，舉凡熟悉本案技藝之 人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本發明具有多功能BIOS的主機板較佳實施方式的架 構圖。 圖2係多功能Bl〇s的程式碼實現示意圖。 圖3係本發明多功能bios主機板的測試方法較佳實施方式 的流程圖。 【主要元件符號說明】 主機板1 多功能BIOS 2 100118783 表單編號A0101 第8頁/共14頁 1002031707-0 201248169 [0029] GPIO介面3 [0030] 跳線4 [0031] 電源5 [0032] 電阻6 [0033] Pin腳 100、200 〇 300 ❹ 100118783 表單編號A0101 第9頁/共14頁 1002031707-0When Pin Pin 300 is shorted, GPIO interface 3 will be low due to ground. The multi-function BIOS 2 can know that the status bit of the GPI0 interface 3 is one of the high level or the low level by reading the level information of the GPI0 interface 3. For example, a status bit of GPI0 interface 3 of 1 indicates that GPI〇 interface 3 is at a high level, and a status bit of GP10 interface 3 is 0 indicating that gp 1〇 interface 3 is at a low level. Multi-function BIOS 2 can set the correspondence between the two status bits of GP10 interface 3 and the function of the test version BIOS and the function of the shipped version BIOS. For example, when the multifunction BIOS 2 reads the status bit of the GPI0 interface 3 to 1, it will choose to execute the test version BI 〇S code portion. When the multi-function BIOS 2 β takes the status bit of GPI0 interface 3 as ’, the BIOS version of the shipping version will be selected. Therefore, when the motherboard 1 needs to be tested, the pin_1〇Q and the piri pin 2〇〇 can be short-circuited by the jump cap, so that the status bit of the GPI0 interface 3 is i, and the multi-function*BI〇s 2 selects to execute the test version BI. 〇S code part, thus implementing the function of the test version BIOS. When the motherboard 1 is tested and needs to be shipped, the pin 200 and the Pin 300 can be short-circuited by the jump cap. The status bit of the Gpi interface 3 is 〇, and the multi-function BIOS 2 selects to execute the shipping version BI〇s program. The code portion thus implements the function of the shipping version BIOS. Referring to Figure 3, there is shown a flow chart of a preferred embodiment of the test method of the multi-function BIGS motherboard of the present invention. First, in the multi-function BIOS 2, the two status bits of the GPI() interface 3 are set to correspond to the functions of the test version BIOS and the functions of the shipping version BI〇s. 100118783 Form No. A0101 Page 7 / Total 14 Page 1002031707-0 [0020] [0020] [0023] [0028] [0028] Step SOI, in the GPIO interface 3 The pin foot 200 is connected, the pin foot loo is connected to the power source 5, and the pin pin 300 is grounded. 'When the computer with the motherboard 1 is started, the multi-function BIOS 2 reads the level information of the GPI0 interface 3, thereby obtaining the GPI0 interface 3. Status bit. When the Pin pin 1〇〇 and the Pin pin 200 are short-circuited, the GP10 interface 3 is at a high level due to the connection of the power source 5, and the status bit of the GPI0 interface 3 is the first value (such as 1). When Pin pin 2 〇〇 and Pin pin 300 are short-circuited, GPI0 interface 3 is low due to grounding, and the status bit of GPI0 interface 3 is the second value (such as 〇). Step S02 ’ Multi-function bios 2 selects the function of the test version BIOS or the function of the shipped version BIOS according to the status bit of the GPI0 interface 3. In summary, the invention conforms to the patent requirements of the invention, and the patent application is filed according to law. The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a preferred embodiment of a motherboard having a multifunction BIOS of the present invention. FIG. 2 is a schematic diagram of the implementation of the code of the multifunctional Bl〇s. Fig. 3 is a flow chart showing a preferred embodiment of the test method of the multifunctional bios motherboard of the present invention. [Main component symbol description] Motherboard 1 Multi-function BIOS 2 100118783 Form No. A0101 Page 8 of 14 1002031707-0 201248169 [0029] GPIO interface 3 [0030] Jumper 4 [0031] Power supply 5 [0032] Resistor 6 [0033] Pin foot 100, 200 〇 300 ❹ 100118783 Form number A0101 Page 9 / Total 14 page 1002031707-0