TW201239993A - Thin film transistor and method for fabricating the same - Google Patents

Abstract

A method of fabricating a thin film transistor (TFT) and a TFT are provided. In the method, a source and a drain electrically isolated from each other are formed on a substrate. A patterned oxide semiconductor layer and a pixel semiconductor layer are simultaneously formed on the substrate. A patterned etching stopper is formed on the oxide semiconductor layer, the patterned etching stopper exposes a part of the oxide semiconductor layer disposed at two sides of the etching stopper. A gate insulation layer is formed on the substrate. A part of the patterned oxide semiconductor layer exposed by the etching stopper is transformed into two ohmic contact layers and the pixel semiconductor layer is transformed into a pixel electrode during the gate insulation layer forming process. A gate is formed on the gate insulation layer on the patterned oxide semiconductor layer.

Description

201239993 117033ITW 37169twf.doc/I VI. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor and a method of fabricating the same, and more particularly to a thin film transistor having an oxide semiconductor layer and Production method. [Prior Art] Recently, liquid crystal display panels with superior power consumption, high space utilization efficiency, no radiation, and high enamel have become mainstream in the market. Conventionally, a liquid crystal display panel has mostly used an amorphous germanium (fl_Si) thin film transistor or a low-temperature polySilicon (LTPS) thin film transistor as a switching element of each halogen structure. However, in recent years, it has been pointed out that an oxide semiconductor (oxide semiconductor) film transistor has a higher carrier mobility* compared to an amorphous germanium film transistor, and The low temperature polycrystalline slab thin film transistor oxide semiconductor thin film transistor has a better threshold voltage (threshold: ltage, Vth) uniformity. Therefore, oxide semiconductor thin film transistors have become potential components of next-generation flat panel displays. In general, the manufacturing process of an oxide semiconductor thin film transistor is roughly the same as that of a seven-mask process. First, a gate is formed on the soil 5 using a first-pass mask process. Then, a gate insulating layer pU gate is formed on the substrate. Then, using the second mask process, an oxide semiconductor layer is formed on the layer A, ', and the layer above the gate. Then, use the third mask 4

201239993 117033ITW 37169twf.doc/I Process 'The resist layer is formed on a portion of the oxide semiconductor layer. Next, a dielectric layer ' is formed on the gate insulating layer, the oxide semiconductor phase, and the squeezing layer, and the oxide semiconductor layer located at the (four) barrier layer is chlorine doped to be converted into a two ohmic contact layer. Thereafter, the thin mask process 'forms two openings in the dielectric layer above the two ohmic contact layers, exposing the two ohmic contact layers, respectively. Then, the fifth ray mask process of Hunan, the shape of the enamel on the dielectric layer _ extremely sister pole, and the impurity and the bungee are filled into the two openings respectively and connected with the two ohmic contact layer, and then formed on the substrate After the insulating layer covers the source ship, the sixth pass mask process is used to form a contact on the insulating layer to expose the drain. Finally, the seventh mask is used to cut the substrate into a pixel, and the pixel electrode is filled in the contact window to be connected to the microelectronics. Here, the fabrication of a conventional oxide semiconductor thin film transistor is completed. However, the above-described oxide semiconductor thin film transistor is complicated in production process and high in manufacturing cost. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method for manufacturing a thin film transistor, which simplifies the process of the thin film transistor and reduces the manufacturing cost. The present invention also provides a thin film transistor which has a simple manufacturing cost. The present invention provides a method of manufacturing a thin film transistor. A source electrically insulated from each other is formed on the substrate: 3⁄4 pole. An oxide semiconductor layer and a pixel semiconductor layer are simultaneously formed on the substrate, wherein the _ oxide conductor layer is located between the secret electrode and the pixel semiconductor layer is located at the pixel electrode 201239993

117033ITW 37169twf.doc/I Formation on the oxide semiconductor layer _etching 狯 layer patterned silver etch barrier to expose the patterned oxide semi-conductive layer on the patterned side of the two households ^ two ^ ί2 process At the same time, the oxide layer of the oxide layer is formed into a two-ohmic contact electrically connected, and the two ohms are respectively combined with: _ is formed on the edge layer. _Chemical + the gate above the conductor layer ^ invention provides a kind of thin film transistor, including: source, no electrode layer, patterned money engraved barrier layer, interlayer insulation layer, between idle, material patterned oxide The semiconductor layer is located on the source and the immersion: = patterned oxide semi-conductive layer and exposes a two-conducting edge, covering the patterned etched resist layer and the patterned oxide half-doped at the patterned oxide semiconductor The gate insulation layer above the layer. The denier electrode is electrically connected to the drain via the ohmic contact layer, wherein the 昼 j pole, the patterned oxide semiconductor layer and the ohmic contact layer are in the same position and layer, and the material of the pixel electrode and the ohmic contact layer are the same. In an embodiment of the invention, the pixel semiconductor layer and the patterned semiconductor layer are made of the same material and are selected from the group consisting of indium gallium zinc oxide (I0), indium zinc oxide (IZ0), and oxidized marriage ( iG〇), tin oxide bismuth, chemistry, oxidization error (2CdO.Ge〇2), oxidized tree Nic〇2〇4) and combinations thereof. 6

201239993 117033ITW 37169twf.doc/I In an embodiment of the invention, the method for forming an ohmic contact layer and a halogen electrode comprises: forming a gate insulating layer, and performing a patterned oxide semiconductor layer and a halogen semiconductor Hydrogen doping. In an embodiment of the invention, the material of the ohmic contact layer and the halogen electrode is selected from the group consisting of nitrogen-containing indium gallium zinc oxide (IGz〇), indium zinc oxide (IZO), and gallium germanium oxide (IG0). Tin oxide (Zn0), oxidized, oxidized (2Cd0.Ge02), nickel oxide (NiC〇2〇4) and combinations thereof. In an embodiment of the present invention, the method for fabricating a thin film transistor further includes forming a data line on the substrate while forming a source and a drain which are electrically insulated from each other on the substrate, and the data line and the source Electrical connection. In an embodiment of the present invention, the method for fabricating a thin film transistor further includes: forming a scan line on the substrate on the substrate of the same day on the gate insulating layer above the patterned oxide semiconductor layer, and scanning lines and Electropolarity = Hair_ In the embodiment, the above-mentioned thin film transistor is formed on the gate insulating layer above the patterned oxide semiconductor layer and a patterned protective layer is formed on the substrate. Patterned protective layer The material line _^ electrically connects the scan line contact opening to the external drive signal supply source. The metal of the film layer or the metal of the composite film layer. Obtained by the open base == in the hair (4) thin film crystal and manufacturing method, the bad (four) into the room, the ', 邑, 彖 layer, while forming the ohmic contact layer and the pixel 201239993

117033ITW 37169twf.doc/I electrode, which can simultaneously reduce the resistance value of the patterned oxide semiconductor layer and the halogen semiconductor layer in the same step, can simplify the fabrication of the thin film transistor, and make the thin film transistor have excellent electrical properties. characteristic. The above described features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] [Manufacturing Method of Thin Film Transistor] Figs. 1A to 1F are schematic top views showing a manufacturing process of a thin film transistor according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views showing a manufacturing process of a thin film transistor according to the line A - A ' of Figs. iA to 1F. Referring to Fig. 1A and Fig. 2A, first, a source S and a gate D which are electrically insulated from each other are formed on the substrate 11A. While the source S and the drain D are formed, the data line DL is formed on the substrate 110, and the data line DL is electrically connected to the source S. The material of the source S, the drain D, and the data line DL may be a metal material (such as Ti, Mo, A1, etc.), a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or the like, and a source thereof. The pole s, the drain D and the data line DL may be a single film layer or a composite stacked film layer. The source S, the drain D and the data line DL can be formed by a general sputtering film formation process, and a lithography process (ie, photoresist coating, lithography, film peeling step) to form a source S The pattern of the immersion D and the data line dl will not be described in detail here. Referring to FIG. 1B and FIG. 2B, a patterned oxide semiconductor layer 122 and a halogen semiconductor layer 124 are simultaneously formed on the substrate 11 , wherein 8 201239993

H7033ITW 37169twfdoc/I The semiconductor layer 122 is located between the source S and the host D, and the pixel + conductor layer m is located opposite to the predetermined area of the pixel electrode. Sound up, as shown in FIG. 1B, 'the patterned oxide semiconductor/xenon oxide conductor layer 124 is made of the same photomask, and the pattern conductor layer 122 covers part of the source S and the drain D, and The material semiconductor layer 122 may be connected to the halogen semiconductor layer 124. In the second embodiment, the patterned oxide semiconductor layer 122 may not be connected to the ϋ=conductor layer 124, as long as the patterned oxide semiconductor layer 122 and the j semiconductor layer m are both located on the secret D (subsequently can be electrically operated via the immersion D). Sexual connection). The pixel semiconductor layer 124 is the same as the patterned oxide semiconductor, and may be selected from the group consisting of: indium gallium zinc oxide (IGZ〇), indium zinc oxide (ITO), = indium gallium (IGO), tin oxide. (Zn〇), cadmium oxide, cerium oxide (10) 〇. 〇 tons), oxidized 姑 (clear (10) 4) and combinations thereof, but not limited to this. The patterning of the patterned oxide semiconductor layer 122 and the pixel semiconductor layer 124 can be performed by sputtering, film formation, and lithography (ie, photoresist coating, lithography, surname etching, film stripping, etc.) The pattern of the patterned oxide semiconductor layer 122 and the pixel half layer 124 shown in FIG. 2 and FIG. 2B is formed, and will not be described in detail herein. Referring to Fig. 1C and Fig. 2C', a patterned engraving block is formed on the patterned oxide semiconductor layer (2). The patterned rice resisting sound (10) is exposed to the portion of the patterned side resist 13 = = oxide semiconductor layer 122. The patterned side resist layer 130 covers a patterned oxide of a partial region 201239993

117033ITW 37169twf.doc/I semiconductor layer 122 for protecting the patterned _ 朗 i i3 (), the oxide semiconductor layer 122 still maintains semi-conductive characteristics after subsequent processes (can be used as the subsequent source s and the immersion D The inter-channel patterned side barrier layer 130 can also be referred to as a channel protection layer/, so that the patterned side P and the formation of the barrier layer U0 can be formed by using a film formation process in conjunction with a photolithography process (ie, photoresist coating, micro The pattern of the patterned two-etch barrier layer 130 as shown in FIG. 1C and FIG. 2C is not described in detail. The material of the patterning and etching resist layer can be Referring to FIG. 1D and FIG. 2D, the gate insulating layer 140 is entirely formed on the substrate 110, and the etching barrier layer is simultaneously patterned during the formation of the gate insulating layer 140. A portion of the patterned oxide semiconductor layer 122 exposed by 130 is formed as a two-ohmic contact layer i22a, and a pixel semiconductor layer 124 located in a predetermined region R of the pixel is formed as a pixel electrode i24a, a halogen electrode 124a and a drain D Electrically connected, and two ohmic contact layers 122 & respectively The source and drain S E) is electrically connected. More specifically, the method of forming the two-ohmic contact layer 122a and the halogen electrode 124a includes: performing hydrogen doping for the patterned oxide semiconductor layer 122 and the pixel semiconductor layer 124 while forming the gate insulating layer 14? The patterned oxide semiconductor layer 122, which is not covered by the patterned etch barrier layer 形成3, forms an electrically conductive ohmic contact layer 122a, and the halogen semiconductor 124 forms a conductive iridium electrode 124a. For example, plasma-assisted chemical vapor deposition (Plasma) can be used.

Enhanced Chemical Vapor Deposition (PECVD) to form gate insulation layer 201239993

117033ITW 37169twf. doc/I 140, the gas used in the plasma-assisted chemical vapor deposition method is selected from the group consisting of tetrahydrogen hydride (SiH4), nitrous oxide (n2 ruthenium), ruthenium (He) and combinations thereof. The gate insulating layer 140 is, for example, yttrium oxide (si〇x). However, the present invention is not limited thereto. In other embodiments, the gas used to form the gate insulating layer 14〇 may be selected from the group consisting of tetrahydrogen hydride (SiH4), hydrogen hydride (nh3), nitrogen (N2), and hydrogen (3⁄4). And a combination thereof, the gate insulating layer 140 may also be tantalum nitride (SiNx). Therefore, when the gate insulating layer 140 is formed, the exposed patterned oxide semiconductor layer 122 and the halogen semiconductor layer 124 (such as indium gallium oxide (IGZ〇)) are exposed to hydrogen ions in the plasma containing hydrogen ions. The doping is converted into a material having a conductive property, that is, the ohmic contact layer 122a and the halogen electrode 12, for example. That is, the material of the ohmic contact layer 122a and the pixel electrode 124a may be selected from hydrogen-containing indium gallium zinc oxide (IGZ0), indium oxide (IZ〇), oxidized gallium (IGO), tin oxide (ZnO), Oxidized crane, cerium oxide (2Cd 〇 & 〇 2), nickel cobalt oxide (NiCo204) and combinations thereof. The 疋' is made by the process steps of FIG. 1D and FIG. 2D, and the __ 14G is simultaneously—and the ohmic and halogen electrodes 124a are formed, so that no additional 22a oxide semiconductor layer 122 and painting are required. The semiconductor semiconductor * _ patterning: the mouth is transformed into a conductive ohmic contact layer 122a spot, resistance value, respectively, to simplify the process of the thin film transistor. Referring to FIG. 1E and FIG. 2E, a semiconductor is formed on the dummy insulating layer 140 above the layer m, and a gate electrode 0 for forming the gate G is formed on the substrate 110. Tian, and scan line with 201239993

117033ITW 37169twf.doc/I The material of the gate G and the scanning line SL can be made of a metal material (such as Ti, Mo, A1, etc.), a nitride of a metal material, oxidation of a metal material, or a nitrogen oxide of a metal material. And the gate G and the scan line may be a single film layer or a composite stacked film layer. The gate G and the scan line 3 can be formed by a general sputtering film formation process and a lithography process (ie, photoresist coating, lithography, surname etching, film stripping, etc.) to form the gate G and The pattern of the scanning line SL will not be described in detail herein. Thus, the inter-electrode g, the source § and the dipole D can constitute the thin film transistor 100. And Figure I can also form a patterned contact H on the substrate (4). The slab 15G has a plurality of contact window openings H, and the contact opening of the thin film transistor and the end portion DLT of the data line DL is exposed so that the W SLT of the scan...= is opened by the contact window. Electrically connected to the outside of the "hidden line sinking pattern of Baoxian 15 〇 矽, gas cut, gas oxygen cut into inorganic materials (for example: nitrided organic materials or a combination of the above. Outer Qiu drive ^ - material stacking Layer), driving W. The external rotation signal supply source PS is, for example, an insulating film transistor 100 manufactured by the _ insulating layer 14G, and formed to form the gate 124a, so that no additional connection is required. The coffee and halogen electrical conductor layer 122 and the pixel semi-conductor reduce the number of patterned oxide half mask processes to reduce and simplify the _day resistance value. The overall required photovoltaic crystal can have an excellent process of the electrical body 100. And film 12

201239993 117U331IW 37169twf. doc/I

[Thin Film Transistor 1 Figure IF is a top view of the thin film transistor of the present invention.

And / 2F is the line A_A according to Fig. 1F, and the thin film transistor surface is not intended. J, while referring to FIG. 1F and FIG. 2F, the thin film transistor may include: etch resist: D, patterned oxide semiconductor layer 122, patterned etch 1a 130, gate insulating layer M 〇, gate G, and ruthenium The electrode 丨 2 is known. The L semiconductor semiconductor layer 122 is located between the source S and the drain D.

The Lrv semiconductor layer 122 has a two ohmic contact layer core. The upper surface of the thyristor layer 122 is replaced by m = γα > The bismuth electrode 124a is of the same quality. The dashed electrode 124a and the ohmic contact layer 122a are drawn by a line SL. The HH, 100 can further include the data line DL and the electrode G electrical connection L, the source S is electrically connected. Scan line SL and gate 150, _^1. /; ^ = body Qing can also include a patterned protective layer t · 蒦 蒦 layer MO covering the entire thin amine transistor scanning line SL end SLt * ^ = H exposed film to make the sweep line SL The end of the line DL DLt, . #枓线DL via contact window opening h Electrical connection 13 201239993

117033ΓΓ W 37l69twf.docA Provides the source PS to the external drive signal. The material of each element of the thin film transistor 100 has been described in the above-described method for manufacturing a thin film transistor, and will not be repeated here. The above-described thin film transistor 100 has a simple structure, low fabrication cost, and excellent electrical characteristics. In summary, the thin film transistor of the present invention and the method of manufacturing the same have at least the following advantages: η is formed by hydrogen doping of the patterned oxide semiconductor layer and the pixel semiconductor layer while forming the gate insulating layer; The ohmic contact layer and the halogen electrode are used, so that the resistance value of the patterned oxide semiconductor layer and the pixel semiconductor layer can be reduced without an additional process, and the process of the thin film transistor is simplified and has excellent electrical characteristics. Further, the number of mask processes for fabricating the above-described thin film transistor can be reduced as compared with the conventional mask process of the oxide semiconductor thin film transistor. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1F are schematic top views showing a manufacturing process of a thin film transistor according to an embodiment of the present invention. 2A to 2F are schematic cross-sectional views showing the manufacturing process of the thin film transistor according to the line Α-Α of Figs. 1A to 1F. 201239993

117U331TW 37169twf.doc/I [Description of main component symbols] 100: thin film transistor 110: substrate 122: patterned oxide semiconductor 122a: ohmic contact layer 124: pixel semiconductor layer 124a: germanium electrode 130: patterned etching barrier layer 140 : gate insulating layer 150 : patterned protective layer D · > and pole DLt · data line end DL : data line G : gate Η : opening PS : external driving signal supply source R: halogen electrode predetermined area S : Source SLT: End of scan line SL: Scan line 15

Claims (1)

201239993 H7033ITW 37169twf.doc/I VII. Patent application scope: 1. A method for manufacturing a seed/transistor crystal, comprising: forming a source and a drain electrically insulated from each other on two substrates; Forming - patterned oxide semiconductor - ^ semiconductor layer 'where 'the _ oxidized semiconductor layer is located at the source of the ^ ^;, the secret between the 昼 半导体 半导体 昼 昼 昼 昼 昼 昼 昼 昼 昼 电极 电极 电极 电极 电极 电极 电极 电极Forming a gate insulating layer in the pattern on the semiconductor layer to form a portion of both sides of the resistive layer, and forming a gate insulating layer in the pattern to form a gate insulating layer The exposed germanium oxide semiconductor layer is formed as a predetermined area of the two-ohmic contact layer, and the germanium semiconductor layer is formed as a pixel electrode, and the pole is electrically connected to the sister, and the source and the electrodeless New connection; Μ (10) and Gu Jicheng-3 patterned oxide oxide layer above the gate insulating layer on the surface of the ancient soil 2 full-scale cofferdam 1 (4) the manufacture of the film transistor II, the pixel semiconductor layer And the patterned oxide semiconductor layer The same quality, and selected from: indium gallium zinc oxide (IGZ0), indium oxide indium gallium oxide, tin oxide (10)), oxidized crane, cerium oxide (0 0 ^), nickel cobalt (NiC 〇 204) and Its combination. The method of manufacturing a thin germanium transistor according to claim 1, wherein the method of forming the ohmic contact layer and the germanium electrode comprises: forming the gate insulating layer At the same time, a hydrogen doping is performed on the patterned oxide semiconductor layer and the pixel semiconductor. 4. The thin film transistor according to claim 1, wherein the ohmic contact layer and the material of the halogen electrode are selected from the group consisting of hydrogen-containing indium gallium zinc oxide (IGZO) and indium zinc oxide (IZ). 〇), indium gallium oxide (IG〇), tin oxide (Zn〇), oxidation recorded, cerium oxide (2Cd0.Ge02), oxidation recorded Nic〇2〇4) and combinations thereof. 5. The fabrication of a thin film transistor according to claim 1, wherein the source and the ancestors are electrically insulated from each other on the ruthenium substrate; and the method further comprises: forming on the substrate Line, and; 'The feed line is electrically connected to the source. μ 方 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A "bulk" is formed on the substrate and the object trace is electrically connected to the pole. ^ Method Item (4) After the fabrication of the crystal of the material into the gate, the method further comprises: forming a gate on the gate insulating layer above the semiconductor layer, exposing = the vine layer has a plurality of contact opening portions, so that the scan = trace The end of the connection with the data line to the external drive =: the line through the contact window opening electrical 17 201239993 117033ITW 37169twf.doc / I •. • As described in the patent scope of the patent section A, the method Wherein the source, the & pole and the metal of the film layer of the gate, or the metal of the composite film layer.匕 :: a single 9. A thin germanium transistor, comprising: a source and a drain; - patterned oxide semiconductor layer, located between the patterned oxide semiconductor layer has a two-ohm contact layer Wei a patterned etch barrier layer on, overlying the ohmic contact layer; 〃 an oxide semiconductor layer-gate insulating layer covering the patterned etched semiconductor layer; a patterned oxygen edge layer and a shaft case The first pixel electrode 'above the oxide semiconductor layer is electrically connected to the drain via the ohmic contact layer, wherein the pixel is in the same position as the patterned oxide semiconductor contact layer And the pixel electrode is the same material as the European layers. 10. The thin film transistor according to claim 9, wherein the patterned oxide semiconductor layer is selected from the group consisting of: copper oxide zinc (IGZO), indium zinc oxide (yttrium), and indium oxide. Gallium (IG〇), tin oxide (Ζη〇), oxidized ore, cerium oxide (2CdO. Ge02), oxidized cobalt (NiCo2〇4), and combinations thereof. 11. The thin film transistor according to claim 9, wherein the material of the ohmic contact layer and the halogen electrode is selected from the group consisting of hydrogen-containing indium gallium zinc oxide (IGZO) and indium zinc oxide (ITO). Indium gallium oxide (IGO) 'oxygen 201239993 117U33HW 37169twf.doc/I tin (ZnO), cadmium oxide, cerium oxide (2Cd0.Ge02), nickel cobalt oxide (NiCo204) and combinations thereof. 12. The thin film transistor of claim 9, further comprising: a data line electrically connected to the source. 13. The thin film transistor of claim 9, further comprising: a scan line electrically connected to the gate. 14. The thin film transistor of claim 9, further comprising: a patterned protective layer covering the entire thin film transistor, the patterned protective layer having a plurality of contact openings for exposing the thin film transistor An end of a scan line and an end of a data line, such that the scan line and the data line are electrically connected to an external drive signal supply source via the contact window openings. 19