201234032 六、發明說明： 【發明所屬之技術領域】 【先前技術】 一般而言，電源雜訊、頻率不匹配、元件雜訊等都會 電路中的擾動。為了確保高速傳輸下的訊號完整度， 資料時脈回覆(Clock/data Recovery, CDR)電路必須要能夠 容忍輸入資料具有的擾動。擾動容忍(Jitter T〇lerance)一般 係用來評估資料時脈回覆電路在位元錯誤率(Bit_err〇r_rate, BER)低於目標值下時能容忍多少輸入資料擾動。然而，一 般而言在量產時必需要外加自動測試儀器來量測資料時脈 電路的擾動容忍。因此，在資料時脈回覆電路内建自我測 試功能將可大量降低成本。 J. E. Jaussei et al., Uln-situ jitter tolerance measurement technique for serial 1/0，” in Symposium on VLSI Circuits， Dig. Tech. Papers, pp_ 168-169, June 2008 揭露 了一種類比式 的擾動自我測試電路。該論文藉由使用數位類比轉換器及 調節充電幫浦產生類比擾動，並疊加一正弦波於一電壓控 制震盪器的控制電壓以調節時脈。然而，因為電路中每一 元件的實際數據係未知的’因此每一次測量前皆必須校 準，造成不便。 因此，目前極需要一種運用於資料時脈電路的數位擾 201234032 動自我測試電路，能準確方便地量測資料時脈電路的擾動 容忍。 【發明内容】 本發明提供一種一種擾動自我測試電路，包括：一待 測電路、一雙模除頻器及一偽隨機二進制序列。該雙模除 頻器耦接該待測電路並產生一帶有擾動之時脈訊號。該偽 隨機二進制序列產生器，耦接該雙模除頻器與該待測電 路，且該偽隨機二進制序列產生器，接收該帶有擾動之時 脈訊號以產生一帶有擾動之資料訊號至該待測電路。 較佳地，該擾動為正弦擾動。 較佳地，本發明擾動自我測試電路，進一步包括： 一 正弦函數產生器，產生一正弦波；及 一一階三角積分調 變器，耦接該正弦函數產生器及該雙模除頻器，該一階三 角積分調變器接收該正弦波以產生一一位元的訊號，以調 變該雙模除頻器。 較佳地，該待測電路為一資料時脈回覆電路。 較佳地，該資料時脈回覆電路包括一亞力山大相位偵 測器、一頻率偵測器、電壓電流轉換器、一被動迴圈濾波 器及一電壓控制震盪器。 較佳地，該待測電路具有一工作模式及一擾動測試模 式。 較佳地，本發明擾動自我測試電路，進一步包括：一 偽隨機二進制序列檢查器，藕接該待測電路，且該偽隨機 二進制序列檢查器具有一同步模式及一擾動自我測試模 201234032 式。 較佳地，該偽隨機二進制序列檢查器於同步模式時， 接收該待，電路的一4新定時訊號以同步該偽隨機二進制 序列產生器，且該偽隨機二進制序列檢查器於擾動自我測 s式模式時’輸出一比較訊號。 综上所述，本發明擾動自我測試電路產生數位擾動， 達到自我擾動容忍測試。 【實施方式】 以下即配合圖式說明本發明之具體實施方式；然需瞭 解的是、’這些圖式中所標示之元件及步驟係為說明清晰之 用，其並不代表實際的尺寸與比例，且為求圖面簡 潔以利 於瞭^，部分圖式中亦省略了，習知元件之繪製。 明參考第-圖，其係繪例示說明本發明擾動自我測試 電路100之基本結構。擾動自我測試電路⑽包括：一待 測電路110、-雙模除頻器12G及—偽隨機二進制序列 (Pseudo Random Binary Sequence，PRBS)產生器 13〇。如第 圖所示°亥雙模除頻器120輕接該待測電路丨1 〇，且該偽 隨機二進制序舰生H 13〇㈣該雙模除齡12()與該待 測電路110。第二圖係顯示該雙模除頻旨12〇的一種實施態 樣。第一圖係顯示该偽隨機二進制序列產生器的一種 實施態樣。 一般而言，該待測電路110為一資料時脈回覆 (Clock/data Recovery)電路。該資料時脈回覆電路包括一亞 201234032 力山大相位债測器111 (Alexander Phase Detector )、一頻率 4貞測器（Frequency Detector) 112 '電壓電流轉換器 (Voltage-to-current Converter)113、一被動迴圈渡波器 (Passive Loop Filter)l 14、一電壓控制震盪器（V〇itage_201234032 VI. Description of the invention: [Technical field to which the invention pertains] [Prior Art] In general, power supply noise, frequency mismatch, component noise, and the like are disturbed in the circuit. In order to ensure signal integrity under high-speed transmission, the clock/data recovery (CDR) circuit must be able to tolerate the disturbance of the input data. Jitter T〇lerance is generally used to evaluate how much input data disturbance the data clock reply circuit can tolerate when the bit error rate (Bit_err〇r_rate, BER) is below the target value. However, in general, it is necessary to add an automatic test instrument to measure the disturbance tolerance of the data clock circuit during mass production. Therefore, the built-in self-test function in the data clock reply circuit can greatly reduce the cost. JE Jaussei et al., Uln-situ jitter tolerance measurement technique for serial 1/0," in Symposium on VLSI Circuits, Dig. Tech. Papers, pp_ 168-169, June 2008 discloses a type of perturbation self-test circuit The paper uses the digital analog converter and adjusts the charge pump to generate an analog disturbance and superimposes a sine wave on a voltage controlled oscillator control voltage to adjust the clock. However, because of the actual data system of each component in the circuit. Unknown 'Therefore, it must be calibrated before each measurement, which is inconvenient. Therefore, there is a great need for a digital disturbance 201234032 dynamic self-test circuit applied to the data clock circuit, which can accurately and conveniently measure the disturbance tolerance of the data clock circuit. SUMMARY OF THE INVENTION The present invention provides a disturbance self-test circuit including: a circuit to be tested, a dual-mode frequency divider, and a pseudo-random binary sequence. The dual-mode frequency divider is coupled to the circuit to be tested and generates a a clock signal of the disturbance. The pseudo-random binary sequence generator is coupled to the dual-mode frequency divider and the circuit to be tested And the pseudo-random binary sequence generator receives the disturbed clock signal to generate a disturbed data signal to the circuit under test. Preferably, the disturbance is a sinusoidal disturbance. Preferably, the present invention disturbs the self. The test circuit further includes: a sine function generator for generating a sine wave; and a first-order triangular integral modulator coupled to the sine function generator and the dual mode frequency divider, the first-order triangular integral modulator Receiving the sine wave to generate a one-bit signal to modulate the dual-mode frequency divider. Preferably, the circuit to be tested is a data clock reply circuit. Preferably, the data clock reply circuit comprises An Alexandria phase detector, a frequency detector, a voltage current converter, a passive loop filter and a voltage controlled oscillator. Preferably, the circuit to be tested has an operating mode and a disturbance test mode. Preferably, the perturbation self-test circuit of the present invention further comprises: a pseudo-random binary sequence checker splicing the circuit to be tested, and the pseudo-random binary sequence checker has a Synchronous mode and a perturbed self-test module 201234032. Preferably, the pseudo-random binary sequence checker receives a 4 new timing signal of the circuit to synchronize the pseudo-random binary sequence generator in the synchronous mode, and the The pseudo-random binary sequence checker outputs a comparison signal when perturbing the self-test s mode. In summary, the perturbation self-test circuit of the present invention generates a digital perturbation to achieve a self-perturbation tolerance test. [Embodiment] The specific embodiments of the present invention are described; it is to be understood that the elements and steps indicated in the drawings are for clarity of description, and do not represent actual dimensions and proportions, and are simple in order to facilitate the drawing. ^, part of the diagram is also omitted, the drawing of the conventional components. Referring to Fig. 1, there is illustrated a basic structure of the disturbance self-test circuit 100 of the present invention. The disturbance self-test circuit (10) includes: a circuit to be tested 110, a dual mode frequency divider 12G, and a Pseudo Random Binary Sequence (PRBS) generator 13A. As shown in the figure, the Haihai dual mode frequency divider 120 is lightly connected to the circuit under test 丨1 〇, and the pseudo random binary sequence ship H 13 〇 (4) the dual mode erasing 12 () and the circuit to be tested 110. The second figure shows an embodiment of the dual mode divide by frequency. The first figure shows an implementation of the pseudo-random binary sequence generator. Generally, the circuit under test 110 is a data clock/recovery (Clock/data Recovery) circuit. The data clock return circuit includes a Asia 201234032 Alexander Phase Detector 111, a Frequency Detector 112 'Voltage-to-current Converter 113, one Passive Loop Filter l 14, a voltage controlled oscillator (V〇itage_
Controlled Oscillator)115 及多工器（Multiplexer)116。一般而 言，該電壓控制震盪器115可為一差分四階環振盪器。Controlled Oscillator) 115 and Multiplexer 116. In general, the voltage controlled oscillator 115 can be a differential fourth order ring oscillator.
忒雙模除頻器120產生一帶有擾動之時脈訊號，且具 ^ N及N+1雙模，其中N為正整數。而第二圖所繪示之雙 极除頻器120，係依據N為16所設計以做說明。該偽隨機 —進制序列產生器130自該雙模除頻器12〇接收該帶有擾 動之時脈訊號以產生一帶有擾動之資料訊號至該待測電路 雖於此以雙模除頻器12〇2N* 16來舉例說明，缺 ，實施例中並不侷限於此，雙模除㈣12〇之n亦可為 7、18等。凡是具有除頻魏之雙模除㈣皆不脫離本發 —本發明一種實施例中，擾動自我測試電路1〇〇更包括 函產生器140及一階三角積分調變器150。該正弦 150，耦丄140 I生一正弦波。該-階三角積分調變器 —H 數產生器14G及該雙模除齡12〇。該 號；^議150接收該正弦波以產生-位元的訊 除^ 魏調㈣雙模⑽。該雙模 制序列產生3 130自動之時脈訊號。該偽隨機二進 座生态130自該雙模除艏哭 動之時脈訊號以產生帶有正弦擾動^收該帶有正弦擾 袼11()。 擾動之資料訊號至該待測電 201234032 該待測電⑯HO I有一工作模式及一擾動測試模式。當 该待測祕11G處於工作模式時，多卫1116進人模式等於 〇的狀態。多工器116於此時連接頻率為f的輸入資料(Din) 及電壓控制震盪器的同相’正交輸出(In/Quadrature 〇帅吣 並傳輸至該亞力山大相位偵測器⑴，此時待測電路11〇即 以正常方歧作；其中朗相/正交輸出包括vc〇」訊號及 VCO—Q訊號。舉例而言，如該待測電路u 覆電路，輸入資料可為頻率為6Gbps的資料。巧貝料子脈口 當該待測電路110處於擾動測試模式時，多工器116 進入模式等於1的狀態。多工器116並傳輸該偽隨機1進制 序列產生器U0之帶有擾動之資料訊號及一參考時脈訊號 (Ref_CK)至該亞力山大相位债測器⑴。此時，因為該雙模 除頻器120設定為輸出頻率為輸入頻率之1/N或是 1/(N+1)’所以雙模除頻器12〇輸出至偽隨機二進制序列產 生器130之訊號的頻率為f/N或是f/(N+1)。而偽隨機二進 制序列產生器130依此產生頻率為f/N或是f/(N+1)之資料 訊號至待測電路110。換句話說，輸入至待測電路之資 料訊號之輸入資料率減少N倍。然而，當輸入資料率減少 N倍時’該待測電路11〇的頻寬迴路增益也減少n倍。所 以’為了維持該待測電路11 〇的迴路增益，電壓電流轉換号 (Voltage-to-current Converter) 113 的電流需增加]^倍。如此 一來’該電壓控制震盪器115的工作頻率將與該待測電路 110處於工作模式下的該電壓控制震盪器n5相同。舉例而 言，該電壓控制震蓋器115的工作頻率在工作模式及擾動測 試模式下皆為6GHz。 201234032 娜述’該正弦函數產生器140及該-階三角積分 °田、:狄係用以調節該雙模除頻器120 ;進一步言之，係 雙換除頻器120的除比率(DivisionRati。）。該雙 二二器120自該電壓控制震盪器115接收vco—1訊號， 、二汛號除頻並輸出該帶有擾動之時脈訊號。如上 1述^偽隨機二進制序列產生器13G接收該帶有擾動之 時脈，唬以產生帶有擾動之資料訊號至該待測電路110。由 上述說明可知，該雙模除頻器120係數位調節該偽隨機二 進制序列產生器130。The dual mode frequency divider 120 produces a clock signal with a perturbation and has a ^N and N+1 dual mode, where N is a positive integer. The bipolar frequency divider 120 shown in the second figure is designed according to N being 16 for illustration. The pseudo-random-sequence generator 130 receives the perturbed clock signal from the dual-mode frequency divider 12 to generate a disturbed data signal to the circuit under test, but the dual-mode frequency divider 12 〇 2N * 16 to illustrate, lack, the embodiment is not limited to this, the dual mode in addition to (four) 12 〇 n can also be 7, 18, and so on. In the embodiment of the present invention, the disturbance self-test circuit 1 further includes a letter generator 140 and a first-order triangular integral modulator 150. The sinusoid 150 has a sine wave coupled to the 140 I. The -order delta-sigma modulator - H number generator 14G and the dual mode are 12 years old. The number 150 receives the sine wave to generate a - bit signal, and the second mode (10). The dual mode sequence produces 3 130 automatic clock signals. The pseudo-random binary façade 130 from the dual mode removes the clock signal of the crying to produce a sinusoidal disturbance with the sinusoidal disturbance 袼11(). Disturbing the data signal to the power to be tested 201234032 The 16HO I to be tested has a working mode and a disturbance testing mode. When the 11G to be tested is in the working mode, the multi-boot 1116 entry mode is equal to the 〇 state. The multiplexer 116 connects the input data (Din) of frequency f and the in-phase quadrature output of the voltage controlled oscillator (In/Quadrature) and transmits it to the Alexandria phase detector (1). The circuit to be tested 11 is in a normal square; wherein the horizontal phase/orthogonal output includes a vc〇 signal and a VCO-Q signal. For example, if the circuit to be tested is u-covered, the input data can be a frequency of 6 Gbps. When the circuit under test 110 is in the disturbance test mode, the multiplexer 116 enters a state in which the mode is equal to 1. The multiplexer 116 transmits the pseudo random random sequence generator U0. The disturbed data signal and a reference clock signal (Ref_CK) are sent to the Alexandria phase detector (1). At this time, because the dual mode frequency divider 120 is set to output frequency is 1/N or 1/ of the input frequency. (N+1)' Therefore, the frequency of the signal output from the dual-mode frequency divider 12〇 to the pseudo-random binary sequence generator 130 is f/N or f/(N+1), and the pseudo-random binary sequence generator 130 The data signal of the frequency f/N or f/(N+1) is generated to the circuit under test 110. In other words, the input The input data rate of the data signal to the circuit under test is reduced by N times. However, when the input data rate is reduced by N times, the bandwidth loop gain of the circuit under test 11 也 is also reduced by n times. Therefore, in order to maintain the circuit to be tested 11 〇 loop gain, voltage-current-to-current converter 113 current needs to be increased by ^ ^. So the voltage control oscillator 115 operating frequency will be in working mode with the circuit under test 110 The voltage control oscillator n5 is the same. For example, the operating frequency of the voltage control jar 115 is 6 GHz in both the operating mode and the disturbance test mode. 201234032 Nashua 'The sine function generator 140 and the - order The triangular integral ° field, the Di system is used to adjust the dual mode frequency divider 120; further, it is the division ratio (DivisionRati.) of the double frequency divider 120. The dual two-pole device 120 controls the oscillator from the voltage. 115 receives the vco-1 signal, and divides the frequency and outputs the clock signal with the disturbance. The pseudo-random binary sequence generator 13G receives the disturbed clock, as described above, to generate a disturbance. Capital Signal to the test circuit 110. From the above description, the dual-mode frequency divider 120 of the coefficient bits adjusted pseudorandom binary sequence generator 130.
如第1圖所示，正弦擾動的振幅及頻率可分別由ACW 端（Amplitude Control Word)及 FCW 端（Frequency ControlAs shown in Figure 1, the amplitude and frequency of the sinusoidal disturbance can be from the ACW end (Amplitude Control Word) and the FCW end (Frequency Control).
Word)分別控制。因此，位元錯誤率與正弦擾動的振幅及頻 率的關係係數位的。此外，該一階三角積分調變器15〇的 輸出可事先被計算並儲存於場式可編程閘 (Field-programmable Gate Array, FPGA)的記憶體。由上述說 明可知，正弦擾動係由該一階三角積分調變器15〇數位化 鲁並用以調節該雙模除頻器120。該雙模除頻器12〇的輸出頻 率^divider可以下式表不· r、 = ^out d-der -N + /K) 其中，f(c〇m)=0.5+NA*sin(〇)mt)且 〇切心〇.5，ωω 及 na 分別為正弦波的頻率及振幅。coQUt為該電壓控制震盈器ll5 的震盪頻率。 當Na/N<<1且該正弦函數產生器14〇的頻率等於^ 201234032 時，正弦擾動的振幅約為_^。因此，本發明中擾動的 頻率及振幅係可被數位程式化的，不需要額外的校準。 本發明擾動自我測試電路100可進一步包括 二進制序列檢查If 16G。、如第-_示，該偽隨機二進制， 列檢查器160耦接該待測電路110。請同時參考第四 四圖係偽隨機二進制序列檢查器16G之—具體實施示意圖第 該偽隨機二進制序列檢查器16〇具有一同步模式及一 擾動自我測試模式。其中該偽隨機二進制序列檢查器16〇 於同步模式時，接收該待測電路11〇的一重新定 (Retimed Data)以同步該偽隨機二進制序列產生器13〇°。具 體而言，當同步訊號(Sync)之位準為高位訊號時'該偽隨； 一進制序列檢查器160係處於同步模式。6個〇正反器（dWord) separately controlled. Therefore, the bit error rate is proportional to the amplitude and frequency of the sinusoidal perturbation. In addition, the output of the first-order delta-sigma modulator 15 可 can be calculated in advance and stored in a field-programmable gate Array (FPGA) memory. As can be seen from the above description, the sinusoidal disturbance is digitally converted by the first-order delta-sigma modulator 15 and used to adjust the dual-mode frequency divider 120. The output frequency of the dual-mode frequency divider 12〇 can be expressed as follows: r, = ^out d-der -N + /K) where f(c〇m)=0.5+NA*sin(〇) Mt) and the heart is cut. 5, ωω and na are the frequency and amplitude of the sine wave, respectively. CoQUt is the oscillation frequency of this voltage controlled oscillator ll5. When Na/N<<1 and the frequency of the sine function generator 14? is equal to ^201234032, the amplitude of the sinusoidal disturbance is about _^. Thus, the frequency and amplitude of the disturbances in the present invention can be digitally programmed without additional calibration. The perturbation self test circuit 100 of the present invention may further include a binary sequence check If 16G. The pseudo-random binary, the column checker 160 is coupled to the circuit under test 110. Please refer to the fourth embodiment of the pseudo-random binary sequence checker 16G. The pseudo-random binary sequence checker 16 has a synchronization mode and a perturbation self-test mode. The pseudo-random binary sequence checker 16 receives a retimed data of the circuit under test 11 以 to synchronize the pseudo-random binary sequence generator 13 〇°. Specifically, when the level of the sync signal (Sync) is a high signal, the pseudo-sequencer 160 is in the synchronous mode. 6 〇 positive and negative devices (d
Flip-fl〇p)41〇及1個7輸入埠的且閘（ANd Gate)420偵測 「iiiiiii」的態樣以同步該偽隨機二進制序列產生器13〇。 另一方面，當該偽隨機二進制序列檢查器16〇於擾動 自我測試模式時，該偽隨機二進制序列檢查器16〇輸出一 ，較Λ號。具體而言，當同步訊號之位準為低位訊號時， 該偽隨機二進制序列檢查器160係處於擾動自我測試模 式。如第1圖及第4圖所示，互斥或閘（X0R 〇ate)比較該偽 隨機一進制序列檢查器160中一偽隨機二進制序列產生器 13〇的輸出訊號及該待測電路11〇的一重新定時訊號 (Retimed Data)。如果此兩訊號不同，則該互斥或閘就輸出 1再父由位元錯誤率§十算器（BER Counter)去計算位元錯誤 率。 201234032 如此一來，藉由在資料時脈回覆電路中内建自我測試 功能，可大幅降低製造成本。如此可減少測量·之不便，進 而提高產品之競爭力。 由上述敘述可知，本發明實為一新穎、進步且具產業 實用性之發明。雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明，任何熟悉此技藝者，在不脫離本 發明之精神和範圍内，當可作各種之更動與潤飾。Flip-fl〇p) 41〇 and a 7-input 且 AND (ANd Gate) 420 detect the "iiiiiii" aspect to synchronize the pseudo-random binary sequence generator 13A. On the other hand, when the pseudo-random binary sequence checker 16 is in the perturbation self-test mode, the pseudo-random binary sequence checker 16 outputs an apostrophe. Specifically, when the level of the sync signal is a low signal, the pseudo random binary sequence checker 160 is in a perturbation self test mode. As shown in FIG. 1 and FIG. 4, the mutual exclusion or gate (X0R 〇ate) compares the output signal of a pseudo-random binary sequence generator 13〇 in the pseudo-random one-ary sequence checker 160 and the circuit under test 11 A retimed signal (Retimed Data). If the two signals are different, the mutex or gate outputs 1 and then the BER Counter is used to calculate the bit error rate. 201234032 As a result, the built-in self-test function in the data clock reply circuit can greatly reduce the manufacturing cost. This can reduce the inconvenience of measurement and increase the competitiveness of the product. As apparent from the above description, the present invention is a novel, progressive, and industrially useful invention. While the invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention.
11 201234032 【圖式簡單說明】 第一圖係例示說明本發明擾動自我測試電路之基本結構。 第二圖係顯示雙模除頻器一種實施態樣的示意圖。 第三圖係顯示偽隨機二進制序列產生器一種實施態樣的示 意圖。 第四圖係偽隨機二進制序列檢查器之具體實施示意圖 【主要元件符號說明】11 201234032 [Simplified description of the drawings] The first figure illustrates the basic structure of the disturbance self-test circuit of the present invention. The second figure shows a schematic diagram of an embodiment of a dual mode frequency divider. The third figure shows a schematic representation of an implementation of a pseudo-random binary sequence generator. The fourth figure is a schematic diagram of the specific implementation of the pseudo-random binary sequence checker.
100 擾動自我測試電路 檢查器 110 待測電路 410 D正反器 111 亞力山大相位偵測器 420 且閘 112 頻率偵測器 ACW 振幅控制端 113 .電壓電流轉換器 Din 輸入資料 114 被動迴圈濾波器 FCW 頻率控制端 115 電壓控制震盪器 Mode 模式 116 多工器 Ref_CK 參考時脈訊號 120 雙模除頻器 Retimed Data 重新定時 130 偽隨機二進制序列 訊號 產生器 Sync 同步訊號 140 正弦函數產生器 VCO_ _1 同相輸出 150 一階三角積分調變 VCO_ .Q 正交輸出 器 160 偽隨機二進制序列100 Disturbance self-test circuit checker 110 Circuit to be tested 410 D-reactor 111 Alexandria phase detector 420 and gate 112 Frequency detector ACW amplitude control terminal 113. Voltage-current converter Din Input data 114 Passive loop filtering FCW frequency control terminal 115 voltage control oscillator Mode mode 116 multiplexer Ref_CK reference clock signal 120 dual mode frequency divider Retimed Data retimed 130 pseudo random binary sequence signal generator Sync synchronization signal 140 sine function generator VCO_ _1 in phase Output 150 first-order triangular integral modulation VCO_ .Q orthogonal output 160 pseudo-random binary sequence
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